There are two limitations on the power handling ability of a
transistor: average junction temperature and second break-
down. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipa-
tion than the curves indicate.
The data of Figure 1 is based on TJ(pk) = 150
_
C; TC is vari-
able depending on conditions. Second breakdown pulse lim-
its are valid for duty cycles to 10% provided TJ(pk)
v
150
_
C.
At high case temperatures, thermal limitations will reduce the
power that can be handled to values less then the limitations
imposed by second breakdown.
IC, COLLECTOR CURRENT (AMP)
hFE, DC CURRENT GAIN, NORMALIZED
7.0
10
0.02 0.03 0.1 4.00.01
1.0
0.7
0.5
0.1 0.05 0.3 0.50.2
150
°
CTJ = 25
°
C
–55
°
C
Figure 2. DC Current Gain Figure 3. “On” Voltage
2.0
IC, COLLECTOR CURRENT (AMP)
1.6
0.4
0
TJ = 25
°
C
VOLTAGE (VOLTS)
VBE(sat) @ IC/IB = 10 VBE(on) @ VCE = 1.0 V
5.0
0.3
0.2
1.2
0.8
t, TIME OR PULSE WIDTH (ms)
0.01
0.01 0.03 1.0 2.0 5.0 10 20 50 100 2000.1 0.50.2
1.0
0.2
0.1
0.05
r(t), EFFECTIVE TRANSIENT
θ
JC(t) = r(t)
θ
JC
θ
JC = 3.12
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk)
θ
JC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
THERMAL RESISTANCE (NORMALIZED)
Figure 4. Thermal Response
0.5 D = 0.5
0.1
0.01
0.3
0.7
0.07
0.03
0.02
3.0
2.0
1.0 3.02.0
VCE = 1.0 Vdc
VCE(sat) @ IC/IB = 10
0.01 0.02 0.05 4.00.005 0.03 0.2 0.30.1 0.5 2.0 3.01.0
0.02 0.05 0.3 3.0 500 1000
0.02
0.05
0.2