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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.4.1 Pull-up Resistor Control
Each I/O line is design ed with a n emb edded pu ll-up re sistor . The p ull-up resistor can be e nabled
or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-
up Disable Resistor). Wr iting in the se regist ers resu lts in sett ing or clear ing the corr esponding bit
in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is dis-
abled and readin g a 0 me a ns the pu ll-u p is enab le d.
Control of the pull-up resistor is possible regardless of the configurat ion of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
27.4.2 I/O Line or Peripheral Func tion Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis-
ter PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates
whether the pin is co ntrolled by the cor respond ing perip heral or by the PIO Contr oller. A va lue of
0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),
PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR
resets at 1. However, in some events, it is important that PIO lines are controlled by the periph-
eral (as in the case of memory chip select lines that must be driven inactive after reset or for
address lines that must be driven low for booting out of an external memory). Thu s, the reset
value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
27.4.3 Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The
selection is performed by writing PIO_ASR (A Select Register) an d PIO_BSR (Select B Re gis-
ter). PIO_ABSR (AB Sele ct Stat us Registe r) indicat es which periph eral l ine is curr ently selecte d.
For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corre-
sponding bit at level 1 indicates t hat peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral
input lines are always co nn ec te d to th e pin inpu t.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A.
However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line
mode.
Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the
pin. Howeve r, assignm ent of a pin to a pe ripheral f unction r equires a wr ite in the co rrespond ing
peripheral selection register (PIO_A SR or PIO_BSR) in addition t o a write in PIO_PDR.
27.4.4 Output ControlWhen the I/0 line is assigned to a peripheral func tio n, i.e. t he correspond ing bit in PIO_PSR is at
0, the drive of the I/O line is co ntrolled by the peripheral. Peripheral A or B, dependin g on the
value in PIO_ABSR, determines whether the pin is driven or not.
When the I/O line is cont ro lled by th e PI O contr oller, th e pi n can be con figur ed t o be d riven . T his
is done by writing PIO_ OER (Output Enable Register) and PIO_ODR (Output Disable Register).
The results of these write operations are detected in PIO_OSR (Output Status Register). When