LM3671MF-1.5/NOPB - NATIONAL SEMICONDUCTOR

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GND

L1: 2.2 PHVOUT

COUT

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4.7 PFLM3671

VIN

2.7V to 5.5V

VIN SW

GND

L1: 2.2 PHVOUT

COUT

10 PF

CIN

4.7 PF

LM3671-

ADJ

VIN

2.7V to 5.5V

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

LM3671/-Q1 2-MHz, 600-mA Step-Down DC-DC Converter

1 Features

1• LM3671-Q1 is Qualified for Automotive

Applications

• AEC Q100-Qualified With the Following Results

– Device Temperature Grade 1: –40°C to

+125°C Ambient Operating Temperature

Range

• 16-µA Typical Quiescent Current

• 600-mA Maximum Load Capability

• 2-MHz PWM Fixed Switching Frequency (Typical)

• Automatic PFM-PWM Mode Switching

• Internal Synchronous Rectification for High

Efficiency

• Internal Soft Start

• 0.01-µA Typical Shutdown Current

• Operates from a Single Li-Ion Cell Battery

• Only Three Tiny Surface-Mount External

Components Required (One Inductor, Two

Ceramic Capacitors)

• Current Overload and Thermal Shutdown

Protection

• Available in Fixed Output Voltages and Adjustable

Version

2 Applications

• Mobile Phones

• PDAs

• MP3 Players

• W-LAN

• Portable Instruments

• Digital Still Cameras

• Portable Hard Disk Drives

• Automotive

• Portable Medical Equipment

• Handheld Transaction Terminals

• Wireless Home-Automation Equipment

3 Description

The LM3671 step-down DC-DC converter is

optimized for powering low voltage circuits from a

single Li-Ion cell battery and input voltage rails from

2.7 V to 5.5 V. It provides up to 600-mA load current,

over the entire input voltage range. There are several

different fixed voltage output options available as well

as an adjustable output voltage version range from

1.1 V to 3.3 V.

The device offers superior features and performance

for mobile phones and similar portable systems.

Automatic intelligent switching between PWM low-

noise and PFM low-current mode offers improved

system control. During PWM mode, the device

operates at a fixed-frequency of 2 MHz (typical).

Hysteretic PFM mode extends the battery life by

reducing the quiescent current to 16 µA (typical)

during light load and standby operation. Internal

synchronous rectification provides high efficiency

during PWM mode operation. In shutdown mode, the

device turns off and reduces battery consumption to

0.01 µA (typical).

A high-switching frequency of 2 MHz (typical) allows

use of tiny surface-mount components. Only three

external surface-mount components, an inductor, and

two ceramic capacitors, are required.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

LM3671 USON (6) 2.00 mm × 2.00 mm (NOM)

LM3671

LM3671-Q1 SOT-23 (5) 2.90 mm × 1.60 mm (NOM)

DSBGA (5) 1.413 mm × 1.083 mm (MAX)

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Circuit: Fixed-Voltage Typical Application Circuit: ADJ

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings: LM3671 .............................................. 4

6.3 ESD Ratings: LM3671-Q1 ........................................ 4

6.4 Recommended Operating Conditions....................... 5

6.5 Thermal Information.................................................. 5

6.6 Dissipation Ratings ................................................... 5

6.7 Electrical Characteristics........................................... 6

6.8 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 13

8 Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application.................................................. 16

9 Power Supply Recommendations...................... 20

10 Layout................................................................... 21

10.1 Layout Guidelines ................................................. 21

10.2 Layout Example .................................................... 22

10.3 DSBGA Package Assembly and Use ................... 22

11 Device and Documentation Support................. 23

11.1 Device Support...................................................... 23

11.2 Documentation Support ........................................ 23

11.3 Related Links ........................................................ 23

11.4 Community Resources.......................................... 23

11.5 Trademarks........................................................... 23

11.6 Electrostatic Discharge Caution............................ 23

11.7 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information........................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision R (November 2014) to Revision S Page

• Added top nav icon for TI Design .......................................................................................................................................... 1

• Added several new "Applications" ......................................................................................................................................... 1

• moved storage temperature to Abs Max table ...................................................................................................................... 4

• Changed Handling Ratings to ESD Ratings .......................................................................................................................... 4

• Changed RθJA for USON from 165°C/W to 174.7°C/W; for SOT-23 from 130°C/W to 165.7°C/W, and for DSBGA

from 85°C/W to 181.0°C/W; added additional thermal values ............................................................................................... 5

• Changed RθJA values in Dissipation Ratings table ................................................................................................................. 5

Changes from Revision Q (November 2013) to Revision R Page

• Added Device Information and Handling Rating tables, Feature Description,Device Functional Modes,Application

and Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and

Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section ............. 1

Changes from Revision O (April 2013) to Revision P Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 22

Top View Bottom View

C3 EN

GND

VIN

GND

VIN

C3 C1

VIN

1GND

2EN

3 4

Pgnd

Vin

2 5

Sgnd

TOP VIEW

LM3671

LM3671-Q1

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SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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5 Pin Configuration and Functions

DBV Package

5 Pin SOT-23

Top View NKH Package

6-Pin USON

YZR Package

5-Pin DSBGA

Pin Functions

TYPE DESCRIPTION

LM3671, LM3671-

Q1 LM3671 NAME

SOT-23 DSBGA USON

1 A1 3 VIN Power Power supply input. Connect to the input filter capacitor (see Input Capacitor

Selection).

2 A3 2 GND Ground Ground pin.

3 C1 1 EN Digital Enable pin. The device is in shutdown mode when voltage to this pin is < 0.4

V and enabled when > 1 V. Do not leave this pin floating.

4 C3 6 FB Analog Feedback analog input. Connect directly to the output filter capacitor for fixed

voltage versions. For adjustable version external resistor dividers are

required (see Typical Application: ADJ Version). The internal resistor dividers

are disabled for the adjustable version.

5 B2 4 SW Analog Switching node connection to the internal PFET switch and NFET

synchronous rectifier.

— — 5 SGND Ground Signal ground (feedback ground).

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and

specifications.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typical) and

disengages at TJ= 130°C (typical).

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)

MIN MAX UNIT

VIN pin: voltage to GND −0.2 6 V

FB, SW, EN pins GND −0.2 VIN + 0.2 V

Continuous power dissipation(3) Internally Limited

Junction temperature, TJ-MAX 125 °C

Maximum lead temperature (soldering, 10 sec.) 260 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings: LM3671 VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

Machine model 200

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings: LM3671-Q1 VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1) ±2000

Charged-device model (CDM), per

AEC Q100-011

All pins except corner pins ±500

Corner pins (1, 3, 4, and 5): SOT-23 ±750

Corner pins (A1, A3, C1, and C3):

DSBGA ±750

Machine model ±200

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LM3671-Q1

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) The input voltage range recommended for ideal applications performance for the specified output voltages are given below: VIN = 2.7 V

to 4.5 V for 1.1 V ≤VOUT < 1.5 VIN = 2.7 V to 5.5 V for 1.5 V ≤VOUT < 1.8 VIN = (VOUT + VDROPOUT) to 5.5 V for 1.8 V ≤VOUT ≤3.3 V

where VDROPOUT = ILOAD × (RDSON, PFET + RINDUCTOR).

(4) In applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to

be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), the

maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package

(RθJA) in the application, as given by the following equation: TA-MAX = TJ-MAX −(RθJA × PD-MAX). Refer to Dissipation Ratings for PD-MAX

values at different ambient temperatures.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Input voltage(3) 2.7 5.5 V

Recommended load current 0 600 mA

Junction temperature, TJ–40 125 °C

Ambient temperature, TA(4) –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Thermal Information

THERMAL METRIC(1) LM3671 LM3671 and LM3671-Q1

UNITNKH (USON) DBV (SOT-23 ) YZR (DSBGA)

6 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 174.7 165.7 181.0 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 87.1 116.6 0.9 °C/W

RθJB Junction-to-board thermal resistance 109.0 26.8 110.3 °C/W

ψJT Junction-to-top characterization parameter 6.4 13.3 7.4 °C/W

ψJB Junction-to-board characterization parameter 109.0 26.3 110.3 °C/W

6.6 Dissipation Ratings

RθJA TA≤25°C

POWER RATING TA= 60°C

POWER RATING TA= 85°C

POWER RATING

165.7°C/W (4 layer board) SOT-23 770 mW 500 mW 310 mW

181°C/W (4 layer board) 5-bump DSBGA 1179 mW 765 mW 470 mW

174.7°C/W (4 layer board) 6-pin USON 606 mW 394 mW 242 mW

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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(1) Minimum (MIN) and maximum (MAX) limits are specified by design, test or statistical analysis. Typical (TYP) numbers are not specified,

but do represent the most likely norm.

(2) The parameters in the electrical characteristic table are tested at VIN = 3.6 V unless otherwise specified. For performance over the input

voltage range refer to datasheet curves.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 150°C (typical) and

disengages at TJ= 130°C (typical).

(4) The input voltage range recommended for ideal applications performance for the specified output voltages are given below: VIN = 2.7 V

to 4.5 V for 1.1 V ≤VOUT < 1.5 VIN = 2.7 V to 5.5 V for 1.5 V ≤VOUT < 1.8 VIN = (VOUT + VDROPOUT) to 5.5 V for 1.8 V ≤VOUT ≤3.3 V

where VDROPOUT = ILOAD × (RDSON, PFET + RINDUCTOR).

(5) Test condition: for VOUT less than 2.5 V, VIN = 3.6 V; for VOUT greater than or equal to 2.5 V, VIN = VOUT + 1 V.

(6) ADJ version is configured to 1.5 V output. For ADJ output version: VIN = 2.7 V to 4.5 V for 0.9 V ≤VOUT < 1.1 VIN = 2.7 V to 5.5 V for 1.1

V≤VOUT < 3.3 V

(7) Refer to Typical Characteristics for closed-loop data and its variation with regards to supply voltage and temperature. Electrical

Characteristics reflects open-loop data (FB = 0 V and current drawn from SW pin ramped up until cycle by cycle current limit is

activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until

output voltage drops by 10%.

6.7 Electrical Characteristics

Unless otherwise noted, limits apply for for TJ= 25°C, and specifications apply to the LM3671MF/TL/LC with VIN = EN = 3.6

V(1)(2)(3)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

VIN Input voltage −40°C to 125°C, see(4) 2.7 5.5 V

VFB

Feedback voltage (fixed) MF PWM mode(5),−40°C to 125°C

−4% 4%

Feedback voltage (fixed) TL −2.5% 2.5%

Feedback voltage (fixed) LC −4% 4%

Feedback voltage (ADJ) MF(6) PWM mode(5),−40°C to 125°C −4% 4%

Feedback voltage (ADJ) TL −2.5 2.5

Line regulation 2.7 V ≤VIN ≤5.5 V, IO= 10 mA 0.031 %/V

Load regulation 100 mA ≤IO≤600 mA, VIN = 3.6 V 0.0013 %/mA

VREF Internal reference voltage 0.5 V

ISHDN Shutdown supply current EN = 0 V 0.01 µA

EN = 0 V, −40°C to 125°C 1

IQDC bias current into VIN

No load, device is not switching (FB

forced higher than programmed output

voltage) 16

µA

No load, device is not switching (FB

forced higher than programmed output

voltage), −40°C to 125°C 35

RDSON (P) Pin-pin resistance for PFET VIN = VGS = 3.6 V 380 500 mΩ

RDSON (N) Pin-pin resistance for NFET VIN = VGS= 3.6 V 250 400 mΩ

ILIM Switch peak current limit Open loop(7) 1020 mA

Open loop(7),−40°C to 125°C 830 1150

VIH Logic high input −40°C to 125°C 1 V

VIL Logic low input −40°C to 125°C 0.4 V

IEN Enable (EN) input current 0.01 µA

−40°C to 125°C 1

ƒOSC Internal oscillator frequency PWM Mode(5) 2MHz

PWM Mode(5),−40°C to 125°C 1.6 2.6

-10 10 30 50 70 90 110

TEMPERATURE (oC)

100

150

200

250

300

350

400

450

500

550

600

RDS(ON) (m:)

-30

NFET VIN = 4.5V

PFET

VIN = 2.7V

VIN = 4.5V VIN = 3.6V

VIN = 3.6V

VIN = 2.7V

3.0 3.5 4.0 4.5 5.0 5.5 6.0

SUPPLY VOLTAGE (V)

QUIESCENT CURRENT (PA)

2.5

TA = 85°C

EN = VIN

IOUT = 0 mA

TA = 25°C

TA = -30°C

-10 10 30 50 70 90

TEMPERATURE (°C)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

SHUTDOWN CURRENT (PA)

-30

EN = GND

VIN = 3.6V

VIN = 2.7V

VIN = 5.5V

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6.8 Typical Characteristics

LM3671MF/TL/LC, circuit of Figure 32, VIN = 3.6 V, VOUT = 1.5 V, TA= 25°C, unless otherwise noted.

Figure 1. Quiescent Supply Current vs Supply Voltage Figure 2. Shutdown Current vs Temp

Figure 3. Feedback Bias Current vs Temperature Figure 4. Switching Frequency vs Temperature

Figure 5. RDS(ON) vs. Temperature Figure 6. Open/Closed Loop Current Limit vs Temperature

0 100 200 300 400 500 600

OUTPUT CURRENT (mA)

1.48

1.5

1.52

1.54

OUTPUT VOLTAGE (V)

VIN = 3.6V

VOUT = 1.5V

PFM Mode

PWM Mode

-10 10 30 50 70 90

TEMPERATURE (oC)

1.4800

1.4850

1.4900

1.4950

1.5000

1.5050

1.5100

1.5150

1.5200

1.5250

1.5300

OUTPUT VOLTAGE (V)

-30

PFM Mode

PWM Mode

IOUT = 300 mA

VIN = 3.6V

VOUT = 1.5V

IOUT = 600 mA

IOUT = 10 mA

2.5 3 3.5 4 4.5 5 5.5

SUPPLY VOLTAGE(V)

1.4800

1.4900

1.5000

1.5100

1.5200

1.5300

= 10 mAIOUT

= 1.5 V

OUT

= 300 mA

IOUT

= 500 mA

IOUT

= 600 mA

IOUT

OUTPUT VOLTAGE (V)

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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Typical Characteristics (continued)

LM3671MF/TL/LC, circuit of Figure 32, VIN = 3.6 V, VOUT = 1.5 V, TA= 25°C, unless otherwise noted.

Figure 7. Output Voltage vs. Supply Voltage Figure 8. Output Voltage vs Supply Voltage

Figure 9. Output Voltage vs Temperature Figure 10. Output Voltage vs Temperature

Figure 11. Output Voltage vs Output Current Figure 12. Output Voltage vs Output Current

VOUT

40 Ps/DIV

3.6V

VIN 3.0V

20 mV/DIV

AC Coupled

VOUT = 1.5V

IOUT = 400 mA

0.10 1.00 10.00 100.00 1000.00

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

0.01

VIN = 2.7V

VIN = 4.5V

VIN = 3.6V

VOUT = 1.5V

0.10 1.00 10.00 100.00 1000.00

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

0.01

VIN = 3.0V

VIN = 4.5V

VIN = 3.6V

VOUT = 1.8V

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LM3671-Q1

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Typical Characteristics (continued)

LM3671MF/TL/LC, circuit of Figure 32, VIN = 3.6 V, VOUT = 1.5 V, TA= 25°C, unless otherwise noted.

L = 2.2 µH

Figure 13. Efficiency vs Output Current

L = 2.2 µH

Figure 14. Efficiency vs Output Current

L = 2.2 µH

Figure 15. Efficiency vs Output Current

L = 2.2 µH

Figure 16. Efficiency vs Output Current

Figure 17. Line Transient Response (PWM Mode) Figure 18. Line Transient Response (PWM Mode)

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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Typical Characteristics (continued)

LM3671MF/TL/LC, circuit of Figure 32, VIN = 3.6 V, VOUT = 1.5 V, TA= 25°C, unless otherwise noted.

Figure 19. Load Transient Response (PWM Mode) Figure 20. Load Transient Response (PWM Mode)

PFM Mode 0.5 mA to 50 mA

Figure 21. Load Transient Response

PFM Mode 0.5 mA to 50 mA

Figure 22. Load Transient Response

PFM Mode 0.5 mA to 50 mA

Figure 23. Load Transient Response

PFM Mode 50 mA to 0.5 mA

Figure 24. Load Transient Response

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Typical Characteristics (continued)

LM3671MF/TL/LC, circuit of Figure 32, VIN = 3.6 V, VOUT = 1.5 V, TA= 25°C, unless otherwise noted.

Figure 25. PFM-to-PWM Mode Change by Load Transients Figure 26. PWM-to-PFM Mode Change by Load Transients

Figure 27. Start-Up into PWM Mode Figure 28. Start-Up into PFM Mode

2 MHz

Oscillator

Soft

Start

Ramp

Generator

Thermal

Shutdown

Undervoltage

Lockout

Frequency

Compensation

Error

Amp Control Logic Driver

Current Limit

Comparator

Ref1

PFM Current

Comparator

Ref2

Zero Crossing

Comparator

EN VIN

PWM Comparator

pfm_low

pfm_hi

GND

Bandgap

Vcomp

1.0V

Fixed Ver

Adj Ver

0.5V

VREF

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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7 Detailed Description

7.1 Overview

The LM3671, a high-efficiency step-down DC-DC switching buck converter, delivers a constant voltage from a

single Li-Ion battery and input voltage rails from 2.7 V to 5.5 V to portable devices such as cell phones and

PDAs. Using a voltage mode architecture with synchronous rectification, the LM3671 has the ability to deliver up

to 600 mA depending on the input voltage, output voltage, ambient temperature and the inductor chosen.

There are three modes of operation depending on the current required: pulse width modulation (PWM), pulse

frequency modulation (PFM), and shutdown. The device operates in PWM mode at load current of approximately

80 mA or higher. Lighter load current cause the device to automatically switch into PFM for reduced current

consumption (IQ= 16 µA typical) and a longer battery life. Shutdown mode turns off the device, offering the

lowest current consumption (ISHUTDOWN = 0.01 µA typical).

Additional features include soft-start, undervoltage protection, current overload protection, and thermal shutdown

protection. As shown in the Figure 35, only three external power components are required for implementation.

The device uses an internal reference voltage of 0.5 V. TI recommends keeping the device in shutdown until the

input voltage is 2.7 V or higher.

7.2 Functional Block Diagram

VOUT

TIME (200 ns/DIV)

200 mA/DIV

VSW 2V/DIV

10 mV/DIV

AC Coupled

VIN = 3.6V

VOUT = 1.5V IOUT = 400 mA

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7.3 Feature Description

7.3.1 Circuit Operation

During the first portion of each switching cycle, the control block in the LM3671 turns on the internal PFET

switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The

inductor limits the current to a ramp with a slope of (VIN – VOUT)/L, by storing energy in a magnetic field.

During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the

input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the

NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –VOUT/L.

The output filter stores charge when the inductor current is high, and releases it when inductor current is low,

smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the

load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and

synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The

output voltage is equal to the average voltage at the SW pin.

7.3.2 Soft Start

The LM3671 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current

limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches 2.7

V. Soft start is implemented by increasing switch current limit in steps of 70 mA, 140 mA, 280 mA and 1020 mA

(typical switch current limit). The start-up time thereby depends on the output capacitor and load current

demanded at startup. Typical start-up times with a 10-µF output capacitor and 300-mA load is 400 µs and with 1-

mA load is 275 µs.

7.4 Device Functional Modes

7.4.1 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to

the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is

introduced.

While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating

the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned

on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The

current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the

NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off

the NFET and turning on the PFET.

Figure 29. Typical PWM Operation

VOUT

TIME (4 Ps/DIV)

200 mA/DIV

VSW 2V/DIV

20 mV/DIV

AC Coupled

VIN = 3.6V

VOUT = 1.5V IOUT = 20 mA

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Device Functional Modes (continued)

7.4.1.1 Internal Synchronous Rectification

While in PWM mode, the LM3671 uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

7.4.1.2 Current Limiting

A current limit feature allows the LM3671 to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1020 mA (typical). If the output

is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer

duration until the inductor current falls below a low threshold. This allows the inductor current more time to

decay, thereby preventing runaway.

7.4.2 PFM Operation

At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

1. The NFET current reaches zero.

2. The peak PMOS switch current drops below the IMODE level, (Typically IMODE < 30 mA + VIN/42 Ω).

Figure 30. Typical PFM Operation

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between approximately 0.6% and 1.7% above the nominal PWM output

voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage reaches the high PFM threshold or the peak current exceeds the IPFM level

set for PFM mode. The typical peak current in PFM mode is: IPFM = 112 mA + VIN/27 Ω.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the ‘high’ PFM comparator threshold (see Figure 31), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM

threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output

switches are turned off, and the device enters an extremely low power mode. Quiescent supply current during

this ‘sleep’ mode is 16 µA (typ.), which allows the device to achieve high efficiency under extremely light load

conditions.

High PFM Threshold

~1.017*Vout

Low1 PFM Threshold

~1.006*Vout

PFM Mode at Light Load

PWM Mode at

Moderate to Heavy

Loads

Pfet on

until

Ipfm limit

reached

Nfet on

drains

inductor

current

until

I inductor = 0

High PFM

Voltage

Threshold

reached,

go into

sleep mode

Low PFM

Threshold,

turn on

PFET

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

Low2 PFM Threshold,

switch back to PWMmode

Load current

increases

Low2 PFM Threshold

Vout

Z-

Axis

LM3671

LM3671-Q1

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Product Folder Links: LM3671 LM3671-Q1

Device Functional Modes (continued)

If the load current should increase during PFM mode (see Figure 31) causing the output voltage to fall below the

low2 PFM threshold, the device will automatically transition into fixed-frequency PWM mode. When VIN = 2.7 V

the device transitions from PWM to PFM mode at approximately 35 mA output current and from PFM to PWM

mode at approximately 85 mA , when VIN = 3.6 V, PWM to PFM transition happens at approximately 50 mA and

PFM to PWM transition happens at approximately 100 mA, when VIN = 4.5 V, PWM to PFM transition happens at

approximately 65 mA and PFM to PWM transition happens at approximately 115 mA.

Figure 31. Operation in PFM Mode and Transfer to PWM Mode

7.4.3 Shutdown

Setting the EN input pin low (< 0.4 V) places the LM3671 in shutdown mode. During shutdown the PFET switch,

NFET switch, reference, control and bias circuitry of the LM3671 are turned off. Setting EN high (> 1 V) enables

normal operation. It is recommended to set EN pin low to turn off the LM3671 during system power up and

undervoltage conditions when the supply is less than 2.7 V. Do not leave the EN pin floating.

7.4.4 Low Dropout Operation (LDO)

The LM3671-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout

support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input

voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV.

The minimum input voltage needed to support the output voltage is

VIN, MIN = ILOAD × (RDSON, PFET + RINDUCTOR)+VOUT

where

• ILOAD: Load current

• RDSON, PFET: Drain to source resistance of PFET switch in the triode region

• RINDUCTOR: Inductor resistance (1)



f

ISAT IOUTMAX + IRIPPLE

where IRIPPLE = VOUT

VIN ¸

§VIN - VOUT

VIN SW

GND

L1: 2.2 PHVOUT

COUT

10 PF

CIN

4.7 PFLM3671

VIN

2.7V to 5.5V

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

www.ti.com

Product Folder Links: LM3671 LM3671-Q1

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The external control of this device is very easy. First make sure the correct voltage been applied at VIN pin, then

simply apply the voltage at EN pin according to the Electrical Characteristics to enable or disable the output

voltage.

8.2 Typical Application

8.2.1 Typical Application: Fixed-Voltage Version

Figure 32. LM3671 Fixed-Voltage Typical Application Circuit

8.2.1.1 Design Requirements

Two ceramic capacitors and one inductor required for this application. These three external components need to

be selected very carefully for property operation. Please read Detailed Design Procedure.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Inductor Selection

There are two main considerations when choosing an inductor; the inductor should not saturate, and the inductor

current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current

rating specifications are followed by different manufacturers so attention must be given to details. Saturation

current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of

application should be requested from the manufacturer. The minimum value of inductance to specify good

performance is 1.76 µH at ILIM (typical) DC current over the ambient temperature range. Shielded inductors

radiate less noise and should be preferred.

There are two methods to choose the inductor saturation current rating.

8.2.1.2.1.1 Method 1

The saturation current should be greater than the sum of the maximum load current and the worst case average

to peak inductor current. This can be written as

where

• IRIPPLE: average to peak inductor current

IRMS = IOUTMAX 

The worst case is when VIN = 2 VOUT



(VIN - VOUT) VOUT

L f IOUTMAX VIN



  

r =

VOUT

VIN

1 - +

VOUT

VIN ¸



LM3671

LM3671-Q1

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Typical Application (continued)

• IOUTMAX: maximum load current (600 mA)

• VIN: maximum input voltage in application

• L : min inductor value including worst case tolerances (30% drop can be considered for method 1)

• f : minimum switching frequency (1.6 MHz)

• VOUT: output voltage (2)

8.2.1.2.1.2 Method 2

A more conservative and recommended approach is to choose an inductor that has a saturation current rating

greater than the maximum current limit of 1150 mA.

A 2.2-µH inductor with a saturation current rating of at least 1150 mA is recommended for most applications.

Inductor resistance should be less than 0.3 Ωfor good efficiency. Table 1 lists suggested inductors and

suppliers. For low-cost applications, an unshielded bobbin inductor could be considered. For noise critical

applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with

overlapping footprints of both types for design flexibility. This allows substitution of a low-noise shielded inductor,

in the event that noise from low-cost bobbin models is unacceptable.

8.2.1.2.2 Input Capacitor Selection

A ceramic input capacitor of 4.7 µF, 6.3 V is sufficient for most applications. Place the input capacitor as close as

possible to the VIN pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or

X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. The minimum input capacitance to specify good performance is 2.2 µF at 3-V DC

bias; 1.5 µF at 5-V DC bias including tolerances and over ambient temperature range. The input filter capacitor

supplies current to the PFET switch of the LM3671 in the first half of each cycle and reduces voltage ripple

imposed on the input power source. A ceramic capacitor’s low ESR provides the best noise filtering of the input

voltage spikes due to this rapidly changing current. Select a capacitor with sufficient ripple current rating. The

input current ripple can be calculated as:

(3)

Table 1. Suggested Inductors and Their Suppliers

MODEL VENDOR DIMENSIONS L × W × H (mm) D.C.R (maximum)(mΩ)

DO3314-222MX Coilcraft 3.3 × 3.3 × 1.4 200

LPO3310-222MX Coilcraft 3.3 × 3.3 × 1 150

ELL5GM2R2N Panasonic 5.2 × 5.2 × 1.5 53

CDRH2D14NP-2R2NC Sumida 3.2 × 3.2 × 1.55 94

8.2.1.2.3 Output Capacitor Selection

A ceramic output capacitor of 10 µF, 6.3 V is sufficient for most applications. Use X7R or X5R types; do not use

Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and

0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be requested

from them as part of the capacitor selection process.

The minimum output capacitance to specify good performance is 5.75 µF at 1.8-V DC bias including tolerances

and over ambient temperature range. The output filter capacitor smoothes out current flow from the inductor to

the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these

functions.

VPP-RMS = VPP-C2 + VPP-ESR2

VPP-C = 4*f*C

IRIPPLE

LM3671

LM3671-Q1

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The output voltage ripple is caused by the charging and discharging of the output capacitor and by the RESR and

can be calculated as:

Voltage peak-to-peak ripple due to capacitance can be expressed by Equation 4:

(4)

Voltage peak-to-peak ripple due to ESR can be expressed by Equation 5:

VPP-ESR = (2 × IRIPPLE) × RESR (5)

Because these two components are out of phase the rms (root mean squared) value can be used to get an

approximate value of peak-to-peak ripple.

The peak-to-peak ripple voltage, rms value can be expressed by Equation 6:

(6)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (RESR).

The RESR is frequency dependent (as well as temperature dependent); make sure the value used for calculations

is at the switching frequency of the part.

Table 2. Suggested Capacitors and Their Suppliers

MODEL TYPE VENDOR VOLTAGE RATING (V) CASE SIZE

INCH (mm)

4.7 µF for CIN

C2012X5R0J475K Ceramic, X5R TDK 6.3 0805 (2012)

JMK212BJ475K Ceramic, X5R Taiyo-Yuden 6.3 0805 (2012)

GRM21BR60J475K Ceramic, X5R Murata 6.3 0805 (2012)

C1608X5R0J475K Ceramic, X5R TDK 6.3 0603 (1608)

10 µF for COUT

GRM21BR60J106K Ceramic, X5R Murata 6.3 0805 (2012)

JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3 0805 (2012)

C2012X5R0J106K Ceramic, X5R TDK 6.3 0805 (2012)

C1608X5R0J106K Ceramic, X5R TDK 6.3 0603 (1608)

8.2.1.3 Application Curves

Figure 33. PFM-to-PWM Mode Change by Load Transients Figure 34. PWM-to-PFM Mode Change by Load Transients

Fp = 1

2 * S * (R1 R2) * (C1+C2)

Fz = 1

(2 * S * R1 * C1)

C2 = 1

(2 * S * R2 * 45 kHz)

C1 = 1

(2 * S * R1 * 45 kHz)

VOUT = VFB 1 + R1

R2 ¹



VIN SW

GND

L1: 2.2 PHVOUT

COUT

10 PF

CIN

4.7 PF

LM3671-

ADJ

VIN

2.7V to 5.5V

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8.2.2 Typical Application: ADJ Version

Figure 35. Typical Application Circuit for ADJ Version

8.2.2.1 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 2.7 V to 5.5 V

Input capacitor 4.7 µF

Output capacitor 10 µF

Inductor 2.2 µH

ADJ programmable output voltage 1.1 V to 3.3 V

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Output Voltage Selection for LM3671-ADJ

The output voltage of the adjustable parts can be programmed through the resistor network connected from VOUT

to FB, then to GND. VOUT is adjusted to make the voltage at FB equal to 0.5 V. The resistor from FB to GND

(R2) should be 200 kΩto keep the current drawn through this network well below the 16-µA quiescent current

level (PFM mode) but large enough that it is not susceptible to noise. If R2 is 200 kΩ, and VFB is 0.5 V, the

current through the resistor feedback network will be 2.5 µA. The output voltage of the adjustable parts ranges

from 1.1 V to 3.3 V.

The formula for output voltage selection is:

where

• VOUT: output voltage (volts)

• VFB : feedback voltage = 0.5 V

• R1: feedback resistor from VOUT to FB

• R2: feedback resistor from FB to GND (7)

For any output voltage greater than or equal to 1.1 V, a zero must be added around 45 kHz for stability. The

formula for calculation of C1 is:

(8)

For output voltages higher than 2.5 V, a pole must be placed at 45 kHz as well. If the pole and zero are at the

same frequency the formula for calculation of C2 is:

(9)

The formula for location of zero and pole frequency created by adding C1 and C2 is given below. By adding C1,

a zero as well as a higher frequency pole is introduced.

(10)

(11)

See the Table 3 table.

VOUT

TIME (100 Ps/DIV)

VSW 2V/DIV

500 mA/DIV

VIN = 3.6V

VOUT = 1.5V

2V/DIV

IOUT = 300 mA

1V/DIV

VOUT

TIME (100 Ps/DIV)

VSW 2V/DIV

500 mV/DIV

VIN = 3.6V

VOUT = 1.5V

IOUT = 1 mA

2V/DIV

LM3671

LM3671-Q1

SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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Table 3. LM3671-ADJ Configurations for Various VOUT

(Circuit of Figure 35)

VOUT (V) R1 (kΩ) R2 (kΩ) C1 (pF) C2 (pF) L (µH) CIN (µF) COUT (µF)

0.9 160 200 22 none 2.2 4.7 10

1.1 240 200 15 none 2.2 4.7 10

1.2 280 200 12 none 2.2 4.7 10

1.3 320 200 12 none 2.2 4.7 10

1.5 357 178 10 none 2.2 4.7 10

1.6 442 200 8.2 none 2.2 4.7 10

1.7 432 178 8.2 none 2.2 4.7 10

1.8 464 178 8.2 none 2.2 4.7 10

1.875 523 191 6.8 none 2.2 4.7 10

2.5 402 100 8.2 none 2.2 4.7 10

2.8 464 100 8.2 33 2.2 4.7 10

3.3 562 100 6.8 33 2.2 4.7 10

8.2.2.3 Application Curves

Figure 36. Start-Up into PWM Mode Figure 37. Start-Up into PFM Mode

9 Power Supply Recommendations

The LM3671 is designed to operate from a stable input supply range of 2.7 V to 5.5 V.

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10 Layout

10.1 Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or

instability.

Good layout for the LM3671 can be implemented by following a few simple design rules below. Refer to

Figure 38 for top layer board layout.

1. Place the LM3671, inductor and filter capacitors close together and make the traces short. The traces

between these components carry relatively high switching currents and act as antennas. Following this rule

reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN

and GND pin.

2. Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor through the LM3671 and inductor to the output filter

capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled

up from ground through the LM3671 by the inductor to the output filter capacitor and then back through

ground forming a second current loop. Routing these loops so the current curls in the same direction

prevents magnetic field reversal between the two half-cycles and reduces radiated noise.

3. Connect the ground pins of the LM3671 and filter capacitors together using generous component-side

copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several

vias. This reduces ground-plane noise by preventing the switching currents from circulating through the

ground plane. It also reduces ground bounce at the LM3671 by giving it a low-impedance ground connection.

4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.

This reduces voltage errors caused by resistive losses across the traces.

5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power

components. The voltage feedback trace must remain close to the LM3671 circuit and should be direct but

must be routed opposite to noisy components. This reduces EMI-radiated onto the voltage feedback trace of

the DC-DC converter. A good approach is to route the feedback trace on another layer and to have a ground

plane between the top layer and layer on which the feedback trace is routed. In the same manner, for the

adjustable part, the feedback dividers should be on the bottom layer.

6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks

and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through

distance.

In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,

arrange the CMOS digital circuitry around it (because this also generates noise), and then place sensitive

preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a

metal pan and power to the circuitry is post-regulated to reduce conducted noise, using LDOs.

LM3671

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10.2 Layout Example

Figure 38. Top Layer Board Layout for SOT-23

10.3 DSBGA Package Assembly and Use

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow

techniques, as detailed in AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Refer to the section

Surface Mount Technology (DSBGA) Assembly Considerations. For best results in assembly, alignment ordinals

on the PC board must be used to facilitate placement of the device. The pad style used with DSBGA package

must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the

pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off

the surface of the board and interfering with mounting. See AN-1112 DSBGA Wafer Level Chip Scale Package

(SNVA009) for specific instructions how to do this. The 5-pin package used for LM3671 has 300-micron solder

balls and requires 10.82 mils pads for mounting on the circuit board. The trace to each pad must enter the pad

with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should

be 7 mil wide, for a section approximately 7 mil long or longer, as a thermal relief. Then each trace must neck up

or down to its optimal width. The important criteria is symmetry. This ensures the solder bumps on the LM3671

re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the

pads for bumps A1 and A3, because VIN and GND are typically connected to large copper planes, inadequate

thermal relief can result in late or inadequate re-flow of these bumps.

The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque

cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is

vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed

circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA

devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges.

LM3671

LM3671-Q1

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For additional information, see the following:

AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

11.3 Related Links

Table 4 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 4. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LM3671 Click here Click here Click here Click here Click here

LM3671-Q1 Click here Click here Click here Click here Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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SNVS294S –NOVEMBER 2004–REVISED MAY 2016

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3671LC-1.2/NOPB ACTIVE USON NKH 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM S39

LM3671LC-1.3/NOPB ACTIVE USON NKH 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM S40

LM3671LC-1.6/NOPB ACTIVE USON NKH 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM S41

LM3671LC-1.8/NOPB ACTIVE USON NKH 6 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM S42

LM3671MF-1.2 NRND SOT-23 DBV 5 1000 Non-RoHS

& Green Call TI Call TI -40 to 85 SBPB

LM3671MF-1.2/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBPB

LM3671MF-1.25/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SDRB

LM3671MF-1.375/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SEDB

LM3671MF-1.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBRB

LM3671MF-1.6/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SDUB

LM3671MF-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBSB

LM3671MF-1.875/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SDVB

LM3671MF-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJRB

LM3671MF-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJSB

LM3671MF-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJEB

LM3671MF-ADJ/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBTB

LM3671MFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBPB

LM3671MFX-1.25/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SDRB

LM3671MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBSB

LM3671MFX-1.875/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SDVB

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3671MFX-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJRB

LM3671MFX-2.8/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJSB

LM3671MFX-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SJEB

LM3671MFX-ADJ/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SBTB

LM3671QMF-1.2/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH4B

LM3671QMFX-1.2/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH4B

LM3671QTL-1.8/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 9

LM3671QTLX-1.8/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 9

LM3671TL-1.2/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C

LM3671TL-1.5/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 D

LM3671TL-1.8/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 B

LM3671TL-2.5/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 L

LM3671TL-2.8/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 K

LM3671TL-3.3/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 J

LM3671TL-ADJ/NOPB ACTIVE DSBGA YZR 5 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 E

LM3671TLX-1.2/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C

LM3671TLX-1.5/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 D

LM3671TLX-1.8/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 B

LM3671TLX-2.5/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 L

LM3671TLX-2.8/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 K

LM3671TLX-3.3/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 J

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3671TLX-ADJ/NOPB ACTIVE DSBGA YZR 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 E

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM3671, LM3671-Q1 :

•Catalog: LM3671

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 4

•Automotive: LM3671-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3671LC-1.2/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1

LM3671LC-1.3/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1

LM3671LC-1.6/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1

LM3671LC-1.8/NOPB USON NKH 6 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1

LM3671MF-1.2 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.2/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.25/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.375/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.6/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-1.875/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-2.5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-2.8/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MF-ADJ/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-1.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-1.25/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3671MFX-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-1.875/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-2.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671MFX-ADJ/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671QMF-1.2/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671QMFX-1.2/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LM3671QTL-1.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671QTLX-1.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-1.2/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-1.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-1.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-2.5/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-2.8/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-3.3/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TL-ADJ/NOPB DSBGA YZR 5 250 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-1.2/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-1.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-1.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-2.5/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-2.8/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-3.3/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

LM3671TLX-ADJ/NOPB DSBGA YZR 5 3000 178.0 8.4 1.14 1.47 0.76 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3671LC-1.2/NOPB USON NKH 6 1000 210.0 185.0 35.0

LM3671LC-1.3/NOPB USON NKH 6 1000 210.0 185.0 35.0

LM3671LC-1.6/NOPB USON NKH 6 1000 210.0 185.0 35.0

LM3671LC-1.8/NOPB USON NKH 6 1000 210.0 185.0 35.0

LM3671MF-1.2 SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.2/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.25/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.375/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.6/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-1.875/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-2.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MF-ADJ/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671MFX-1.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-1.25/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-1.875/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 3

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3671MFX-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-2.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671MFX-ADJ/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671QMF-1.2/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LM3671QMFX-1.2/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LM3671QTL-1.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671QTLX-1.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TL-1.2/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-1.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-1.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-2.5/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-2.8/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-3.3/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TL-ADJ/NOPB DSBGA YZR 5 250 210.0 185.0 35.0

LM3671TLX-1.2/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-1.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-1.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-2.5/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-2.8/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-3.3/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

LM3671TLX-ADJ/NOPB DSBGA YZR 5 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 29-Sep-2019

Pack Materials-Page 4

MECHANICAL DATA

YZR0005xxx

www.ti.com

TLA05XXX (Rev C)

0.600±0.075

NOTES:

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

4215043/A 12/12

D: Max =

E: Max =

1.413 mm, Min =

1.083 mm, Min =

1.352 mm

1.022 mm

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PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.9

1.45

0.90

0.15

0.00 TYP

5X 0.5

0.3

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/E 09/2019

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

MECHANICAL DATA

NKH0006B

www.ti.com

LCA06B (Rev A)

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