MC14070BCPG - ON SEMICONDUCTOR

June, 2011 − Rev. 8

1Publication Order Number:

MC14070B/D

MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad

exclusive NOR gate are constructed with MOS P−channel and

N−channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use

where low power dissipation and/or high noise immunity is desired.

Features

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

•Double Diode Protection on All Inputs

•MC14070B − Replacement for CD4030B and CD4070B Types

•MC14077B − Replacement for CD4077B Type

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC140xxBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

1

14

140xxBG

AWLYWW

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

SOEIAJ−14

F SUFFIX

CASE 965

1

14

MC140xxB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

MC14070B, MC14077B

http://onsemi.com

2

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

Figure 1. Power Dissipation Test Circuit and Waveform

VDD

Vin

CL

*

IDD

20 ns 20 ns

VDD

VSS

90%

50%

10%

Vin

1/f

50% DUTY CYCLE

*Inverted output on MC14077B only.

Figure 2. Switching Time Test Circuit and Waveforms

VDD

CL

20 ns

VSS

90%

OUTPUT

#

*

20 ns

VOH

VOL

VDD

tTHL tTLH

50%

10%

90%

50%

10%

tPLH

tPHL

INPUT

*Inverted output on MC14077B only.

PULSE

GENERATOR

#Connect unused input to VDD for MC14070B, to VSS for MC14077B.

MC14070B

QUAD Exclusive OR

Gate

MC14077B

QUAD Exclusive NOR

Gate

13

11

12

9

8

6

5

2

1

10

4

3

13

12

9

8

6

5

2

1

11

10

4

3

VDD = PIN 14

VSS = PIN 7

(BOTH DEVICES)

MC14070B, MC14077B

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3

ORDERING INFORMATION

Device Package Shipping†

MC14070BCPG PDIP−14

(Pb−Free) 500 Units / Rail

MC14070BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14070BDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC14070BFELG

SOEIAJ−14

(Pb−Free) 2000 / Tape & Reel

MC14077BCPG PDIP−14

(Pb−Free) 500 Units / Rail

MC14077BDG

SOIC−14

(Pb−Free) 55 Units / Rail

MC14077BDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC14077BFELG

SOEIAJ−14

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14070B, MC14077B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 2)

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎÎ

0

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎ

5.0

10

15

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎ

5.0

10

15

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎ

5.0

10

15

ÎÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎ

5.0

10

15

ÎÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎ

15

ÎÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎÎ

±0.00001

ÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎ

±1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

—

ÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎ

7.5

15

30

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 mA/kHz) f + IDD

IT = (0.6 mA/kHz) f + IDD

IT = (0.9 mA/kHz) f + IDD

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Times (Note 3)

(CL = 50 pF)

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎ

200

100

80

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Times (Note 3)

(CL = 50 pF)

tPLH, tPHL = (0.90 ns/pF) CL + 130 ns

tPLH, tPHL = (0.36 ns/pF) CL + 57 ns

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

ÎÎÎÎ

tPLH,

tPHL

ÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

175

75

55

ÎÎÎ

350

150

110

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

ns

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14070B, MC14077B

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5

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14070B, MC14077B

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6

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M

_

S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14070B, MC14077B

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7

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14070B/D

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