DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
INT
A1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
GND
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
24 23 22 21 20
7 8 9 10 11
1
2
3
4
5
6
18
17
16
15
14
13
RGE PACKAGE
(TOP VIEW)
A1
INT
P10
P11 SDA
P06
P07
GND VCC
19
SCL
12
P12
P00
P01
P02
P03
P04
P05
A0
P17
P16
P15
P14
P13
RESET
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
REMOTE 16-BIT I
2
C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
Check for Samples: PCA9539
1FEATURES
• Low Standby-Current Consumption of • Address by Two Hardware Address Pins for
1mA Max Use of up to Four Devices
• I2C to Parallel Port Expander • Latched Outputs With High-Current Drive
Capability for Directly Driving LEDs
• Open-Drain Active-Low Interrupt Output • Latch-Up Performance Exceeds 100 mA Per
• Active-Low Reset Input JESD 78, Class II
• 5-V Tolerant I/O Ports • ESD Protection Exceeds JESD 22
• Compatible With Most Microcontrollers – 2000-V Human-Body Model (A114-A)
• 400-kHz Fast I2C Bus – 1000-V Charged-Device Model (C101)
• Polarity Inversion Register
DESCRIPTION/ORDERING INFORMATION
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock
(SCL), serial data (SDA)].
The PCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register
can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the PCA9539 in the event of a time-out or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.
The PCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9539 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low
current consumption.
The PCA9539 is identical to the PCA9555, except for the removal of the internal I/O pullup resistor, which greatly
reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address
range.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices
to share the same I2C bus or SMBus.
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 2000 PCA9539DBR
SSOP – DB PCA9539
Tube of 60 PCA9539DB
QSOP – DBQ Reel of 2500 PCA9539DBQR PD9539
TVSOP – DGV Reel of 2000 PCA9539DGVR PD9539
Tube of 25 PCA9539DW
–40°C to 85°C SOIC – DW PCA9539
Reel of 2000 PCA9539DWR
Tube of 60 PCA9539PW
TSSOP – PW Reel of 2000 PCA9539PWR PD9539
Reel of 250 PCA9539PWT
QFN – RGE Reel of 3000 PCA9539RGER PD9539
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
TERMINAL FUNCTIONS
NO.
SOIC (DW),
SSOP (DB), NAME DESCRIPTION
QSOP (DBQ), QFN (RGE)
TSSOP (PW), AND
TVSOP (DGV)
1 22 INT Interrupt output. Connect to VCC through a pullup resistor.
2 23 A1 Address input. Connect directly to VCC or ground.
Active-low reset input. Connect to VCC through a pullup resistor if no active
3 24 RESET connection is used.
4 1 P00 P-port input/output. Push-pull design structure.
5 2 P01 P-port input/output. Push-pull design structure.
6 3 P02 P-port input/output. Push-pull design structure.
7 4 P03 P-port input/output. Push-pull design structure.
8 5 P04 P-port input/output. Push-pull design structure.
9 6 P05 P-port input/output. Push-pull design structure.
10 7 P06 P-port input/output. Push-pull design structure.
11 8 P07 P-port input/output. Push-pull design structure.
12 9 GND Ground
13 10 P10 P-port input/output. Push-pull design structure.
14 11 P11 P-port input/output. Push-pull design structure.
15 12 P12 P-port input/output. Push-pull design structure.
16 13 P13 P-port input/output. Push-pull design structure.
17 14 P14 P-port input/output. Push-pull design structure.
18 15 P15 P-port input/output. Push-pull design structure.
19 16 P16 P-port input/output. Push-pull design structure.
20 17 P17 P-port input/output. Push-pull design structure.
21 18 A0 Address input. Connect directly to VCC or ground.
22 19 SCL Serial clock bus. Connect to VCC through a pullup resistor.
23 20 SDA Serial data bus. Connect to VCC through a pullup resistor.
24 21 VCC Supply voltage
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22
I/O
Port P17−P10
Shift
Register 16 Bits
LP Filter
Interrupt
Logic
Input
Filter
23
Power-On
Reset Read Pulse
Write Pulse
PCA9539
3
2
21
1
24
12
GND
VCC
SDA
SCL
A1
A0
INT
I2C Bus
Control
P07−P00
RESET
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
B. All I/Os are set to inputs at reset.
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VCC
CLK
D Q
FF
Configuration
Register
Data From
Shift Register
Data From
Shift Register
Q
Write Configuration
Pulse
CLK
D Q
FF
Q
Write Pulse
Output Port
Register
Q1
Q2
GND
I/O Pin
Output Port
Register Data
CLK
D Q
FF
Q
Input Port
Register
Read Pulse
CLK
D Q
FF
Q
Polarity Inversion
Register
Write Polarity
Pulse
Input Port
Register Data
Polarity
Register Data
To INT
Data From
Shift Register
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
SIMPLIFIED SCHEMATIC OF P-PORT I/Os
(1) At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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Product Folder Link(s): PCA9539
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte
is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call
address.
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse. The address inputs (A0 and A1) of the slave device must not be
changed between the Start and Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
Figure 3. Acknowledgment on I2C Bus
Table 1. Interface Definition
BIT
BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address H H H L H A1 A0 R/W
P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00
P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
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1 1 1 0 A1 A0
Slave Address R/W
Fixed Programmable
1
0 0 0 B2 B1 B000
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
Device Address
Figure 4 shows the address byte of the PCA9539.
Figure 4. PCA9539 Address
Table 2. Address Reference
INPUTS I2C BUS SLAVE ADDRESS
A1 A0
L L 116 (decimal), 74 (hexadecimal)
L H 117 (decimal), 75 (hexadecimal)
H L 118 (decimal), 76 (hexadecimal)
H H 119 (decimal), 77 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9539. Three bits of this data byte state the operation (read or write) and
the internal register (input, output, Polarity Inversion or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 5. Control Register Bits
Table 3. Command Byte
CONTROL REGISTER BITS COMMAND POWER-UP
REGISTER PROTOCOL
BYTE (HEX) DEFAULT
B2 B1 B0
0 0 0 0x00 Input Port 0 Read byte xxxx xxxx
0 0 1 0x01 Input Port 1 Read byte xxxx xxxx
0 1 0 0x02 Output Port 0 Read/write byte 1111 1111
0 1 1 0x03 Output Port 1 Read/write byte 1111 1111
1 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 0000
1 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 0000
1 1 0 0x06 Configuration Port 0 Read/write byte 1111 1111
1 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111
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PCA9539
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SCPS130F –AUGUST 2005–REVISED JANUARY 2011
Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to
these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register will be accessed next.
Table 4. Registers 0 and 1 (Input Port Registers)
Bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default XXXXXXXX
Bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default XXXXXXXX
The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 5. Registers 2 and 3 (Output Port Registers)
Bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 11111111
Bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 11111111
The Polarity Inversion registers (registers 4 and 5) allow Polarity Inversion of pins defined as inputs by the
Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Table 6. Registers 4 and 5 (Polarity Inversion Registers)
Bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this
register is cleared to 0, the corresponding port pin is enabled as an output.
Table 7. Registers 6 and 7 (Configuration Registers)
Bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9539 in a reset condition until
VCC has reached VPOR. At that point, the reset condition is released and the PCA9539 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
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SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The PCA9539 registers and
I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to VCC, if no active connection is used.
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and PCA9539 through write and read commands.
Writes
Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are Input
Ports, Output Ports, Polarity Inversion ports, and Configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent
to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
Figure 6. Write to Output Port Registers
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Product Folder Link(s): PCA9539
1 0 1 A1 A01 11 0 1 A1 A01 1S 0 A A A
R/W
A
PNA
S
R/W
1 MSB LSB
MSB LSB
Slave Address Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master
transmitter becomes master
receiver, and slave receiver
becomes slave transmitter.
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
Figure 7. Write to Configuration Registers
Reads
The bus master first must send the PCA9539 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9539 (see Figure 8 through Figure 10).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Figure 8. Read From Register
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Product Folder Link(s): PCA9539
123456789
S11101 A1 A0 1 A 7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 A
I1.x
7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 1
I1.x
P
R/W
SCL
SDA
INT
tir
tiv
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master No Acknowledge
From Master
123456789
S 1 1 1 0 1 A1 A0 1 A A
I0.x
A
I1.x
A
I0.x
1
I1.x
P
R/W
SCL
SDA
INT
tir
tiv
tph
00 10 03 12
tps
tph tps
11 12
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Data 02Data 01Data 00 Data 03
DataDataData 10
Acknowledge
From Slave Acknowledge
From Master
Acknowledge
From Master Acknowledge
From Master
No Acknowledge
From Master
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
<br/>
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 10. Read Input Port Register, Scenario 2
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PCA9539
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SCPS130F –AUGUST 2005–REVISED JANUARY 2011
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6 V
VIInput voltage range(2) –0.5 6 V
VOOutput voltage range(2) –0.5 6 V
IIK Input clamp current VI< 0 –20 mA
IOK Output clamp current VO< 0 –20 mA
IIOK Input/output clamp current VO< 0 or VO> VCC ±20 mA
IOL Continuous output low current VO= 0 to VCC 50 mA
IOH Continuous output high current VO= 0 to VCC –50 mA
Continuous current through GND –250
ICC mA
Continuous current through VCC 160
DB package 63
DBQ package 61
DGV package 86
qJA Package thermal impedance, junction to free air(3) °C/W
DW package 46
PW package 88
RGE package 45
qJP Package thermal impedance, junction to pad RGE package 1.5 °C/W
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
SCL, SDA 0.7 × VCC 5.5
VIH High-level input voltage V
A0, A1, RESET, P07–P00, P17–P10 0.7 × VCC 5.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
A0, A1, RESET, P07–P00, P17–P10 –0.5 0.3 × VCC
IOH High-level output current P07–P00, P17–P10 –10 mA
IOL Low-level output current P07–P00, P17–P00 25 mA
TAOperating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VIK Input diode clamp voltage II= –18 mA 2.3 V to 5.5 V –1.2 V
VPOR Power-on reset voltage VI= VCC or GND, IO= 0 VPOR 1.5 1.65 V
2.3 V 1.8
IOH = –8 mA 3 V 2.6
4.75 V 4.1
VOH P-port high-level output voltage(2) V
2.3 V 1.7
IOH = –10 mA 3 V 2.5
4.75 V 4
SDA VOL = 0.4 V 3
VOL = 0.5 V 8 20
IOL P port(3) 2.3 V to 5.5 V mA
VOL = 0.7 V 10 24
INT VOL = 0.4 V 3
SCL, SDA ±1
IIVI= VCC or GND 2.3 V to 5.5 V mA
A0, A1, RESET ±1
IIH P port VI= VCC 2.3 V to 5.5 V 1 mA
IIL P port VI= GND 2.3 V to 5.5 V –1 mA
5.5 V 100 200
VI= VCC or GND, IO= 0,
Operating mode 3.6 V 30 75
I/O = inputs, fSCL = 400 kHz 2.7 V 20 50
ICC mA
5.5 V 0.5 1
VI= GND, IO= 0, I/O = inputs,
Standby mode 3.6 V 0.4 0.9
fSCL = 0 kHz 2.7 V 0.25 0.8
One input at VCC – 0.6 V,
ΔICC Additional current in standby mode 2.3 V to 5.5 V 200 mA
Other inputs at VCC or GND
CiSCL VI= VCC or GND 2.3 V to 5.5 V 3 7 pF
SDA 3 7
Cio VIO = VCC or GND 2.3 V to 5.5 V pF
P port 3.7 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA= 25°C.
(2) Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07–P00 and P17–P10) must be limited to a maximum
current of 100 mA, for a device total of 200 mA.
(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10).
14 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11)MIN MAX UNIT
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 ms
tscl I2C clock low time 1.3 ms
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 20 + 0.1Cb(1) 300 ns
ticf I2C input fall time 20 + 0.1Cb(1) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 20 + 0.1Cb(1) 300 ns
tbuf I2C bus free time between Stop and Start 1.3 ms
tsts I2C Start or repeated Start condition setup 0.6 ms
tsth I2C Start or repeated Start condition hold 0.6 ms
tsps I2C Stop condition setup 0.6 ms
tvd(data) Valid-data time SCL low to SDA output valid 50 ns
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low 0.1 0.9 ms
CbI2C bus capacitive load 400 pF
(1) Cb= total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14)MIN MAX UNIT
tWReset pulse duration 6 ns
tREC Reset recovery time 0 ns
tRESET Time to reset 400 ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 12 and Figure 13)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tiv Interrupt valid time P port INT 4 ms
tir Interrupt reset delay time SCL INT 4 ms
tpv Output data valid SCL P port 200 ns
tps Input data setup time P port SCL 150 ns
tph Input data hold time P port SCL 1 ms
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCA9539
0
5
10
15
20
25
30
35
40
45
50
55
-50 -25 0 25 50 75 100
TA– Free -Air Te mpe rature – °C
ICC – Supply Current – µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os Unloaded
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
ICC – Supply Current – µA
fSCL = 400 kHz
I/Os Unloaded
0
5
10
15
20
25
30
-50 -25 0 25 50 75 100
TA– Free -Air Tem perature – °C
ICC – Supply Current – nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 125°C
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 125°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA– Free -Air Temperature – °C
VOL – Output Low Voltage – mV
VCC = 5 V, ISINK = 10 m A
VCC = 2.5 V, ISINK = 10 m A
VCC = 2.5 V, ISINK = 1 m A
VCC = 5 V, ISINK = 1 m A
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
TA= 25°C (unless otherwise noted)
SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENT
vs vs vs
TEMPERATURE TEMPERATURE SUPPLY VOLTAGE
I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENT
vs vs vs
OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
I/O OUTPUT LOW VOLTAGE I/O SOURCE CURRENT I/O SOURCE CURRENT
vs vs vs
TEMPERATURE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE
16 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 125°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA– Free -Air Temperature – °C
VOH – Output High Voltage – mV
VCC = 5 V, IOL = 10 m A
VCC = 2.5 V, IOL = 10 m A
0
25
50
75
100
125
150
175
200
225
250
275
300
-50 -25 0 25 50 75 100
TA– Free -Air Temperature – °C
VOH – Output High Voltage – mV
VCC = 5 V, IOL = 10 m A
VCC = 2.5 V, IOL = 10 m A
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
TA= 25°C (unless otherwise noted)
I/O SOURCE CURRENT I/O HIGH VOLTAGE OUTPUT HIGH VOLTAGE
vs vs vs
OUTPUT HIGH VOLTAGE TEMPERATURE SUPPLY VOLTAGE
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PCA9539
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. I2C Interface Load Circuit and Voltage Waveforms
18 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
A
A
A
A
S 1 1 1 0 A11 A0 1 Data 1 1 PData 2
Start
Condition 8 Bits
(One Data Byte)
From Port Data From PortSlave Address R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 2
INT
Data
Into
Port
B
B
A
A
Pn INT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PCA9539
P0 A 0.7 × VCC
0.3 × VCC
SCL P3
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
(see Note B)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
WRITE MODE (R/W = 0)
P0 A 0.7 × VCC
0.3 × VCC
SCL P3
0.7 × VCC
0.3 × VCC
tps tph
READ MODE (R/W = 1)
DUT
CL = 50 pF
(see Note A)
P-PORT LOAD CONFIGURATION
Pn 2 × VCC
500 W
500 W
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 13. P-Port Load Circuit and Voltage Waveforms
20 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
0.3 y VCC
VCC/2
tRESET
Pn
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
DUT SDA
P-PORT LOAD CONFIGURATION
VCC/2
tRESET
DUT
CL = 50 pF
(see Note A)
Pn 2 × VCC
500 W
500 W
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
E. All parameters and waveforms are not applicable to all devices.
Figure 14. Reset Load Circuits and Voltage Waveforms
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PCA9539
P00
P01
P02
P03
P04
P05
A1
A0
A
B
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
VCC
VCC
VCC
(5 V)
Controlled Switch
(e.g., CBT Device)
GND INT
SDA
SCL
10 kW10 kW10 kW10 kW2 kW
INT
Subsystem 1
(e.g., Temperature
Sensor)
Subsystem 2
(e.g., Counter)
PCA9539
SDA
SCL
INT
GND
Keypad ALARM
RESET
ENABLE
Subsystem 3
(e.g., Alarm)
Master
Controller
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
22
23
1
2
21
12
24 100 kW
100 kW100 kW
RESET
3
VCC
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
APPLICATION INFORMATION
Figure 15 shows an application in which the PCA9539 can be used.
A. Device address is configured as 1110100 for this example.
B. P00, P02, and P03 are configured as outputs.
C. P01 and P04 to P17 are configured as inputs.
D. Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
Figure 15. Typical Application
22 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
VCC
VCC
LED
Pn
100 kW
VCC
3.3 V 5 V
LED
Pn
VCC
Ramp-Up Re-Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC_RT VCC_RT
VCC_FT
VCC_TRR_GND
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
Minimizing ICC When I/O Is Used to Control LED
When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 15).
Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For
battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the
LED is off, to minimize current consumption.
Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional
supply-current consumption when the LED is off.
Figure 16. High-Value Resistor in Parallel With LED
Figure 17. Device Supplied by Lower Voltage
Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9539 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 18 and Figure 19.
Figure 18. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): PCA9539
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VIN drops below POR levels
VCC_RT
VCC_FT
VCC_TRR_VPOR50
VCC
Time
VCC_GH
VCC_GW
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 8 specifies the performance of the power-on reset feature for PCA9539 for both types of power-on reset.
Table 8. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1)
PARAMETER MIN TYP MAX UNIT
VCC_FT Fall rate See Figure 18 1 100 ms
VCC_RT Rise rate See Figure 18 0.01 100 ms
VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 18 0.001 ms
VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 19 0.001 ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH See Figure 20 1.2 V
disruption when VCCX_GW = 1 ms
Glitch width that will not cause a functional disruption when
VCC_GW See Figure 20 ms
VCCX_GH = 0.5 × VCCx
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on rising VCC 1.033 1.428 V
(1) TA= –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 20 and Table 8 provide more
information on how to measure these specifications.
Figure 20. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 21 and Table 8 provide more details on this specification.
24 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
VCC
VPOR
VPORF
Time
POR
Time
PCA9539
www.ti.com
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
Figure 21. VPOR
Interrupt Requirements
The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input
register is read or all inputs return to the last read values. INT is also de-asserted when both of the following
occur:
• The last I2C command byte (register pointer) written was 00h. This generally means the last operation with
the device was a read of the input register, but the command byte may have been written with 00h without
ever going on to read the Input register.
• Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high. This occurs
when reading any other valid device on the bus.
In order to prevent INT from de-asserting when another device is read on the I2C bus, the user needs to change
the command byte to something other than 00 (hex) after a read operation to the device.
RESET Requirements
For proper operation of the RESET feature, it is essential that the RESET pin is at the same or lower voltage
than the VCC pin. If RESET is at a higher voltage than VCC, current drains from the RESET pin into VCC and pulls
VCC above its voltage level.
Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): PCA9539
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011
www.ti.com
REVISION HISTORY
Changes from Revision E (May 2008) to Revision F Page
• Changed reel quantity to 2000 from 1200 for the PCA9539PWR part. ................................................................................ 2
26 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Product Folder Link(s): PCA9539
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9539DB ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DBG4 ACTIVE SSOP DB 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9539DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9539DBR ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539PW NRND TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539PWE4 NRND TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539PWG4 NRND TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539PWR NRND TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539PWRE4 NRND TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9539PWRG4 NRND TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9539RGER ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9539RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9539DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PCA9539DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1
PCA9539DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9539DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PCA9539PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PCA9539RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9539DBQR SSOP DBQ 24 2500 367.0 367.0 38.0
PCA9539DBR SSOP DB 24 2000 367.0 367.0 38.0
PCA9539DGVR TVSOP DGV 24 2000 367.0 367.0 35.0
PCA9539DWR SOIC DW 24 2000 367.0 367.0 45.0
PCA9539PWR TSSOP PW 24 2000 367.0 367.0 38.0
PCA9539RGER VQFN RGE 24 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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