PCA9539PW - Philips Semiconductors / NXP Semiconductors

Philips

Semiconductors

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

Product data sheet

Supersedes data of 2004 Aug 27 2004 Sep 30

INTEGRATED CIRCUITS

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30

FEATURES

•16-bit I2C GPIO with interrupt and reset

•Operating power supply voltage range of 2.3 V–5.5 V

•5 V tolerant I/Os

•Polarity inversion register

•Active LOW interrupt output

•Active LOW reset input

•Low stand-by current

•Noise filter on SCL/SDA inputs

•No glitch on power-up

•Internal power-on reset

•16 I/O pins which default to 16 inputs

•0 kHz to 400 kHz clock frequency

•ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101

•Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

•Offered in three dif ferent packages: SO24, TSSOP24, and

HVQFN24

DESCRIPTION

The PCA9539 is a 24-pin CMOS device that provide 16 bits of

General Purpose parallel Input/Output (GPIO) expansion with

interrupt and reset for I2C/SMBus applications and was developed

to enhance the Philips family of I2C I/O expanders. I/O expanders

provides a simple solution when additional I/O is needed for ACPI

power switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9539 consists of two 8-bit Configuration (Input or Output

selection); Input, Output and Polarity inversion (Active HIGH or

Active LOW operation) registers. The system master can enable the

I/Os as either inputs or outputs by writing to the I/O configuration

bits. The data for each Input or Output is kept in the corresponding

Input or Output register. The polarity of the read register can be

inverted with the Polarity Inversion Register. All registers can be

read by the system master.

The PCA9539 is identical to the PCA9555 except for the removal of

the internal I/O pull-up resistor which greatly reduces power

consumption when the I/Os are held LOW, repleacement of A2 with

RESET and different address range.

The PCA9539 open-drain interrupt output is activated when any

input state differs from its corresponding input port register state and

is used to indicate to the system master that an input state has

changed. The power-on reset sets the registers to their default

values and initializes the device state machine. The RESET pin

causes the same reset/sonfiguration to occur without depowering

the device.

Two hardware pins (A0, A1) vary the fixed I2C address and allow up

to four devices to share the same I2C/SMBus.

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER

24-Pin Plastic SO –40 °C to +85 °C PCA9539D PCA9539D SOT137-1

24-Pin Plastic TSSOP –40 °C to +85 °C PCA9539PW PCA9539PW SOT355-1

24-Pin Plastic HVQFN –40 °C to +85 °C PCA9539BS 9539 SOT616-1

Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.

I2C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30 3

PIN CONFIGURATION — SO, TSSOP

SW02200

12 13

INT

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

VDD

SDA

SCL

I/O1.7

I/O1.6

I/O1.5

I/O1.3

I/O1.4

I/O1.2

I/O1.1

I/O1.0VSS

RESET

Figure 1. Pin configuration — SO, TSSOP

PIN CONFIGURATION —HVQFN

SW02201

TOP VIEW

I/O0.0 A0

613

12 19

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5 I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

I/O0.6

I/O0.7

I/O1.0

I/O1.1

I/O1.2

INT

SDA

SCL

VSS

RESET

Figure 2. Pin configuration — HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN NUMBER HVQFN

PIN NUMBER SYMBOL FUNCTION

1 22 INT Interrupt output (open drain)

2 23 A1 Address input 1

3 24 RESET Active LOW reset input

4–11 1–8 I/O0.0–I/O0.7 I/O0.0 to I/O0.7

12 9 VSS Supply ground

13–20 10–17 I/O1.0–I/O1.7 I/O1.0 to I/O1.7

21 18 A0 Address input 0

22 19 SCL Serial clock line

23 20 SDA Serial data line

24 21 VDD Supply voltage

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30 4

BLOCK DIAGRAM

POWER-ON

RESET

INPUT

FILTER

I2C/SMBUS

CONTROL

INPUT/

OUTPUT

PORTS

WRITE pulse

READ pulse

SCL

SDA

VDD

VSS

8-BIT

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

SW02202

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

8-BIT INPUT/

OUTPUT

PORTS

I/O1.0

I/O1.1

I/O1.2

I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

WRITE pulse

READ pulse

VCC

INT

FILTER

RESET

PCA9539

Figure 3. Block diagram

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30 5

SIMPLIFIED SCHEMATIC OF I/Os

WRITE PULSE

DATA FROM

SHIFT REGISTER

VDD

I/O PIN

VSS

WRITE CONFIGURATION

PULSE

INPUT PORT

POLARITY

INVERSION

OUTPUT

PORT

DATA FROM

SHIFT REGISTER

DATA FROM

SHIFT REGISTER

WRITE

POLARITY

PULSE

CONFIGURATION

OUTPUT PORT

INPUT PORT

POLARITY

READ PULSE

SU02203

TO INT

ESD PROTECTION DIODE

NOTE: At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high impedance input. The input voltage may be raised

above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on,

depending on the state of the Output Port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance path that exists between the

pin and either VDD or VSS.

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30 6

REGISTERS

Command Byte

Command Register

0Input port 0

1Input port 1

2Output port 0

3Output port 1

4Polarity inversion port 0

5Polarity inversion port 1

6Configuration port 0

7Configuration port 1

The command byte is the first byte to follow the address byte during

a write transmission. It is used as a pointer to determine which of the

following registers will be written or read.

Registers 0 and 1 — Input Port Registers

bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 IO.0

default X X X X X X X X

bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0

default X X X X X X X X

This register is an input-only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by Register 3. Writes to this register have no effect.

The default value ‘X’ is determined by the externally applied logic

level.

Registers 2 and 3 — Output Port Registers

bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0

default 11111111

bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0

default 11111111

This register is an output-only port. It reflects the outgoing logic

levels of the pins defined as outputs by Register 6 and 7. Bit values

in this register have no effect on pins defined as inputs. In turn,

reads from this register reflect the value that is in the flip-flop

controlling the output selection, NOT the actual pin value.

Registers 4 and 5 — Polarity Inversion Registers

bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

default 0 0 0 0 0 0 0 0

bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

default 0 0 0 0 0 0 0 0

This register allows the user to invert the polarity of the Input Port

Port data polarity is inverted. If a bit in this register is cleared (written

with a ‘0’), the Input Port data polarity is retained.

Registers 6 and 7 — Configuration Registers

bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

default 1 1 1 1 1 1 1 1

bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

default 1 1 1 1 1 1 1 1

This register configures the directions of the I/O pins. If a bit in this

as an input with high impedance output driver. If a bit in this register

is cleared (written with ‘0’), the corresponding port pin is enabled as

an output. At reset the device’s ports are inputs.

POWER-ON RESET

When power is applied to VDD, an internal power-on reset holds the

PCA9539 in a reset condition until VDD has reached VPOR. At that

point, the reset condition is released and the PCA9539 registers and

SMBus state machine will initialize to their default states. Therefore,

VDD must be lowered below 0.2 V to reset the device.

For a power reset cycle, VDD must be lowered below 0.2 V and then

restored to the operating voltage.

RESET Input

A reset can be accomplished by holding the RESET pin LOW for a

minimum of tW. The PCA9539 registers and SMBus/I2C state

machine will be held in their default state until the RESET input is

once again HIGH. This input typically requires a pull-up to VDD.

DEVICE ADDRESS

slave address

fixed programmable

R/W

11101 A0

SW02204

Figure 5. PCA9539 address

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

2004 Sep 30 7

BUS TRANSACTIONS

Writing to the port registers

Data is transmitted to the PCA9539 by sending the device address

and setting the least significant bit to a logic 0 (see Figure 5 for

device address). The command byte is sent after the address and

determines which register will receive the data following the

command byte.

The eight registers within the PCA9539 are configured to operate

as four register pairs. The four pairs are Input Ports, Output Ports,

Polarity Inversion Ports, and Configuration Ports. After sending data

to one register, the next data byte will be sent to the other register in

the pair (see Figures 6 and 7). For example, if the first byte is sent to

Output Port (register 3), then the next byte will be stored in Output

Port 0 (register 2). There is no limitation on the number of data bytes

sent in one write transmission. In this way, each 8-bit register may

be updated independently of the other registers.

Reading the port registers

In order to read data from the PCA9539, the bus master must first

send the PCA9539 address with the least significant bit set to a

logic 0 (see Figure 5 for device address). The command byte is sent

after the address and determines which register will be accessed.

After a restart, the device address is sent again but this time, the

least significant bit is set to a logic 1. Data from the register defined

by the command byte will then be sent by the PCA9539 (see

Figures 8 , 9, and 10). Data is clocked into the register on the falling

edge of the acknowledge clock pulse. After the first byte is read,

additional bytes may be read but the data will now reflect the

information in the other register in the pair. For example, if you read

Input Port 1, then the next byte read would be Input Port 0. There is

no limitation on the number of data bytes received in one read

transmission but the final byte received, the bus master must not

acknowledge the data.

Interrupt Output

The open-drain interrupt output is activated when one of the port

pins change state and the pin is configured as an input. The

interrupt is deactivated when the input returns to its previous state or

the input port register is read (see Figure 9). A pin configured as an

output cannot cause an interrupt. Since each 8-bit port is read

independently, the interrupt caused by Port 0 will not be cleared by a

read of Port 1 or the other way around.

Note that changing an I/O from an output to an input may cause a

false interrupt to occur if the state of the pin does not match the

contents of the Input Port register.

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

82004 Sep 30

SCL

WRITE TO

PORT

DATA OUT

FROM PORT 0

345678

SDA AA A

DATA 0

slave address data to port 0

start condition R/W acknowledge

from slave acknowledge

from slave

tpv

SW02205

00000001

command byte

0.7 0.0 DATA 11.7 1.0 A

data to port 1

S 1 1 1 0 1 A1 A0 0

DATA OUT

FROM PORT 1 DATA VALID

tpv

Figure 6. WRITE to output port registers

SCL 345678

SDA AA A

DATA 0

slave address data to register

start condition R/W acknowledge

from slave acknowledge

from slave

SU02206

00000011

command byte

MSB LSB DATA 1MSB LSB A

data to register

S 1 1 1 0 1 A1 A0 0

12345678912345678912345

Figure 7. WRITE to configuration registers

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

92004 Sep 30

1 0 1 A1 A01 11 0 1 A1 A01 1

S0A A A

COMMAND BYTE

acknowledge

from slave

R/W

acknowledge

from slave

PNA

acknowledge

from slave acknowledge

from master

SDATA

DATA

R/W first byte

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

last byte

SW02207

no acknowledge

from master

slave address

data from upper

or lower byte of

data from lower

or upper byte

of register

slave address

MSB LSB

NOTE: T ransfer can be stopped at any time by a STOP condition. Figure 8. READ from register

123456789

S11101A1A01A76543210A

I0.x

76543210A

I1.x

76543210A

I0.x

765432101

I1.x

R/W ACKNOWLEDGE

FROM SLAVE

SCL

SDA

ACKNOWLEDGE

FROM MASTER ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

tIR

tIV

SW02208

NOTES: T ransfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9. READ input port register — scenario 1

Philips Semiconductors Product data sheet

PCA9539

16-bit I2C and SMBus, low power I/O port

with interrupt and reset

102004 Sep 30

123456789

S11101A1A01A A

I0.x

I1.x

I0.x

I1.x

R/W ACKNOWLEDGE

FROM SLAVE

SCL

SDA

ACKNOWLEDGE

FROM MASTER ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

tIR

tIV

SW02209

tph

DATA 00 DATA 10 DATA 03 DATA 12

DATA 00 DATA 01 DATA 02 DATA 03

tps

tph tps

DATA 10 DATA 11 DATA 12

NOTES: T ransfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 10. READ input port register — scenario 2

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 11

TYPICAL APPLICATION

SW02094

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

VDD

(5 V)

VDD

SCL

SDA

INT

RESET

MASTER

CONTROLLER

GND

SCL

SDA

PCA9539

VSS

VDD

SUBSYSTEM 3

(e.g. alarm system)

SUBSYSTEM 2

(e.g. counter)

SUBSYSTEM 1

(e.g. temp sensor)

INT

VDD

ALARM

Controlled Switch

(e.g. CBT device)

ENABLE

10 kΩ10 kΩ10 kΩ2 kΩ

NOTE: Device address configured as 1110100 for this example

I/O0.0, I/O0.2, I/O0.3, configured as outputs

I/O0.1, I/O0.4, I/O0.5, configured as inputs

I/O0.6, I/O0.7, and I/O1.0 to I/O1.7 configured as inputs

10 kΩ

INT

I/O0.6

I/O0.7

I/O1.0

I/O1.1

I/O1.2

I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

10 DIGIT

NUMERIC

KEYPAD

RESET RESET

100 kΩ

(×3)

Figure 11. Typical application

Minimizing IDD when the I/O is used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 11. Since the LED acts as a

diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current, IDD, increases as VIN becomes lower than VDD and is

specified as ∆IDD in the DC characteristics table.

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or

equal to VDD when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when

the LED is off.

VDD

LEDx

LED 100 kΩ

SW02086

Figure 12. High value resistor in parallel with the LED

VDD

3.3 V

LEDx

LED

SW02087

5 V

Figure 13. Device supplied by a lower voltage

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 12

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN MAX UNIT

VDD Supply voltage –0.5 6.0 V

VI/O DC input current on an I/O VSS – 0.5 6 V

II/O DC output current on an I/O —± 50 mA

IIDC input current —± 20 mA

IDD Supply current — 160 mA

ISS Supply current — 200 mA

Ptot Total power dissipation — 200 mW

Tstg Storage temperature range –65 +150 °C

Tamb Operating ambient temperature –40 +85 °C

TJ(MAX) Maximum junction temperature — +125 °C

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 13

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under “

Handling MOS devices

”.

DC CHARACTERISTICS

VDD = 2.3 V to 5.5 V ; V SS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Supplies

VDD Supply voltage 2.3 — 5.5 V

IDD Supply current Operating mode; VDD = 5.5 V ; no load;

fSCL = 100 kHz; I/O = inputs — 135 200 µA

Istbl Standby current Standby mode; VDD = 5.5 V ; no load;

VI = VSS; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA

Istbh Standby current Standby mode; VDD = 5.5 V ; no load;

VI = VDD; fSCL = 0 kHz; I/O = inputs — 0.25 1 µA

VPOR Power-on reset voltage (Note 1) No load; VI = VDD or VSS — 1.5 1.65 V

input SCL; input/output SDA

VIL LOW-level input voltage –0.5 — 0.3VDD V

VIH HIGH-level input voltage 0.7VDD — 5.5 V

IOL LOW-level output current VOL = 0.4 V 3 tbd — mA

ILLeakage current VI = VDD = VSS –1 — +1 µA

CIInput capacitance VI = VSS — 6 10 pF

I/Os

VIL LOW-level input voltage –0.5 — 0.3VDD V

VIH HIGH-level input voltage 0.7VDD — 5.5 V

LOW level out

ut current

VOL = 0.5 V ; VDD = 2.3 V to 5.5 V; Note 2 8 8–20 — mA

LOW

rrent

VOL = 0.7 V ; VDD = 2.3 V to 5.5 V; Note 2 10 10–24 — mA

IOH = –8 mA; VDD = 2.3 V ; Note 3 1.8 — — V

IOH = –10 mA; VDD = 2.3 V ; Note 3 1.7 — — V

HIGH level out

ut voltage

IOH = –8 mA; VDD = 3.0 V ; Note 3 2.6 — — V

HIGH

oltage

IOH = –10 mA; VDD = 3.0 V ; Note 3 2.5 — — V

IOH = –8 mA; VDD = 4.75 V ; Note 3 4.1 — — V

IOH = –10 mA; VDD = 4.75 V ; Note 3 4.0 — — V

IIH Input leakage current VDD = 5.5 V ; VI = VDD — — 1 µA

IIL Input leakage current VDD = 5.5 V ; VI = VSS — — –1 µA

CIInput capacitance — 3.7 5 pF

COOutput capacitance — 3.7 5 pF

Interrupt INT

IOL LOW-level output current VOL = 0.4 V 3 tbd — mA

Select Inputs A0, A1, and RESET

VIL LOW-level input voltage –0.5 — 0.3VDD V

VIH HIGH-level input voltage 0.7VDD — 5.5 V

ILI Input leakage current –1 — 1 µA

NOTES:

1. VDD must be lowered to 0.2 V in order to reset part.

2. Each I/O must be externally limited to a maximum of 25 mA and each octal (I/O0.0 to I/O0.7, and I/O1.0 to I/O1.7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

3. The total current sourced by all I/Os must be limited to 160 mA (80 mA for I/O 0.0 through 0.7 and 80 mA for I/O 1.0 through 1.7).

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 14

AC CHARACTERISTICS

SYMBOL PARAMETER STANDARD MODE

I2C-bus FAST MODE

I2C-bus UNITS

MIN MAX MIN MAX

fSCL Operating frequency 0 100 0 400 kHz

tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs

tHD;STA Hold time after (repeated) ST ART condition 4.0 — 0.6 — µs

tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs

tSU;STO Set-up time for ST OP condition 4.0 — 0.6 — µs

tVD;ACK Valid time of ACK condition20.3 3.45 0.1 0.9 µs

tHD;DAT Data in hold time 0 — 0 — ns

tVD;DAT Data out valid time3300 — 50 — ns

tSU;DAT Data set-up time 250 — 100 — ns

tLOW Clock LOW period 4.7 — 1.3 — µs

tHIGH Clock HIGH period 4.0 — 0.6 — µs

tFClock/Data fall time — 300 20 + 0.1Cb 1300 ns

tRClock/Data rise time — 1000 20 + 0.1Cb 1300 ns

tSP Pulse width of spikes that must be suppressed by the input filters — 50 — 50 ns

Port Timing

tPV Output data valid — 200 — 200 ns

tPS Input data set-up time 150 — 150 — ns

tPH Input data hold time 1 — 1 — µs

Interrupt Timing

tIV Interrupt valid — 4 — 4 µs

tIR Interrupt reset — 4 — 4 µs

RESET

tWReset pulse width 4 — 4 — ns

tREC Reset recovery time 0 — 0 — ns

tRESET5,6 Time to reset 400 — 400 — ns

NOTES:

1. Cb = total capacitance of one bus line in pF.

2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

4. tPV measured from 0.7VDD on SCL to 50% I/O output.

5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.

6. Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.

SDA

SCL

SU01469

tHD;STA

tLOW tR

tHD;DAT

tSU;DAT

tHIGH

tSU;STA SR

tHD;STA tSP

tSU;STD P

tRtBUF

Figure 14. Definition of timing

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 15

SDA

SCL

SW02340

tRESET

50%

30%

50% 50%

50%

tREC tW

RESET

I/Ox I/O configured as inputs

ACK OR READ CYCLESTART

Figure 15. Definition of RESET timing

SCL

SW02329

210AP

70 %

30 %

SDA

INPUT 50 %

INT

tPS tPH

tIV tIR

Figure 16. Expanded view of Read input port register

SCL

SW02330

210AP

70 %

30 %

SDA

OUTPUT 50 %

tPV

Figure 17. Expanded view of Write to output port register

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 16

PROTOCOL

SCL

SDA

tHD;STA tSU;DAT tHD;DAT tVD;DAT

tBUF

tSU;STA tLOW tHIGH 1 / f SCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

tVD;ACK

SW02210

STOP

CONDITION

(S)

BIT 0

(R/W)ACKNOWLEDGE

(A)

tSU;STO

Figure 18. I2C-bus timing diagram; rise and fall times refer to VIL and VIH

TEST CIRCUITS

PULSE

GENERATOR

VIVO

50 pF

VDD

DEFINITIONS

RL = Load resistor.

CL = Load capacitance includes jig and probe capacitance

RT = Termination resistance should be equal to the output

impedance ZO of the pulse generators.

VDD

Open

D.U.T.

RL = 500 Ω

SW02181

Figure 19. Test circuitry for switching times

CL = 50 pF 500 Ω

Load Circuit

TEST S1

tpv 2 VDD

SA00652

500 Ω

From Output

Under Test

S1 2VDD

Open

GND

Figure 20. Test circuit

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 17

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 18

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 19

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;

body 4 x 4 x 0.85 mm SOT616-1

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 20

REVISION HISTORY

Rev Date Description

_2 20040930 Product data sheet (9397 750 14048). Supersedes data of 2004 Aug 27 (9397 750 12898).

Modifications:

•Section “Registers 0 and 1—Input Port Registers” on page 6:

–add table and second paragraph

•Figure 11 on page 11: resistor values modified

•“DC Characteristics” table on page 13:

–sub-section “I/Os”:

change VIL (max) from 0.8 V to 0.3VDD

change VIH (min) from 2.0 V to 0.7VDD

–sub-section “Select inputs A0, A1, and RESET:

change VIL (max) from 0.8 V to 0.3VDD

change VIH (min) from 2.0 V to 0.7VDD

•Figure 15 on page 15 modified.

_1 20040827 Product data sheet (9397 750 12898).

Philips Semiconductors Product data sheet

PCA953916-bit I2C and SMBus, low power I/O port with interrupt

2004 Sep 30 21

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent

to use the components in the I2C system provided the system conforms to the

I2C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys

no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,

Contact information

For additional information please visit

http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

 Koninklijke Philips Electronics N.V. 2004

Date of release: 09-04

Document order number: 9397 750 14048

Philips

Semiconductors

Data sheet status[1]

Objective data sheet

Preliminary data sheet

Product data sheet

Product

status[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III