This is information on a product in full production.
January 2017 DocID027240 Rev 2 1/42
M24512-DRE
512-Kbit serial I²C bus EEPROM - 105°C operation
Datasheet - production data
Features
•Compatible with all I2C bus modes
–1 MHz
– 400 kHz
– 100 kHz
•Memory array
– 512 Kbits (64 Kbytes) of EEPROM
– Page size: 128 bytes
– Additional Write lockable page
(Identification page)
•Extended temperature and voltage range
– -40 °C to 105 °C; 1.7 V to 5.5 V
•Schmitt trigger inputs for noise filtering
•Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
•Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 900 k Write cycles at 105 °C
•Data retention
– more than 50 years at 105 °C
– 200 years at 55 °C
•ESD Protection (Human Body Model)
– 4000 V
•Packages
– RoHS compliant and halogen-free
(ECOPACK2®)
SO8 (MN)
TSSOP8 (DW)
WFDFPN8 (MF)
DFN8 - 2 x 3 mm
169 mil width
150 mil width
www.st.com
Contents M24512-DRE
2/42 DocID027240 Rev 2
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DocID027240 Rev 2 3/42
M24512-DRE Contents
5 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.3 WFDFPN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
List of tables M24512-DRE
4/42 DocID027240 Rev 2
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Significant address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID027240 Rev 2 5/42
M24512-DRE List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C
bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 35
Figure 15. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Description M24512-DRE
6/42 DocID027240 Rev 2
1 Description
The M24512-DRE is a 512-Kbit serial EEPROM device operating up to 105 °C. The
M24512-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2.
The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.
The memory array is based on advanced true EEPROM technology (electrically erasable
programmable memory). The M24512-DRE is a byte-alterable memory (64 K × 8 bits)
organized as 512 pages of 128 bytes in which the data integrity is significantly improved
with an embedded Error Correction Code logic.
The M24512-DRE offers an additional Identification Page (128 bytes) in which the ST
device identification can be read. This page can also be used to store sensitive application
parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
-36
7#
#ONTROLLOGIC (IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
)DENTIFICATIONPAGE
%
%
3#,
3$!
DocID027240 Rev 2 7/42
M24512-DRE Description
Figure 2. 8-pin package connection
1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Table 1. Signal names
Signal name Function Direction
E2, E1, E0 Chip enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage -
VSS Ground -
$,I
6'$966
6&/
:&(
( 9&&
(
Signal description M24512-DRE
8/42 DocID027240 Rev 2
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on this input is used to strobe the data available on SDA(in) and to output
the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected between SDA and VCC (Figure 10 and Figure 11
indicate how to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0).
Figure 3. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
!I
6##
-XXX
633
%I
6##
-XXX
633
%I
DocID027240 Rev 2 9/42
M24512-DRE Signal description
2.5 VSS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
VCC is the supply voltage pin.
Device operation M24512-DRE
10/42 DocID027240 Rev 2
3 Device operation
The device supports the I2C protocol (see Figure 4).
The I2C bus is controlled by the bus master and the device is always a slave in all
communications.
The device (bus master or a slave) that sends data on to the bus is defined as a transmitter;
the device (bus master or a slave) is defined as a receiver when reading the data.
Figure 4. I2C bus protocol
3#,
3$!
3#,
3$!
3$!
34!24
#ONDITION
3$!
)NPUT
3$!
#HANGE
!)"
34/0
#ONDITION
-3" !#+
34!24
#ONDITION
3#,
-3" !#+
34/0
#ONDITION
DocID027240 Rev 2 11/42
M24512-DRE Device operation
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
3.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
Device operation M24512-DRE
12/42 DocID027240 Rev 2
3.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2.
The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable
address (E2, E1, E0). A device select code handling any value other than 1010b (to select
the memory) or 1011b (to select the Identification page) is not acknowledged by the memory
device.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the memory device only responds if the Chip Enable Address is the same as the
value decoded on the E2, E1, E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Once the memory device has acknowledged the device select code (Table 2), the memory
device waits for the master to send two address bytes (most significant address byte sent
first, followed by the least significant address byte (Table 3). The memory device responds
to each address byte with an acknowledge bit.
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)
2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.
RW
b7 b6 b5 b4 b3 b2 b1 b0
When accessing the
memory 1 0 1 0 E2 E1 E0 RW
When accessing the
Identification page 1 0 1 1 E2 E1 E0 RW
DocID027240 Rev 2 13/42
M24512-DRE Device operation
Note: A: significant address bit.
X: bit is Don’t Care.
Table 3. Significant address bits
Memory
(Device type identifier = 1010b)
Identification page
(Device type identifier = 1011b)
Random
Address Read Write
Read
Identification
page
Write
Identification
page
Lock
Identification
page
Read lock
status
Most
significant
address bits
b15A15A15XXX X
b14A14A14XXX X
b13A13A13XXX X
b12A12A12XXX X
b11A11A11XXX X
b10 A10 A10 X 0 1 0
b9 A9 A9 X X X X
b8 A8 A8 X X X X
Address byte
b7 A7 A7 X X X X
b6 A6 A6 A6 A6 X X
b5 A5 A5 A5 A5 X X
b4 A4 A4 A4 A4 X X
b3 A3 A3 A3 A3 X X
b2 A2 A2 A2 A2 X X
b1 A1 A1 A1 A1 X X
b0 A0 A0 A0 A0 X X
Device operation M24512-DRE
14/42 DocID027240 Rev 2
3.6 Identification page
The M24512-DRE offers an Identification Page (128 bytes) in addition to the 512-Kbit
memory.
The Identification page contains two fields:
•Device identification code: the first three bytes are programmed by STMicroelectronics
with the Device identification code, as shown in Table 4.
•Application parameters: the bytes after the Device identification code are available for
application specific data.
Note: If the end application does not need to read the Device identification code, this field can be
overwritten and used to store application-specific data. Once the application-specific data
are written in the Identification page, the whole Identification page should be permanently
locked in Read-only mode.
The instructions Read, Write and Lock Identification Page are detailed in Section 4:
Instructions.
Table 4. Device identification code
Address in
Identification page Content Value
00h ST manufacturer code 20h
01h I2C family code E0h
02h Memory density code 10h (512-Kbit)
DocID027240 Rev 2 15/42
M24512-DRE Instructions
4 Instructions
4.1 Write operations
For a Write operation, the bus master sends a Start condition followed by a device select
code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and
waits for the master to send two address bytes (most significant address byte sent first,
followed by the least significant address byte (Table 3). The device responds to each
address byte with an acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
After the successful completion of an internal Write cycle (tW), the device internal address
counter is automatically incremented to point to the next byte after the last modified byte.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 6.
Instructions M24512-DRE
16/42 DocID027240 Rev 2
4.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the
addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 5.
Figure 5. Write mode sequences with WC = 0 (data write enabled)
3TOP
3TART
"YTE7RITE $EVSEL "YTEADDR "YTEADDR $ATAIN
7#
3TART
0AGE7RITE $EVSEL "YTEADDR "YTEADDR $ATAIN
7#
$ATAIN
!)D
0AGE7RITECONTgD
7#CONTgD
3TOP
$ATAIN.
!#+
27
!#+ !#+ !#+
!#+ !#+ !#+ !#+
27
!#+!#+
DocID027240 Rev 2 17/42
M24512-DRE Instructions
4.1.2 Page Write
The Page Write mode allows up to N(1) bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A7, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
Note: The bus master sends from 1 to N(1) bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte received by the device is
not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte
address counter is incremented. The transfer is terminated by the bus master generating a
Stop condition.
Figure 6. Write mode sequences with WC = 1 (data write inhibited)
1. N is the number of bytes in a page.
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Instructions M24512-DRE
18/42 DocID027240 Rev 2
4.1.3 Write Identification Page
The Identification Page (128 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•Device type identifier = 1011b
•Most significant address bits A15/A7 are don't care, except for address bit A10 which
must be “0”. Least significant address bits A6/A0 define the byte location inside the
Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
4.1.4 Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
•Device type identifier = 1011b
•Address bit A10 must be ‘1’; all other address bits are don't care
•The data byte must be equal to the binary value xxxx xx1x, where x is don't care
DocID027240 Rev 2 19/42
M24512-DRE Instructions
4.1.5 Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 7, is:
•Initial condition: a Write cycle is in progress.
•Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
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Instructions M24512-DRE
20/42 DocID027240 Rev 2
4.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
Figure 8. Read mode sequences
4.2.1 Random Address Read
The Random Address Read is a sequence composed of a truncated Write sequence (to
define a new address pointer value, see Table 3) followed by a current Read.
The Random Address Read sequence is therefore the sum of [Start + Device Select code
with R/W=0 + two address bytes] (without Stop condition, as shown in Figure 8) and [Start
condition + Device Select code with R/W=1]. The memory device acknowledges the
sequence and then outputs the contents of the addressed byte. To terminate the data
transfer, the bus master does not acknowledge the last data byte and then issues a Stop
condition.
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DocID027240 Rev 2 21/42
M24512-DRE Instructions
4.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte pointed by the internal address counter. The counter is then incremented.
The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without
acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the Identification page byte location, when accessing the memory, it is
safer to always use the Random Address Read instruction (this instruction loads the
address counter with the byte location to read in the memory) instead of the Current
Address Read instruction.
4.2.3 Sequential Read
A sequential Read can be used after a Current Address Read or a Random Address Read.
After a Read instruction, the device can continue to output the next byte(s) in sequence if
the bus master sends additional clock pulses and if the bus master does acknowledge each
transmitted data byte. To terminate the stream of bytes, the bus master must not
acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8.
The sequential read is controlled with the device internal address counter which is
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
4.2.4 Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The most significant address bits A15/A7
are don't care and the least significant address bits A6/A0 define the byte location inside the
Identification page. The number of bytes to read in the ID page must not exceed the page
boundary.
4.2.5 Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit after the data byte if the Identification page is
unlocked, otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
•Start: the truncated command is not executed because the Start condition resets the
device internal logic,
•Stop: the device is then set back into Standby mode by the Stop condition.
Instructions M24512-DRE
22/42 DocID027240 Rev 2
4.2.6 Acknowledge in Read mode
For all Read instructions, the device waits, after each byte sent out, for an acknowledgment
during the “9th bit” time. If the bus master does not send the Acknowledge (the master drives
SDA high during the 9th bit time), the device terminates the data transfer and enters its
Standby mode.
DocID027240 Rev 2 23/42
M24512-DRE Application design recommendations
5 Application design recommendations
5.1 Supply voltage
5.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 7).
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
5.1.2 Power-up conditions
When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to
the minimum VCC operating voltage defined in Table 7.
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC reaches the internal
threshold voltage (this threshold is defined in the DC characteristic Table 10 as VRES).
When VCC passes over the POR threshold, the device is reset and in the following state:
•in the Standby power mode
•deselected
As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)]
range (defined in Table 7), the device is ready for operation.
5.1.3 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 7), the device must be in Standby power mode (that
is after a STOP condition or after the completion of the Write cycle tW if an internal Write
cycle is in progress).
Application design recommendations M24512-DRE
24/42 DocID027240 Rev 2
5.2 Cycling with Error Correction Code (ECC)
The error correction code (ECC) is an internal logic function which is transparent for the I2C
communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes (1). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(1). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 6.
Example 1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example 2: maximum cycling limit reached with unequal byte cycling
Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million
cycles.
1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer
DocID027240 Rev 2 25/42
M24512-DRE Delivery state
6 Delivery state
The device is delivered as follows:
•The memory array is set to all 1s (each byte = FFh).
•Identification page: the first three bytes define the Device identification code (value
defined in Table 4). The content of the following bytes is Don’t Care.
Maximum rating M24512-DRE
26/42 DocID027240 Rev 2
7 Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
- Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous
Substances (RoHS directive 2011/65/EU of July 2011).
°C
VIO Input or output range –0.50 6.5 V
IOL DC output current (SDA = 0) - 5 mA
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (Human Body model)(2)
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012, C1=100 pF, R1=1500 Ω, R2=500 Ω).
- 4000 V
DocID027240 Rev 2 27/42
M24512-DRE DC and AC parameters
8 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Figure 9. AC measurement I/O waveform
Table 6. Cycling performance by groups of four bytes
Symbol Parameter Test condition Min. Max. Unit
Ncycle Write cycle
endurance(1)
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,
4*N+1, 4*N+2, 4*N+3] where N is an integer, or for the status register byte (refer also to
Section 5.2: Cycling with Error Correction Code (ECC)). The Write cycle endurance is defined
by characterization and qualification.
TA ≤ 25 °C, 1.7 V < VCC < 5.5 V - 4,000,000
Write
cycle(2)
2. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or
a Lock Identification Page instruction is decoded. When using those Write instructions, refer
also to Section 5.2: Cycling with Error Correction Code (ECC).
TA = 85 °C, 1.7 V < VCC < 5.5 V - 1,200,000
TA = 105 °C, 1.7 V < VCC < 5.5 V - 900,000
Table 7. Operating conditions (voltage range R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TAAmbient operating temperature –40 105 °C
Table 8. AC measurement conditions
Symbol Parameter Min. Max. Unit
Cbus Load capacitance 100 pF
- SCL input rise/fall time, SDA input fall time - 50 ns
- Input levels 0.2 VCC to 0.8 VCC V
- Input and output timing reference levels 0.3 VCC to 0.7 VCC V
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DC and AC parameters M24512-DRE
28/42 DocID027240 Rev 2
Table 9. Input parameters
Symbol Parameter (1)
1. Characterized only, not tested in production.
Test condition Min. Max. Unit
CIN Input capacitance (SDA) - - 8 pF
CIN Input capacitance (other pins) - - 6 pF
ZLInput impedance (E2, E1, E0, WC)(2)
2. E2, E1, E0 input impedance when the memory is selected (after a Start condition).
VIN < 0.3 VCC 30 - kΩ
ZHVIN > 0.7 VCC 500 - kΩ
DocID027240 Rev 2 29/42
M24512-DRE DC and AC parameters
Table 10. DC characteristics
Symbol Parameter Test conditions (in addition to
those in Table 7 and Table 8)Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, Ei)
VIN = VSS or VCC,
device in Standby mode -± 2µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
-± 2µA
ICC Supply current (Read)
fC = 400 kHz, VCC = 5.5 V - 2 mA
fC = 400 kHz, VCC = 2.5 V - 2 mA
fC = 400 kHz, VCC = 1.7 V - 1 mA
fC = 1 MHz, VCC = 5.5 V - 2 mA
fC = 1 MHz, VCC = 2.5 V - 2 mA
fC = 1 MHz, VCC = 1.7 V - 2 mA
ICC0 Supply current (Write) During tW-2mA
ICC1 Standby supply current
Device not selected(1)(2), t° = 85
°C, VIN = VSS or VCC, VCC = 1.7 V -1
µA
Device not selected(1)(2), t° = 85
°C, VIN = VSS or VCC, VCC = 2.5 V -2
Device not selected(1)(2), t° = 85
°C, VIN = VSS or VCC, VCC = 5.5 V -3
Device not selected(1), t° = 105 °C,
VIN = VSS or VCC, VCC = 1.7 V -2.5
Device not selected(1), t° = 105 °C
VIN = VSS or VCC, VCC = 2.5 V -2.5
Device not selected(1), t° = 105 °C,
VIN = VSS or VCC, VCC = 5.5 V -5
VIL Input low voltage (SCL, SDA, WC, Ei)(3) - –0.45 0.3 VCC V
VIH
Input high voltage (SCL, SDA) - 0.7 VCC 6.5 V
Input high voltage (WC, Ei)(4) - 0.7 VCC VCC +0.6 V
VOL Output low voltage
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V -0.4V
IOL = 1 mA, VCC = 1.7 V - 0.3 V
VRES (2) Internal reset threshold voltage - 0.5 1.5 V
1. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
2. Characterized only, not 100% tested.
3. Ei inputs should be tied to Vss (see Section 2.3).
4. Ei inputs should be tied to VCC (see Section 2.3).
DC and AC parameters M24512-DRE
30/42 DocID027240 Rev 2
Table 11. 400 kHz AC characteristics
Symbol Alt. Parameter(1)
1. Test conditions (in addition to those in Table 7 and Table 8).
Min. Max. Unit
fCfSCL Clock frequency - 400 kHz
tCHCL tHIGH Clock pulse width high 600 - ns
tCLCH tLOW Clock pulse width low 1300 - ns
tQL1QL2 (2)
2. Characterized value, not tested in production.
tFSDA (out) fall time (3)
3. With CL = 10 pF.
20 120 ns
tXH1XH2 tRInput signal rise time (4)
4. There is no min. or max. values for the input signal rise and fall times. It is however
recommended by the I²C specification that the input signal rise and fall times be more than 20
ns and less than 300 ns when fC < 400 kHz.
(4) ns
tXL1XL2 tFInput signal fall time (4) (4) ns
tDXCH tSU:DAT Data in set up time 100 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX (5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
tDH Data out hold time 100 - ns
tCLQV (6)
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in
Figure 10.
tAA Clock low to next data valid (access time) - 900 ns
tCHDL tSU:STA Start condition setup time 600 - ns
tDLCL tHD:STA Start condition hold time 600 - ns
tCHDH tSU:STO Stop condition set up time 600 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 - ns
tWLDL(2)(7)
7. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(2)(8)
8. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 4 ms
tNS(2) -Pulse width ignored (input filter on SCL and
SDA) - single glitch -80ns
DocID027240 Rev 2 31/42
M24512-DRE DC and AC parameters
Table 12. 1 MHz AC characteristics
Symbol Alt. Parameter(1)
1. Test conditions (in addition to those in Ta ble 7 and Ta ble 8).
Min. Max. Unit
fCfSCL Clock frequency 0 1 MHz
tCHCL tHIGH Clock pulse width high 260 - ns
tCLCH tLOW Clock pulse width low 400 - ns
tXH1XH2 tRInput signal rise time (2)
2. There is no min. or max. values for the input signal rise and fall times. However, it is
recommended by the I²C specification that the input signal rise and fall times be more than
20 ns and less than 120 ns when fC < 1 MHz.
(2) ns
tXL1XL2 tFInput signal fall time (2) (2) ns
tQL1QL2 (3)
3. Characterized only, not tested in production.
tFSDA (out) fall time - 120 ns
tDXCH tSU:DAT Data in setup time 50 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX (4)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
tDH Data out hold time 100 - ns
tCLQV (5)
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified
in Figure 11.
tAA Clock low to next data valid (access time) - 450 ns
tCHDL tSU:STA Start condition setup time 250 - ns
tDLCL tHD:STA Start condition hold time 250 - ns
tCHDH tSU:STO Stop condition setup time 250 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 500 - ns
tWLDL(6)(3)
6. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(7)(3)
7. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 4 ms
tNS (3) -Pulse width ignored (input filter on SCL and
SDA) -80ns
DC and AC parameters M24512-DRE
32/42 DocID027240 Rev 2
Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC = 400 kHz
Figure 11. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C
bus at maximum frequency fC = 1MHz
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DocID027240 Rev 2 33/42
M24512-DRE DC and AC parameters
Figure 12. AC waveforms
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Package mechanical data M24512-DRE
34/42 DocID027240 Rev 2
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.1 TSSOP8 package information
Figure 13.TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package outline
1. Drawing is not to scale.
Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
CP - - 0.100 - - 0.0039
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.650 - - 0.0256 -
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
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DocID027240 Rev 2 35/42
M24512-DRE Package mechanical data
9.2 SO8N package information
Figure 14. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width,
package outline
1. Drawing is not to scale.
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
α0° - 8° 0° - 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Table 13. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch,
package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
Table 14. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.170 - 0.230 0.0067 - 0.0091
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 -
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Package mechanical data M24512-DRE
36/42 DocID027240 Rev 2
Figure 15. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package recommended footprint
1. Dimensions are expressed in millimeters.
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
Table 14. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
2B)3B9
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DocID027240 Rev 2 37/42
M24512-DRE Package mechanical data
9.3 WFDFPN8 package information
Figure 16.WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package outline
1. Drawing is not to scale.
Table 15. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package mechanical data
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
A 0.700 0.750 0.800 0.0276 0.0295 0.0315
A1 0.025 0.045 0.065 0.0010 0.0018 0.0026
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
D 1.900 2.000 2.100 0.0748 0.0787 0.0827
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.500 - - 0.0197 -
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - -
D2 1.050 - 1.650 0.0413 - 0.0650
E2 1.050 - 1.450 0.0413 - 0.0571
K 0.400 - - 0.0157 - -
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Package mechanical data M24512-DRE
38/42 DocID027240 Rev 2
L 0.300 - 0.500 0.0118 - 0.0197
NX(2) 8
ND(3) 4
aaa - - 0.150 - - 0.0059
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee(4) - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. NX is the number of terminals.
3. ND is the number of terminals on “D” sides.
4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle
from measuring.
Table 15. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package mechanical data (continued)
Symbol
millimeters inches(1)
Min. Typ. Max. Min. Typ. Max.
DocID027240 Rev 2 39/42
M24512-DRE Part numbering
10 Part numbering
Note: For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Table 16. Ordering information scheme
Example: M24 512-D R MN 8 T P /K
Device type
M24 = I2C serial access EEPROM
Device function
512-D = 512 Kbit (64 x 8 bits) plus identification page
Operating voltage
R = VCC = 1.7 V to 5.5 V
Package(1)
1. All package are ECOPACK2® (RoHS-compliant and free of brominated, chlorinated and
antimony-oxide flame retardants)
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MF = WFDFPN8 (2 x 3 mm)
Device grade
8 = -40 to 105 °C.
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK2®
Process
/K = Manufacturing technology code
Part numbering M24512-DRE
40/42 DocID027240 Rev 2
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
DocID027240 Rev 2 41/42
M24512-DRE Revision history
11 Revision history
Table 17. Document revision history
Date Revision Changes
22-Jan-2015 1 Initial release.
31-Jan-2017 2
Updated Features, Table 7: Operating conditions (voltage range R),
Table 6: Cycling performance by groups of four bytes, Table 10: DC
characteristics, Table 16: Ordering information scheme.
Updated format of Section 9: Package mechanical data
M24512-DRE
42/42 DocID027240 Rev 2
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