1
FEATURES APPLICATIONS
DESCRIPTION
TYPICAL APPLICATION
Computer/Notebook/DockingStation
GPU DP++ SN75DP128
DP++
DP++
DisplayPort
Enabled
MonitororHDTV
DisplayPort
Enabled
MonitororHDTV
SN75DP128
SLLS893 – FEBRUARY 2008www.ti.com
DisplayPort 1:2 Switch
•Personal Computer Market2
•One Input Port to One of Two Output Ports
– Desktop PC•Supports Data Rates up to 2.7Gbps
– Notebook PC•Supports Dual-Mode DisplayPort
– Docking Station•Output Waveform Mimics Input Waveform
– Standalone Video CardCharacteristics
•Enhanced ESD:– 12kV on all Main Link Pins– 10kV on all Auxiliary Pins•Enhanced Commercial Temperature Range:0°C to 85 °C•56 Pin 8 ×8 QFN Package
The SN75DP128 is a one Dual-Mode DisplayPort input to one of two Dual-Mode DisplayPort outputs. Theoutputs will follow the input signal in a manner that provides the highest level of signal integrity while supportingthe EMI benefits of spread spectrum clocking. Through the SN75DP128 data rates of up to 2.7Gbps througheach link for a total throughput of up to 10.8Gbps can be realized.
In addition to the switching of the DisplayPort high speed signal lines, the SN75DP128 also supports theswitching of the bi-directional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD)channels. The Auxiliary differential pair supports Dual-Mode DisplayPort operation with the ability to beconfigured as a bi-directional differential bus while in DisplayPort mode or an I
2
C™ bus while in TMDS mode
The SN75DP128 is characterized for operation over ambient air temperature of 0 °C to 85 °C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DATA FLOW BLOCK DIAGRAM
ML _ B 3 (p )
ML _ B 3 (n )
ML _ B 0 (p )
ML _ B 0 (n )
ML _IN 2 (p )
ML _IN 2 (n )
ML _IN 3 (n )
ML _IN 3 (p )
ML _IN 0 (p )
ML _IN 0 (n )
ML _IN 1 (p )
ML _IN 1 (n )
AUX (p )
AUX (n )
AUX _A (p )
AUX _A (n )
ML _A 0 ( n)
ML _A 0 ( p)
ML _A 3 ( p)
ML _A 3 ( n)
Receiver
50Ω 50Ω
VBIAS
AUX _B (p )
AUX _B (n )
Priority
HPD _ A
HPD _ B
HPD
CAD
CAD _A
Receiver
50Ω 50Ω
VBIAS
Receiver
50Ω 50Ω
VBIAS
Receiver
50Ω 50Ω
VBIAS
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Driver
2-to-1
MUX
Switching
Logic
DPVadj
CAD _B
__
LP
SN75DP128
SLLS893 – FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
2Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
AUX (p)
HPD_B
ML_B 2(n)
ML_B 0(p)
LP
Priority
ML_IN 0(p)
ML_B 3(n)
ML_B 1(p)
ML_IN 1(n)
ML_IN 1(p)
ML_IN 0(n)
ML_IN 3(n)
ML_IN 3(p)
ML_IN 2(n)
ML_IN 2(p)
ML_B 3(p)
GND
VDD
ML_B 1(n)
ML_B 2(p)
VDD
GND
VDD
VDD
AUX_A (p)
AUX_B (p)
VDD
VDD
AUX_A (n)
CAD_B
AUX (n)
GND
ML_B 0(n)
GND
GND
GND
VDD
1
24
23
22
21
20
19
18
17
16
15
141312111098765432
25
26
34 33 32 31 30 29
28
27
40 39 38 37 36 35
48
47
46
45
44
43
42 41
53
56
55
54
52
51
50
49
HPD
VDD*1
CAD
HPD_A
CAD_A
GND
ML_A 3(n)
ML_A 3(p)
ML_A 2(n)
ML_A 2(p)
ML_A 1(n)
ML_A 1(p)
VDD
ML_A 0(n)
ML_A 0(p)
GND
AUX_B(n)
DPVadj
SN75DP128
SN75DP128
SLLS893 – FEBRUARY 2008
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
MAIN LINK INPUT PINS
ML_IN 0 3, 4 I DisplayPort Main Link Channel 0 Differential InputML_IN 1 6, 7 I DisplayPort Main Link Channel 1 Differential InputML_IN 2 9, 10 I DisplayPort Main Link Channel 2 Differential InputML_IN 3 12, 13 I DisplayPort Main Link Channel 3 Differential Input
MAIN LINK PORT A OUTPUT PINS
ML_A 0 56, 55 O DisplayPort Main Link Port A Channel 0 Differential OutputML_A 1 53, 52 O DisplayPort Main Link Port A Channel 1 Differential OutputML_A 2 50, 49 O DisplayPort Main Link Port A Channel 2 Differential OutputML_A 3 47, 46 O DisplayPort Main Link Port A Channel 3 Differential Output
MAIN LINK PORT B OUTPUT PINS
ML_B 0 25, 24 O DisplayPort Main Link Port B Channel 0 Differential OutputML_B 1 22, 21 O DisplayPort Main Link Port B Channel 1 Differential OutputML_B 2 19, 18 O DisplayPort Main Link Port B Channel 2 Differential OutputML_B 3 16, 15 O DisplayPort Main Link Port B Channel 3 Differential Output
HOT PLUG DETECT PINS
HPD 37 O Hot Plug Detect Output to the DisplayPort SourceHDP_A 40 I Port A Hot Plug Detect InputHPD_B 32 I Port B hot Plug Detect Input
AUXILIARY DATA PINS
AUX 36, 35 I/O Source Side Bidirectional DisplayPort Auxiliary Data LineAUX_A 45, 43 I/O Port A Bidirectional DisplayPort Auxiliary Data Line
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN75DP128
www.ti.com
SN75DP128
SLLS893 – FEBRUARY 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
AUX_B 28, 26 I/O Port B Bidirectional DisplayPort Auxiliary Data Line
CABLE ADAPTER DETECT PINS
CAD 39 O Cable Adapter Detect Output to the DisplayPort SourceCAD_A 41 I Port A Cable Adapter Detect InputCAD_B 33 I Port B Cable Adapter Detect Input
CONTROL PINS
LP 30 I Low Power Select BarPriority 29 I Output Port Priority selectionDPVadj 1 I DisplayPort Main Link Output Gain Adjustment
SUPPLY and GROUND PINS
2, 8, 14, 17, 23,VDD Primary Supply Voltage34, 48, 54VDD
*1
38 HPD and CAD Output Voltage5, 11, 20, 27,GND Ground42, 44, 51
Table 1. Control Pin Lookup Table
SIGNAL LEVEL
(1)
STATE DESCRIPTION
H Normal Mode Normal operational mode for deviceLP
Device is forced into a Low Power state causing the outputs to go to a high impedanceL Low Power Mode
state. All other inputs are ignoredH Port B has Priority If both HPD_A and HPD_B are high, Port B will be selectedPriority
L Port A has Priority If both HPD_A and HPD_B are high, Port A will be selected4.53 k ΩIncreased Gain Main Link DisplayPort Output will have an increased voltage swingDP
Vadj
6.49 k ΩNormal Gain Main Link DisplayPort Output will have a nominal voltage swing10 k ΩDecreased Gain Main Link DisplayPort Output will have a decreased voltage swing
(1) (H) Logic High; (L) Logic Low
Explanation of the internal switching logic of the SN75DP128 is located in the Application Information section atthe end of the data sheet.
ORDERING INFORMATION
(1)
PART NUMBER PART MARKING PACKAGE
SN75DP128RTQR DP128 56-pin QFN Reel (large)SN75DP128RTQT DP128 56-pin QFN Reel (small)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
4Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
THERMAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
SN75DP128
SLLS893 – FEBRUARY 2008
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
Supply Voltage Range
(2)
V
DD
, V
DD
*1
– 0.3 to 5.25 VMain Link I/O (ML_IN x, ML_A x, ML_B x) Differential Voltage 1.5 VHPD and CAD I/O – 0.3 to VDD + 0.3 VVoltage Range
Auxiliary I/O – 0.3 to VDD + 0.3 VControl I/O – 0.3 to VDD + 0.3 VHuman body model
(3)
Auxiliary I/O (AUX +/-, AUX_A +/-, & AUX_B +/-) ± 10000 VAll Other Pins ± 12000Electrostatic discharge
Charged-device model
(3)
± 1000 VMachine model
(4)
± 200 VContinuous power dissipation See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B(4) Tested in accordance with JEDEC Standard 22, Test Method A115-A
PACKAGE PCB JEDEC T
A
≤25 °C DERATING FACTOR
(1)
T
A
= 85 °CSTANDARD
ABOVE T
A
= 25 °C POWER RATING
Low-K 3623 mW 36.23 mW/ °C 1449 mW56-pin QFN (RTQ)
High-K 1109 mW 11.03 mW/ °C 443.9 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX
(1)
UNIT
R
θJB
Junction-to-board thermal 4x4 Thermal vias under powerpad 11.03 °C/Wresistance
R
θJC
Junction-to-case thermal 20.4 C/Wresistance
LP = 5V, ML: V
ID
= 600 mV, 2.7 Gbps PRBS;Device power dissipationP
D
AUX: V
ID
= 500 mV, 1Mbps PRBS; 300 340 mWDisplayPort selected
HPD/CAD A and B = 5V; V
DD
*1
= V
DD
Device power dissipation under lowP
SD
LP = 0V, HPD/CAD A and B = 5V; V
DD
*1
= V
DD
85 µWpower
(1) The maximum rating is simulated under 5.25 V VDD.
MIN NOM MAX UNIT
V
DD
Supply Voltage 4.5 5 5.25 VV
DD
*1
HPD and CAD Output reference voltage 1.62 5.25 VT
A
Operating free-air temperature 0 85 °C
MAIN LINK DIFFERENTIAL PINS
V
ID
Peak-to-peak input differential voltage 0.15 1.4 Vd
R
Data rate 2.7 GbpsR
t
Termination resistance 45 50 55 Ω
V
Oterm
Output termination voltage 0 2 V
AUXILIARY PINS
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN75DP128
www.ti.com
DEVICE POWER
ELECTRICAL CHARACTERISTICS
HOT PLUG AND CABLE ADAPTER DETECT
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN75DP128
SLLS893 – FEBRUARY 2008
RECOMMENDED OPERATING CONDITIONS (continued)
MIN NOM MAX UNIT
V
I
Input voltage 0 3.6 Vd
R
Data rate 1 MHz
HPD, CAD, AND CONTROL PINS
V
IH
High-level input voltage 2 5.25 VV
IL
Low-level input voltage 0 0.8 V
The SN75DP128 is designed to operate off a single 5V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LP = 5V, V
DD
*1
= V
DDML: V
ID
= 600 mV, 2.7 Gbps PRBSI
DD
Supply current 60 65 mAAUX: V
ID
= 500 mV, 1 Mbps PRBSHPD/CAD A and B = 5 VI
DD
*1
Supply current V
DD
*1
= 5.25 V 0.1 4 mAI
SD
Shutdown current LP = 0 V 1 16 µA
The SN75DP128 is designed to support the switching of the Hot Plug Detect and Cable adapter Detect signals.The SN75DP128 has a built in level shifter for the HPD and CAD outputs. The output voltage level of the HPDand CAD pins is defined by the voltage level of the V
DD
*1
pin. Explanation of HPD and the internal logic of theSN75DP128 is located in the application section at the end of the data sheet.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH5
High-level output voltage I
OH
= – 100 µA, V
DD
*1
= 5 V 4.5 5 VV
OH3.3
High-level output voltage I
OH
= – 100 µA, V
DD
*1
= 3.3 V 3 3.3 VV
OH2.5
High-level output voltage I
OH
= – 100 µA, V
DD
*1
= 2.5 V 2.25 2.5 VV
OH1.8
High-level output voltage I
OH
= – 100 µA, V
DD
*1
= 1.8 V 1.62 1.8 VV
OL
Low-level output voltage I
OH
= 100 µA 0 0.4 VI
H
High-level input current V
IH
= 2.0 V, V
DD
= 5.25 V – 10 10 µAI
L
Low-level input current V
IL
= 0.8 V, V
DD
= 5.25 V – 10 10 µA
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PD(CAD)
Propagation delay V
DD
*1
= 5 V 5 30 nst
PD(HPD)
Propagation delay V
DD
*1
= 5 V 30 110 nst
T1(HPD)
HPD logic switch pause time V
DD
*1
= 5 V 2 4.7 mst
T2(HPD)
HPD logic switch time V
DD
*1
= 5 V 170 400 mst
M(HPD)
Minimum output pulse duration V
DD
*1
= 5 V 100 nst
Z(HPD)
Low Power to High-level propagation delay V
DD
*1
= 5 V 30 50 110 ns
6Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
DP128
100KΩ100KΩ
HPDInput HPDOutput
0 V
SinkHotPlugDetect
PulseDuration
0 V
Minimum
HotPlugDetect
OutputPulseDuration
HPD_A
HPD
0 V HPD_B
50%
50%
VDD
VDD*1
tPD(HPD)
tm(HPD)
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 1. HPD Test Circuit
Figure 2. HPD Timing Diagram #1
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN75DP128
www.ti.com
0 V
SinkHotPlugDetect
Timeout
0V
PortB
Selected Port A
Selected
HPD
Priority
VDD
VDD
HPD_A &HPD_B
VDD*1
t1(HPD)
tT2(HPD)
0 V
0 V
HPD
0 V HPD_B
50 %
50 %
VDD HPD_A
VDD*1
tZ(HPD)
Auxiliary Pins
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 3. HPD Timing Diagram #2
Figure 4. HPD Timing Diagram #3
The SN75DP128 is designed to support the 1:2 switching of the bidirectional auxiliary signals in both adifferential (DisplayPort) mode and an I
2
C (DVI, HDMI) mode. The performance of the Auxiliary bus is optimizedbased on the status of the selected output port ’ s CAD pin.
8Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
AUX
+ or -
3.3 V
100 KΩ
3.3V
2 KΩ
10 pF 50 pF
CAD = 1
SN75DP128
SN75DP128
SLLS893 – FEBRUARY 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Pass1
Maximum passthrough voltage (CAD=1) V
DD
= 4.5 V, V
I
= 5 V, I
O
= 100 µA 2.4 3.6 VI
OZ
Output current from unselected output V
DD
= 5.25 V, V
O
= 0 – 3.6 V, V
I
= 0 V – 5 5 µAC
IO(off)
I/O capacitance when in low power DC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, 9 12 pFDC bias = 1 V, AC = 1.4 Vp-p, F = 100 kHz, CAD =C
IO(on)
I/O capacitance when in normal operation 18 25 pFHighr
ON(C0)
On resistance V
DD
= 4.5 V, V
I
= 0 – 3.6 V, I
O
= 5 mA, CAD = Low 3.5 10 Ω
Δr
ON
On resistance V
DD
= 4.5 V, V
I
= 0 – 3.6 V, I
O
= 5 mA, CAD = Low 1 5 Ω
r
ON(C1)
On resistance V
DD
= 4.5 V, V
I
= 0.4 V, I
O
= 3 mA, CAD = High 10 18 Ω
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
sk(AUX)
Intra-pair skew V
ID
= 400 mV, V
IC
= 2 V 40 80 psI
L(AUX)
Single Line Insertion Loss V
ID
= 500 mV, V
IC
= 2 V, F = 1 MHz, CAD = Low 0.4 dBt
PLH(AUXC0)
Propagation delay time, low to high CAD = Low, F = 1 MHz 3 pst
PHL(AUXC0)
Propagation delay time, high to low CAD = Low, F = 1 MHz 3 pst
PLH(AUXC1)
Propagation delay time, low to high CAD = High, F = 100 kHz 3 nst
PHL(AUXC1)
Propagation delay time, high to low CAD = High, F = 100 kHz 3 ns
Figure 5. Auxiliary Channel Test Circuit (CAD = LOW)
Figure 6. Auxiliary Channel Test Circuit (CAD = HIGH)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN75DP128
www.ti.com
2. 2 V
1. 8 V
50 %
Tsk(AUX)
2.2V
1.8V
0 V
0 V
Differential
AUXInput
Differential
AUXOutput
AUXInput
tPHL(AUXC0) tPLH(AUXC0)
1 V
1 V
AUX
Input
+ or -
2V
0V
AUX
Output
+ or -
2V
0V
tPHL(AUX1) tPLH(AUX1)
Main Link Pins
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 7. Auxiliary Channel Skew Measurement
Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW)
Figure 9. Auxiliary Channel Delay Measurement (CAD = HIGH)
The SN75DP128 is designed to support the 1:2 switching of DisplayPort ’ s high speed differential main link. Themain link I/O of the SN75DP128 are designed to track the magnitude and frequency characteristics of the inputwaveform and replicate them on the output. A feature has also been incorporated in the SN75DP128 to eitherincrease or decrease the output amplitude via the resistor connected between the DPVADJ pin and ground.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
Driver
50 W
Receiver
D+
D-
VD+
VD-
VID
0.5 pF
Y
Z
VY
VZ
100 pF
100 pF
0Vto 2V
VIterm
50 W
50 W
50 W
V =V -V
V =(V +V )
2
ID D+ D-
ICM D+ D-
V =V -V
V =(V +V )
2
OD Y Z
OC Y Z
Output
Input
InputEdgeRate
20% to 80%
80 ps
tR/FDP
DVI/O
DVI/O
SN75DP128
SLLS893 – FEBRUARY 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ΔV
I/O(2)
V
ID
= 200 mV, DPV
adj
= 6.5 k Ω0 30 60 mVDifference between input and output)ΔV
I/O(3)
V
ID
= 300 mV, DPV
adj
= 6.5 k Ω– 24 11 36 mVvoltagesΔV
I/O(4)
V
ID
= 400 mV, DPV
adj
= 6.5 k Ω– 45 – 15 15 mV(V
OD
– V
ID
)
ΔV
I/O(6)
V
ID
= 600 mV, DPV
adj
= 6.5 k Ω– 87 – 47 – 22 mVR
INT
Input termination impedance 45 50 55 Ω
V
Iterm
Input termination voltage 0 2 V
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
R/F(DP)
Output edge rate (20% – 80%) Input edge rate = 80 ps (20% – 80%) 115 160 pst
PD
Propagation delay time F= 1 MHz, V
ID
= 400 mV 200 240 280 pst
SK(1)
Intra-pair skew F= 1 MHz, V
ID
= 400 mV 20 pst
SK(2)
Inter-pair skew F= 1 MHz, V
ID
= 400 mV 40 pst
DPJIT(PP)
Peak-to-peak output residual jitter d
R
= 2.7 Gbps, V
ID
= 400 mV, PRBS 27-1 25 35 ps
Figure 10. Main Link Test Circuit
Figure 11. Main Link ΔV
I/O
and Edge Rate Measurements
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN75DP128
www.ti.com
ML_INx+
ML_INx-
0 V
0 V
MainLink
Input
MainLink
Output
tPD(ML)
tPD(ML)
ML x+
ML x-
50%
Tsk1
2.2V
1.8V
50%
Tsk1
2.2V
1.8V
ML y+
ML y-
Tsk2
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 12. Main Link Delay Measurements
Figure 13. Main Link Skew Measurements
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
TYPICAL CHARACTERISTICS
V − SupplyVoltage
DD − V
DV − Input/OutputVoltage − mV
I/O
-20
-10
0
10
20
30
40
50
60
70
80
4.4 4.6 4.8 5 5.2 5.4
V =200mV
ID
V =300mV
ID
V =400mV
ID
V =600mV
ID
Temp=25 C
o
−150
−100
−50
0
50
100
150
DP − Resistance
Vadj −W
DV − Input/OutputVoltage − mV
I\O
0 10k 12k2k 4k 6k 8k 14k
V =200mV
ID
V =300mV
ID
V =400mV
ID
V =600mV
ID
Temp=25 C
o
InputEdgeRate20%-80%(ps)
OutputEdgeRate20%-80%(ps)
0
20
40
60
80
100
120
140
160
180
200
0 50 100 150 200
V =5.25V,85 C
DD
o
V =5V
DD ,25 C
o
V =4.5V
DD ,0 C
o
200
210
230
260
270
280
300
DataRate − Bps
P − PowerDissipation − mW
D
0 2G 2.5G500M 1G 1.5G 3G
85 C
o
290
250
240
220
0 C
o
25 C
o
SN75DP128
SLLS893 – FEBRUARY 2008
INPUT/OUTPUT VOLTAGE INPUT/OUTPUT VOLTAGEvs vsRESISTANCE SUPPLY VOLTAGE
Figure 14. Figure 15.
INPUT EDGE RATE POWER DISSIPATIONvs vsOUTPUT EDGE RATE DATA RATE
Figure 16. Figure 17.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN75DP128
www.ti.com
APPLICATION INFORMATION
SWITCHING LOGIC
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
HI-Z
SN75DP128
SLLS893 – FEBRUARY 2008
The switching logic of the SN75DP128 is tied to the state of the HPD input pins as well as the priority pin and lowpower pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP128 enters the low power state. Inthis state the outputs are high impedance, and the device is shutdown to optimize power conservation. Wheneither HPD_A or HPD_B goes high, the device enters the normal operational state, and the port associated withthe HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection is determined bythe state of the priority pin.
Several key factors were taken into consideration with this digital logic implementation of channel selection aswell as HPD repeating. This logic has been divided into the following four scenarios.1. Low power state to active state. There are two possible cases for this scenario depending on the state of thelow power pin:– Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initialstate the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the deviceremains in the low power mode with both the main link and auxiliary I/O in a high impedance state.However, the port associated with the HPD input that went HIGH is still selected and the HPD output tothe source is enabled and follows the logic state of the input HPD (see Figure 18 ). The state of thePriority pin has no effect in this scenario as only one HPD input port is active.
Figure 18.
– Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initialstate the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the devicecomes out of the low power mode and enters active mode enabling the main link and auxiliary I/O. Theport associated with the HPD input that went HIGH is selected and the HPD output to the source isenabled and follows the logic state of the input HPD (see Figure 19 ). This is specified as t
Z(HPD)
. Again,thestate of the Priority pin has no effect in this scenario as only one HPD input port is active.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
HI-Z
DATA
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 19.
2. HPD Changes on the selected port. There are also two possible starting cases for this scenario:– Case one: In this case only one HPD input is initially HIGH. The HPD output logic state follows the stateof the HPD input. If the HPD input pulses LOW, as may be the case if the Sink device is requesting aninterrupt, the HPD output to the source also pulses LOW for the same duration of time with a slight delay(see Figure 20 ). The delay of this signal through the SN75DP128 is specified as t
PD(HPD)
. If the duration ofthe LOW pulse is less then t
M(HPD)
, it may not be accurately repeated to the source. If the duration of theLOW pulse exceeds t
T2(HPD)
, the device assumes that an unplug event has occurred and enters the lowpower state (see Figure 21 ). Once the HPD input goes high again, the device returns to the active stateas indicated in scenario 1. The state of the Priority pin has no effect in this scenario as only one HPDinput port is active.
Figure 20.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN75DP128
www.ti.com
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
HI-Z
DATA
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 21.
– Case two: In this case both HPD inputs are initially HIGH and the selected port has been determined bythe state of the priority pin. The HPD output logic state follows the state of the selected HPD input. If theHPD input pulses LOW, the HPD output to the source also pulses LOW for the same duration of time,again with a slight delay (see Figure 22 ). If the duration of the LOW pulse exceeds t
T2(HPD)
, the deviceassumes that an unplug event has occurred and the other port is selected (see Figure 23 ). The case inwhich the previously selected port with priority goes high again is covered in scenario 3.
Figure 22.
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA HI-Z
DATA
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 23.
3. One channel becomes active while other channel is already selected. There are also two possible startingcases for this scenario:– Case one: In this case the HPD input that is initially HIGH is from the port that has priority. Since the portwith priority is already selected, any activity on the HPD input from the other port doesnot have any effecton the switch whatsoever (see Figure 24 ).
Figure 24.
– Case two: In this case the HPD input that is initially HIGH is not the port with priority. When the HPD inputof the port that has priority goes high, the HPD output is forced LOW for some time in order to simulatean unplug event to the source device. The duration of this LOW output is defined as t
T2(HPD)
. If the HPDinput of the port with priority pulses LOW for a short duration while the t
T2(HPD)
timer is counting down, thetimer is reset. Once this time has passed the switch switches to the port with priority and the output HPD
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN75DP128
www.ti.com
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA HI-Z
DATA
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA
SN75DP128
SLLS893 – FEBRUARY 2008
once again follows the state of the newly selected channel ’ s HPD input (see Figure 25 ).
Figure 25.
4. 4. Priority pin is toggled. There are also two possible starting cases for this scenario:– Case one: In this case only one HPD input is HIGH. A port whose HPD input is LOW cannot be selected.In this case, the state of the priority pin has no effect on the switch (see Figure 26 ).
Figure 26.
– Case two: In this case both HPD inputs are HIGH. Changing the state of the priority pin when both HPDinputs are high forces the device to switch which channel is selected. When a state change is detected onthe priority pin, the device waits for a short period of time t
T1(HPD)
before responding (see Figure 27 ). Thepurpose for this pause is to allow for the priority signal to settle and also to allow the device to ignorepotential glitches on the priority pin. Once t
T1(HPD)
has expired, the HPD output is forced LOW for t
T2(HPD)and the device follows the chain of events outlined in scenario 3 case 2.
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP128
www.ti.com
LP
Priority
HPD_A
0
1
0
1
0
1
HPD_B
0
1
HPD_OUT
0
1
Channel A
Z
0
1
ChannelB
0
1
HI-Z
DATA HI-Z
DATA
SN75DP128
SLLS893 – FEBRUARY 2008
Figure 27.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): SN75DP128
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75DP128RTQR NRND QFN RTQ 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN75DP128RTQRG4 NRND QFN RTQ 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN75DP128RTQT NRND QFN RTQ 56 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN75DP128RTQTG4 NRND QFN RTQ 56 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75DP128RTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2
SN75DP128RTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75DP128RTQR QFN RTQ 56 2000 367.0 367.0 38.0
SN75DP128RTQT QFN RTQ 56 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated