R5F21335DDFP - Renesas Electronics

REJ03B0287-0100 Rev.1.00 Page 1 of 42

Mar 31, 2010

R8C/33D Group

RENESAS MCU

Datasheet

1. Overview

1.1 Features

The R8C/33D Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions

for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high

speed. In addition, the CPU core boast s a multiplier for high-speed operation processing.

Power consumption is low, and the supported o perating modes allow addit ional power control. These MCUs are

designed to maximize EMI/EMS performance.

Integration of many peri pheral functions, incl uding m ultif unction t imer and serial int erface, reduces th e number of

system components.

1.1.1 Applications

Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.

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R8C/33D Group 1. Overview

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1.1.2 Specifications

Tables 1.1 and 1.2 outline the Specifications for R8C/ 33D Group.

Table 1.1 Specifications for R8C/33D Group (1)

Item Function Specification

CPU Central processing

unit R8C CPU core

• Number of fundamental instructions: 89

• Minimum instruction execution time:

50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)

200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)

• Multiplier: 16 bits × 16 bits → 32 bits

• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits

• Operation mode: Single-chip mode (address space: 1 Mbyte)

Memory ROM, RAM Refer to Table 1.3 Product List for R8C/33D Group.

Power Supply

Voltage

Detection

Voltage detection

circuit • Power-on reset

• Voltage detection 3 (detection level of voltage detection 0 and voltage

detection 1 selectable)

I/O Ports Programmable I/O

ports • Input-only: 1 pin

• CMOS I/O ports: 27, selectable pull-up resistor

• High current drive ports: 27

Clock Clock generation

circuits • 4 circuits:XIN clock oscillation circuit,

XCIN clock oscillation circuit (32 kHz),

High-speed on-chip oscillator (with frequency adjustment function),

Low-speed on-chip oscillator

• Oscillation stop detection: XIN clock oscillation stop detection function

• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16

• Low power consumption modes:

Standard operating mode (high-speed clock, low-speed clock, high-speed

on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode

Real-time clock (timer RE)

Interrupts • Number of interrupt vectors: 69

• External Interrupt: 7 (INT × 3, Key input × 4)

• Priority levels: 7 levels

Watchdog Timer • 14 bits × 1 (with prescaler)

• Reset start selectable

• Low-speed on-chip oscillator for watchdog timer selectable

Timer Timer RA 8 bits × 1 (with 8-bit prescaler)

Timer mode (period timer), pulse output mode (output level inverted every

period), event counter mode, pulse width measurement mode, pulse period

measurement mode

Timer RB 8 bits × 1 (with 8-bit prescaler)

T imer mode (period timer), programmable waveform generation mode (PWM

output), programmable one-shot generation mode , programmable wait one-

shot generation mode

Timer RC 16 bits × 1 (with 4 capture/compare registers)

Timer mode (input capture function, output compare function), PWM mode

(output 3 pins), PWM2 mode (PWM output pin)

Timer RE 8 bits × 1

Real-time clock mode (count seconds, minutes, hours, days of week), output

compare mode

Serial

Interface UART0 Clock synchronous serial I/O/UART

UART2 Clock synchronous serial I/O/UART, I2C mode (I2C-bus),

multiprocessor communication function

A/D Converter 10-bit resolution × 12 channels, includes sample and hold function, with sweep

mode

Comparator B 2 circuits

R8C/33D Group 1. Overview

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Note:

1. Specify the D version if D version functions are to be used.

Table 1.2 Specifications for R8C/33D Group (2)

Item Function Specification

Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V

• Programming and erasure endurance: 1,000 times (program ROM)

• Program security: ROM code protect, ID code check

• Debug functions: On-chip debug, on-board flash rewrite function

Operating Frequency/Supply

Voltage f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)

f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)

Current Consumption Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)

Ty p. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)

Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))

Typ. 2.0 µA (VCC = 3.0 V, stop mode)

Operating Ambient Temperature -20 to 85°C (N version)

-40 to 85°C (D version) (1)

Package 32-pin LQFP

Package code: PLQP0032GB-A (previous code: 32P6U-A)

R8C/33D Group 1. Overview

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1.2 Product List

Table 1.3 lists Product List for R8C/ 33D Group, and Figure 1 .1 shows a Part Number, Memory Size, and Package

of R8C/33D Group.

(D): Under deve lop m en t

Figure 1.1 Part Number, Memory Size, and Package of R8C/3 3 D Grou p

Table 1.3 Product List for R8C/33D Group Current of Mar. 2010

Part No. ROM Capacity RAM Capacity Package Type Remarks

R5F21331DNFP 4 Kbytes 1 Kbyte PLQP0032GB-A N version

R5F21332DNFP 8 Kbytes 1 Kbyte PLQP0032GB-A

R5F21334DNFP 16 Kbytes 1 Kbyte PLQP0032GB-A

R5F21335DNFP 24 Kbytes 1 Kbyte PLQP0032GB-A

R5F21336DNFP 32 Kbytes 1 Kbyte PLQP0032GB-A

R5F21331DDFP (D) 4 Kbytes 1 Kbyte PLQP0032GB-A D version

R5F21332DDFP (D) 8 Kbytes 1 Kbyte PLQP0032GB-A

R5F21334DDFP (D) 16 Kbytes 1 Kbyte PLQP0032GB-A

R5F21335DDFP (D) 24 Kbytes 1 Kbyte PLQP0032GB-A

R5F21336DDFP (D) 32 Kbytes 1 Kbyte PLQP0032GB-A

Part No. R 5 F 21 33 6 D N FP

Package type:

FP: PLQP0032GB-A (0.8 mm pin-pitch, 7 mm square body)

Classification

N: Operating ambient temperature -20°C to 85°C

D: Operating ambient temperature -40°C to 85°C

ROM capacity

1: 4 KB

2: 8 KB

4: 16 KB

5: 24 KB

6: 32 KB

R8C/33D Group

R8C/3x Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductor

R8C/33D Group 1. Overview

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1.3 Block Diagram

Figure 1.2 shows a Block Diagram.

Figure 1.2 Block Dia gram

R8C CPU core

System clock generation

circuit

XIN-XOUT

High-speed on-chip oscillator

Low-speed on-chip oscillator

XCIN-XCOUT

Memory

ROM (1)

RAM (2)

Multiplier

R0H R0L

R1H R2

R1L

USP

ISP

INTB

FLG

I/O ports

Notes:

1. ROM size varies with MCU type.

2. RAM size varies with MCU type.

Port P1

Port P3

3 1

Port P4

Port P0

Port P2

Timers

Timer RA (8 bits × 1)

Timer RB (8 bits × 1)

Timer RC (16 bits × 1)

Timer RE (8 bits × 1)

UART or

clock synchronous serial I/O

(8 bits × 2)

Peripheral functions

Watchdog timer

(14 bits)

A/D converter

(10 bits × 12 channels) Voltage detection circuit

Comparator B

Low-speed on-chip oscillator

for watc hd og timer

R8C/33D Group 1. Overview

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1.4 Pin Assignment

Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.

Figure 1.3 Pin Assignment (Top View)

R8C/33D Group

PLQP0032GB-A

(32P6U-A)

(top vi e w)

P4_6/XIN(/XCIN)

P4_7/XOUT(/XCOUT)

VSS/AVSS

RESET

VCC/AVCC

MODE

P3_7/TRAO(/RXD2/SCL2/TXD2/SDA2)

P3_5(/CLK2/TRCIOD)

P3_4/IVREF3(/RXD2/SCL2/TXD2/SDA2/TRCIOC)

P3_3/IVCMP3/INT3(/CTS2/RTS2/TRCCLK)

P4_2/VREF

P1_2/AN10/Kl2(/TRCIOB)

P1_7/IVCMP1/INT1(/TRAIO)

P1_4(/TXD0/TRCCLK)

P1_6/IVREF1(/CLK0)

P1_1/AN9/KI1(/TRCIOA/TRCTRG)

P1_3/AN11/Kl3/TRBO(/TRCIOC)

P1_5(/INT1/RXD0/TRAIO)

P0_3/AN4(/TRCIOB)

P0_2/AN5(/TRCIOA/TRCTRG)

P0_1/AN6(/TRCIOA/TRCTRG)

P0_0/AN7(/TRCIOA/TRCTRG)

P0_7/AN0(/TRCIOC)

P0_6/AN1(/TRCIOD)

P0_5/AN2(/TRCIOB)

P4_5/ADTRG/INT0(/RXD2/SCL2)

P3_1(/TRBO)

P2_0(/INT1/TRCIOB)

P2_1(/TRCIOC)

P2_2(/TRCIOD)

P1_0/AN8/KI0(/TRCIOD)

P0_4/AN3/TREO(/TRCIOB)

Notes:

1. Can be assigned to the p in in parentheses by a program.

2. Confirm the pin 1 position on the package by referring to the package dimensions.

24 23 22 21 20 19 18 17

5781234 6

R8C/33D Group 1. Overview

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Note:

1. Can be assigned to the pin in parentheses by a program.

Table 1.4 Pin Name Information by Pin Number

Number Contro l Pin Port I/O Pin Functions for Peripheral Modules

Interrupt Timer Serial Interface A/D Converter,

Comparator B

1 P4_2 VREF

2MODE

3RESET

4 XOUT(/XCOUT) P4_7

5 VSS/AVSS

6 XIN(/XCIN) P4_6

7 VCC/AVCC

8 P3_7 TRAO (RXD2/SCL2/

TXD2/SDA2)

9 P3_5 (TRCIOD) (CLK2)

10 P3_4 (TRCIOC) (RXD2/SCL2/

TXD2/SDA2) IVREF3

11 P3_3 INT3 (TRCCLK) (CTS2/RTS2)IVCMP3

12 P2_2 (TRCIOD)

13 P2_1 (TRCIOC)

14 P2_0 (INT1)(TRCIOB)

15 P3_1 (TRBO)

16 P4_5 INT0 (RXD2/SCL2) ADTRG

17 P1_7 INT1 (TRAIO) IVCMP1

18 P1_6 (CLK0) IVREF1

19 P1_5 (INT1)(TRAIO) (RXD0)

20 P1_4 (TRCCLK) (TXD0)

21 P1_3 KI3 TRBO(/TRCIOC) AN11

22 P1_2 KI2 (TRCIOB) AN10

23 P1_1 KI1 (TRCIOA/TRCTRG) AN9

24 P1_0 KI0 (TRCIOD) AN8

25 P0_7 (TRCIOC) AN0

26 P0_6 (TRCIOD) AN1

27 P0_5 (TRCIOB) AN2

28 P0_4 TREO(/TRCIOB) AN3

29 P0_3 (TRCIOB) AN4

30 P0_2 (TRCIOA/TRCTRG) AN5

31 P0_1 (TRCIOA/TRCTRG) AN6

32 P0_0 (TRCIOA/TRCTRG) AN7

R8C/33D Group 1. Overview

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1.5 Pin Functions

Table 1.5 lists Pi n Functions.

I: Input O: Output I/O: Input and output

Note:

1. Refer to the oscillator manufacturer for oscillation characteristics.

Table 1.5 Pin Functions

Item Pin Name

I/O Type

Description

Power supply input VCC, VSS – Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.

Analog power

supply input AVCC, AVSS – Power supply for the A/D converter.

Connect a capacitor between AVCC and AVSS.

Reset input RESET I Input “L” on this pin resets the MCU.

MODE MODE I Connect this pin to VCC via a resistor.

XIN clock input XIN I These pins are provid ed for XIN clock generation circuit I/O.

Connect a ceramic resonator or a crystal oscillator between

the XIN and XOUT pins

(1). To use an external clock, input it

to the XOUT pin and leave the XIN pin open.

XIN clock output XOUT I/O

XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.

Connect a crystal oscillator between the XCIN and XCOUT

pins (1). To use an external clock, input it to the XCIN pin and

leave the XCOUT pin open.

XCIN clock output XCOUT O

INT interrupt input INT0, INT1, INT3 IINT interrupt input pins.

INT0 is timer RB, and RC input pin.

Key input interrupt KI0 to KI3 I Key input interrupt in put pins

Timer RA TRAIO I/O Timer RA I/O pin

TRAO O Timer RA output pin

Timer RB TRBO O Timer RB output pin

Timer RC TRCCLK I External clock input pin

TRCTRG I External trigger input pin

TRCIOA, TRCIOB,

TRCIOC, TRCIOD I/O Timer RC I/O pins

Timer RE TREO O Divided clock output pin

Serial interface CLK0, CLK2 I/O Transfer clock I/O pins

RXD0, RXD2 I Serial data input pins

TXD0, TXD2 O Serial data output pins

CTS2 I Transmission control input pin

RTS2 O Reception control output pin

SCL2 I/O I2C mode clock I/O pin

SDA2 I/O I2C mode data I/O pin

Reference voltage

input VREF I Reference voltage input pin to A/D converter

A/D converter AN0 to AN11 I Analog input pi ns to A/D converter

ADTRG I A/D external trigger inp ut pin

Comparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins

IVREF1, IVREF3 I Comparator B reference voltage input pin s

I/O port P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_2,

P3_1,

P3_3 to P3_5,

P3_7,

P4_5 to P4_7

I/O CMOS I/O ports. Each port has an I/O select direction

or output individually.

Any port set to input can be set to use a pull-up resistor or not

by a program.

All ports can be used as LED drive ports.

Input port P4_2 I Input-only port

R8C/33D Group 2. Central Processing Unit (CPU)

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2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. Th e CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

Figure 2.1 CPU Registers

b31 b15 b8b7 b0

Data registers (1)

Address registers (1)

R3 R0H (high-order of R0)

INTBHb15b19 b0

INTBL

FB Frame base register (1)

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

Interrupt table register

b19 b0

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bi t

Processor interrupt priority level

Reserved bi t

IPL DZSBOIU

b15 b0

b8 b7

Note:

1. These registers comprise a register bank. There are two register banks.

R1H (high-order of R1)

R0L (low-order of R0)

R1L (low-order of R1)

R8C/33D Group 2. Central Processing Unit (CPU)

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2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, ar ithmetic, and logic operations. The same applies to R1 to R3. R0 can be split

into high-order bits (R0H) and low-order bits (R0L) to be used separat ely as 8-bit dat a reg isters. R1H and R1L are

analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R 0). R3R1 is

analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also

used for transfer , arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-

bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between

USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

R8C/33D Group 2. Central Processing Unit (CPU)

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2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt prio rity levels from level 0 to level 7.

If a requested interrupt has higher priori ty than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/33D Group 3. Memory

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3. Memory

3.1 R8C/33D Group

Figure 3.1 is a Memory Map of R8C/33D Group. The R8C/33D Group ha s a 1-Mbyte address space from addresses

00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address

0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.

The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt

routine is stored here.

The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal

RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for data storage but also as

a stack area when a subroutine is called or when an interrupt request is acknowledged.

Special function registers (SFRs) are allocated addresses 00000h to 002FFh. Peripheral function control registers

are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users.

Figure 3.1 Memory Map of R8C/33D Group

Part Number

R5F21331DNFP, R5F21331DDFP

R5F21332DNFP, R5F21332DDFP

R5F21334DNFP, R5F21334DDFP

R5F21335DNFP, R5F21335DDFP

R5F21336DNFP, R5F21336DDFP

Internal ROM Internal RAM

Size Addre ss 0YYYYh Size Address 0XXXXh

4 Kbytes

8 Kbytes

16 Kbytes

24 Kbytes

32 Kbytes

0F000h

0E000h

0C000h

0A000h

08000h

1 Kbyte

007FFh

0FFFFh

0FFDCh

Note:

1. The blank areas are reserved a nd cannot be accessed by users.

FFFFFh

0FFFFh

0YYYYh

0XXXXh

00400h

002FFh

00000h

Internal ROM

(program ROM)

Internal RAM

SFR

(Refer to 4. Special

Function Registers

(SFRs))

0FFD8h

Reserved area

Undefined instruction

Overflow

BRK instru c tio n

Address match

Single step

Watchdog timer, oscillation stop detection, voltage monitor

(Reserved)

Reset

R8C/33D Group 4. Special Function Registers (SFRs)

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4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.8 list the special

function registers and Table 4.9 lists the ID Code Areas and Option Function Select Area.

Table 4.1 SFR Information (1) (1)

X: Undefined

Notes:

1. The blank areas are reserved and cannot be accessed by users.

2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer

reset does not affect t his bit.

3. The CSPROINI bit in the OFS register is set to 0.

4. The LVDAS bit in the OFS register is set to 1.

5. The LVDAS bit in the OFS register is set to 0.

Address Register Symbol After Reset

0000h

0001h

0002h

0003h

0004h Processor Mode Register 0 PM0 00h

0005h Processor Mode Register 1 PM1 00h

0006h System Clock Control Register 0 CM0 00101000b

0007h System Clock Control Register 1 CM1 00100000b

0008h Module Standby Control Register MSTCR 00h

0009h System Clock Control Register 3 CM3 00h

000Ah Protect Register PRCR 00h

000Bh Reset Source Determination Register RSTFR 0XXXXXXXb (2)

000Ch Oscillation Stop Detection Register OCD 00000100b

000Dh Watchdog Timer Reset Register WDTR XXh

000Eh Watchdog Timer Start Register WDTS XXh

000Fh Watchdog Timer Control Register WDTC 00111111b

0010h

0011h

0012h

0013h

0014h

0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch Count Sour ce Protection Mode Register CSPR 00h

10000000b (3)

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h

0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping

0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h

0026h On-Chip Reference Voltage Control Register OCVREFCR 00h

0027h

0028h Clock Prescaler Reset Flag CPSRF 00h

0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping

002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 When shipping

002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping

002Ch

002Dh

002Eh

002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 When shipping

0030h Volt age Monitor Circuit Control Register CMPA 00h

0031h Voltage Monitor Circuit Edge Select Regist er VCAC 00h

0032h

0033h Voltage Detect Register 1 VCA1 00001000b

0034h Voltage Detect Register 2 VCA2 00h (4)

00100000b (5)

0035h

0036h Voltage Detection 1 Level Select Register VD1LS 00000111b

0037h

0038h Volt age Monitor 0 Circuit Control Register VW0C 1100X010b (4)

1100X011b (5)

0039h Volt age Monitor 1 Circuit Control Register VW1C 10001010b

R8C/33D Group 4. Special Function Registers (SFRs)

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Table 4.2 SFR Information (2) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

003Ah Voltage Monit or 2 Circuit Control Register VW2C 10000010b

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

0041h Flash Memory Ready Interrupt Control Register FMRDYIC XXXXX000b

0042h

0043h

0044h

0045h

0046h

0047h Timer RC Interrupt Control Register TRCIC XXXXX000b

0048h

0049h

004Ah Timer RE Interrupt Control Register TREIC XXXXX000b

004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b

004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b

004Dh Key Input Interrupt Control Register KUPIC XXXXX000b

004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b

004Fh

0050h

0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b

0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b

0053h

0054h

0055h

0056h Timer RA Interrupt Control Register TRAIC XXXXX000b

0057h

0058h Timer RB Interrupt Control Register TRBIC XXXXX000b

0059h INT1 Interrupt Control Register INT1IC XX00X000b

005Ah INT3 Interrupt Control Register INT3IC XX00X000b

005Bh

005Ch

005Dh INT0 Interrup t Control Register INT0IC XX 00X000b

005Eh UART2 Bus Collision Detection In terrupt Control Register U2BCNIC XXXXX000b

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h Voltage Monitor 1 Interrupt Control Register VCMP1IC XXXXX000b

0073h Voltage Monitor 2 Interrupt Control Register VCMP2IC XXXXX000b

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

R8C/33D Group 4. Special Function Registers (SFRs)

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Table 4.3 SFR Information (3) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h UART0 Transmit/Receive Mode Regist er U0MR 00h

00A1h UART0 Bit Rate Register U0BRG XXh

00A2h UART0 Transmit Buffer Register U0TB XXh

00A3h XXh

00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b

00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b

00A6h UART0 Receive Buffer Register U0RB XXh

00A7h XXh

00A8h UART2 Transmit/Receive Mode Regist er U2MR 00h

00A9h UART2 Bit Rate Register U2BRG XXh

00AAh UART2 Transmit Buffer Register U2TB XXh

00ABh XXh

00ACh UART2 Transmit/Receive Control Register 0 U2C0 00001000b

00ADh UART2 Transmit/Receive Control Register 1 U2C1 00000010b

00AEh UART2 Receive Buffer Register U2RB XXh

00AFh XXh

00B0h UART2 Digital Filter Function Select Register URXDF 00h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh UART2 Special Mode Register 5 U2SMR5 00h

00BCh UART2 Special Mode Register 4 U2SMR4 00h

00BDh UART2 Special Mode Register 3 U2SMR3 000X0X0Xb

00BEh UART2 Special Mode Register 2 U2SMR2 X0000000b

00BFh UART2 Special Mode Register U2SMR X0000000b

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.4 SFR Information (4) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

00C0h A/D Register 0 AD0 XXh

000000XXb00C1h

00C2h A/D Register 1 AD1 XXh

00C3h 000000XXb

00C4h A/D Register 2 AD2 XXh

00C5h 000000XXb

00C6h A/D Register 3 AD3 XXh

00C7h 000000XXb

00C8h A/D Register 4 AD4 XXh

00C9h 000000XXb

00CAh A/D Register 5 AD5 XXh

00CBh 000000XXb

00CCh A/D Register 6 AD6 XXh

00CDh 000000XXb

00CEh A/D Register 7 AD7 XXh

00CFh 000000XXb

00D0h

00D1h

00D2h

00D3h

00D4h A/D Mode Register ADMOD 00h

00D5h A/D Input Select Register ADINSEL 11000000b

00D6h A/D Control Register 0 ADCON0 00h

00D7h A/D Control Register 1 ADCON1 00h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h Port P0 Register P0 XXh

00E1h Port P1 Register P1 XXh

00E2h Port P0 Direction Regi ster PD0 00h

00E3h Port P1 Direction Regi ster PD1 00h

00E4h Port P2 Register P2 XXh

00E5h Port P3 Register P3 XXh

00E6h Port P2 Direction Regi ster PD2 00h

00E7h Port P3 Direction Regi ster PD3 00h

00E8h Port P4 Register P4 XXh

00E9h

00EAh Port P4 Direction Register PD4 00h

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.5 SFR Information (5) (1)

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0100h Timer RA Control Register TRACR 00h

0101h Timer RA I/O Control Register TRAIOC 00h

0102h Timer RA Mode Register TRAMR 00h

0103h Timer RA Prescaler Register TRAPRE FFh

0104h Timer RA Register TRA FFh

0105h

0106h

0107h

0108h Timer RB Control Register TRBCR 00h

0109h Timer RB One-Shot Control Register TRBOCR 00h

010Ah Timer RB I/O Control Register TRBIOC 00h

010Bh Timer RB Mode Register TRBMR 00h

010Ch Timer RB Prescaler Register TRBPRE FFh

010Dh Timer RB Secondary Register TRBSC FFh

010Eh Timer RB Primary Register TRBPR FFh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h

0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h

011Ah Timer RE Hour Data Register TREHR 00h

011Bh Timer RE Day of Week Data Register TREWK 00h

011Ch Timer RE Control Register 1 TRECR1 00h

011Dh Timer RE Control Register 2 TRECR2 00h

011Eh Timer RE Count Source Select Register TRECSR 00001000b

011Fh

0120h Timer RC Mode Register TRCMR 01001000b

0121h Timer RC Control Register 1 TRCCR1 00h

0122h Timer RC Interrupt Enable Register TRCIER 01110000b

0123h Timer RC Status Register TRCSR 01110000b

0124h Timer RC I/O Control Regist er 0 TRCIOR0 10001000b

0125h Timer RC I/O Control Regist er 1 TRCIOR1 10001000b

0126h Timer RC Counter TRC 00h

0127h 00h

0128h Timer RC General Register A TRCGRA FFh

0129h FFh

012Ah Timer RC General Register B TRCGRB FFh

012Bh FFh

012Ch Timer RC General Register C TRCGRC FFh

012Dh FFh

012Eh Timer RC General Register D TRCGRD FFh

012Fh FFh

0130h Timer RC Control Register 2 TRCCR2 00011000b

0131h Timer RC Digital Filter Function Select Register TRCDF 00h

0132h Timer RC Output Master Enable Regi ster TRCOER 01111111b

0133h Timer RC Trigger Control Register TRCADCR 00h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.6 SFR Information (6) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.7 SFR Information (7) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

0180h Timer RA Pin Select Register TRASR 00h

0181h Timer RB/RC Pin Select Register TRBRCSR 00h

0182h Timer RC Pin Select Register 0 TRCPSR0 00h

0183h Timer RC Pin Select Register 1 TRCPSR1 00h

0184h

0185h

0186h

0187h

0188h UART0 Pin Select Register U0SR 00h

0189h

018Ah UART2 Pin Select Register 0 U2SR0 00h

018Bh UART2 Pin Select Register 1 U2SR1 00h

018Ch

018Dh

018Eh INT Interrupt Input Pin Select Register INTSR 00h

018Fh I/O Function Pin Select Register PINSR 00h

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h Flash Memory Status Register FST 10000X00b

01B3h

01B4h Flash Memory Control Register 0 FMR0 00h

01B5h Flash Memory Control Register 1 FMR1 00h

01B6h Flash Memory Control Register 2 FMR2 00h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.8 SFR Information (8) (1)

X: Undefined

Note:

1. The blank areas are reserved and cannot be accessed by users.

Address Register Symbol After Reset

01C0h Address Match Interrupt Register 0 RMAD0 XXh

01C1h XXh

01C2h 0000XXXXb

01C3h Address Match Interrupt Enable Register AIER 00h

01C4h Address Match Interrupt Register 1 RMAD1 XXh

01C5h XXh

01C6h 0000XXXXb

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h Pull-Up Control Register 0 PUR0 00h

01E1h Pull-Up Control Register 1 PUR1 00h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h Port P1 Drive Capacity Control Register P1DRR 00h

01F1h Port P2 Drive Capacity Control Register P2DRR 00h

01F2h Drive Capacity Control Register 0 DRR0 00h

01F3h Drive Capacity Control Register 1 DRR1 00h

01F4h

01F5h I nput Threshold Control Register 0 VLT0 00h

01F6h I nput Threshold Control Register 1 VLT1 00h

01F7h

01F8h Comparator B Control Register 0 INTCMP 00h

01F9h

01FAh External Input Enable Regist er 0 INTEN 00h

01FBh

01FCh INT Input Filter Select Register 0 INTF 00h

01FDh

01FEh Key Input Enable Register 0 KIEN 00h

01FFh

R8C/33D Group 4. Special Function Registers (SFRs)

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Mar 31, 2010

Table 4.9 ID Code Areas and Option Function Select Area

Notes:

1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriat e values as ROM data by a program.

Do not write additions to t he option function select area. If the block incl uding the opt ion function select area is erased, the option f unction select

area is set to FFh.

When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.

When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.

2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.

Do not write additions to the ID code areas. If the block inclu ding the ID code areas is erased, the ID code areas are set to FFh.

When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after wri tt en by the user.

When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.

Address Area Name Symbol After Reset

FFDBh Option Function Select Register 2 OFS2 (Note 1)

FFDFh ID1 (Note 2)

FFE3h ID2 (Note 2)

FFEBh ID3 (Note 2)

FFEFh ID4 (Note 2)

FFF3h ID5 (Note 2)

FFF7h ID6 (Note 2)

FFFBh ID7 (Note 2)

FFFFh Optio n Func tio n Select Re gis te r OFS (Note 1)

R8C/33D Group 5. Electrical Characteristics

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Mar 31, 2010

5. Electrical Characteristics

Table 5.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit

VCC/AVCC Supply voltage −0.3 to 6.5 V

VIInput voltage −0.3 to VCC + 0.3 V

VOOutput voltage −0.3 to VCC + 0.3 V

PdPower dissipation −40°C ≤ Topr ≤ 85°C 500 mW

Topr Operating ambient temperature −20 to 85 (N version) /

−40 to 85 (D version) °C

Tstg Storage temperature −65 to 150 °C

R8C/33D Group 5. Electrical Characteristics

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Mar 31, 2010

Notes:

1. VCC = 1.8 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. The average output current indicates the average value of current measured during 100 ms.

3. fOCO40M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5 V.

Table 5.2 Recommended Operating Conditions

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

VCC/AVCC Supply voltage 1.8 – 5.5 V

VSS/AVSS Supply voltage –0–V

VIH Input “H” voltage Other than CMOS input 0.8 VCC –VCC V

CMOS

input Input level

switching

function

(I/O port)

Input level selection:

0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.5 VCC –VCC V

2.7 V ≤ VCC < 4.0 V 0.55 VCC –VCC V

1.8 V ≤ VCC < 2.7 V 0.65 VCC –VCC V

Input level selection:

0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.65 VCC –VCC V

2.7 V ≤ VCC < 4.0 V 0.7 VCC –VCC V

1.8 V ≤ VCC < 2.7 V 0.8 VCC –VCC V

Input level selection:

0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0.85 VCC –VCC V

2.7 V ≤ VCC < 4.0 V 0.85 VCC –VCC V

1.8 V ≤ VCC < 2.7 V 0.85 VCC –VCC V

External clock input (XOUT) 1.2 – VCC V

VIL Input “L” voltage Other than CMOS input 0 – 0.2 VCC V

CMOS

input Input level

switching

function

(I/O port)

Input level selection:

0.35 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 – 0.2 VCC V

2.7 V ≤ VCC < 4.0 V 0 – 0.2 VCC V

1.8 V ≤ VCC < 2.7 V 0 – 0.2 VCC V

Input level selection:

0.5 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 – 0.4 VCC V

2.7 V ≤ VCC < 4.0 V 0 – 0.3 VCC V

1.8 V ≤ VCC < 2.7 V 0 – 0.2 VCC V

Input level selection:

0.7 VCC 4.0 V ≤ VCC ≤ 5.5 V 0 – 0.55 VCC V

2.7 V ≤ VCC < 4.0 V 0 – 0.45 VCC V

1.8 V ≤ VCC < 2.7 V 0 – 0.35 VCC V

External clock input (XOUT) 0 – 0.4 V

IOH(sum) Peak sum output

“H” current Sum of all pins IOH(peak) ––−160 mA

IOH(sum) Average sum

output “H” current Sum of all pins IOH(avg) ––−80 mA

IOH(peak) Peak output “H”

current Drive capacity Low – – −10 mA

Drive capacity High – – −40 mA

IOH(avg) Average output

“H” current Drive capacity Low – – −5mA

Drive capacity High – – −20 mA

IOL(sum) Peak sum output

“L” current Sum of all pins IOL(peak) ––160mA

IOL(sum) Average sum

output “L” current Sum of all pins IOL(avg) ––80mA

IOL(peak) Peak output “L”

current Drive capacity Low – – 10 mA

Drive capacity High – – 40 mA

IOL(avg) Average output

“L” current Drive capacity Low – – 5 mA

Drive capacity High – – 20 mA

f(XIN) XIN clock input oscillation frequency 2.7 V ≤ VCC ≤ 5.5 V – – 20 MHz

1.8 V ≤ VCC < 2.7 V – – 5 MHz

f(XCIN) XCIN clock input oscillation frequency 1.8 V ≤ VCC ≤ 5.5 V – 32.768 50 kHz

fOCO40M

When used as the count source for timer RC (3) 2.7 V ≤ VCC ≤ 5.5 V 32 – 40 MHz

fOCO-F fOCO-F frequency 2.7 V ≤ VCC ≤ 5.5 V – – 20 MHz

1.8 V ≤ VCC < 2.7 V – – 5 MHz

- System clock frequency 2.7 V ≤ VCC ≤ 5.5 V – – 20 MHz

1.8 V ≤ VCC < 2.7 V – – 5 MHz

f(BCLK) CPU clock frequency 2.7 V ≤ VCC ≤ 5.5 V – – 20 MHz

1.8 V ≤ VCC < 2.7 V – – 5 MHz

R8C/33D Group 5. Electrical Characteristics

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Mar 31, 2010

Figure 5.1 Port s P0 to P4 Timing Measu rement Circuit

30 pF

R8C/33D Group 5. Electrical Characteristics

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Mar 31, 2010

Notes:

1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise

specified.

2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current-

consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.

3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in

8-bit mode.

Notes:

1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. When the digital filter is disabled.

Table 5.3 A/D Converter Characteristics (1)

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

– Resolution Vref = AVCC ––10Bit

– Absolute accuracy 10-bit mode Vref = AVCC = 5.0 V AN0 to AN7 input,

AN8 to AN11 input ––±3LSB

Vref = AVCC = 3.3 V AN0 to AN7 input,

AN8 to AN11 input ––±5LSB

Vref = AVCC = 3.0 V AN0 to AN7 input,

AN8 to AN11 input ––±5LSB

Vref = AVCC = 2.2 V AN0 to AN7 input,

AN8 to AN11 input ––±5LSB

8-bit mode Vref = AVCC = 5.0 V AN0 to AN7 input,

AN8 to AN11 input ––±2LSB

Vref = AVCC = 3.3 V AN0 to AN7 input,

AN8 to AN11 input ––±2LSB

Vref = AVCC = 3.0 V AN0 to AN7 input,

AN8 to AN11 input ––±2LSB

Vref = AVCC = 2.2 V AN0 to AN7 input,

AN8 to AN11 input ––±2LSB

φAD A/D conversion clock 4.0 V ≤ Vref = AVCC ≤ 5.5 V (2) 2–20MHz

3.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 2–16MHz

2.7 V ≤ Vref = AVCC ≤ 5.5 V (2) 2–10MHz

2.2 V ≤ Vref = AVCC ≤ 5.5 V (2) 2–5MHz

– Tolerance level impedance – 3 – kΩ

tCONV Conversion time 10-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz 2.15 – – µs

8-bit mode Vref = AVCC = 5.0 V, φAD = 20 MHz 2.15 – – µs

tSAMP Sampling time φAD = 20 MHz 0.75 – – µs

IVref Vref current VCC = 5.0 V, XIN = f1 = φAD = 20 MHz – 45 – µA

Vref Reference voltage 2.2 – AVCC V

VIA Analog input voltage (3) 0–Vref V

OCVREF On-chip reference voltage 2 MHz ≤ φAD ≤ 4 MHz 1.19 1.34 1.49 V

Table 5.4 Comparator B Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vref IVREF1, IVREF3 input reference voltage 0 – VCC − 1.4 V

VIIVCMP1, IVCMP3 input voltage −0.3 – VCC + 0.3 V

– Offset – 5 100 mV

tdComparator output delay time (2) VI = Vref ± 100 mV – 0.1 – µs

ICMP Comparator operating current VCC = 5.0 V – 17.5 – µA

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 26 of 42

Mar 31, 2010

Notes:

1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.

2. Definition of programming/erasure endurance

The programming and erasure endurance is defined on a per-block basis.

If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte

writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the

programming/erasure endurance still stands at one.

However, the same address must not be programmed more than once per erase operation (overwriting prohibited).

3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential

addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,

when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups

before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit

the number of erase operations to a certain number.

5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase

command at least three times until the erase error does not occur.

6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.

7. The data hold time includes time that the power supply is off or the clock is not supplied.

Figure 5.2 Time delay until Su sp e nd

Table 5.5 Flash Memory (Program ROM) Electrical Characteristics

Symbol Parameter Conditions Standard Unit

Min. Typ. Max.

–Program/erase endurance (2) 1,000 (3) ––times

– Byte program time – 80 500 µs

– Block erase time – 0.3 – s

td(SR-SUS) Time delay from suspend request until

suspend – – 5 + CPU clock

× 3 cycles ms

– Interval from erase start/rest a rt until

following suspend request 0– – µs

– Time from suspend until erase restart – – 30 + CPU clock

× 1 cycle µs

td(CMDRST-

READY) Time from when command is forcibly

stopped until reading is enabled – – 30 + CPU clock

× 1 cycle µs

– Program, erase voltage 2.7 – 5.5 V

– Read voltage 1.8 – 5.5 V

– Program, erase temperature 0 – 60 °C

–Data hold time (7) Ambient temperature = 55°C 20 – – year

FST6 bit

Suspend request

(FMR21 bit)

Fixed time Clock-dependent

time Access restart

FST6, FST7: Bits in FST register

FMR21: Bit in FMR2 register

FST7 bit

td(SR-SUS)

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 27 of 42

Mar 31, 2010

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.

3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2

4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.

3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.

4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2

Table 5.6 Voltage Detection 0 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet0 Voltage detection level Vdet0_0 (2) 1.80 1.90 2.05 V

Voltage detection level Vdet0_1 (2) 2.15 2.35 2.50 V

Voltage detection level Vdet0_2 (2) 2.70 2.85 3.05 V

Voltage detection level Vdet0_3 (2) 3.55 3.80 4.05 V

–Voltage detection 0 circuit response time (4) At the falling of VCC from 5 V

to (Vdet0_0 − 0.1) V – 6 150 µs

– Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V – 1.5 – µA

td(E-A) Waiting time until voltage detection circuit

operation starts (3) – – 100 µs

Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet1 Voltage detection level Vdet1_0 (2) At the falling of VCC 2.00 2.20 2.40 V

Voltage detection level Vdet1_1 (2) At the falling of VCC 2.15 2.35 2.55 V

Voltage detection level Vdet1_2 (2) At the falling of VCC 2.30 2.50 2.70 V

Voltage detection level Vdet1_3 (2) At the falling of VCC 2.45 2.65 2.85 V

Voltage detection level Vdet1_4 (2) At the falling of VCC 2.60 2.80 3.00 V

Voltage detection level Vdet1_5 (2) At the falling of VCC 2.75 2.95 3.15 V

Voltage detection level Vdet1_6 (2) At the falling of VCC 2.85 3.10 3.40 V

Voltage detection level Vdet1_7 (2) At the falling of VCC 3.00 3.25 3.55 V

Voltage detection level Vdet1_8 (2) At the falling of VCC 3.15 3.40 3.70 V

Voltage detection level Vdet1_9 (2) At the falling of VCC 3.30 3.55 3.85 V

Voltage detection level Vdet1_A (2) At the falling of VCC 3.45 3.70 4.00 V

Voltage detection level Vdet1_B (2) At the falling of VCC 3.60 3.85 4.15 V

Voltage detection level Vdet1_C (2) At the falling of VCC 3.75 4.00 4.30 V

Voltage detection level Vdet1_D (2) At the falling of VCC 3.90 4.15 4.45 V

Voltage detection level Vdet1_E (2) At the falling of VCC 4.05 4.30 4.60 V

Voltage detection level Vdet1_F (2) At the falling of VCC 4.20 4.45 4.75 V

– Hysteresis width at the rising of VCC in voltage

detection 1 circuit Vdet1_0 to Vdet1_5

selected –0.07– V

– Vdet1_6 to Vdet1_F

selected –0.10– V

–Voltage detection 1 circuit response time (3) At the falling of VCC from

5 V to (Vdet1_0 − 0.1) V – 60 150 µs

– Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V – 1.7 – µA

td(E-A) Waiting time until voltage detection circuit operation

starts (4) – – 100 µs

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 28 of 42

Mar 31, 2010

Notes:

1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).

2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.

3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2

Notes:

1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.

Figure 5.3 Power-o n Re se t Circ ui t Ele ct rica l Ch ara cteri st ic s

Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

Vdet2 Voltage detection level Vdet2_0 At the falling of VCC 3.70 4.00 4.30 V

– Hysteresis width at the rising of VCC in voltage detection

2 circuit –0.10– V

–Voltage detection 2 circuit response time (2) At the falling of VCC from

5 V to (Vdet2_0 − 0.1) V – 20 150 µs

– Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V – 1.7 – µA

td(E-A) Waiting time until voltage detection circuit operation

starts (3) – – 100 µs

Table 5.9 Power-on Reset Circuit (2)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

trth External power VCC rise gradient (1) 0 – 50000 mV/msec

Notes:

1. Vdet0 indicates the voltage d etection level of the voltage detection 0 circuit.

2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable

a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain

tw(por) for 1 ms or more.

Vdet0 (1)

0.5 V

Internal

reset signal

tw(por) (2) Voltage detection 0

circuit response time

Vdet0 (1)

fOCO-S × 32 1

fOCO-S × 32

External

Power VCC trth trth

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 29 of 42

Mar 31, 2010

Notes:

1. VCC = 1.8 V to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in

UART mode.

Note:

1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.

Notes:

1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.

2. Waiting time until the internal power supply generation circuit stabilizes during power-on.

Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

– High-speed on-chip oscillator frequency after

reset VCC = 1.8 V to 5.5 V

−20°C ≤ Topr ≤ 85°C38.4 40 41.6 MHz

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C38.0 40 42.0 MHz

High-speed on-chip oscillator frequency when

the FRA4 register correction value is written into

the FRA1 register and the FRA5 register

correction value into the FRA3 register (2)

VCC = 1.8 V to 5.5 V

−20°C ≤ Topr ≤ 85°C35.389 36.864 38.338 MHz

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C35.020 36.864 38.707 MHz

High-speed on-chip oscillator frequency when

the FRA6 register correction value is written into

the FRA1 register and the FRA7 register

correction value into the FRA3 register

VCC = 1.8 V to 5.5 V

−20°C ≤ Topr ≤ 85°C30.72 32 33.28 MHz

VCC = 1.8 V to 5.5 V

−40°C ≤ Topr ≤ 85°C30.40 32 33.60 MHz

– Oscillation stability time VCC = 5.0 V, Topr = 25°C–0.53ms

– Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C – 400 – µA

Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

fOCO-S Low-speed on-chip oscillator frequency 60 125 250 kHz

– Oscillation stability time VCC = 5.0 V, Topr = 25°C – 30 100 µs

– Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C– 2 –µA

Table 5.12 Power Supply Circuit Timing Characteristics

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

td(P-R) Time for internal power supply stabilization during

power-on (2) – – 2000 µs

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 30 of 42

Mar 31, 2010

Note:

1. 4.2 V ≤ VCC ≤ 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.

Table 5.13 Electrical Characteristics (1) [4.2 V ≤ VCC ≤ 5.5 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H”

voltage Other than XOUT Drive capacity High VCC = 5V IOH = −20 mA VCC − 2.0 – VCC V

Drive capacity Low VCC = 5V IOH = −5 mA VCC − 2.0 – VCC V

XOUT VCC = 5 V IOH = −200 µA1.0 – VCC V

VOL Output “L”

voltage Other than XOUT Drive capacity High VCC = 5V IOL = 20 mA – – 2.0 V

Drive capacity Low VCC = 5V IOL = 5 mA – – 2.0 V

XOUT VCC = 5 V IOL = 200 µA– –0.5V

VT+-VT- Hysteresis INT0, INT1, INT3,

KI0,KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD2,

CLK0, CLK2

0.1 1.2 – V

RESET 0.1 1.2 – V

IIH Input “H” current VI = 5 V, VCC = 5.0 V – – 5.0 µA

IIL Input “L” current VI = 0 V, VCC = 5.0 V – – −5.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 5.0 V 25 50 100 kΩ

RfXIN Feedback

resistance XIN – 0.3 – MΩ

RfXCIN Feedback

resistance XCIN – 8 – MΩ

VRAM RAM hold voltage During stop mode 1.8 – – V

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 31 of 42

Mar 31, 2010

Table 5.14 Electrical Characteristics (2) [3.3 V ≤ VCC ≤ 5.5 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply

current

(VCC = 3.3 to 5.5 V)

Single-chip mode,

output pins are

open, other pins are

VSS

High-speed

clock mode XIN = 20 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

No division

–6.515mA

XIN = 16 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

No division

– 5.3 12.5 mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

No division

–3.6–mA

XIN = 20 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–3.0–mA

XIN = 16 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–2.2–mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–1.5–mA

High-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

–7.015mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–3.0–mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTTRC = 1

–1–mA

Low-speed

on-chip

oscillator mode

XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

– 90 400 µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator of f

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

– 85 400 µA

XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator of f

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

–47–µA

Wait mode XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

– 15 100 µA

XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

–490µA

XIN clock off

High-speed on-chip oscillator of f

Low-speed on-chip oscillator of f

XCIN clock oscillator on = 32 kHz (peripheral clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

–3.5–µA

Stop mode XIN cl ock off, Topr = 25°C

High-speed on-chip oscillator of f

Low-speed on-chip oscillator of f

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–2.05.0µA

XIN clock off, Topr = 85°C

High-speed on-chip oscillator of f

Low-speed on-chip oscillator of f

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–5.0–µA

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 32 of 42

Mar 31, 2010

Timing Requirements

(Unless Otherwise Specified: V CC = 5 V, V SS = 0 V at Topr = 25°C)

Figure 5.4 External Clock Input Timing Diagram when VCC = 5 V

Figure 5.5 TRAIO Input Timing Diagram when VCC = 5 V

Table 5.15 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 50 – ns

tWH(XOUT) XOUT input “H” width 24 – ns

tWL(XOUT) XOUT input “L” width 24 – ns

tc(XCIN) XCIN input cycle time 14 – µs

tWH(XCIN) XCIN input “H” width 7 – µs

tWL(XCIN) XCIN input “L” width 7 – µs

Table 5.16 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 100 – ns

tWH(TRAIO) TRAIO input “H” width 40 – ns

tWL(TRAIO) TRAIO input “L” width 40 – ns

VCC = 5 V

External Clo ck Input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

TRAIO input

VCC = 5 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 33 of 42

Mar 31, 2010

i = 0, 2

Figure 5.6 Serial Interfa ce Timing Diagra m wh en VCC = 5 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.7 Input Timing for External Interrupt INT i and Key Input Interrupt KIi when VCC = 5 V

Table 5.17 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 200 – ns

tW(CKH) CLKi input “H” width 100 – ns

tW(CKL) CLKi input “L” width 100 – ns

td(C-Q) TXDi output delay time – 50 ns

th(C-Q) TXDi hold time 0 – ns

tsu(D-C) RXDi input setup time 50 – ns

th(C-D) RXDi input hold time 90 – ns

Table 5.18 External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 250 (1) –ns

tW(INL) INTi input “L” width, KIi input “L” width 250 (2) –ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

i = 0, 2

VCC = 5 V

INTi input

(i = 0, 1, 3) tW(INL)

tW(INH)

VCC = 5 V

KIi input

(i = 0 to 3)

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 34 of 42

Mar 31, 2010

Note:

1. 2.7 V ≤ VCC < 4.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.

Table 5.19 Electrical Characteristics (3) [2.7 V ≤ VCC < 4.2 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage Other than XOUT Drive capacity High IOH = −5 mA VCC − 0.5 – VCC V

Drive capacity Low IOH = −1 mA VCC − 0.5 – VCC V

XOUT IOH = −200 µA1.0 – VCC V

VOL Output “L” voltage Other than XOUT Drive capacity High IOL = 5 mA – – 0.5 V

Drive capacity Low IOL = 1 mA – – 0.5 V

XOUT IOL = 200 µA– –0.5V

VT+-VT- Hysteresis INT0, INT1, INT3,

KI0,KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD2,

CLK0, CLK2

VCC = 3.0 V 0.1 0.4 – V

RESET VCC = 3.0 V 0.1 0.5 – V

IIH Input “H” current VI = 3 V, VCC = 3.0 V – – 4.0 µA

IIL Input “L” current VI = 0 V, VCC = 3.0 V – – −4.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 3.0 V 42 84 168 kΩ

RfXIN Feedback

resistance XIN – 0.3 – MΩ

RfXCIN Feedback

resistance XCIN – 8 – MΩ

VRAM RAM hold voltage During stop mode 1.8 – – V

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 35 of 42

Mar 31, 2010

Table 5.20 Electrical Characteristics (4) [2.7 V ≤ VCC < 3.3 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 2.7 to 3.3 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

clock mode XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

–3.510mA

XIN = 10 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–1.57.5mA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

–7.015mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 20 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–3.0–mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

–4.0–mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 10 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–1.5–mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTTRC = 1

–1–mA

Low-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

– 90 390 µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

– 80 400 µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

–40–µA

Wait mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

–1590

µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

–480

µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral clock

off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

–3.5–µA

Stop mode XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–2.05.0

µA

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–5.0–µA

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 36 of 42

Mar 31, 2010

Timing requirements

(Unless Otherwise Specified: V CC = 3 V, VSS = 0 V at Topr = 25°C)

Figure 5.8 External Clock Input Timing Diagram when VCC = 3 V

Figure 5.9 TRAIO Input Timing Diagram when VCC = 3 V

Table 5.21 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 50 – ns

tWH(XOUT) XOUT input “H” width 24 – ns

tWL(XOUT) XOUT input “L” width 24 – ns

tc(XCIN) XCIN input cycle time 14 – µs

tWH(XCIN) XCIN input “H” width 7 – µs

tWL(XCIN) XCIN input “L” width 7 – µs

Table 5.22 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 300 – ns

tWH(TRAIO) TRAIO input “H” width 120 – ns

tWL(TRAIO) TRAIO input “L” width 120 – ns

VCC = 3 V

External Clock Input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

TRAIO in pu t

VCC = 3 V

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 37 of 42

Mar 31, 2010

i = 0, 2

Figure 5.10 Serial Interface Timing Diagram when VCC = 3 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.11 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when VCC = 3 V

Table 5.23 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 300 – ns

tW(CKH) CLKi input “H” width 150 – ns

tW(CKL) CLKi Input “L” width 150 – ns

td(C-Q) TXDi output delay time – 80 ns

th(C-Q) TXDi hold time 0 – ns

tsu(D-C) RXDi input setup time 70 – ns

th(C-D) RXDi input hold time 90 – ns

Table 5.24 External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 380 (1) –ns

tW(INL) INTi input “L” width, KIi input “L” width 380 (2) –ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 3 V

i = 0, 2

tW(INL)

tW(INH)

VCC = 3 V

INTi input

(i = 0, 1, 3)

KIi input

(i = 0 to 3)

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 38 of 42

Mar 31, 2010

Note:

1. 1.8 V ≤ VCC < 2.7 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.

Table 5.25 Electrical Characteristics (5) [1.8 V ≤ VCC < 2.7 V]

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

VOH Output “H” voltage Other than XOUT Drive capacity High IOH = −2 mA VCC − 0.5 – VCC V

Drive capacity Low IOH = −1 mA VCC − 0.5 – VCC V

XOUT IOH = −200 µA1.0 – VCC V

VOL Output “L” voltage Other than XOUT Drive capacity High IOL = 2 mA – – 0.5 V

Drive capacity Low IOL = 1 mA – – 0.5 V

XOUT IOL = 200 µA– –0.5V

VT+-VT- Hysteresis INT0, INT1, INT3,

KI0,KI1, KI2, KI3,

TRAIO, TRBO,

TRCIOA, TRCIOB,

TRCIOC, TRCIOD,

TRCTRG, TRCCLK,

ADTRG,

RXD0, RXD2,

CLK0, CLK2

0.05 0.20 – V

RESET 0.05 0.20 – V

IIH Input “H” current VI = 2.2 V, VCC = 2.2 V – – 4.0 µA

IIL Input “L” current VI = 0 V, VCC = 2.2 V – – −4.0 µA

RPULLUP Pull-up resistance VI = 0 V, VCC = 2.2 V 70 140 300 kΩ

RfXIN Feedback

resistance XIN – 0.3 – MΩ

RfXCIN Feedback

resistance XCIN – 8 – MΩ

VRAM RAM hold voltage During stop mode 1.8 – – V

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 39 of 42

Mar 31, 2010

Table 5.26 Electrical Characteristics (6) [1.8 V ≤ VCC < 2.7 V]

(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)

Symbol Parameter Condition Standard Unit

Min. Typ. Max.

ICC Power supply current

(VCC = 1.8 to 2.7 V)

Single-chip mode,

output pins are open,

other pins are VSS

High-speed

clock mode XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

No division

–2.2–mA

XIN = 5 MHz (square wave)

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–0.8–mA

High-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

No division

–2.510mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 5 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8

–1.7–mA

XIN clock off

High-speed on-chip oscillator on fOCO-F = 4 MHz

Low-speed on-chip oscillator on = 125 kHz

Divide-by-16

MSTTRC = 1

–1–mA

Low-speed

on-chip

oscillator

mode

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

Divide-by-8, FMR27 = 1, VCA20 = 0

– 90 300 µA

Low-speed

clock mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

FMR27 = 1, VCA20 = 0

– 80 350 µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz

No division

Program operation on RAM

Flash memory off, FMSTP = 1, VCA20 = 0

–40–µA

Wait mode XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock operation

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

–1590

µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator on = 125 kHz

While a WAIT instruction is executed

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

–480

µA

XIN clock off

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

XCIN clock oscillator on = 32 kHz (peripheral

clock off)

While a WAIT instruction is executed

VCA27 = VCA26 = VCA25 = 0

VCA20 = 1

–3.5–µA

Stop mode XIN clock off, Topr = 25°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–2.05µA

XIN clock off, Topr = 85°C

High-speed on-chip oscillator off

Low-speed on-chip oscillator off

CM10 = 1

Peripheral clock off

VCA27 = VCA26 = VCA25 = 0

–5.0–µA

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 40 of 42

Mar 31, 2010

Timing requirements

(Unless Otherwise Specified: V CC = 2.2 V, VSS = 0 V at Topr = 25°C)

Figure 5.12 External Clock Input T iming Diagram when VCC = 2.2 V

Figure 5.13 TRAIO Input Timing Diagram when VCC = 2.2 V

Table 5.27 External Clock Input (XOUT, XCIN)

Symbol Parameter Standard Unit

Min. Max.

tc(XOUT) XOUT input cycle time 200 – ns

tWH(XOUT) XOUT input “H” width 90 – ns

tWL(XOUT) XOUT input “L” width 90 – ns

tc(XCIN) XCIN input cycle time 14 – µs

tWH(XCIN) XCIN input “H” width 7 – µs

tWL(XCIN) XCIN input “L” width 7 – µs

Table 5.28 TRAIO Input

Symbol Parameter Standard Unit

Min. Max.

tc(TRAIO) TRAIO input cycle time 500 – ns

tWH(TRAIO) TRAIO input “H” width 200 – ns

tWL(TRAIO) TRAIO input “L” width 200 – ns

VCC = 2.2 V

External Clock Input

tWH(XOUT),

tWH(XCIN)

tC(XOUT), tC(XCIN)

tWL(XOUT), tWL(XCIN)

TRAIO input

tC(TRAIO)

tWL(TRAIO)

tWH(TRAIO)

VCC = 2.2 V

R8C/33D Group 5. Electrical Characteristics

REJ03B0287-0100 Rev.1.00 Page 41 of 42

Mar 31, 2010

i = 0, 2

Figure 5.14 Serial Interface Timing Diagram when VCC = 2.2 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.15 Input Timing for External Interrupt INTi and Key Input Interrupt KIi when VCC = 2.2 V

Table 5.29 Serial Interface

Symbol Parameter Standard Unit

Min. Max.

tc(CK) CLKi input cycle time 800 – ns

tW(CKH) CLKi input “H” width 400 – ns

tW(CKL) CLKi input “L” width 400 – ns

td(C-Q) TXDi output delay time – 200 ns

th(C-Q) TXDi hold time 0 – ns

tsu(D-C) RXDi input setup time 150 – ns

th(C-D) RXDi input hold time 90 – ns

Table 5.30 External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol Parameter Standard Unit

Min. Max.

tW(INH) INTi input “H” width, KIi input “H” width 1000 (1) –ns

tW(INL) INTi input “L” width, KIi input “L” width 1000 (2) –ns

tW(CKH)

tC(CK)

tW(CKL) th(C-Q)

th(C-D)

tsu(D-C)td(C-Q)

CLKi

TXDi

RXDi

VCC = 2.2 V

i = 0, 2

tW(INL)

tW(INH)

VCC = 2.2 V

INTi input

(i = 0, 1, 3)

KIi input

(i = 0 to 3)

R8C/33D Group Package Dimensions

REJ03B0287-0100 Rev.1.00 Page 42 of 42

Mar 31, 2010

Package Dimensions

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of

the Renesas Electronics website.

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

24 17

Detail F

Previous CodeJEITA Package Code RENESAS Code

PLQP0032GB-A 32P6U-A

MASS[Typ.]

0.2gP-LQFP32-7x7-0.80

1.0

0.125

0.35

0.7

0.20

0.145

0.09

0.420.370.32

MaxNomMin

Dimension in Millimeters

Symbol

Reference

7.17.06.9

1.4

9.29.08.8

1.7

0.20.1

0.70.50.3

8°0°

0.8

0.10

Terminal cross section

R8C/33D Group Datasheet

C - 1

Rev. Date Description

Page Summary

0.01 Sep 10, 2009 — First Edition issued

1.00 Mar 31, 2010 All pages “Preliminary”, “Under development” deleted

4 Table 1.3 revised

22 to 41 “5. Electrical Characteristics” added

All trademarks and registered trademarks are the property of their respective owners.

REVISION HIST ORY

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to

be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or

technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or

others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the

use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to

the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is

prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics

assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product

depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the

use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;

personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

designed for life support.

"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical

implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage

range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the

use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and

malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the

possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,

please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics

products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes

no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

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