1. General description
The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC245 and 74HCT245.
The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in
both send and receive directions. A send/receive (DIR) input controls direction, and an
output enable (OE) input makes easy cascading possible. Pin OE controls the outputs so
that the buses are effectively isolated.
2. Features
nWide operating voltage: 1.0 V to 5.5 V
nOptimized for low voltage applications: 1.0 V to 3.6 V
nAccepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
nTypical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
nTypical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb =25°C
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nMultiple package options
nSpecified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Ordering information
74LV245
Octal bus transceiver; 3-state
Rev. 03 — 15 April 2009 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV245N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV245D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74LV245DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74LV245PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 2 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
2
1DIR
18
19
B0
B1
B2
B3
B4
B5
B6
B7
3
17
4
16
5
15
6
14
7
13
8
12
9
A0
A1
A2
A3
A4
A5
A6
A7
11
OE
mna174
173
1
19
2
1
16
4
15
5
14
6
13
7
12
8
119
18
G3
3EN1
3EN2
2
mna175
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 3 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Fig 3. Pin configuration DIP20, SO20 Fig 4. Pin configuration SSOP20, TSSOP20
74LV245
DIR VCC
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
001aaj962
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
74LV245
DIR VCC
A0 OE
A1 B0
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
GND B7
001aaj963
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
DIR 1 direction control
A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output
GND 10 ground (0 V)
B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output
OE 19 output enable input (active LOW)
VCC 20 supply voltage
Table 3. Function selection[1]
Input Output/input
OE DIR An Bn
L L A = B input
L H input B = A
HXZZ
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 4 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±50 mA
IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±35 mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2]
DIP20 - 750 mW
SO20, SSOP20, TSSOP20 - 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage[1] 1.0 3.3 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
VCC = 3.6 V to 5.5 V - - 50 ns/V
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 5 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
9. Static characteristics
[1] Typical values are measured at Tamb = 25 °C.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.2 V - 1.2 - - - V
IO = −100 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - V
IO = −100 µA; VCC = 2.7 V 2.5 2.7 - 2.5 - V
IO = −100 µA; VCC = 3.0 V 2.8 3.0 - 2.8 - V
IO = −100 µA; VCC = 4.5 V 4.3 4.5 - 4.3 - V
IO = −8 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V
IO = −16 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V - 0 - - - V
IO = 100 µA; VCC = 2.0 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 2.7 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 3.0 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 4.5 V - 0 0.2 - 0.2 V
IO = 8 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V
IO = 16 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V
IIinput leakage current VI=V
CC or GND;
VCC = 5.5 V - - 1.0 - 1.0 µA
IOZ OFF-state output current VI =V
IH or VIL;
VO=V
CC or GND;
VCC = 5.5 V
--5 - 10µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - - 20 - 160 µA
∆ICC additional supply current per input; VI = VCC − 0.6 V;
VCC = 2.7 V to 3.6 V - - 500 - 850 µA
CIinput capacitance - 3.5 - - - pF
CI/O input/output capacitance - 10 - - - pF
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 6 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
10. Dynamic characteristics
[1] All typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL×VCC2×fo) = sum of the outputs.
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay An, Bn to Bn, An; see Figure 5 [2]
VCC = 1.2 V - 45 28 - - ns
VCC = 2.0 V - 15 28 - 34 ns
VCC = 2.7 V - 11 19 - 24 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -7- - -ns
VCC = 3.0 V to 3.6 V [3] - 9 16 - 20 ns
VCC = 4.5 V to 5.5 V [3] - 8 11 - 14 ns
ten enable time OE to An, Bn; see Figure 6 [2]
VCC = 1.2 V - 55 - - - ns
VCC = 2.0 V - 19 31 - 39 ns
VCC = 2.7 V - 14 23 - 29 ns
VCC = 3.0 V to 3.6 V [3] - 10 18 - 23 ns
VCC = 4.5 V to 5.5 V [3] - 8.5 14 - 18 ns
tdis disable time OE to An, Bn; see Figure 6 [2]
VCC = 1.2 V - 65 - - - ns
VCC = 2.0 V - 24 32 - 39 ns
VCC = 2.7 V - 18 24 - 29 ns
VCC = 3.0 V to 3.6 V [3] - 14 20 - 24 ns
VCC = 4.5 V to 5.5 V [3] - 11.5 16 - 19 ns
CPD power dissipation
capacitance CL= 50 pF; fi = 1 MHz;
VI= GND to VCC; VCC = 3.3 V [4] -40- - -pF
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 7 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. The input (An, Bn) to output (Bn, An) propagation delays
mna176
An, Bn input
Bn, An output
tPLH tPHL
GND
VI
VM
VM
VM
VM
VOH
VOL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Enable and disable times
mna367
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
< 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
≥ 4.5 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 8 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuit for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae331
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
< 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩopen GND 2VCC
2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩopen GND 2VCC
≥ 4.5 V VCC ≤ 2.5 ns 50 pF 1 kΩopen GND 2VCC
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 9 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
12. Package outline
Fig 8. Package outline SOT146-1 (DIP20)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 26.92
26.54 6.40
6.22 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 24.2 0.51 3.2
0.068
0.051 0.021
0.015 0.014
0.009 1.060
1.045 0.25
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0780.17 0.02 0.13
SC-603MS-001
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 10 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
Fig 9. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 11 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
Fig 10. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 12 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
Fig 11. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 13 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV245_3 20090415 Product data sheet - 74LV245_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name when appropriate.
74LV245_2 19980420 Product specification - 74LV245_1
74LV245_1 19970303 Product specification - -
74LV245_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 15 April 2009 14 of 15
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LV245
Octal bus transceiver; 3-state
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 April 2009
Document identifier: 74LV245_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
