LH28F800BVN-TTL90
8M (x8/x16) Flash Memory
Date Nov. 7. 1998
LHF80V05
Rev. 1.1
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●When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative of the
company.
LHF80V05 1
Rev. 1.1
CONTENTS
PAGE
1 INTRODUCTION..............................................................3
1.1 Features ........................................................................3
1.2 Product Overview.........................................................3
2 PRINCIPLES OF OPERATION........................................6
2.1 Data Protection.............................................................7
3 BUS OPERATION ............................................................7
3.1 Read..............................................................................7
3.2 Output Disable..............................................................7
3.3 Standby.........................................................................7
3.4 Deep Power-Down .......................................................7
3.5 Read Identifier Codes Operation..................................8
3.6 Write.............................................................................8
4 COMMAND DEFINITIONS.............................................8
4.1 Read Array Command................................................11
4.2 Read Identifier Codes Command ...............................11
4.3 Read Status Register Command.................................11
4.4 Clear Status Register Command.................................11
4.5 Block Erase Command...............................................11
4.6 Word/Byte Write Command.......................................12
4.7 Block Erase Suspend Command ................................12
4.8 Word/Byte Write Suspend Command........................13
4.9 Considerations of Suspend.........................................13
4.10 Block Locking..........................................................13
4.10.1 VPP=VIL for Complete Protection......................13
4.10.2 RP#=VIH for Block Locking ..............................13
4.10.3 RP#=VHH for Block Unlocking..........................13
PAGE
5 DESIGN CONSIDERATIONS...................................... 19
5.1 Three-Line Output Control....................................... 19
5.2 Power Supply Decoupling ........................................ 19
5.3 VPP Trace on Printed Circuit Boards........................ 19
5.4 VCC, VPP, RP# Transitions....................................... 19
5.5 Power-Up/Down Protection...................................... 20
5.6 Power Dissipation..................................................... 20
6 ELECTRICAL SPECIFICATIONS ............................... 21
6.1 Absolute Maximum Ratings..................................... 21
6.2 Operating Conditions................................................ 21
6.2.1 Capacitance......................................................... 21
6.2.2 AC Input/Output Test Conditions....................... 22
6.2.3 DC Characteristics.............................................. 23
6.2.4 AC Characteristics - Read-Only Operations....... 25
6.2.5 AC Characteristics - Write Operations ............... 28
6.2.6 Alternative CE#-Controlled Writes..................... 30
6.2.7 Reset Operations................................................. 32
6.2.8 Block Erase and Word/Byte Write Performance 33
LHF80V05 2
Rev. 1.1
LH28F800BVN-TTL90
8M-BIT (1Mbit × 8 / 512Kbit × 16)
Smart3 Flash MEMORY
■Smart3 Technology
2.7V-3.6V VCC
2.7V-3.6V or 11.4V-12.6V VPP
■User-Configurable ×8 or ×16 Operation
■High-Performance Access Time
90ns(2.7V-3.6V)
■Operating Temperature
0°C to +70°C
■Optimized Array Blocking Architecture
Two 4K-word Boot Blocks
Six 4K-word Parameter Blocks
Fifteen 32K-word Main Blocks
Top Boot Location
■Extended Cycling Capability
100,000 Block Erase Cycles
■Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
■Enhanced Data Protection Features
Absolute Protection with VPP=GND
Block Erase and Word/Byte Write Lockout
during Power Transitions
Boot Blocks Protection except RP#=VHH
■Automated Word/Byte Write and Block Erase
Command User Interface
Status Register
■Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode Decreases
ICC in Static Mode
■SRAM-Compatible Write Interface
■Industry-Standard Packaging
44-Lead PSOP
■ETOXTM* Nonvolatile Flash Technology
■CMOS Process (P-type silicon substrate)
■Not designed or rated as radiation hardened
SHARP’s LH28F800BVN-TTL90 Flash memory with Smart3 technology is a high-density, low-cost, nonvolatile, read/write
storage solution for a wide range of applications. LH28F800BVN-TTL90 can operate at VCC=2.7V-3.6V and VPP=2.7V-3.6V.
Its low voltage operation capability realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible
component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal
solution for code + data storage applications. For secure code storage applications, such as networking, where code is either
directly executed out of flash or downloaded to DRAM, the LH28F800BVN-TTL90 offers two levels of protection: absolute
protection with VPP at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their
code security needs.
The LH28F800BVN-TTL90 is manufactured on SHARP’s 0.35µm ETOXTM* process technology. It come in industry-
standard package: the 44-lead PSOP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
LHF80V05 3
Rev. 1.1
1 INTRODUCTION
This datasheet contains LH28F800BVN-TTL90
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVN-TTL90 Smart3
Flash memory are:
•Smart3 Technology
•Enhanced Suspend Capabilities
•Boot Block Architecture
Please note following important differences:
•VPPLK has been lowered to 1.5V to support 2.7V-3.6V
block erase and word/byte write operations. The VPP
voltage transitions to GND is recommended for
designs that switch VPP off during read operation.
•To take advantage of Smart3 technology, allow VCC
and VPP connection to 2.7V-3.6V.
1.2 Product Overview
The LH28F800BVN-TTL90 is a high-performance 8M-bit
Smart3 Flash memory organized as 1M-byte of 8 bits or
512K-word of 16 bits. The 1M-byte/512K-word of data is
arranged in two 8K-byte/4K-word boot blocks, six 8K-
byte/4K-word parameter blocks and fifteen 64K-byte/32K-
word main blocks which are individually erasable in-
system. The memory map is shown in Figure 3.
Smart3 technology provides a choice of VCC and VPP
combinations, as shown in Table 1, to meet system
performance and power expectations. VPP at 2.7V-3.6V
eliminates the need for a separate 12V converter, while
VPP=12V maximizes block erase and word/byte write
performance. In addition to flexible erase and program
voltages, the dedicated VPP pin gives complete data
protection when VPP≤VPPLK.
Table 1. VCC and VPP Voltage Combinations Offered by
Smart3 Technology
VCC Voltage VPP Voltage
2.7V-3.6V 2.7V-3.6V, 11.4V-12.6V
Internal VCC and VPP detection Circuitry automatically
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32K-
word blocks typically within 0.51s (2.7V-3.6V VCC,
11.4V-12.6V VPP), 4K-word blocks typically within 0.31s
(2.7V-3.6V VCC, 11.4V-12.6V VPP) independent of other
blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software
to suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 12.6µs (2.7V-3.6V VCC, 11.4V-12.6V VPP), 4K-
word blocks typically within 24.5µs (2.7V-3.6V VCC,
11.4V-12.6V VPP). Word/byte write suspend mode
enables the system to read data or execute code from any
other flash memory array location.
The boot blocks can be locked for the RP# pin. Block
erase or word/byte write for boot block must not be carried
out by RP# to VIH.
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
The access time is 90ns (tAVQV) over the commercial
temperature range (0°C to +70°C) and VCC supply voltage
range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical ICCR
current is 3mA at 2.7V VCC.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (tPHQV) is required from RP# switching
high until outputs are valid. Likewise, the device has a
wake time (tPHEL) from RP#-high until writes to the CUI
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 44-lead PSOP (Plastic Small
Outline Package). Pinout is shown in Figure 2.
Input
Buffer
Buffer
Output
Multiplexer
I/O
Command
User
VCC
CE#
RP#
OE#
Identifier
Register
Status
Register
Data
Register
Data
Comparator
Y-Gating
Y
Decoder
Decoder
X
Address
Latch
Address
Counter
Write
Machine
Program/Erase
Voltage
VPP
VCC
GND
A0-A18
DQ0-DQ15
Input
Buffer
Logic
State
Boot Block 0
Boot Block 1
Parameter Block 0
Parameter Block 5
Parameter Block 4
Parameter Block 3
Parameter Block 2
Parameter Block 1
Main Block 0
Main Block 1
Main Block 13
Main Block 14
15
32K-Word
WE#
Output
Interface
Switch
Main blocks
A-1
BYTE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VPP
A17 A8
A6
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
GND GND
44-LEAD PSOP
13.2mm x 28.2mm
TOP VIEW
RP#
A16
A9
A10
A11
A12
A13
A14
A15
BYTE#
WE#
DQ14
DQ6
DQ5
DQ4
VCC
A7
A5
A4
CE#
OE#
DQ9
DQ11
DQ10
DQ15
DQ7
DQ13
DQ12
DQ8
/A-1
A18
LHF80V05 4
Rev. 1.1
Figure 1. Block Diagram
Figure 2. PSOP 44-Lead Pinout
LHF80V05 5
Rev. 1.1
Table 2. Pin Descriptions
Symbol Type Name and Function
A-1
A0-A18 INPUT
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
A-1 : Byte Select Address. Not used in ×16 mode.
A0-A10 : Row Address. Selects 1 of 2048 word lines.
A11-A14 : Column Address. Selects 1 of 16 bit lines.
A15-A18 : Main Block Address. (Boot and Parameter block Addresses are A12-A18.)
DQ0-DQ15 INPUT/
OUTPUT
DATA INPUT/OUTPUTS:
DQ0-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory array,
status register and identifier code read cycles. Data pins float to high-impedance when the chip is
deselected or outputs are disabled. Data is internally latched during a write cycle.
DQ8-DQ15:Inputs data during CUI write cycles in ×16 mode; outputs data during memory array
read cycles in ×16 mode; not used for status register and identifier code read mode. Data pins float
to high-impedance when the chip is deselected, outputs are disabled, or in ×8 mode (Byte#=VIL).
Data is internally latched during a write cycle.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RP# INPUT
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
device to read array mode. With RP#=VHH, block erase or word/byte write can operate to all
blocks. Block erase or word/byte write with VIH<RP#<VHH produce spurious results and should
not be attempted.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
BYTE# INPUT BYTE ENABLE: BYTE# VIL places device in ×8 mode. All data is then input or output on DQ0-7,
and DQ8-15 float. BYTE# VIH places the device in ×16 mode , and turns off the A-1 input buffer.
VPP SUPPLY
BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or
writing words/bytes. With VPP≤VPPLK, memory contents cannot be altered. Block erase and
word/byte write with an invalid VPP (see DC Characteristics) produce spurious results and should
not be attempted.
VCC SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. With VCC≤VLKO, all write attempts to
the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics)
produce spurious results and should not be attempted.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internal connected; it may be driven or floated.
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
4K-word Parameter Block 3
4K-word Parameter Block 2
4K-word Parameter Block 1
4K-word Parameter Block 0
32K-word Main Block 0
32K-word Main Block 1
32K-word Main Block 2
32K-word Main Block 3
32K-word Main Block 5
32K-word Main Block 6
4K-word Parameter Block 5
4K-word Parameter Block 4
Top Boot
4K-word Boot Block 0
4K-word Boot Block 1
32K-word Main Block 4
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
32K-word Main Block 8
32K-word Main Block 9
32K-word Main Block 10
32K-word Main Block 11
32K-word Main Block 13
32K-word Main Block 14
32K-word Main Block 12
3FFFF
38000 32K-word Main Block 7
[A18-A0]
LHF80V05 6
Rev. 1.1
2 PRINCIPLES OF OPERATION
The LH28F800BVN-TTL90 Smart3 Flash memory
includes an on-chip WSM to manage block erase and
word/byte write functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block erasure
and word/byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. High
voltage on VPP enables successful block erasure and
word/byte writing. All functions associated with altering
memory contents−block erase, word/byte write, status and
identifier codes−are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
Figure 3. Memory Map
LHF80V05 7
Rev. 1.1
2.1 Data Protection
Depending on the application, the system designer may
choose to make the VPP power supply switchable
(available only when memory block erases or word/byte
writes are required) or hardwired to VPPH1/2. The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
When VPP≤VPPLK, memory contents cannot be altered.
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to VPP. All
write functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The device’s
boot blocks locking capability for RP# provides additional
protection from inadvertent code or data alteration by
block erase and word/byte write operations. Refer to
Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the VPP voltage. RP# can
be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Five control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP# and BYTE#. CE# and OE# must be
driven active to obtain data at the outputs. CE# is the
device selection control, and when active enables the
selected memory device. OE# is the data output
(DQ0-DQ15) control and when active drives the selected
memory data onto the I/O bus. WE# must be at VIH and
RP# must be at VIH or VHH. Figure 11, 12 illustrates read
cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0-DQ15 outputs are placed in a high-
impedance state independent of OE#. If deselected during
block erase or word/byte write, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time tPHQV is required after return from power-
down until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase or word/byte write modes, RP#-low
will abort the operation. Memory contents being altered
are no longer valid; the data may be partially erased or
written. Time tPHWL is required after RP# goes to logic-
high (VIH) before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
Device Code
Manufacturer Code
7FFFF
00001
00000
Reserved for Future Implementation
00002
[A18-A0]
LHF80V05 8
Rev. 1.1
3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
Figure 4. Device Identifier Code Memory Map
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When VCC=2.7V-3.6V and
VPP=VPPH1/2, the CUI additionally controls block erasure
and word/byte write.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word/Byte Write command requires the command and
address of the location to be written.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 13 and 14 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the VPP voltage ≤VPPLK, Read operations from the
status register, identifier codes, or blocks are enabled.
Placing VPPH1/2 on VPP enables successful block erase
and word/byte write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
LHF80V05 9
Rev. 1.1
Table 3.1. Bus Operations(BYTE#=VIH)(1,2)
Mode Notes RP# CE# OE# WE# Address VPP DQ0-15
Read 7 VIH or VHH VIL VIL VIH X X DOUT
Output Disable VIH or VHH VIL VIH VIH X X High Z
Standby VIH or VHH VIH X X X X High Z
Deep Power-Down 3 VIL X X X X X High Z
Read Identifier Codes 7 VIH or VHH VIL VIL VIH See
Figure 4 XNote 4
Write 5,6,7 VIH or VHH VIL VIH VIL X X DIN
Table 3.2. Bus Operations(BYTE#=VIL)(1,2)
Mode Notes RP# CE# OE# WE# Address VPP DQ0-7 DQ8-15
Read 7VIH or
VHH VIL VIL VIH X X DOUT High Z
Output Disable VIH or
VHH VIL VIH VIH X X High Z High Z
Standby VIH or
VHH VIH X X X X High Z High Z
Deep Power-Down 3 VIL X X X X X High Z High Z
Read Identifier Codes 7,8 VIH or
VHH VIL VIL VIH See
Figure 4 XNote 4 High Z
Write 5,6,7 VIH or
VHH VIL VIH VIL X X DIN X
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3. RP# at GND±0.2V ensures the lowest deep power-down current.
4. See Section 4.2 for read identifier code data.
5. Command writes involving block erase or word/byte write are reliably executed when VPP=VPPH1/2 and VCC=2.7V-3.6V.
Block erase or word/byte write with VIH<RP#<VHH produce spurious results and should not be attempted.
6. Refer to Table 4 for valid DIN during a write operation.
7. Never hold OE# low and WE# low at the same timing.
8. A-1 set to VIL or VIH in byte mode (BYTE#=VIL).
LHF80V05 10
Rev. 1.1
Table 4. Command Definitions(7)
Bus Cycles First Bus Cycle Second Bus Cycle
Command Req’d. Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array/Reset 1Write XFFH
Read Identifier Codes ≥24Write X90H Read IA ID
Read Status Register 2Write X70H Read XSRD
Clear Status Register 1Write X50H
Block Erase 2 5 Write BA 20H Write BA D0H
Word/Byte Write 25,6 Write WA 40H or
10H Write WA WD
Block Erase and Word/Byte
Write Suspend 1 5 Write XB0H
Block Erase and Word/Byte
Write Resume 1 5 Write XD0H
NOTES:
1. BUS operations are defined in Table 3.1 and Table 3.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4. A-1 set to VIL or VIH in Byte Mode (BYTE#=VIL).
BA=Address within the block being erased. The each block can select by the address pin A18 through A12 combination.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
read identifier code data.
5. If the block is boot block, RP# must be at VHH to enable block erase or word/byte write operations. Attempts to issue a
block erase or word/byte write to a boot block while RP# is VIH.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
LHF80V05 11
Rev. 1.1
4.1 Read Array Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word/byte write, the device will
not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word/Byte Write Suspend command.
The Read Array command functions independently of the
VPP voltage and RP# can be VIH or VHH.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the VPP voltage and RP# can be VIH or
VHH. Following the Read Identifier Codes command, the
following information can be read:
Table 5. Identifier Codes
Code Address
[A18-A0]Data
[DQ7-DQ0]
Manufacture Code 00000H B0H
Device Code 00001H 4AH
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or word/byte write is complete and whether the
operation completed successfully. It may be read at any
time by writing the Read Status Register command. After
writing this command, all subsequent read operations
output data from the status register until another valid
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to VIH before further
reads to update the status register latch. The Read Status
Register command functions independently of the VPP
voltage. RP# can be VIH or VHH.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied VPP Voltage. RP# can be VIH or VHH. This
command is not functional during block erase or
word/byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the output data of the status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
VCC=2.7V-3.6V and VPP=VPPH1/2. In the absence of this
high voltage, block contents are protected against erasure.
If block erase is attempted while VPP≤VPPLK, SR.3 and
SR.5 will be set to "1". Successful block erase for boot
blocks requires that the corresponding if set, that
RP#=VHH. If block erase is attempted to boot block when
the corresponding RP#=VIH, SR.1 and SR.5 will be set to
"1". Block erase operations with VIH<RP#<VHH produce
spurious results and should not be attempted.
LHF80V05 12
Rev. 1.1
4.6 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the status register bit
SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable word/byte writes can only occur when
VCC=2.7V-3.6V and VPP=VPPH1/2. In the absence of this
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
VPP≤VPPLK, status register bits SR.3 and SR.4 will be set
to "1". Successful word/byte write for boot blocks requires
that the corresponding if set, that RP#=VHH. If word/byte
write is attempted to boot block when the corresponding
RP#=VIH, SR.1 and SR.4 will be set to "1". Word/byte
write operations with VIH<RP#<VHH produce spurious
results and should not be attempted.
4.7 Block Erase Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
Specification section 6.2.8 defines the block erase suspend
latency.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0".
However, SR.6 will remain "1" to indicate block erase
suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear. After the Erase Resume command is
written, the device automatically outputs status register
data when read (see Figure 7). VPP must remain at
VPPH1/2 (the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at VIH or
VHH (the same RP# level used for block erase). Block
erase cannot resume until word/byte write operations
initiated during block erase suspend have completed.
LHF80V05 13
Rev. 1.1
4.8 Word/Byte Write Suspend Command
The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the word/byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). Specification section 6.2.8
defines the word/byte write suspend latency.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear. After
the Word/Byte Write Resume command is written, the
device automatically outputs status register data when read
(see Figure 8). VPP must remain at VPPH1/2 (the same VPP
level used for word/byte write) while in word/byte write
suspend mode. RP# must also remain at VIH or VHH (the
same RP# level used for word/byte write).
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
4.10 Block Locking
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
4.10.1 VPP=VIL for Complete Protection
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash device.
4.10.2 RP#=VIH for Block Locking
The lockable blocks are locked when RP#=VIH; any
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom tow boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless VPP is below VPPLK).
4.10.3 RP#=VHH for Block Unlocking
RP#=VHH unlocks all lockable blocks.
These blocks can now be programmed or erased.
RP# controls 2 boot blocks locking and VPP provides
protection against spurious writes. Table 6 defines the
write protection methods.
Table 6. Write Protection Alternatives
Operation VPP RP# Effect
Block Erase VIL XAll Blocks Locked.
or VIL All Blocks Locked.
Word/Byte Write >VPPLK VHH All Blocks Unlocked.
VIH 2 Boot Blocks Locked.
LHF80V05 14
Rev. 1.1
Table 7. Status Register Definition
WSMS ESS ES WBWS VPPS WBWSS DPS R
76543210
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = WORD/BYTE WRITE STATUS (WBWS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
Check SR.7 to determine block erase or word/byte write
completion. SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase attempt,
an improper command sequence was entered.
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase or Word/Byte Write command sequences. SR.3
is not guaranteed to reports accurate feedback only when
VPP≠VPPH1/2.
The WSM interrogates the RP# only after Block Erase or
Word/Byte Write command sequences. It informs the
system, depending on the attempted operation, if the RP# is
not VHH.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Bus
Operation Command Comments
Write
Write
Read
Standby
Erase Setup
Erase
Confirm
Data=20H
Addr=Within Block to be Erased
Data=D0H
Addr=Within Block to be Erased
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last operation to place device in read array mode.
Bus
Operation Command Comments
Standby
1=VPP Error Detect
1=Device Protect Detect
Check SR.4,5
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.5
1=Block Erase Error
Standby
Standby
Standby Check SR.3
Check SR.1
Both 1=Command Sequence Error
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status
Register
SR.7= 0
1
Suspend
Block Erase
No
Yes
Suspend Block
Erase Loop
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3= 1
0
VPP Range Error
Device Protect Error
Command Sequence
Error
Block Erase Error
SR.1= 1
0
SR.4,5=
SR.5= 1
1
0
0
Block Erase Successful
LHF80V05 15
Rev. 1.1
Figure 5. Automated Block Erase Flowchart
Bus
Operation Command Comments
Write
Write
Read
Standby
Setup Word/Byte Write
Word/Byte Write
Data=40H or 10H
Addr=Location to Be Written
Data=Data to Be Written
Addr=Location to Be Written
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent byte writes.
SR full status check can be done after each Word/Byte write, or after a sequence of
Word/Byte writes.
Write FFH after the last Word/Byte write operation to place device in
read array mode.
Bus
Operation Command Comments
1=VPP Error Detect
1=Device Protect Detect
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Check SR.4
1=Data Write Error
Standby
Standby
Standby Check SR.3
Check SR.1
Start
Write 40H or 10H,
Address
Write Word/Byte
Data and Address
Read
Status Register
SR.7= 0
1
Suspend
Word/Byte Write
No
Yes
Suspend Word/Byte
Write Loop
Full Status
Check if Desired
Word/Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
SR.3= 1
0
VPP Range Error
Device Protect Error
Word/Byte Write Error
SR.1= 1
0
SR.4= 1
0
Word/Byte Write
Successful
LHF80V05 16
Rev. 1.1
Figure 6. Automated Word/Byte Write Flowchart
Start
Write B0H
Word/Byte Write Loop
Read
Status Register
SR.7= 0
1
No
Bus
Operation Command Comments
Write
Read
Standby
Data=B0H
Addr=X
Data=D0H
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Yes
SR.6= 0
1
Read Array Data
Done?
Block Erase Resumed Read Array Data
Block Erase Completed
Write FFH
Write D0H
Standby
Write
Erase
Suspend
Erase
Resume
Addr=X
Addr=X
Check SR.6
1=Block Erase Suspended
0=Block Erase Completed
Read Word/Byte Write
Read or
Word/Byte
Write?
LHF80V05 17
Rev. 1.1
Figure 7. Block Erase Suspend/Resume Flowchart
Start
Write B0H
Write FFH
Read
Status Register
SR.7= 0
1
No
Bus
Operation Command Comments
Write
Read
Standby
Data=B0H
Addr=X
Data=D0H
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Yes
SR.2= 0
1
Read Array Data
Done
Reading
Word/Byte Write
Resumed Read Array Data
Write FFH
Write D0H
Standby
Write
Write
Read
Word/Byte Write
Suspend
Read Array
Word/Byte Write
Resume
Addr=X
Addr=X
Data=FFH
Addr=X
Check SR.2
1=Word/Byte Write Suspended
0=Word/Byte Write Completed
Read Array locations other
than that being written.
Word/Byte Write
Completed
LHF80V05 18
Rev. 1.1
Figure 8. Word/Byte Write Suspend/Resume Flowchart
LHF80V05 19
Rev. 1.1
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between VCC and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.3 VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the VPP Power supply trace. The VPP pin
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the VCC power bus. Adequate VPP
supply traces and decoupling will decrease VPP voltage
spikes and overshoots.
5.4 VCC, VPP, RP# Transitions
Block erase and word/byte write are not guaranteed if VPP
falls outside of a valid VPPH1/2 range, VCC falls outside of
a valid 2.7V-3.6V range, or RP#≠VIH or VHH. If VPP error
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to VIL during block erase or word/byte
write, the reset operation will execute. Then, the operation
will abort and the device will enter deep power-down. The
aborted operation may leave data partially altered.
Therefore, the command sequence must be repeated after
normal operation is restored. Device power-off or RP#
transitions to VIL clear the status register.
The CUI latches commands issued by system software and
is not altered by VPP or CE# transitions or WSM actions.
Its state is read array mode upon power-up, after exit from
deep power-down or after VCC transitions below VLKO.
After block erase or word/byte write, even after VPP
transitions down to VPPLK, the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
LHF80V05 20
Rev. 1.1
5.5 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (VPP or VCC)
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
A system designer must guard against spurious writes for
VCC voltages above VLKO when VPP is active. Since both
WE# and CE# must be low for a command write, driving
either to VIH will inhibit writes. The CUI’s two-step
command sequence architecture provides added level of
protection against data alteration.
RP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=VIL
regardless of its control inputs state.
5.6 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read following
the tPHQV and tPHWL wake-up cycles required after RP# is
first raised to VIH. See AC Characteristics− Read Only
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
LHF80V05 21
Rev. 1.1
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase and
Word/Byte Write.................................0°C to +70°C(1)
Temperature under Bias...................... -10°C to +80°C
Storage Temperature................................ -65°C to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#) ............ -0.5V to +7.0V(2)
VCC Supply Voltage................................ -0.2V to +7.0V(2)
VPP Update Voltage during Block
Erase and Word/Byte Write.........-0.2V to +14.0V(2,3)
RP# Voltage........................................-0.5V to +14.0V(2,3)
Output Short Circuit Current................................100mA(4)
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for commercial temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC and VPP pins. During transitions,
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins and VCC is
VCC+0.5V which, during transitions, may overshoot to
VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP and RP# may overshoot
to +14.0V for periods <20ns.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
6.2 Operating Conditions
Temperature and VCC Operating Conditions
Symbol Parameter Min. Max. Unit Test Condition
TAOperating Temperature 0+70 °C Ambient Temperature
VCC VCC Supply Voltage (2.7V-3.6V) 2.7 3.6 V
6.2.1 CAPACITANCE(1)
TA=+25°C, f=1MHz
Symbol Parameter Typ. Max. Unit Condition
CIN Input Capacitance 710 pF VIN=0.0V
COUT Output Capacitance 912 pF VOUT=0.0V
NOTE:
1. Sampled, not 100% tested.
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
2.7
0.0
INPUT TEST POINTS OUTPUT
1.35 1.35
1.3V
1N914
DEVICE
UNDER
TEST
CL
OUT
CL Includes Jig
RL=3.3kΩ
Capacitance
LHF80V05 22
Rev. 1.1
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
Figure 9. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Test Configuration Capacitance Loading Value
Test Configuration CL(pF)
VCC=2.7V-3.6V 30
Figure 10. Transient Equivalent Testing Load
Circuit
LHF80V05 23
Rev. 1.1
6.2.3 DC CHARACTERISTICS
DC Characteristics
VCC=2.7V-3.6V Test
Sym. Parameter Notes Typ. Max. Unit Conditions
ILI Input Load Current 1±0.5 µA VCC=VCCMax.
VIN=VCC or GND
ILO Output Leakage Current 1 ±0.5 µA VCC=VCCMax.
VOUT=VCC or GND
ICCS VCC Standby Current 1,5,9 25 50 µA CMOS Inputs
VCC=VCCMax.
CE#=RP#=VCC±0.2V
1,5 0.2 2mA TTL Inputs
VCC=VCCMax.
CE#=RP#=VIH
ICCD VCC Deep Power-Down Current 1,9 510 µA RP#=GND±0.2V
ICCR VCC Read Current 1,4,5 15 25 mA CMOS Inputs
VCC=VCCMax., CE#=GND
f=5MHz, IOUT=0mA
30 mA TTL Inputs
VCC=VCCMax., CE#=GND
f=5MHz, IOUT=0mA
ICCW VCC Word/Byte Write Current 1,6 517 mA VPP=2.7V-3.6V
512 mA VPP=11.4V-12.6V
ICCE VCC Block Erase Current 1,6 417 mA VPP=2.7V-3.6V
412 mA VPP=11.4V-12.6V
ICCWS
ICCES
VCC Word/Byte Write or
Block Erase Suspend Current 1,2 1 6 mA CE#=VIH
IPPS VPP Standby or Read Current 1±2 ±15 µA VPP≤VCC
IPPR 10 200 µA VPP>VCC
IPPD VPP Deep Power-Down Current 10.1 5µA RP#=GND±0.2V
IPPW VPP Word/Byte Write Current 1,6 12 40 mA VPP=2.7V-3.6V
30 mA VPP=11.4V-12.6V
IPPE VPP Block Erase Current 1,6 825 mA VPP=2.7V-3.6V
20 mA VPP=11.4V-12.6V
IPPWS
IPPES
VPP Word/Byte Write or
Block Erase Suspend Current 110 200 µA VPP=VPPH1/2
LHF80V05 24
Rev. 1.1
DC Characteristics (Continued)
VCC=2.7V-3.6V
Sym. Parameter Notes Min. Max. Unit Test Conditions
VIL Input Low Voltage 6-0.5 0.8 V
VIH Input High Voltage 62.0 VCC
+0.5 V
VOL Output Low Voltage 60.4 VVCC=VCC Min.
IOL=2.0mA
VOH1 Output High Voltage
(TTL) 62.4 VVCC=VCC Min.
IOH=-1.5mA
VOH2 Output High Voltage
(CMOS) 60.85
VCC VVCC=VCC Min.
IOH=-2.0mA
VCC
-0.4 VVCC=VCC Min.
IOH=-100µA
VPPLK VPP Lockout Voltage during Normal
Operations 3,6 1.5 V
VPPH1 VPP Voltage during Word/Byte Write
or Block Erase Operations 2.7 3.6 V
VPPH2 VPP Voltage during Word/Byte Write
or Block Erase Operations 11.4 12.6 V
VLKO VCC Lockout Voltage 2.0 V
VHH RP# Unlock Voltage 7,8 11.4 12.6 VUnlock boot blocks
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25°C.
2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Block erases and word/byte writes are inhibited when VPP≤VPPLK, and not guaranteed in the range between VPPLK(max.)
and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above VPPH2(max.).
4. Automatic Power Savings (APS) reduces typical ICCR to 3mA at 2.7V VCC in static operation.
5. CMOS inputs are either VCC±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.
6. Sampled, not 100% tested.
7. Boot block erases and word/byte writes are inhibited when the corresponding RP#=VIH. Block erase and word/byte write
operations are not guaranteed with VIH<RP#<VHH and should not be attempted.
8. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
9. BYTE# input level is VCC±0.2V in word mode or GND±0.2V in byte mode.
LHF80V05 25
Rev. 1.1
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(1)
VCC=2.7V-3.6V, TA=0°C to +70°C
Sym. Parameter Notes Min. Max. Unit
tAVAV Read Cycle Time 90 ns
tAVQV Address to Output Delay 90 ns
tELQV CE# to Output Delay 290 ns
tPHQV RP# High to Output Delay 600 ns
tGLQV OE# to Output Delay 250 ns
tELQX CE# to Output in Low Z 3 0 ns
tEHQZ CE# High to Output in High Z 355 ns
tGLQX OE# to Output in Low Z 3 0 ns
tGHQZ OE# High to Output in High Z 320 ns
tOH Output Hold from Address, CE# or OE# Change, Whichever
Occurs First 3 0 ns
tFVQV BYTE# and A-1 to Output Delay 390 ns
tFLQZ BYTE# Low to Output in High Z 330 ns
tELFV CE# to BYTE# High or Low 3,4 5ns
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. If BYTE# transfer during reading cycle, exist the regulations separately.
ADDRESSES(A)
CE#(E)
OE#(G)
WE#(W)
DATA(D/Q)
RP#(P)
VCC
Standby Device
Address Selection Data Valid
Address Stable
tAVAV
tEHQZ
tGHQZ
HIGH Z Valid Output
tGLQV
tELQV
tGLQX
tELQX
tAVQV
tPHQV
HIGH Z
tOH
VIL
VOH
VOL
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
(DQ0-DQ15)
LHF80V05 26
Rev. 1.1
Figure 11. AC Waveform for Read Operations
ADDRESSES(A)
CE#(E)
OE#(G)
BYTE#(F)
DATA(D/Q)
Standby Device
Address Selection Data Valid
Address Stable
tAVAV
tEHQZ
tGHQZ
HIGH Z Data Output
tGLQV
tELQV
tGLQX
tELQX
tAVQV
HIGH Z
tOH
VIL
VOH
VOL
VIH
VIH
VIH
VIH
VIL
VIL
VIL
Valid
Output
DATA(D/Q) HIGH Z HIGH Z
VOH
VOL
Data
Output
(DQ0-DQ7)
(DQ8-DQ15)
tELFV tFVQV
tFLQZ
LHF80V05 27
Rev. 1.1
Figure 12. BYTE# timing Waveform
LHF80V05 28
Rev. 1.1
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(1)
VCC=2.7V-3.6V, TA=0°C to +70°C
Sym. Parameter Notes Min. Max. Unit
tAVAV Write Cycle Time 90 ns
tPHWL RP# High Recovery to WE# Going Low 2 1 µs
tELWL CE# Setup to WE# Going Low 10 ns
tWLWH WE# Pulse Width 50 ns
tPHHWH RP# VHH Setup to WE# Going High 2100 ns
tVPWH VPP Setup to WE# Going High 2100 ns
tAVWH Address Setup to WE# Going High 350 ns
tDVWH Data Setup to WE# Going High 350 ns
tWHDX Data Hold from WE# High 0ns
tWHAX Address Hold from WE# High 0ns
tWHEH CE# Hold from WE# High 10 ns
tWHWL WE# Pulse Width High 30 ns
tWHGL Write Recovery before Read 0ns
tQVVL VPP Hold from Valid SRD 2,4 0ns
tQVPH RP# VHH Hold from Valid SRD 2,4 0ns
tFVWH BYTE# Setup to WE# Going High 550 ns
tWHFV BYTE# Hold from WE# High 590 ns
NOTES:
1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations.
Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write.
4. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VHH
VIL
VPPLK
VPPH2,1
VIH
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
ADDRESSES(A)
CE#(E)
OE#(G)
WE#(W)
DATA(D/Q)
RP#(P)
VPP(V)
}
}
}
}
}
}
123456
AIN AIN
tAVAV tAVWH tWHAX
tELWL tWHEH tWHGL
tWHWL tWHQV1,2
tWLWH
tDVWH
tWHDX Valid
SRD
tPHWL
tVPWH tQVVL
DIN
DIN
High Z DIN
tPHHWH tQVPH
VIH
VIL
BYTE#(F)
tFVWH tWHFV
LHF80V05 29
Rev. 1.1
Figure 13. AC Waveform for WE#-Controlled Write Operations
LHF80V05 30
Rev. 1.1
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(1)
VCC=2.7V-3.6V, TA=0°C to +70°C
Sym. Parameter Notes Min. Max. Unit
tAVAV Write Cycle Time 90 ns
tPHEL RP# High Recovery to CE# Going Low 2 1 µs
tWLEL WE# Setup to CE# Going Low 0ns
tELEH CE# Pulse Width 50 ns
tPHHEH RP# VHH Setup to CE# Going High 2100 ns
tVPEH VPP Setup to CE# Going High 2100 ns
tAVEH Address Setup to CE# Going High 350 ns
tDVEH Data Setup to CE# Going High 350 ns
tEHDX Data Hold from CE# High 0ns
tEHAX Address Hold from CE# High 0ns
tEHWH WE# Hold from CE# High 0ns
tEHEL CE# Pulse Width High 30 ns
tEHGL Write Recovery before Read 0ns
tQVVL VPP Hold from Valid SRD 2,4 0ns
tQVPH RP# VHH Hold from Valid SRD 2,4 0ns
tFVEH BYTE# Setup to CE# Going High 550 ns
tEHFV BYTE# Hold from CE# High 590 ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write.
4. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
VIL
VIH
VIH
VIL
VIL
VIH
VHH
VIL
VPPLK
VPPH2,1
VIH
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
ADDRESSES(A)
OE#(G)
DATA(D/Q)
RP#(P)
VPP(V)
AIN AIN
tAVAV tAVEH tEHAX
tEHGL
tEHDX Valid
SRD
tPHEL
tVPEH tQVVL
DIN
DIN
High Z DIN
}
}
}
}
}
}
123456
tPHHEH tQVPH
VIH
VIL
BYTE#(F)
tFVEH tEHFV
VIH
VIL
WE#(W)
tWLEL tEHWH tEHQV1,2
tDVEH
VIH
VIL
CE#(E) tEHEL
tELEH
LHF80V05 31
Rev. 1.1
Figure 14. AC Waveform for CE#-Controlled Write Operations
VIL tPLPH
VIH
RP#(P)
VIL
t2VPH
(B)RP# rising Timing
VIH
2.7V
VIL
RP#(P)
VCC
(A)Reset Timing
Device
State Device Busy
(Reset Operation)
Device
Busy Device
Ready
Reset Operating Time
LHF80V05 32
Rev. 1.1
6.2.7 RESET OPERATIONS
Figure 15. AC Waveform for Reset Operation
Reset AC Specifications VCC=2.7V-3.6V
Sym. Parameter Notes Min. Max. Unit
tPLPH RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable) 100 ns
Reset Operating Time
(During block erase or word/byte write operation is executing) 1,2 22 µs
t2VPH VCC 2.7V to RP# High 3100 ns
NOTES:
1. If RP# is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the later of reset operation is finished or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also
has been in stable there.
LHF80V05 33
Rev. 1.1
6.2.8 BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE(3)
VCC=2.7V-3.6V, TA=0°C to +70°C
VPP=2.7V-3.6V VPP=11.4V-12.6V
Sym. Parameter Notes Typ.(1) Max. Typ.(1) Max. Unit
tWHQV1 Word/Byte Write Time 32K word Block 244.6 12.6 µs
tEHQV1 4K word Block 245.9 24.5 µs
Block Write Time 32K word Block 2,4 1.46 0.42 s
4K word Block 2,4 0.19 0.11 s
tWHQV2 Block Erase Time 32K word Block 21.14 0.51 s
tEHQV2 4K word Block 20.38 0.31 s
Word/Byte Write Suspend Latency Time to
Read 7867µs
Erase Suspend Latency Time to Read 18 22 11 14 µs
NOTES:
1. Typical values measured at TA=+25°C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. All values are in word mode (BYTE#=VIH). At byte mode (BYTE#=VIL), those values are double.
Flash memory LHFXXVXX family Data Protection
Noises having a level exceeding the limit specified in this document may be generated under specific
operating conditions on some systems.
Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing
undesired memory updating.
To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash
memory should have the following write protect designs, as appropriate:
1) Protecting data in specific block
By setting a RP# to high, only the boot block can be protected against overwriting.
Parameter and main blocks cannot be locked.
System program, etc. , can be locked by storing them in the boot block.
When a high voltage is applied to RP#, overwrite operation is enabled for all blocks.
For further information on controlling of RP#, refer to the chapter 4.10.
2) Data protection through VPP
When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is
disabled. All blocks are locked and the data in the blocks are completely write protected.
For the lockout voltage, refer to the chapter 4.10 and 6.2.3.
3) Data protection through RP#
When the RP# is kept low during power up and power down sequence such as voltage transition, write
operation on the flash memory is disabled, write protecting all blocks.
For the details of RP# control, refer to the chapter 5.5 and 6.2.7.
4) Noise rejection of WE#
Consider noise rejection of WE# in order to prevent false write command input.
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control si gnals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Powe r-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t2VPH *1
VCC
GND
VCC(min)
RP#
VIL
VIH
(P)
tPHQV
VCCW *2
GND
VCCWH1/2
(V)
CE#
VIL
VIH
(E)
WE#
VIL
VIH
(W)
OE#
VIL
VIH
(G)
WP#
VIL
VIH
(S)
VOH
VOL
(D/Q)
DATA High Z Valid
Output
tVR
tF
tR
tELQV
tFtGLQV
(A)ADDRESS Valid
(RST#)
(VPP)
tR or tF
Address
VIL
VIH
tAVQV
*1 t5VPH for the device in 5V operations.
tR or tF
tR
tR
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
(VPPH1/2)
See the application note AP-007-SW-E for details.
Rev. 1.10
ii
A-1.1.1 Rise a nd Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
tR(Ma x.) and tF(Max.) for RP# (RST#) are 100µs/V.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 0.5 30000 µs/V
tRInput Sig nal Rise Tim e 1, 2 1 µs/V
tFInput Si gnal Fall Time 1, 2 1 µs/V
Rev. 1.10
iii
A-1.2 Glitch Noises
Do n ot input the glitch no ises whic h a re bel ow VIH (Min .) or above VIL ( Max.) on address, dat a, reset, and c ont rol s ign al s,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ descri bed in specifications for VIH (Min.) and VIL (Max.).
(a) Acceptable Glitch Noises
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
Input Signal
VIL (Max.)
Input Signal
VIL (Max.)
(b)
NOT
Acceptable Glitch Noises
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No. Document Name
AP-001-SD-E Flash Memory Family Software Drivers
AP-006-PT-E Data Protection Method of SHARP Flash Memory
AP-007-SW-E RP#, VPP Electric Potential Switching Circu i t
