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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarChip Scale Package
DFixed/ADJ Versions
DOutput Tolerance of:
− 0.75% (A Grade)
− 1.25% (Standard Grade)
DUltra-Low Dropout, Typically
− 200 mV at Full Load of 100 mA
− 7 mV at 1 mA
DWide VIN Range ... 16 V Max
DLow IQ... 600 µA Typ at Full Load of
100 mA
DShutdown Current...0.01 µA Typ
DFast Transient Response to Line and Load
DOvercurrent and Thermal Protection
DHigh Peak Current Capability
DPortable Applications
− Mobile Phones
− Laptops
− Personal Digital Assistants (PDAs)
− Digital Cameras and Camcorders
− CD and MP3 Players
description/ordering information
The LP2981 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for
both portable and nonportable applications. Available in adjustable version and in fixed voltages of 1.8 V,
2.5 V, 2.7 V, 2.8 V, 2.9 V, 3 V, 3.2 V, 3.3 V, 3.6 V, and 5 V, the family has an output tolerance of 0.75% for the
A-grade devices (1.25% for the standard grade) and is capable of delivering 100-mA continuous load current.
Standard regulator features, such as over-current and over-temperature protection, are included.
The LP2981 has features that make the regulator an ideal candidate for a variety of portable applications:
•Low dropout: A PNP pass element allows a typical dropout of 200 mV at 100-mA load current and 7 mV
at 1-mA load.
•Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are
considerably lower than those associated with traditional lateral PNP regulators.
•Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the
ON/OFF pin is pulled low.
•Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package
and NanoStar chip scale packaging. NanoStar package technology is a major breakthrough in IC
packaging concepts, using the die as the package.
Copyright 2004, Texas Instruments Incorporated
DBV (SOT-23) PACKAGE
(TOP VIEW)
1
2
3
5
4
VIN
GND
ON/OFF
VOUT
ADJ/NC†
ON/OFF
YEQ, YEU, YZQ, OR YZU (WCSP) PACKAGE
(TOP VIEW)
2
5
1
43
GND
ADJ/NC†
VOUT VIN
† Must be left open in fixed-output versions
NanoStar is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ
Reel of 3000 LP2981DBVR
ADJ Reel of 250 LP2981DBVT
1.25 V
Reel of 3000 LP2981A-125DBVR
1.25 V Reel of 250 LP2981A-125DBVT
1.8 V
Reel of 3000 LP2981A-18DBVR
1.8 V Reel of 250 LP2981A-18DBVT
2.5 V
Reel of 3000 LP2981A-25DBVR
2.5 V Reel of 250 LP2981A-25DBVT
2.7 V
Reel of 3000 LP2981A-27DBVR
2.7 V Reel of 250 LP2981A-27DBVT
2.8 V
Reel of 3000 LP2981A-28DBVR
LP6_
−40°C to 125°C
A grade:
2.8 V
SOT23-5 (DBV)
Reel of 250 LP2981A-28DBVT LP6_
−40°C to 125°C
A grade:
0.75% tolerance
2.9 V
SOT23-5 (DBV) Reel of 3000 LP2981A-29DBVR
0.75% tolerance
2.9 V Reel of 250 LP2981A-29DBVT
3 V
Reel of 3000 LP2981A-30DBVR
LP8_
3 V Reel of 250 LP2981A-30DBVT LP8_
3.2 V
Reel of 3000 LP2981A-32DBVR
3.2 V Reel of 250 LP2981A-32DBVT
3.3 V
Reel of 3000 LP2981A-33DBVR
LPC_
3.3 V Reel of 250 LP2981A-33DBVT LPC_
3.6 V
Reel of 3000 LP2981A-36DBVR
3.6 V Reel of 250 LP2981A-36DBVT
5 V
Reel of 3000 LP2981A-50DBVR
5 V Reel of 250 LP2981A-50DBVT
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV: The actual top-side marking has one additional character that designates the assembly/test site.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ LP2981YEQR
1.25 V LP2981A-125YEQR
1.8 V LP2981A-18YEQR
2.5 V LP2981A-25YEQR
2.7 V
NanoStar − WCSP
LP2981A-27YEQR
2.8 V NanoStar − WCSP
0.17-mm Bump (YEQ)
Reel of 3000 LP2981A-28YEQR
2.9 V
0.17-mm Bump (YEQ)
Reel of 3000
LP2981A-29YEQR
3 V LP2981A-30YEQR
3.2 V LP2981A-32YEQR
3.3 V LP2981A-33YEQR
−40°C to 125°C
A grade:
5 V LP2981A-50YEQR
−40°C to 125°C
A grade:
0.75% tolerance ADJ LP2981YZQR
0.75% tolerance
1.25 V LP2981A-125YZQR
1.8 V LP2981A-18YZQR
2.5 V LP2981A-25YZQR
2.7 V
NanoFree
− WCSP
LP2981A-27YZQR
2.8 V
NanoFree − WCSP
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000 LP2981A-28YZQR
2.9 V
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000
LP2981A-29YZQR
3 V LP2981A-30YZQR
3.2 V LP2981A-32YZQR
3.3 V LP2981A-33YZQR
5 V LP2981A-50YZQR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡YEQ/YZQ: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character
to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ LP2981YEUR
1.25 V LP2981A-125YEUR
1.8 V LP2981A-18YEUR
2.5 V LP2981A-25YEUR
2.7 V
NanoStar − WCSP
LP2981A-27YEUR
2.8 V NanoStar − WCSP
0.30-mm Bump (YEU)
Reel of 3000 LP2981A-28YEUR
2.9 V
0.30-mm Bump (YEU)
Reel of 3000
LP2981A-29YEUR
3 V LP2981A-30YEUR
3.2 V LP2981A-32YEUR
3.3 V LP2981A-33YEUR
−40°C to 125°C
A grade:
5 V LP2981A-50YEUR
−40°C to 125°C
A grade:
0.75% tolerance ADJ LP2981YZUR
0.75% tolerance
1.25 V LP2981A-125YZUR
1.8 V LP2981A-18YZUR
2.5 V LP2981A-25YZUR
2.7 V
NanoFree
− WCSP
LP2981A-27YZUR
2.8 V
NanoFree − WCSP
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000 LP2981A-28YZUR
2.9 V
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000
LP2981A-29YZUR
3 V LP2981A-30YZUR
3.2 V LP2981A-32YZUR
3.3 V LP2981A-33YZUR
5 V LP2981A-50YZUR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character
to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ
Reel of 3000 LP2981DBVR
ADJ Reel of 250 LP2981DBVT
1.25 V
Reel of 3000 LP2981-125DBVR
1.25 V Reel of 250 LP2981-125DBVT
1.8 V
Reel of 3000 LP2981-18DBVR
1.8 V Reel of 250 LP2981-18DBVT
2.5 V
Reel of 3000 LP2981-25DBVR
2.5 V Reel of 250 LP2981-25DBVT
2.7 V
Reel of 3000 LP2981-27DBVR
2.7 V Reel of 250 LP2981-27DBVT
2.8 V
Reel of 3000 LP2981-28DBVR
LP5_
−40°C to 125°C
Standard grade:
2.8 V
SOT-23 (DBV)
Reel of 250 LP2981-28DBVT LP5_
−40°C to 125°C
Standard grade:
1.25% tolerance
2.9 V
SOT-23 (DBV) Reel of 3000 LP2981-29DBVR
1.25% tolerance
2.9 V Reel of 250 LP2981-29DBVT
3 V
Reel of 3000 LP2981-30DBVR
LP7_
3 V Reel of 250 LP2981-30DBVT LP7_
3.2 V
Reel of 3000 LP2981-32DBVR
3.2 V Reel of 250 LP2981-32DBVT
3.3 V
Reel of 3000 LP2981-33DBVR
LPB_
3.3 V Reel of 250 LP2981-33DBVT LPB_
3.6 V
Reel of 3000 LP2981-36DBVR
3.6 V Reel of 250 LP2981-36DBVT
5 V
Reel of 3000 LP2981-50DBVR
5 V Reel of 250 LP2981-50DBVT
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV: The actual top-side marking has one additional character that designates the assembly/test site.
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ LP2981YEQR
1.25 V LP2981−125YEQR
1.8 V LP2981−18YEQR
2.5 V LP2981-25YEQR
2.7 V
NanoStar − WCSP
LP2981-27YEQR
2.8 V NanoStar − WCSP
0.17-mm Bump (YEQ)
Reel of 3000 LP2981-28YEQR
2.8 V
0.17-mm Bump (YEQ)
Reel of 3000
LP2981-29YEQR
3 V LP2981-30YEQR
3.2 V LP2981-32YEQR
3.3 V LP2981-33YEQR
−40°C to 125°C
Standard grade:
5 V LP2981-50YEQR
−40°C to 125°C
Standard grade:
1.25% tolerance ADJ LP2981YZQR
1.25% tolerance
1.25 V LP2981−125YZQR
1.8 V LP2981−18YZQR
2.5 V LP2981-25YZQR
2.7 V
NanoFree
− WCSP
LP2981-27YZQR
2.8 V
NanoFree − WCSP
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000 LP2981-28YZQR
2.8 V
0.17-mm Bump
(YZQ, Pb-free)
Reel of 3000
LP2981-29YZQR
3 V LP2981-30YZQR
3.2 V LP2981-32YZQR
3.3 V LP2981-33YZQR
5 V LP2981-50YZQR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡YEQ/YZQ: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character
to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION (continued)
TJPART GRADE VOUT
(NOM) PACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
ADJ LP2981YEUR
1.25 V LP2981−125YEUR
1.8 V LP2981−18YEUR
2.5 V LP2981-25YEUR
2.7 V
NanoStar − WCSP
LP2981-27YEUR
2.8 V NanoStar − WCSP
0.30-mm Bump (YEU)
Reel of 3000 LP2981-28YEUR
2.8 V
0.30-mm Bump (YEU)
Reel of 3000
LP2981-29YEUR
3 V LP2981-30YEUR
3.2 V LP2981-32YEUR
3.3 V LP2981-33YEUR
−40°C to 125°C
Standard grade:
5 V LP2981-50YEUR
−40°C to 125°C
Standard grade:
1.25% tolerance ADJ LP2981YZUR
1.25% tolerance
1.25 V LP2981−125YZUR
1.8 V LP2981−18YZUR
2.5 V LP2981-25YZUR
2.7 V
NanoFree
− WCSP
LP2981-27YZUR
2.8 V
NanoFree − WCSP
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000 LP2981-28YZUR
2.8 V
0.30-mm Bump
(YZU, Pb-free)
Reel of 3000
LP2981-29YZUR
3 V LP2981-30YZUR
3.2 V LP2981-32YZUR
3.3 V LP2981-33YZUR
5 V LP2981-50YZUR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character
to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
VIN
VOUT
GND
ON/OFF
Overcurrent/
Overtemperature
Protection
VREF 1.23 V −
+
R1
R2
ADJ/NC†
†Fixed versions: Must be left open
ADJ versions: R1 = ∞, R2 = ∞
Figure 1
basic application circuit
VOUT
3.3 µF†
1 µF†
VIN 1
ON/OFF‡
†Minimum Cout value for stability (can be increased without limit for improved stability and transient response)
‡ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used.
§Must be left open
2GND
3
5
4NC§
LP2981A-xxDBVR (Fixed Version)
Figure 2
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
basic application circuit (continued)
3.3 µF†
1 µF†
VIN 1
ON/OFF‡
2GND
3
5
4ADJ
LP2981-xxDBVR (Adjustable Version)
VOUT = VREF
ǒ1)RADJ
R1Ǔ
RADJ
R1 3 39.5 kW‡
†Minimum Cout value for stability (can be increased without limit for improved stability and transient response)
‡See Application Information
Figure 3
absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)†
Continuous input voltage range, VIN −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON/OFF input voltage range, VON/OFF −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (see Note 1) −0.3 V to 9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/output voltage differential range, VIN-VOUT (see Note 2) −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IOUT (see Note 3) Internally limited (short-circuit protected). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 3 and 4): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . .
YEQ/YZQ package TBD°C/W. . . . . . . . . . . . . . . . . .
YEU/YZU package TBD°C/W. . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. If load is returned to a negative power supply, the output must be diode clamped to GND.
2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode normally is reverse biased
(VIN > VOUT), but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information
for more details).
3. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
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10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
VIN Supply input voltage 2.2†16 V
VON/OFF ON/OFF input voltage 0 VIN V
VIN-VOUT Input-output differential 0.7 11 V
IOUT Output current 100 mA
TJVirtual junction temperature −40 125 °C
†Minimum VIN of 2.2 V is needed for proper biasing of LDO control circuitry.
electrical characteristics at specified free-air temperature range, VIN = VOUT(NOM) + 1 V,
VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF, ADJ version: ADJ connected to VOUT (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA
LP2981A-XX LP2981-XX
UNIT
PARAMETER
TEST CONDITIONS
TAMIN TYP MAX MIN TYP MAX
UNIT
Output voltage
IL = 1 mA 25°C −0.75 0.75 −1.25 1.25
nV
OUT
Output voltage
tolerance
(see Note 5)
IL = 1 mA to 100 mA
25°C −1 1 −2 2 %V
NOM
nVOUT
tolerance
(see Note 5) IL = 1 mA to 100 mA −40°C to 125°C −2.5 2.5 −3.5 3.5
%VNOM
nVOUT/nVIN
Output voltage
VIN =
25°C 0.007 0.014 0.007 0.014
%/V
nVOUT/nVIN
Output voltage
line regulation
VIN =
[VOUT(NOM) + 1 V] to 16 V −40°C to 125°C 0.032 0.032 %/V
IL = 0
25°C 1 3 1 3
IL = 0 −40°C to 125°C 5 5
Dropout
IL = 1 mA
25°C 7 10 7 10
VIN-VOUT
Dropout
voltage
IL = 1 mA −40°C to 125°C 15 15
mV
VIN-VOUT
voltage
(see Note 6)
IL = 25 mA
25°C 70 100 70 100 mV
(see Note 6)
IL = 25 mA −40°C to 125°C 150 150
IL = 100 mA
25°C 200 250 200 250
IL = 100 mA −40°C to 125°C 375 375
IL = 0
25°C 65 95 65 95
IL = 0 −40°C to 125°C 125 125
IL = 1 mA
25°C 80 110 80 110
IL = 1 mA −40°C to 125°C 170 170
Ground pin
IL = 25 mA
25°C 200 300 200 300
I
GND
Ground pin
current
IL = 25 mA −40°C to 125°C 550 550 µA
IGND
current
IL = 100 mA
25°C 600 800 600 800
µA
IL = 100 mA −40°C to 125°C 1500 1500
VON/OFF < 0.3 V (OFF) 25°C 0.01 0.8 0.01 0.8
VON/OFF 0.15 V (OFF)
−40°C to 105°C 0.05 2 0.05 2
VON/OFF < 0.15 V (OFF
)
−40°C to 125°C 5 5
ON/OFF input
High = O/P ON
25°C 1.4 1.4
VON/OFF
ON/OFF input
voltage
High = O/P ON −40°C to 125°C 1.6 1.6
V
VON/OFF
voltage
(see Note 7)
Low = O/P OFF
25°C 0.5 0.5 V
(see Note 7)
Low = O/P OFF −40°C to 125°C 0.15 0.15
NOTES: 5. VOUT = VREF for ADJ version
6. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured
with a 1-V differential. This dropout specification does not apply to the 1.8-V option, as the minimum VIN = 2.2 V must be observed
for proper biasing of LDO control circuitry.
7. The ON/OFF input must be actively terminated. Connect to VIN if this function is not used (see Application Information).
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature range, VIN = VOUT(NOM) + 1 V,
VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF, ADJ version: ADJ connected to VOUT (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TA
LP2981A-XX LP2981-XX
UNIT
PARAMETER
TEST CONDITIONS
TAMIN TYP MAX MIN TYP MAX
UNIT
VON/OFF = 0
25°C 0.01 0.01
ION/OFF
ON/OFF input
VON/OFF = 0 −40°C to 125°C −1 −1
A
ION/OFF
ON/OFF input
current
VON/OFF = 5 V
25°C 5 5 µA
current
VON/OFF = 5 V −40°C to 125°C 15 15
IOUT(PK) Peak output
current VOUT ≥VOUT(NOM) − 5% 25°C 150 400 150 400 mA
VnOutput noise
voltage (RMS) BW = 300 Hz to 50 kHz,
COUT = 10 µF25°C 160 160 µV
nVOUT/nVIN Ripple
rejection f = 1kHz, COUT = 10 µF 25°C 63 63 dB
IOUT(MAX) Short-circuit
current RL = 0 (steady state) 25°C 150 150 mA
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12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
capacitors
input capacitor (Cin)
A minimum value of 1 mF (over the entire operating temperature range) is required at the input of the LP2981.
In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog
ground. There is no Equivalent Series Resistance (ESR) requirement for this capacitor, and the capacitance
can be increased without limit. A good quality ceramic or tantalum capacitor can be used.
output capacitor (Cout)
As a PNP regulator, the LP2981 requires the output capacitor to meet both a minimum capacitance and ESR
value. Required ESR values as a function of load current are provided for various output voltages, load currents,
and capacitances (see Figures 1–4).
Minimum Cout: 3.3 µF (can be increased without limit to improve transient response stability margin)
ESR range: see Figures 1–4
Figure 4. 5-V/3.3-µF ESR Curves Figure 5. 5-V/10-µF ESR Curves
Figure 6. 3-V/3.3-µF ESR Curves Figure 7. 3-V/10-µF ESR Curves
ESR − Ω
Load Current − mA
ESR − Ω
Load Current − mA
ESR − Ω
Load Current − mA
ESR − Ω
Load Current − mA
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APPLICATION INFORMATION
output capacitor (Cout) (continued)
It is critical that both the minimum capacitance and ESR requirement be met over the entire operating
temperature range. Depending on the type of capacitor used, both of these parameters can vary significantly
with temperature (see capacitor characteristics section).
capacitor characteristics
ceramics
Due to their very low ESR values, ceramic capacitors are not suitable for use as the output capacitor. For
instance, a typical 2.2-µF ceramic capacitor has an ESR in the range of 10 mΩ to 20 mΩ and, thus, easily can
fall out of minimum ESR requirements under certain operating conditions.
If a ceramic capacitor is used at the output, a 1-Ω resistor should be placed in series with the capacitor to raise
the ESR seen by the regulator.
tantalum
Solid tantalum capacitors are optimal choices for the LP2981, but they still must meet the minimum ESR
requirement. Note that the ESR of a tantalum capacitor increases as temperature drops, as much as double
from 25°C to −40°C. Thus, ESR margins must be maintained over the temperature range to prevent regulator
instability. For operation at very low temperatures, paralleling a tantalum capacitor with a ceramic one keeps
the combined ESR from increasing near the upper limit of the ESR curve.
aluminum
Aluminum capacitors can be used, but use with the LP2981 is impractical due to their large physical dimensions.
They also must meet the ESR requirements over the full temperature range. In this regard, aluminium capacitors
are at a big disadvantage due to their sharp ESR increase as temperature drops. For example, over a
temperature drop from 20°C to −40°C, the ESR of an aluminum electrolytic capacitor can increase by a factor
of 50. In addition, some of the electrolytes used in these capacitors can freeze at −25°C, making the capacitor
nonoperational.
ON/OFF operation
The LP2981 allows for a shutdown mode via the ON/OFF pin. If the shutdown feature is not used, ON/OFF
should be connected to the input to ensure that the regulator is on at all times. To drive ON/OFF:
•A LOW (≤0.3 V) turns the regulator OFF; a HIGH (≥1.6 V) turns it ON.
•Use either a totem-pole output or an open-collector output with a pullup resistor tied to VIN (or another
logic supply). The HIGH signal can exceed VIN, but must not exceed the absolute maximum ratings of
20 V for the ON/OFF pin.
•Apply a signal with a slew rate of ≥40 mV/µs. A slow slew rate can cause the shutdown function to
operate incorrectly.
ADJ version
From Figure 3, VOUT is set according to the following equation:
VOUT = VREF
ǒ1)RADJ
R1Ǔ
where V REF = 1.23 V (nominal). Under no-load conditions, a minimum “bias” current is required through the RADJ
and R1 divider to maintain regulator stability. Therefore, the maximum value for R1 should be X39.5 kΩ.
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
reverse input-output voltage
An inherent diode is present across the PNP pass element of the LP2981.
VOUT
VIN
With the anode connected to the output, this diode is reverse biased during normal operation, since the input
voltage is higher than the output. However, if the output is pulled one VBE higher than the input, or if the input
is abruptly stepped below the output, this diode is forward biased and can cause a parasitic silicon-controlled
rectifier (SCR) to latch, resulting in current flowing from the output to the input (values in excess of 100 mA can
cause damage). Thus, to prevent possible damage to the regulator in any application where the output may be
pulled above the input, an external Schottky diode must be connected between the output and input. With the
anode on output, this Schottky limits the reverse voltage across the output and input pins to 0.3 V, preventing
the regulator’s internal diode from forward biasing.
VOUT
VIN
Schottky
LP2981
pin 4: NC
Pin 4 must be left OPEN. Do not connect anything to this pin, as it is used for post package trim.
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WAFER CHIP SCALE INFORMATION
LP2981x-xxYEQ NanoStar (0.17-mm Bump)
LP2981x-xxYZQ NanoFree (0.17-mm Pb-Free Bump)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
1,287
1,337
Pin A1 Index Area 0,19
0,15
0,15
0,10
987
1,037
0,625 Max
SLVS521B − JULY 2004 − REVISED OCTOBER 2004
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WAFER CHIP SCALE INFORMATION
LP2981x-xxYEU NanoStar (0.30-mm Bump)
LP2981x-xxYZU NanoFree (0.30-mm Pb-Free Bump)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
1,287
1,337
Pin A1 Index Area 0,35
0,25
0,30
0,20
987
1,037
0,75 Max
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