120
100 10k 10M
-40
20
GAIN (dB)
1M
100k
1k
80
60
0
-20
40
100
FREQUENCY (Hz)
PHASE
GAIN
VS = 5V
120
-40
20
80
60
0
-20
40
100
PHASE (°)
CC1
+VOUT
+
-
-
CF
VIN
+
-
RB1
V+
RB2
R2
100 NŸ
R1
1 NŸ
Copyright © 2016, Texas Instruments Incorporated
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
LMV55x 3-MHz, Micropower RRO Amplifiers
1
1 Features
1• Specified 3-V and 5-V Performance
• High Unity Gain Bandwidth 3 MHz
• Supply Current (Per Amplifier) 37 µA
• CMRR 93 dB
• PSRR 90 dB
• Slew Rate 1 V/µs
• Output Swing With 100-kΩLoad 70 mV From Rail
• Total Harmonic Distortion: 0.003% at 1 kHz, 2 kΩ
• Temperature Range: −40°C to 125°C
2 Applications
• Active Filters
• Portable Equipment
• Automotive
• Battery Powered Systems
• Sensors and Instrumentation
3 Description
The LMV55x are high-performance, low-power
operational amplifiers implemented with TI’s
advanced VIP50 process. They feature 3 MHz of
bandwidth while consuming only 37 µA of current per
amplifier, which is an exceptional bandwidth to power
ratio in this op amp class. These ultra-low power
amplifiers are unity gain stable and provide an
excellent solution for ultra-low power applications
requiring a wide bandwidth.
The LMV55x have a rail-to-rail output stage and an
input common mode range that extends below
ground.
The LMV55x have an operating supply voltage range
from 2.7 V to 5.5 V. These amplifiers can operate
over a wide temperature range (−40°C to 125°C),
making them a great choice for automotive
applications, sensor applications as well as portable
instrumentation applications. The LMV551 is offered
in the ultra tiny 5-Pin SC70 and 5-Pin SOT-23
package. The LMV552 is offered in an 8-Pin VSSOP
package. The LMV554 is offered in the 14-Pin
TSSOP.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM551 SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
LMV552 VSSOP (8) 3.00 mm × 3.00 mm
LMV554 TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic Open Loop Gain and Phase vs Frequency
2
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics: 3 V................................... 6
6.6 Electrical Characteristics: 5 V................................... 7
6.7 Typical Characteristics.............................................. 9
7 Detailed Description............................................ 14
7.1 Overview................................................................. 14
7.2 Functional Block Diagram....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8 Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application.................................................. 18
8.3 Do's and Don'ts ...................................................... 20
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support................. 22
11.1 Device Support .................................................... 22
11.2 Documentation Support ....................................... 22
11.3 Related Links ........................................................ 22
11.4 Receiving Notification of Documentation Updates 22
11.5 Community Resource............................................ 22
11.6 Trademarks........................................................... 22
11.7 Electrostatic Discharge Caution............................ 23
11.8 Glossary................................................................ 23
12 Mechanical, Packaging, and Orderable
Information........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
Changes from Revision F (February 2013) to Revision G Page
• Changed layout of National Semiconductor Data Sheet to TI format. ................................................................................. 18
OUT A
IN A-
IN A+
V+
IN B+
IN B-
OUT B
1
2
3
4
5
6
7
+-
-+
OUT C
IN C-
IN C+
V-
IN D+
IN D-
OUT D
8
9
10
11
12
13
14
+
-
+
-A D
BC
OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
3
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
DBV and DCK Packages
5-Pin SOT-23 and SC70
Top View DGK Package
8-Pin VSSOP
Top View
PW Package
14-Pin TSSOP
Top View
4
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
(1) I = Input; O = Output; P = Power
Pin Functions: LMV551
PIN
TYPE(1) DESCRIPTION
NAME LMV551
SOT-23, SC70
+IN 1 I Noninverting Input
-IN 3 I Inverting Input
OUT 4 O Output
V- 2 P Negative Supply
V+ 5 P Positive Supply
(1) I = Input; O = Output; P = Power
Pin Functions: LMV552 and LMV554
PIN
TYPE(1) DESCRIPTION
NAME LMV552 LMV554
SOIC, VSSOP SOIC, TSSOP
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
+IN C — 10 I Noninverting input, channel C
+IN D — 12 I Noninverting input, channel D
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
–IN C — 9 I Inverting input, channel C
–IN D — 13 I Inverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C — 8 O Output, channel C
OUT D — 14 O Output, channel D
V+ 8 4 P Positive (highest) power supply
V– 4 11 P Negative (lowest) power supply
5
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and
specifications.
(3) The maximum power dissipation is a function of TJ(MAX),θJA, The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN Differential (at V+= 5 V) ±2.5 V
Supply voltage (V+– V−) 6 V
Voltage at input/output pins V−–0.3 V++0.3 V
Junction temperature, TJ(3) 150 °C
Storage temperature, Tstg –65 150 °C
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.
(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-
C101-C (ESD FICDM std. of JEDEC).
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge
Human-body model (HBM)(1) ±2000 V
Machine model (MM)(2) LMV551 ±100
LMV552 / LMV554 ±250
(1) The maximum power dissipation is a function of TJ(MAX),θJA, The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Temperature (1) –40 125 °C
Supply voltage (V+– V−) 2.7 5.5 V
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
LMV551 LMV552 LMV554
UNIT
DBV
(SOT-23) DCK
(SC70) DGK
(VSSOP) PW
(TSSOP)
5 PINS 5 PINS 8 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 213.6 303.5 200.3 134.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 174.8 135.5 89.1 60.9 °C/W
RθJB Junction-to-board thermal resistance 72.6 81.1 120.9 77.3 °C/W
ψJT Junction-to-top characterization parameter 56.6 8.4 21.7 11.5 °C/W
ψJB Junction-to-board characterization parameter 72.2 80.4 119.4 76.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W
6
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ= TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Positive current corresponds to current flowing into the device.
(4) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.
(5) Slew rate is the average of the rising and falling slew rates.
6.5 Electrical Characteristics: 3 V
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3 V, V−= 0 V, VCM = V+/2 = VO.(1)
PARAMETER TEST CONDITIONS MIN
(2) TYP(2) MAX(2) UNIT
VOS Input offset voltage TA= 25°C 1 3 mV
TA= –40°C to 125°C 4.5
TC VOS Input offset average drift TA= –40°C to 125°C 3.3 µV/°C
IBInput bias current(3) TA= 25°C 20 38 nA
IOS Input offset current TA= 25°C 1 20 nA
CMRR Common mode rejection
ratio 0 V ≤VCM 2 V TA= 25°C 74 92 dB
TA= –40°C to +125°C 72
PSRR Power supply rejection ratio
3≤V+≤5 V,
VCM = 0.5 V
LMV551 and
LMV552
TA= 25°C 80 92
dB
TA= –40°C to
+125°C 78
LMV554 TA= 25°C 78 92
TA= –40°C to
+125°C 76
2.7 ≤V+≤5.5 V,
VCM = 0.5 V
LMV551 and
LMV552
TA= 25°C 80 92
TA= –40°C to
+125°C 78
LMV554 TA= 25°C 78 92
TA= -40°C to
+125°C 76
CMVR Input common-mode voltage CMRR ≥68 dB TA= 25°C 0 2.1 V
CMRR ≥60 dB TA= -40°C to +125°C 0 2.1
AVOL Large signal voltage gain
0.4 ≤VO≤2.6,
RL= 100 kΩto V+/2
LMV551 and
LMV552
TA= 25°C 81 90
dB
TA= –40°C to
+125°C 78
LMV554 TA= 25°C 79 90
TA= –40°C to
+125°Ce 77
0.4 ≤VO≤2.6, RL=
10 kΩto V+/2 TA= 25°C 71 80
TA= -40°C to +125°C 68
VO
Output swing high
RL= 100 kΩto V+/2 TA= 25°C 40 48
mV from
rail
TA= –40°C to
+125°C 58
RL= 10 kΩto V+/2 TA= 25°C 85 100
TA= –40°C to
+125°C 120
Output swing low
RL= 100 kΩto V+/2 TA= 25°C 50 65
TA= –40°C to
+125°C 77
RL= 10 kΩto V+/2 TA= 25°C 95 110
TA= –40°C to
+125°C 130
ISC Output short circuit current Sourcing (4) 10 mA
Sinking (4) 25
ISSupply current per amplifier TA= 25°C 34 42 µA
TA= –40°C to +125°C 52
SR Slew rate AV= +1,
10% to 90% (5) 1 V/µs
7
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
Electrical Characteristics: 3 V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3 V, V−= 0 V, VCM = V+/2 = VO.(1)
PARAMETER TEST CONDITIONS MIN
(2) TYP(2) MAX(2) UNIT
Φm Phase margin RL= 10 kΩ, CL= 20 pF 75 °
GBW Gain bandwidth product 3 MHz
enInput-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
InInput-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 kΩ0.003%
(1) Electrical Table values apply only for factor testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ= TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Positive current corresponds to current flowing into the device.
(5) The part is not short-circuit protected and is not recommended for operation with heavy resistive loads.
6.6 Electrical Characteristics: 5 V
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2 = VO.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VOS Input offset voltage TA= 25°C 1 3 mV
TA= –40°C to +125°C 4.5
TC VOS Input offset average drift TA= 25°C 3.3 µV/°C
IBInput bias current (4) TA= 25°C 20 38 nA
IOS Input offset current 1 20 nA
CMRR Common mode rejection ratio TA= 25°C 76 93 nA
TA= –40°C to +125°C 74
PSRR Power supply rejection ratio 3 V ≤V+≤5 V to VCM = 0.5 V TA= 25°C 78 90
dB
TA= –40°C to +125°C 75
2.7 V ≤V+≤5.5 V to VCM = 0.5 V TA= 25°C 78 90
TA= –40°C to +125°C 75
CMVR Input common-mode voltage CMRR ≥68 dB
CMRR ≥60 dB TA= 25°C 0 4.1 V
TA= –40°C to +125°C 0 4.1
AVOL Large signal voltage gain 0.4 ≤VO≤4.6, RL= 100 kΩto V+/2 78 90
dB
75
0.4 ≤VO≤4.6, RL= 10 kΩto V+/2 75 80
72
VO
Output swing high RL= 100 kΩto V+/2 TA= 25°C 70 92
mV from
rail
TA= –40°C to +125°C 122
RL= 10 kΩto V+/2 TA= 25°C 125 155
TA= –40°C to +125°C 210
Output swing low RL= 100 kΩto V+/2 TA= 25°C 60 70
TA= –40°C to +125°C 82
RL= 10 kΩto V+/2 TA= 25°C 110 130
TA= –40°C to +125°C 155
ISC Output short-circuit current Sourcing (5) 10 mA
Sinking (5) 25
ISSupply current per amplifier TA= 25°C 37 46 µA
TA= –40°C to +125°C 54
8
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Electrical Characteristics: 5 V (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2 = VO.(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
(6) Slew rate is the average of the rising and falling slew rates.
SR Slew rate AV= +1, VO= 1 VPP
10% to 90% (6) 1 V/µs
Φm Phase margin RL= 10 kΩ, CL= 20 pF 75 °
GBW Gain bandwidth product 3 MHz
enInput-referred voltage noise f = 100 kHz 70 nV/√Hz
f = 1 kHz 70
InInput-referred current noise f = 100 kHz 0.1 pA/√Hz
f = 1 kHz 0.15
THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 kΩ0.003%
33.25 3.5 3.75 4 4.25 4.5 4.75 5
VS (V)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
SLEW RATE (V/Ps)
RISING EDGE
FALLING EDGE
140
100 10k 10M
-20
40
GAIN (dB)
1M
100k
1k
100
80
20
0
60
120
FREQUENCY (Hz)
PHASE
GAIN
VS = 5V
RL = 100 k:
CL = 20 pF
158
-23
45
113
90
23
0
68
135
PHASE (°)
140
100 10k 10M
-20
40
GAIN (dB)
1M
100k
1k
100
80
20
0
60
120
FREQUENCY (Hz)
PHASE
GAIN
VS = 3V
RL = 10 k:
CL = 20 pF
158
-23
45
113
90
23
0
68
135
PHASE (°)
140
100 10k 10M
-20
40
GAIN (dB)
1M
100k
1k
100
80
20
0
60
120
FREQUENCY (Hz)
158
-23
45
113
90
23
0
68
135
PHASE (°)
GAIN
PHASE 20 pF
50 pF
100 pF
100 pF
50 pF
20 pF
VS = +5V
RL = 100 k:
140
100 10k 10M
-20
40
GAIN (dB)
1M
100k
1k
100
80
20
0
60
120
FREQUENCY (Hz)
PHASE
GAIN
VS = +3V
RL = 100 k:
CL = 20 pF
158
-23
45
113
90
23
0
68
135
PHASE (°)
9
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
6.7 Typical Characteristics
Figure 1. Open-Loop Gain and Phase With Capacitive Load Figure 2. Open-Loop Gain and Phase With Resistive Load
Figure 3. Open-Loop Gain and Phase With Resistive Load Figure 4. Open-Loop Gain and Phase With Resistive Load
Figure 5. Open-Loop Gain and Phase With Resistive Load Figure 6. Slew Rate vs Supply voltage
0.01 0.1 1 10
0.00
0.01
0.10
1.00
THD+N (%)
VOUT (VPP)
VS = 3V
AV = +2
VIN = 1 kHz SINE WAVE
RL = 10 k:
RL = 100 k:
0.01 0.1 1 10
0.00
0.01
0.10
1.00
THD+N (%)
VOUT (VPP)
VS = 5V
AV = +2
VIN = 1 kHz SINE WAVE
RL = 10 k:
RL = 100 k:
0.1 110 100 10k
FREQUENCY (Hz)
0
0.1
100
1000
1k
1
10
INPUT REFERRED NOISE
VOLTAGE nV/ Hz
CURRENT pA/ Hz
0 20 40 60 80
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
VOUT (V)
TIME (Ps)
VS = 5V
CL = 15 pF
VIN = 20 mVPP, 20 kHz
0 20 40 60 80 100
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
VOUT (V)
TIME (Ps)
VS = 5V
CL = 50 pF
VIN = 20 mVPP, 20 kHz
0 20 40 60 80 100
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (Ps)
VS = 5V
CL = 15 pF, AV = +1
VIN = 2 VPP, 20 kHz
10
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Figure 7. Small-Signal Transient Response Figure 8. Large-Signal Transient Response
Figure 9. Small-Signal Transient Response Figure 10. Input Referred Noise vs Frequency
Figure 11. THD+N vs Amplitude at 3 V Figure 12. THD+N vs Amplitude at 5 V
2.7 3.4 4.1 4.8 5.5
VS (V)
-2
-1.5
-1
0
2
VOS (mV)
1
1.5
125qC
25qC
-40qC
-0.5
0.5
0 1 2 3 4 5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
VOS (mV)
VCM (V)
VS = 5V
-40qC25qC
125qC
2.7 3.4 4.1 4.8 5.5
VS (V)
20
25
30
35
50
IS (PA)
40
45 PER CHANNEL
125°C
25°C
-40°C
0 0.5 1 1.5 2 2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
VOS (mV)
VCM (V)
VS = 3V
-40qC25qC
125qC
10 100 1k 10k 100k
0.001
0.01
0.1
THD+N (%)
FREQUENCY (Hz)
1
RL = 10 k:
RL = 100 k:
VS = 5V
AV = +2
VOUT = 2 VPP
10 100 1k 10k 100k
0.001
0.01
0.1
THD+N (%)
FREQUENCY (Hz)
1
RL = 10 k:
RL = 100 k:
VS = 3V
AV = +2
VOUT = 1 VPP
11
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Figure 13. THD+N vs Amplitude Figure 14. THD+N vs Amplitude
Figure 15. Supply Current vs Supply Voltage Figure 16. VOS vs VCM
Figure 17. VOS vs VCM Figure 18. VOS vs Supply Voltage
3 3.5 4 4.5 5
20
30
40
50
60
70
80
90
100
VOUT FROM RAIL (mV)
VS (V)
-40°C
25°C
125°C
RL = 100 k:
3 3.5 4 4.5 5
20
30
40
50
60
70
80
90
100
VOUT FROM RAIL (mV)
VS (V)
-40°C
25°C
125°C
RL = 100 k:
2.5 3 3.5 4 4.5 5.5
10
12
14
16
18
20
22
24
26
IBIAS (nA)
VS (V)
-40° C
25°C
125°C
5
3 3.5 4 4.5 5
20
40
60
80
100
120
140
160
180
VOUT FROM RAIL (mV)
VS (V)
-40°C
25°C
125°C
RL = 10 k:
0 0.5 1 1.5 2 2.5
10
12
14
16
18
20
22
24
26
IBIAS (nA)
VCM (V)
-40°C
25°C 125°C
VS = 3V
0 1 2 3 4 5
10
12
14
16
18
20
22
24
26
IBIAS (nA)
VCM (V)
-40°C
25°C
125°C
VS = 5V
12
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Figure 19. IBIAS vs VCM Figure 20. IBIAS vs VCM
Figure 21. IBIAS vs Supply Voltage Figure 22. Positive Output Swing vs Supply Voltage
Figure 23. Negative Output Swing vs Supply Voltage Figure 24. Positive Output Swing vs Supply Voltage
3 3.5 4 4.5 5
20
40
60
80
100
120
140
160
180
VOUT FROM RAIL (mV)
VS (V)
-40°C
25°C
125°C
RL = 10 k:
13
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
Typical Characteristics (continued)
Figure 25. Negative Output Swing vs Supply Voltage
14
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The LMV55x are high performance, low power operational amplifiers implemented with TI’s advanced VIP50
process. They feature 3 MHz of bandwidth while consuming only 37 µA of current per amplifier, which is an
exceptional bandwidth to power ratio in this op amp class. These amplifiers are unity gain stable and provide an
excellent solution for low power applications requiring a wide bandwidth.
7.2 Functional Block Diagram
(Each Amplifier)
7.3 Feature Description
The differential inputs of the amplifier consist of a noninverting input (+IN) and an inverting input (–IN). The
amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input
voltage. The output voltage of the op-amp VOUT is given by Equation 1:
VOUT = AOL (IN+- IN-)
where
• AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10 uV per volt). (1)
7.3.1 Low Voltage and Low Power Operation
The LMV55x have performance ensured at supply voltages of 3 V and 5 V and are ensured to be operational at
all supply voltages from 2.7 V to 5.5 V. For this supply voltage range, the LMV55x draw the extremely low supply
current of less than 37 μA per amp.
7.3.2 Wide Bandwidth
The bandwidth to power ratio of 3 MHz to 37 μA per amplifier is one of the best bandwidth to power ratios ever
achieved. This makes these devices ideal for low power signal processing applications such as portable media
players and instrumentation.
7.3.3 Low Input Referred Noise
The LMV55x provide a flatband input referred voltage noise density of 70 nV/√Hz , which is significantly better
than the noise performance expected from an ultra low power op amp. They also feature the exceptionally low 1/f
noise corner frequency of 4 Hz. This noise specification makes the LMV55x ideal for low power applications such
as PDAs and portable sensors.
7.3.4 Ground Sensing and Rail-to-Rail Output
The LMV55x each have a rail-to-rail output stage, which provides the maximum possible output dynamic range.
This is especially important for applications requiring a large output swing. The input common mode range
includes the negative supply rail which allows direct sensing at ground in a single supply operation.
0
UNSTABLE
ROC = 40 dB/decade
STABLE
ROC ± 20 dB/decade
FREQUENCY (Hz)
GAIN
15
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
Feature Description (continued)
7.3.5 Small Size
The small footprints of the LMV55x packages save space on printed circuit boards, and enable the design of
smaller and more compact electronic products. Long traces between the signal source and the op amp make the
signal path susceptible to noise. By using a physically smaller package, the amplifiers can be placed closer to
the signal source, reducing noise pickup and enhancing signal integrity.
7.4 Device Functional Modes
7.4.1 Stability Of Op Amp Circuits
7.4.1.1 Stability and Capacitive Loading
As seen in the Phase Margin vs Capacitive Load graph, the phase margin reduces significantly for CLgreater
than 100 pF. This is because the op amp is designed to provide the maximum bandwidth possible for a low
supply current. Stabilizing them for higher capacitive loads would have required either a drastic increase in
supply current, or a large internal compensation capacitance, which would have reduced the bandwidth of the op
amp. Hence, if the LMV55x are to be used for driving higher capacitive loads, they must be externally
compensated.
Figure 26. Gain vs Frequency for an Op Amp
An op amp, ideally, has a dominant pole close to DC, which causes its gain to decay at the rate of 20 dB/decade
with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until
the op amp’s unity gain bandwidth, the op amp is stable. If, however, a large capacitance is added to the output
of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency
response before its unity gain frequency (Figure 26). This increases the ROC to 40 dB/ decade and causes
instability.
In such a case a number of techniques can be used to restore stability to the circuit. The idea behind all these
schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which
ensures stability.
7.4.1.1.1 In the Loop Compensation
Figure 27 illustrates a compensation technique, known as ‘in the loop’ compensation, that employs an RC
feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series
resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF,
is inserted across the feedback resistor to bypass CLat higher frequencies.
¨
¨
©
§RF + 2RIN
RF2
¨
¨
©
§
CLROUT
CF = ¨
¨
©
§1
ACL
¨
¨
©
§
1 +
RS = ROUTRIN
RF
ROUT
-
+
VIN
RF
CF
RIN
RL
CL
RS
Copyright © 2016, Texas Instruments Incorporated
16
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Device Functional Modes (continued)
Figure 27. In the Loop Compensation
The values for RSand CFare decided by ensuring that the zero attributed to CFlies at the same frequency as the
pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for
by the presence of the zero, and that the ROC is maintained at 20 dB/decade. For the circuit shown in Figure 27
the values of RSand CFare given by Equation 2. Values of RSand CFrequired for maintaining stability for
different values of CL, as well as the phase margins obtained, are shown in Table 1. RF, RIN, and RLare to be 10
kΩ, while ROUT is 340Ω.
(2)
Table 1. Phase Margins
CL(pF) RS(Ω) CF(pF) PHASE MARGIN (°)
50 340 8 47
100 340 15 42
150 340 22 40
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed loop bandwidth of the circuit is now limited by RFand CF.
Copyright © 2016, Texas Instruments Incorporated
+
±VIN
RISO
CL
VOUT
17
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
7.4.1.1.2 Compensation by External Resistor
In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the
loop compensation is not viable. A simpler scheme for compensation is shown in Figure 28. A resistor, RISO, is
placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer
function, which counteracts the effect of the pole formed by the load capacitance and ensures stability. The value
of RISO to be used should be decided depending on the size of CLand the level of performance desired. Values
ranging from 5 Ωto 50 Ωare usually sufficient to ensure stability. A larger value of RISO results in a system with
less ringing and overshoot, but also limits the output swing and the short-circuit current of the circuit.
Figure 28. Compensation by Isolation Resistor
+
R3
R2 R1
C1
C2
VIN VOUT
R4
18
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV55x have an operating supply voltage range from 2.7 V to 5.5 V. These amplifiers can operate over a
wide temperature range (−40°C to 125°C), making them a great choice for automotive applications, sensor
applications as well as portable instrumentation applications.
With a wide unity gain bandwidth of 3 MHz, low input referred noise density and an excellent BW to supply
current ratio, the LMV55x are well suited for low-power filtering applications. Active filter topologies, such as the
Sallen-Key low pass filter shown in Figure 29, are very versatile, and can be used to design a wide variety of
filters (Chebyshev, Butterworth or Bessel). For best results, the amplifier must have a bandwidth that is eight to
ten times the filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier
and premature roll-off. The Sallen-Key topology, in particular, can be used to attain a wide range of Q, by using
positive feedback to reject the undesired frequency range.
8.2 Typical Application
Figure 29. Two Pole Sallen-Key Low Pass Filter
8.2.1 Design Requirements
As a design example:
Require: ALP = 10, less than 1dB passband ripple, and a cutoff frequency of 1kHz.
8.2.2 Detailed Design Procedure
There are many resources discussing the Sallen-Key lowpass filter topology.
Texas Instruments has made filter design easy by creating on-line and stand alone design tools, such as
Webench Filter Designer and Filter Pro Desktop.
For this design, the stand-alone Filter Pro Desktop is used.
For the design, the following parameters are entered into the Filterpro software:
1. Filter Type = Lowpass
2. Gain = 10 V/V (20dB)
3. Passband Frequency = 1 kHz
19
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
Typical Application (continued)
4. Allowable Ripple = 1 dB
5. Filter Order = Checked and set to 2
6. Response Type = Butterworth
7. Filter Topology = Sallen-Key
8. Component Tolerance - Resistor = E96 1%
9. Component Tolerance - Capacitor = E6 20%
After entering these values, FilterPro returns the following recommended values:
1. R1 = 44.2 kΩ
2. R2 = 38.3 kΩ
3. R3 = 2.49 kΩ
4. R4 = 22.6 kΩ
5. C1 = 10 nF
6. C2 = 1.5 nF
The LMV55x is targeted for low power operation. The above resistor values are assumed for a standard power
application. To save power, both quiescent and dynamic, the values of the resistors can be increased.
The largest consumer of power is the gain setting feedback resistors R3 and R4, as these are DC coupled and
represent a constant DC load to the amplifier. If the output is biased at 2.5 V, then 2.5 V / (22.6 k + 2.49 k) =
99.6 µA is flowing through the feedback network. This is significantly more than the 37uA quiescent current of the
amplifier alone! Increasing the size of the feedback resistors by a decade from 22.6k to 226k, the current in the
feedback network can be reduced down to 9.9uA.
Increasing the resistor values requires a proportional decrease in the values of the capacitors. If a resistor value
is increased 10×, then the corresponding capacitor value must be decreased 10×. However, note that increasing
the resistor values increases the contributed noise, and decreasing the capacitors to small values increases the
sensitivity to stray capacitance.
There is a decision to be made about also scaling the filter components (R1, R2, C1 & C2). R1 and R2 are AC
coupled to the output, so the only DC current flowing through these resistors is the input bias current of the
LMV55x (typically 20 nA). However, large AC currents can flow through C2 and C1 during large signal swings.
Scaling the filter components also reduces the peak AC signal currents. If the AC signals are expected to large
(several Vpp) and frequent, then scaling the filter values may be beneficial to overall power consumption. If the
expected AC signals are small, it may not be worth the noise tradeoff to scale these values.
Because the LMV55x has a bipolar input, to maintain DC accuracy, the equivalent resistance seen by each
amplifier input should be equal to cancel the bias current effects.
To maintain DC accuracy through bias current cancelling, the following relationship should be maintained:
(R1 + R2) = (R3 // R4) (3)
Fortunately, the filter Pro software makes changing and recalculating the values easy. By changing the value of
any of the filter components (R1, R2, C1 & C2) in the schematic tab, the program automatically recalculates and
scale these components. Conversely, changing the gain feedback components (R3 or R4) also causes the other
feedback resistor to scale. However, Filter Pro does NOT maintain the relationship between the feedback and
filter elements as described in Equation 3 above. The feedback resistor values can be 'seeded' and scaled
appropriately, as long as the original feedback resistor ratio is maintained.
10 100 1k 10k 100k
-30
-20
-10
0
10
20
30
Gain (dB)
Frequency (Hz)
C001
-3dB @ 1kHz
+
R3
634NŸ
R2
158NŸ
R1
158NŸ
C1
1nF
C2
1nF
VIN VOUT
R4
634NŸ
20
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
Typical Application (continued)
Figure 30. 1kHz Sallen-Key Low Pass Filter with Values
8.2.3 Application Curve
Figure 31 shows the simulated results of the example 1-KHz Sallen-Key Low Pass Filter.
Figure 31. 1KHz, 2-Pole Sallen-Key Low Pass Filter Results
8.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩper volt).
21
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single-
supply, place a capacitor between V+and V−supply leads. For dual supplies, place one capacitor between V+
and ground, and one capacitor between V-and ground.
10 Layout
10.1 Layout Guidelines
The V+pin should be bypassed to ground with a low-ESR capacitor.
The optimum placement is closest to the V+and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V+and ground.
The ground pin should be connected to the PCB ground plane at the pin of the device.
The feedback components should be placed as close to the device as possible minimizing strays.
10.2 Layout Example
Figure 32. SOT-23 Layout Example
22
LMV551
,
LMV552
,
LMV554
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
www.ti.com
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV551 PSPICE Model (SNOM060)
LMV552 PSPICE Model (SNOM061)
LMV554 PSPICE Model (SNOM062)
TINA-TI SPICE-Based Analog Simulation Program
DIP Adapter Evaluation Module
TI Universal Operational Amplifier Evaluation Module
TI Filterpro Software
11.2 Documentation Support
11.2.1 Related Documentation
For additional applications, see the following: AN-31 Op Amp Circuit Collection (SNLA140)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LMV551 Click here Click here Click here Click here Click here
LMV552 Click here Click here Click here Click here Click here
LMV554 Click here Click here Click here Click here Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
23
LMV551
,
LMV552
,
LMV554
www.ti.com
SNOSAQ5H –FEBRUARY 2007–REVISED AUGUST 2016
Product Folder Links: LMV551 LMV552 LMV554
Submit Documentation FeedbackCopyright © 2007–2016, Texas Instruments Incorporated
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Feb-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV551MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AF3A
LMV551MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AF3A
LMV551MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94
LMV551MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A94
LMV552MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH3A
LMV552MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AH3A
LMV554MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV55
4MT
LMV554MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV55
4MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Feb-2016
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV551MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV551MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV551MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV551MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV552MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV552MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV554MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV551MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV551MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV551MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV551MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV552MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV552MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMV554MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LMV554MT/NOPB LMV554MTX/NOPB