4
Layout and Power Supplies
The HI5703 evaluation board is a three layer board with a
layout optimized for the best performance of the ADC. The
application note includes an electrical schematic of the eval-
uation board, a component layout and the various board lay-
ers. The user should feel free to copy the layout in their
application. Refer to the component layout and the evalua-
tion board electrical schematic for the following discussion.
The HI5703 A/D has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The evaluation board provides separate low imped-
ance analog and digital ground planes. Since the analog and
digital ground planes are connected together under the
ADC, DO NOT tie them together back at the power supplies.
The analog and digital supplies are also kept separate on the
evaluation board and should be driven by clean linear regu-
lated supplies. They can be hooked up with external 20 gauge
wires to the holes marked AVCC1,AV
CC2,AV
EE,DV
CC1,
DVCC2,DV
EE, AGND and DGND in the prototyping area.
DVCC1,DV
CC2, and DVEE are digital supplies and should be
returned to DGND. AVCC1,AV
CC2, and AVEE are the analog
supplies and should be returned to AGND. Table 1 lists the
operational supply voltages for the evaluation board. Single
supply operation of the converter is possible but the overall
perf ormance of the converter may deg r ade .
Configuration Jumpers
The evaluation board is provided with eight removable jump-
ers (JP1-8) that allow for various operational configurations.
The following is a description of the feature provided by each
of the configuration jumpers.
JP1 is used to establish the analog signal path input to the
HI5703 A/D through the VIDEO SMA input connector.
JP2 is used to connect the HI5703 bias voltage output (VDC)
to the differential inputs, VIN+ and VIN-, of the A/D.
JP3 is used to connect an external user supplied DC bias
voltage to the differential inputs, VIN+ and VIN-, of the A/D.
JP4 configures the digital output data format of the HI5703
by setting the logic level of the Data Format Select (DFS)
input pin. With the JP4 jumper installed DFS is set to a logic
“0” establishing the digital data output format to offset binary.
With the JP4 jumper removed DFS is set to a logic “1” estab-
lishing the digital data output format to two’s complement.
JP5 is used to connect the evaluation board positive refer-
ence voltage generator output, nominally +3.25V, to the
HI5703 positive reference voltage input pin, VREF+.
JP6 is used to connect the evaluation board negative refer-
ence voltage generator output, nominally +2.0V, to the
HI5703 negative reference voltage input pin, VREF-.
JP7 is used to control the operational state of the HI5703
digital output drivers. With JP7 installed the digital Output
Enable (OE) control input pin is set to a logic “0” enabling the
digital data outputs. To place the digital data outputs in the
three-state high impedance mode, JP7 is removed and and
a TTL logic “1” needs to be applied to the jumper pin con-
nected to the HI5703 digital Output Enable (OE) control
input pin.
JP8 is used to supply the HI5703 digital output supply pin
(DVCC2) with the desired output logic operating voltage
level. With JP8 installed the HI5703 digital output supply is
connected to the evaluation board +5V digital supply,
DVCC1. For operation of the digital outputs at voltages from
+3.3V to +5V, JP8 is removed and the desired operating volt-
age needs to be applied to the jumper pin connected to the
HI5703 A/D digital output supply pin (DVCC2, pin 23).
Reference Voltage Generator Circuit
The HI5703 A/D contains a resistive ladder between the
reference voltage input pins. The A/D requires two reference
voltages, one connected to the VREF+ input pin and the
other connected to the VREF- input pin. The reference
voltage that drives VREF+ must be able to source the
maximum reference current which will then flow into the
VREF- reference. The HI5703 is tested with VREF- equal to
2V and VREF+ equal to 3.25V for a fully differential analog
input voltage range of ±1.25V. VREF+ and VREF- can differ
from the above voltages as long as the reference common
mode voltage, (VREF++V
REF-)/2, at the reference pins
does not exceed 2.625V ±50mV.
The reference circuit on the evaluation board contains a pre-
cision +2.5V reference (U4) along with operational amplifiers
(U5A and U5B) that are utilized to generate the reference
voltages for the HI5703. The reference voltages are set at
the factory to the levels required by the HI5703 as follows.
The VREF- reference input is set FIRST by monitoring JP6
with a DVM and adjusting R11 until a reading of 2.0V ±5mV
is obtained. Next the VREF+ reference input is set by moni-
toring JP5 with a DVM and adjusting R15 until a reading of
3.25V ±5mV is obtained.
Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5703, the duty
cycle of the sample clock should be held at 50%. It must also
have low phase noise and operate at standard TTL levels.
It can be difficult to find a low phase noise generator that will
provide a 40MHz squarewave at TTL logic levels. Therefore,
a TTL voltage comparator (U3) is provided on the evaluation
board to generate a TTL level sampling clock for the HI5703
when a sinewave (< ±3V) or squarewave clock is applied to
TABLE 1. EVALUATION BOARD POWER SUPPLIES
POWER
SUPPLY MIN TYP MAX
AVCC1 +4.75V +5.0V +5.25V
AVCC2 +4.75V +5.0V +5.25V
AVEE -5.25V -5.0V -4.75V
DVCC1 +4.75V +5.0V +5.25V
DVCC2 +4.75V +5.0V +5.25V
DVEE -5.45V -5.2V -4.95V
Application Note 9534