W681310SGT&R - Winbond Electronics

Publication Release Date: September 2005

- 1 - Revision B13

W681310

3V SINGLE-CHANNEL VOICEBAND CODEC

Data Sheet

W681310

- 2 -

1. GENERAL DESCRIPTION

The W681310 is a general-purpose single channel PCM CODEC with pin-selectable μ-Law or A-Law

companding. The device is compliant with the ITU G.712 specification. It operates from a single +3V

power supply and is available in 20-pin SOG, SSOP and TSSOP package options. Functions

performed include digitization and reconstruction of voice signals, and band limiting and smoothing

filters required for PCM systems. W681310 performance is specified over the industrial temperature

range of –40°C to +85°C.

The W681310 includes an on-chip precision voltage reference and an additional power amplifier,

capable of driving 300Ω loads differentially up to a level of 3.544V peak-to-peak. The analog section is

fully differential, reducing noise and improving the power supply rejection ratio. The data transfer

protocol supports both long-frame and short-frame synchronous communications for PCM

applications, and IDL and GCI communications for ISDN applications. W681310 accepts eight master

clock rates between 256 kHz and 4.800 MHz, and an on-chip pre-scaler automatically determines the

division ratio for the required internal clock.

For fast evaluation and prototyping purposes, the W681310DK development kit is available.

2. FEATURES

• Single +3V power supply (2.7V to 5.25V)

• Typical power dissipation of 10 mW,

power-down mode of 0.5 μW

• Fully-differential analog circuit design

• On-chip precision reference of 0.886 V for

a -5 dBm TLP at 600 Ω

• Push-pull power amplifiers with external

gain adjustment with 300 Ω load capability

• Eight master clock rates of 256 kHz to

4.800 MHz

• Pin-selectable μ-Law and A-Law

companding (compliant with ITU G.711)

• CODEC A/D and D/A filtering compliant

with ITU G.712

• Industrial temperature range (–40°C to

+85°C)

• Packages: 20-pin SOG (SOP), SSOP and

TSSOP

• Pb-Free package options available

• ApplIcations

• VoIP, Voice over Networks

• Digital telephone and communication

systems

• Wireless voice devices

• PABX/SOHO systems

• Local loop card

• SOHO routers

• Fiber-to-curb equipment

• Enterprise phones

• ISDN equipment

• Modems/PC cards

• Digital Voice Recorders

W681310

Publication Release Date: September 2005

- 3 - Revision B13

3. BLOCK DIAGRAM

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

4096 kHz

MCLK 256 kHz

8 kHz

512 kHz

Pre - scaler

Power Conditioning

Voltage reference V

PUI

G.712 CODEC

G.711

/A -Law

PAO+

PAO-

PAI

RO-

AI+

AI-

/A-Law

Tra

mit

Int

erf

ace

cei

Int

erf

ace

FST

BCLKT

PCMT

FSR

BCLKR

PCMR

REF

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

MCLK 256 kHz

8 kHz

Pre - Scaler

Power Conditioning

Voltage reference V

G.712 CODEC

G.711

/A -Law

/A-Law

G.712 CODEC

G.711

/A -Law

/A-Law

Transmit

PCM

Interface

Receive

PCM

Interface

BCLKT BCLKT

BCLKR

& 4800 kHz

W681310

- 4 -

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM .............................................................................................................................. 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION............................................................................................................ 8

7.1. Transmit Path ................................................................................................................................8

7.2. Receive Path .................................................................................................................................9

7.3. Power Management....................................................................................................................... 9

7.3.1. Analog and Digital Supply.....................................................................................................10

7.3.2. Analog Ground Reference Bypass .......................................................................................10

7.3.3. Analog Ground Reference Voltage Outpt .............................................................................10

7.4. PCM INTERFACE .......................................................................................................................10

7.4.1. Long Frame Sync.................................................................................................................. 11

7.4.2. Short Frame Sync ................................................................................................................. 11

7.4.3. General Circuit Interface (GCI) .............................................................................................11

7.4.4. Interchip Digital Link (IDL)..................................................................................................... 12

7.4.5. System Timing ......................................................................................................................12

8. TIMING DIAGRAMS.......................................................................................................................... 13

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20

9.1. Absolute Maximum Ratings.........................................................................................................20

9.2. Operating Conditions ................................................................................................................... 20

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21

10.1. General Parameters ..................................................................................................................21

10.2. Analog Signal Level and Gain Parameters ...............................................................................22

10.3. Analog Distortion and Noise Parameters .................................................................................. 23

10.4. Analog Input and Output Amplifier Parameters.........................................................................24

10.5. DIGITAL I/O ...............................................................................................................................26

10.5.1. μ-Law Encode Decode Characteristics...............................................................................26

10.5.2. A-Law Encode Decode Characteristics .............................................................................. 27

10.5.3. PCM Codes for Zero and Full Scale ...................................................................................28

10.5.4. PCM Codes for 0dBm0 Output ........................................................................................... 28

11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29

12. PACKAGE SPECIFICATION .......................................................................................................... 31

W681310

Publication Release Date: September 2005

- 5 - Revision B13

12.1. 20L SOG (SOP)-300mil.............................................................................................................31

12.2. 20L SSOP-209 mil .....................................................................................................................32

12.3. 20L TSSOP - 4.4X6.5mm ..........................................................................................................33

13. ORDERING INFORMATION........................................................................................................... 34

14. VERSION HISTORY ....................................................................................................................... 35

W681310

- 6 -

5. PIN CONFIGURATION

SINGLE

CHANNEL

CODEC

SOG/SSOP/TSSOP

REF

RO -

PAI

PAO-

PAO+

FSR

PCMR

BCLKR

PUI

AI+

AI-

FST

PCMT

BCLKT

MCLK

SINGLE

CHANNEL

CODEC

RO -

FSR

BCLKR

/A-Law

BCLKT

MCLK

W681310

Publication Release Date: September 2005

- 7 - Revision B13

6. PIN DESCRIPTION

Name

No.

Functionality

VREF 1 This pin is used to bypass the on-chip VDD/2 voltage reference. It needs to be decoupled to VSS

through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin.

RO- 2

Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 0.886

volt peak referenced to the analog ground level.

PAI 3 This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.

PAO- 4 Inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially to

1.772 volt peak referenced to the VAG voltage level.

PAO+ 5 Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300 Ω load differentially

to 1.772 volt peak referenced to the VAG voltage level.

VDD 6 Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.

FSR 7 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or

channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit

and receive are synchronous operations.

PCMR 8 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.

BCLKR 9 PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is

selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.

This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.

PUI 10 Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,

the part is powered down.

MCLK 11 System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544

kHz, 2048 kHz, 2560 kHz, 4096 kHz & 4800 kHz. For a better performance, it is recommended

to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in

the case of 256 and 512 kHz frequency.

BCLKT 12 PCM transmit bit clock input pin. This pin accepts clocks of 512 kHz to 6176 kHz in the GCI

mode and 256 kHz to 4800kHz in all other PCM modes.

PCMT 13 PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.

FST 14 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.

VSS 15 This is the supply ground. This pin should be connected to 0V.

μ/A-Law 16 Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law

companding is selected when this pin is tied to VSS.

AO 17 Analog output of the first gain stage in the transmit path.

AI- 18 Inverting input of the first gain stage in the transmit path.

AI+ 19 Non-inverting input of the first gain stage in the transmit path.

VAG 20 Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for all-analog

signal processing. This pin should be decoupled to VSS with a 0.01μF capacitor. This pin

becomes high impedance when the chip is powered down.

W681310

- 8 -

7. FUNCTIONAL DESCRIPTION

W681310 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC

complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a

complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply

with the specifications of the ITU-T G.711 recommendation.

The block diagram in section 3 shows the main components of the W681310. The chip consists of a

PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.

The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate

with the external frame sync frequency. The power conditioning block provides the internal power

supply for the digital and the analog section, while the voltage reference block provides a precision

analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in

section 3.

PAO

Cont

Ant

Aliasi

Fil

Ant

Aliasi

Figure 7.1 The W681310 Signal Path

7.1. Transmit Path

The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain

setting (see application examples in section 11). The device has an input operational amplifier whose

output is the input to the encoder section. If the input amplifier is not required for operation it can be

powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or

the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The

input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected as

an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see

Table 7.1).

Fil

200

High

Pas

Fil

oot

Filter

oot

Filter

PAI

+ -

Ant

Fil

Aliasing

Fil

Ant

Fil

High Pass

Fil

ter

oot

hin

Filter

Smoothing

Filter

Receive Path

Transmit Path

A +

ter

Converter

3400Hz

200Hz

W681310

Publication Release Date: September 2005

- 9 - Revision B13

AI+ Input Amplifier Input

VDD Powered Down AO

1.2 to VDD-1.2 Powered Up AI+, AI-

VSS Powered Down AI-

Table 7.1 Input Amplifier Modes of operation

When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the

analog ground voltage VAG.

The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent

aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass

filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to

the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal

is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or

A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression

format can be selected according to Table 7.2.

μ/A-Law Pin Format

VSS A-Law

VDD μ-Law

Table 7.2. Pin-selectable Compression Format

The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the

sample rate supplied by the external frame sync FST.

7.2. Receive Path

The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of

expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a

low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A

sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered

to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to

provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external

resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If

the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDD.

7.3. POWER MANAGEMENT

W681310

- 10 -

7.3.1. Analog and Digital Supply

The power supply for the analog and digital parts of the W681310 must be 2.7V to 5.25V. This supply

voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF

ceramic capacitor.

7.3.2. Analog Ground Reference Bypass

The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog

ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 μF ceramic

capacitor.

7.3.3. Analog Ground Reference Voltage Outpt

The analog ground reference voltage is available for external reference at the VAG pin. This voltage

needs to be decoupled to VSS through a 0.01 μF ceramic capacitor. The analog ground reference

voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing.

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of

operation of the interface are shown in Table 7.3.

BCLKR FSR Interface Mode

64 kHz to 4.800 MHz 8 kHz Long or Short Frame Sync

VSS VSS ISDN GCI with active channel B1

VSS VDD ISDN GCI with active channel B2

VDD VSS ISDN IDL with active channel B1

VDD VDD ISDN IDL with active channel B2

Table 7.3 PCM Interface mode selections

W681310

Publication Release Date: September 2005

- 11 - Revision B13

7.4.1. Long Frame Sync

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR

or BCLKT pin to a 64 kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8 kHz frame

sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the

positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held

HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync

pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec.

During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low

impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted.

The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes

LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will

determine whether the next frame sync is a long or a short frame sync, based on the previous frame

sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles

after every power down state. More detailed timing information can be found in the interface timing

section.

7.4.2. Short Frame Sync

The W681310 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH

for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the

bit-clock, the W681310 starts clocking out the data on the PCMT pin, which will also change from high

to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway

the LSB. The Short Frame Sync operation of the W681310 is based on an 8-bit data word. When

receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that

coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame

sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions,

the PCMT pin will be high impedance for two frame sync cycles after every power down state. More

detailed timing information can be found in the interface timing section.

7.4.3. General Circuit Interface (GCI)

The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface

consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects

channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock

DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data

rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively.

Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the

second 16 clock cycles of DCL. For more timing information, see the timing section. The GCI interface

supports bit clocks of 512 kHz to 6176 kHz for data rates of 256 kHz to 3088 kHz.

W681310

- 12 -

7.4.4. Interchip Digital Link (IDL)

The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface

consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR

pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first

positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle

long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL

SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL

SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after

the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data

transmission and also in the time slot of the unused channel. For more timing information, see the

timing section.

7.4.5. System Timing

The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz, 4096 kHz &

4800 kHz master clock rates. The system clock is supplied through the master clock input MCLK and

can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz

and 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for

the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681310

will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When

the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync

pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low

impedance.

W681310

Publication Release Date: September 2005

- 13 - Revision B13

8. TIMING DIAGRAMS

FST

BCLKT

D7 D6 D5 D4 D3 D2 D1PCM T

MSB LSB

THID TBCK

TBCKH TBCKL

TFS

TFTFH

TFTRS

TFTRH

THID

TBDTD

TFDTD

01 23 45 7 8 0 1

MSB LSB

FSR

BCLKR

TBCK

D6 D5 D4 D3 D2 D1 D0PCM R D7

TDRH

TDRS

TBCKH TBCKL

TFS

TFRFH

TFRRS

TFRRH

01 23 45 6 7 8 0 1

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFA LL

TFSL

Figure 8.1 Long Frame Sync PCM Timing

W681310

- 14 -

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

TFSL FST / FSR Minimum Low Width 1TBCK sec

1/TBCK BCLKT, BCLKR Frequency 64 --- 4800 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT 0 Falling Edge to FST Rising

Edge Hold Time

20 --- --- ns

TFTRS FST Rising Edge to BCLKT 1 Falling

edge Setup Time

80 --- --- ns

TFTFH BCLKT 2 Falling Edge to FST Falling

Edge Hold Time

50 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay

Time

--- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT

Delay Time

--- --- 60 ns

THID Delay Time from the Later of FST

Falling Edge, or

BCLKT 8 Falling Edge to PCMT Output

High Impedance

10 --- 60 ns

TFRRH BCLKR 0 Falling Edge to FSR Rising

Edge Hold Time

20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 1 Falling

edge Setup Time

80 --- --- ns

TFRFH BCLKR 2 Falling Edge to FSR Falling

Edge Hold Time

50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge

Setup Time

0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling

Edge

50 --- --- ns

Table 8.1 Long Frame Sync PCM Timing Parameters

1 TFSL must be at least ≥ TBCK

W681310

Publication Release Date: September 2005

- 15 - Revision B13

D7 D6 D5 D4 D3 D2 D1

MSB LSB

TBCK

TBCKH TBCK L

TFS

TFTRS

TFTRH

THID

TBDTD

01 2 3 45 6 7 8 01

FST

BCLKT

PCM T

TBDTD

TFTFH

-1

TFTFS

MSB LSB

TBCK

D6 D5 D4 D3 D2 D1 D0D7

TDRH

TDRS

TBCKH TBCK L

TFS

TFRRS

TFRRH

01 2 3 45 6 7 8 01

FSR

BCLKR

PCM R

TFRFH

-1

TFRFS

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFA L L

Figure 8.2 Short Frame Sync PCM Timing

W681310

- 16 -

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

1/TBCK BCLKT, BCLKR Frequency 64 --- 4800 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT –1 Falling Edge to FST Rising Edge Hold

Time

20 --- --- ns

TFTRS FST Rising Edge to BCLKT 0 Falling edge Setup

Time

80 --- --- ns

TFTFH BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50 --- --- ns

TFTFS FST Falling Edge to BCLKT 1 Falling Edge Setup

Time

50 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns

THID Delay Time from BCLKT 8 Falling Edge to PCMT

Output High Impedance

10 --- 60 ns

TFRRH BCLKR –1 Falling Edge to FSR Rising Edge Hold

Time

20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 0 Falling edge Setup

Time

80 --- --- ns

TFRFH BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns

TFRFS FSR Falling Edge to BCLKR 1 Falling Edge Setup

Time

50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge Setup Time 0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns

Table 8.2 Short Frame Sync PCM Timing Parameters

W681310

Publication Release Date: September 2005

- 17 - Revision B13

FST

BCLKT

PCM T

PCM R

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

TFS

TFSRH

TFSFH

TFSRS

TBDTD TBDTD TBDTD TBDTD

THID

TDRS TDRS

TDRH TDRH

BCH = 0

B 1 C hannel

BCH = 1

B2 Channel

MSB

LSB

TBCK

TBCKH TBCKL

-1

Figure 8.3 IDL PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 256 --- 4800 kHz

TBCKH BCLKT HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT LOW Pulse Width 50 --- --- ns

TFSRH BCLKT –1 Falling Edge to FST Rising Edge

Hold Time

20 --- --- ns

TFSRS FST Rising Edge to BCLKT 0 Falling edge

Setup Time

60 --- --- ns

TFSFH BCLKT 0 Falling Edge to FST Falling Edge

Hold Time

20 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay

Time

10 --- 60 ns

THID Delay Time from the BCLKT 8 Falling Edge

(B1 channel) or BCLKT 18 Falling Edge (B2

Channel) to PCMT Output High Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Falling Edge Setup

Time

20 --- --- ns

TDRH PCMR Hold Time from BCLKT Falling Edge 75 --- --- ns

Table 8.3 IDL PCM Timing Parameters

W681310

- 18 -

FST

BCLKT

PCM T

PCM R

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

TFS

TFDTD TBDTD TBDTD TBDTD

THID

TDRS TDRS

TDRH TDRH

BCH = 0

B1 Channel

BCH = 1

B2 Channel

MSB

LSB

TFSRH

TFSFH

TFSRS

TBCK

TBCKH TBCKL

234567891011121314151617181920212223242526272829303132333410

Figure 8.4 GCI PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFST FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 512 --- 6176 kHz

TBCKH BCLKT HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT LOW Pulse Width 50 --- --- ns

TFSRH BCLKT 0 Falling Edge to FST Rising Edge Hold Time 20 --- --- ns

TFSRS FST Rising Edge to BCLKT 1 Falling edge Setup Time 60 --- --- ns

TFSFH BCLKT 1 Falling Edge to FST Falling Edge Hold Time 20 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay Time --- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time --- --- 60 ns

THID Delay Time from the BCLKT 16 Falling Edge (B1

channel) or BCLKT 32 Falling Edge (B2 Channel) to

PCMT Output High Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Rising Edge Setup Time 20 --- --- ns

TDRH PCMR Hold Time from BCLKT Rising Edge --- --- 60 ns

Table 8.4 GCI PCM Timing Parameters

W681310

Publication Release Date: September 2005

- 19 - Revision B13

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TMCK Master Clock Frequency --- 256

512

1536

1544

2048

2560

4096

4800

--- kHz

TMCKH /

TMCK

MCLK Duty Cycle for 256 kHz

Operation

45% 55%

TMCKH Minimum Pulse Width HIGH for

MCLK(512 kHz or Higher)

50 --- --- ns

TMCKL Minimum Pulse Width LOW for MCLK

(512 kHz or Higher)

50 --- --- ns

TFTRHM MCLK falling Edge to FST Rising Edge

Hold Time

50 --- --- ns

TFTRSM FST Rising Edge to MCLK Falling edge

Setup Time

50 --- --- ns

TRISE Rise Time for All Digital Signals --- --- 50 ns

TFALL Fall Time for All Digital Signals --- --- 50 ns

Table 8.5 General PCM Timing Parameters

W681310

- 20 -

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition Value

Junction temperature 1500C

Storage temperature range -650C to +1500C

Voltage Applied to any pin (VSS - 0.3V) to (VDD + 0.3V)

Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VDD + 1.0V)

VDD - VSS -0.5V to +6V

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

9.2. OPERATING CONDITIONS

Condition Value

Industrial operating temperature -400C to +850C

Supply voltage (VDD) +2.7V to +5.25V

Ground voltage (VSS) 0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

W681310

Publication Release Date: September 2005

- 21 - Revision B13

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

Symbol Parameters Conditions Min (2) Typ (1) Max (2) Units

VIL Input LOW Voltage 0.6 V

VIH Input HIGH Voltage 2.2 V

VOL PCMT Output LOW Voltage IOL = 1.6 mA 0.4 V

VOH PCMT Output HIGH Voltage IOL = -1.6 mA VDD –

0.5

IDD VDD Current (Operating) - ADC + DAC No Load 3.3 5 mA

ISB VDD Current (Standby) FST & FSR =Vss ;

PUI=VDD

10 100

μA

Ipd VDD Current (Power Down) PUI= Vss 0.1 10

μA

IIL Input Leakage Current VSS<VIN<VDD -10 +10

μA

IOL PCMT Output Leakage Current VSS<PCMT<VDD

High Z State

-10 +10

μA

CIN Digital Input Capacitance 10 pF

COUT PCMT Output Capacitance PCMT High Z 15 pF

1. Typical values: TA = 25°C , VDD = 3.0 V

2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications

are 100 percent tested.

W681310

- 22 -

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz;

FST=FSR=8kHz Synchronous operation.

TRANSMIT

(A/D)

RECEIVE

(D/A)

UNIT PARAMETER SYM. CONDITION TYP.

MIN. MAX. MIN. MAX.

Absolute

Level

LABS 0 dBm0 = -5dBm @ 600Ω0.616

0.436

--- --- --- --- VPK

VRMS

Max. Transmit

Level

TXMAX 3.17 dBm0 for μ-Law

3.14 dBm0 for A-Law

0.8873

0.8843

---

VPK

Absolute Gain

(0 dBm0 @

1020 Hz;

TA=+25°C)

GABS 0 dBm0 @ 1020 Hz;

TA=+25°C

0 -0.20 +0.20 -0.20 +0.20 dB

Absolute Gain

variation with

Temperature

GABST TA=0°C to TA=+70°C

TA=-40°C to TA=+85°C

0 -0.05

-0.10

+0.05

+0.10

-0.05

-0.10

+0.05

+0.10

Frequency

Response,

Relative to

0dBm0 @

1020 Hz

GRTV 15 Hz

50 Hz

60 Hz

200 Hz

300 to 3000 Hz

3300 Hz

3400 Hz

3600 Hz

4000 Hz

4600 Hz to 100 kHz

---

-1.4

-0.15

-0.35

-0.8

---

-40

-30

-26

-0.4

+0.2

+0.1

-14

-32

-0.5

-0.20

-0.4

-0.8

---

+0.2

+0.15

-14

-30

Gain Variation

vs. Level Tone

(1020 Hz

relative to –10

dBm0)

GLT +3 to –40 dBm0

-40 to –50 dBm0

-50 to –55 dBm0

---

-0.3

-0.6

-1.6

+0.3

+0.6

+1.6

-0.2

-0.4

-1.6

+0.2

+0.4

+1.6

W681310

Publication Release Date: September 2005

- 23 - Revision B13

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz

FST=FSR=8kHz Synchronous operation.

TRANSMIT (A/D) RECEIVE (D/A) PARAMETER SYM. CONDITION

MIN. TYP. MAX. MIN. TYP. MAX.

UNIT

Total Distortion vs.

Level Tone (1020 Hz,

μ-Law, C-Message

Weighted)

DLTμ+3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

33.5

---

dBC

Total Distortion vs.

Level Tone (1020 Hz,

A-Law, Psophometric

Weighted)

DLTA -3 dBm0

-6 dBm0 to -27 dBm0

-34 dBm0

-40 dBm0

-55 dBm0

34.5

28.5

13.5

---

34.2

---

dBp

Spurious Out-Of-Band

at RO- (300 Hz to

3400 Hz @ 0dBm0)

DSPO 4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 100000 Hz

---

-30

-40

-30

Spurious In-Band (700

Hz to 1100 Hz @

0dBm0)

DSPI 300 to 3000 Hz ---

--- -47

---

--- -47

Intermodulation

Distortion (300 Hz to

3400 Hz –4 to –21

dBm0

DIM Two tones

--- --- -41 --- --- -41 dB

Crosstalk (1020 Hz @

0dBm0)

DXT --- --- -75 --- --- -75 dBm0

Absolute Group Delay τABS 1200Hz --- --- 360 --- --- 240

μsec

Group Delay

Distortion (relative to

group delay @ 1200

Hz)

τD500 Hz

600 Hz

1000 Hz

2600 Hz

2800 Hz

---

750

380

130

750

---

750

370

120

750

μsec

Idle Channel Noise NIDL μ-Law; C-message

A-Law; Psophometric

---

-68

---

-75

dBrnc0

dBm0p

W681310

- 24 -

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

AI Input Offset Voltage VOFF,AI AI+, AI- --- --- ±25 mV

AI Input Current IIN,AI AI+, AI- --- ±0.1 ±1.0 μA

AI Input Resistance RIN,AI AI+, AI- to VAG 10 --- ---

MΩ

AI Input Capacitance CIN,AI AI+, AI- --- --- 10 pF

AI Common Mode Input

Voltage Range

VCM,AI AI+, AI- 1.2 --- VDD-1.2 V

AI Common Mode Rejection

Ratio

CMRRTI AI+, AI- --- 60 --- dB

AI Amp Gain Bandwidth

Product

GBWTI AO, RLD≥10kΩ --- 2150 --- kHz

AI Amp DC Open Loop Gain GTI AO, RLD≥10kΩ --- 95 --- dB

AI Amp Equivalent Input Noise NTI C-Message Weighted --- -24 --- dBrnC

AO Output Voltage Range VTG RLD=2kΩ to VAG 0.4 --- VDD-0.4 V

Load Resistance RLDTGRO AO, RO to VAG 2 --- ---

kΩ

Load Capacitance CLDTGRO AO, RO --- --- 200 pF

AO & RO Output Current IOUT1 0.5 ≤AO,RO-≤ VDD-0.5 ±1.0 --- --- mA

RO- Output Resistance RRO- RO-, 0 to 3400 Hz --- 1 --- Ω

RO- Output Offset Voltage VOFF,RO- RO- to VAG --- ---

±25 mV

Analog Ground Voltage VAG Relative to VSS VDD/2-0.1 VDD/2 VDD/2+0.

VAG Output Resistance RVAG Within ±25mV change --- 12.5 25

Power Supply Rejection Ratio

(0 to 100 kHz to VDD, C-

message)

PSRR Transmit

Receive

---

dBC

PAI Input Offset Voltage VOFF,PAI PAI --- ---

±25 mV

PAI Input Current IIN,PAI PAI ---

±0.05 ±1.0 μA

PAI Input Resistance RIN,PAI PAI to VAG 10 --- ---

MΩ

PAI Amp Gain Bandwidth

Product

GBWPI PAO- no load --- 1000 --- kHz

Output Offset Voltage VOFF,PO PAO+ to PAO- --- --- ±50 mV

W681310

Publication Release Date: September 2005

- 25 - Revision B13

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

Load Resistance RLDPO PAO+, PAO-

differentially

300 --- ---

Load Capacitance CLDPO PAO+, PAO-

differentially

--- --- 1000 pF

PAO Output Current IOUTPAO 0.4 ≤ PAO+,PAO--≤ VDD-

0.4

±6.0 --- --- mA

PAO Output Resistance RPAO PAO+ to PAO- --- 1 --- Ω

PAO Differential Gain GPAO RLD=300Ω, +3dBm0, 1

kHz, PAO+ to PAO-

-0.2 0 +0.2 dB

PAO Differential Signal to

Distortion C-Message

weighted

DPAO ZLD=300Ω

ZLD=100nF + 20Ω

ZLD=100nF + 100Ω

---

dBC

PAO Power Supply Rejection

Ratio (0 to 25 kHz to VDD,

Differential out)

PSRRP

0 to 4 kHz

4 to 25 kHz

---

W681310

- 26 -

10.5. DIGITAL I/O

10.5.1. μ-Law Encode Decode Characteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels

Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 0 0 0 0 0 0 8031

1 0 0 0 1 1 1 1 4191

1 0 0 1 1 1 1 1 2079

1 0 1 0 1 1 1 1 1023

1 0 1 1 1 1 1 1 495

1 1 0 0 1 1 1 1 231

1 1 0 1 1 1 1 1 99

1 1 1 0 1 1 1 1 33

1 1 1 1 1 1 1 0 2

1 1 1 1 1 1 1 1 0

8159

7903

4319

4063

2143

2015

1055

991

511

479

239

223

103

Notes:

Sign bit = 0 for negative values, sign bit = 1 for positive values

W681310

Publication Release Date: September 2005

- 27 - Revision B13

10.5.2. A-Law Encode Decode Characteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 1 0 1 0 1 0 4032

1 0 1 0 0 1 0 1 2112

1 0 1 1 0 1 0 1 1056

1 0 0 0 0 1 0 1 528

1 0 0 1 0 1 0 1 264

1 1 1 0 0 1 0 1 132

1 1 1 0 0 1 0 1 66

1 1 0 1 0 1 0 1 1

4096

3968

2048

1088

1024

544

512

272

256

136

128

Notes:

1. Sign bit = 0 for negative values, sign bit = 1 for positive values

2. Digital code includes inversion of all even number bits

W681310

- 28 -

10.5.3. PCM Codes for Zero and Full Scale

μ-Law A-Law

Level Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

+ Full Scale 1 000 0000 1 010 1010

+ Zero 1 111 1111 1 101 0101

- Zero 0 111 1111 0 101 0101

- Full Scale 0 000 0000 0 010 1010

10.5.4. PCM Codes for 0dBm0 Output

μ-Law A-Law

Sample Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

1 0 001 1110 0 011 0100

2 0 000 1011 0 010 0001

3 0 000 1011 0 010 0001

4 0 001 1110 0 011 0100

5 1 001 1110 1 011 0100

6 1 000 1011 1 010 0001

7 1 000 1011 1 010 0001

8 1 001 1110 1 011 0100

W681310

Publication Release Date: September 2005

- 29 - Revision B13

11. TYPICAL APPLICATION CIRCUIT

0.01 uF

27K

PCM OUT

1.0 uF 8 KHz Frame Sy nc

DIFFERENTIAL

AUDIO IN

PCM IN

0.1 uF

DIFFERENTIAL

AUDIO OUT

RL > 150 ohms

POWER CONTROL

27K

1.0 uF 27K

0.1 uF

2.048 MHz

Bit Clock

MODE SELECT

27K

W681310

615

VDDVSS

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

+27K

27K

VDD

Figure 11.1 Typical circuit for Differential Analog I/O’s

AUDIO OUT

RL > 2K ohms

1.0 uF

27K

AUDIO IN

W681310

615

VDDVSS

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

27K

PCM IN

8 KHz Frame Sy nc

27K

PCM OUT

MODE SELECT

100 uF

VDD

0.1 uF0.01 uF

27K

POWER CONTROL

1.0 uF

0.1 uF

2.048 MHz

Bit Clock

27K

AUDIO OUT

RL > 150 ohms

27K

Figure 11.2 Typical circuit for Single Ended Analog I/O’s

W681310

- 30 -

100pF

8 KHz Frame Sy nc

POWER CONTROL

62k

2.048 MHz

Bit Clock

1.0 uF

3.9K

MICROPHONE

27K

3.9K

VDD

27K

0.1 uF

0.01 uF

SPEAKER

0.1 uF

1.0 uF

22 uF

27K

100pF

W681310

615

VDDVSS

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

1.5K

PCM OUT

1.5K

62K

ELECTRET

PCM IN

MODE SELECT

Figure 11.3 Handset Interface

0.1 uF

27K

600

0.01 uF

TR AN SF OR ME R B1/B2 SELECT

W681310

615

VDDVSS

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

27K

PCM OUT

27K600 OHM 1:1

MODE SELECT

VDD

27K

0.1 uF

POWER CONTROL

4.096 MHz

Bit Clock

8 KHz Frame Sy nc

PCM IN

1.0 uF

Figure 11.4 Transformer Interface Circuit in GCI mode

W681310

Publication Release Date: September 2005

- 31 - Revision B13

12. PACKAGE SPECIFICATION

12.1. 20L SOG (SOP)-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

DIMENSION (MM) DIMENSION (INCH)

SYMBOL MIN. MAX. MIN. MAX.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

b 0.33 0.51 0.013 0.020

c 0.23 0.32 0.009 0.013

E 7.40 7.60 0.291 0.299

D 12.60 13.00 0.496 0.512

e 1.27 BSC 0.050 BSC

HE10.00 10.65 0.394 0.419

Y - 0.10 - 0.004

L 0.40 1.27 0.016 0.050

0 0º 8º 0º 8º

SEATING

GAUGE

W681310

- 32 -

12.2. 20L SSOP-209 MIL

SHRINK SMALL OUTLINE PACKAGE DIMENSIONS

SEATING

DTEAIL

DETAIL

SEATING

DIMENSION (MM) DIMENSION (INCH)

SYMBOL MIN. NOM. MAX. MIN. NOM. MAX.

A - - 2.00 - - 0.079

A1 0.05 - - 0.002 - -

A2 1.65 1.75 1.85 0.065 0.069 -

b 0.22 - 0.38 0.009 - 0.015

c 0.09 - 0.25 0.004 - 0.010

D 6.90 7.20 7.50 0.272 0.283 0.295

E 5.00 5.30 5.60 0.197 0.209 0.220

HE7.40 7.80 8.20 0.291 0.307 0.323

e - 0.65 - - 0.0256 -

L 0.55 0.75 0.95 0.021 0.030 0.037

L1 - 1.25 - - 0.050 -

Y - - 0.10 - - 0.004

0 0º - 8º 0 - 8º

W681310

Publication Release Date: September 2005

- 33 - Revision B13

12.3. 20L TSSOP - 4.4X6.5MM

PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS

DIMENSION (MM) DIMENSION (INCH)

SYMBOL MIN. NOM. MAX. MIN. NOM. MAX.

A - - 1.20 - - 0.047

A1 0.05 - 0.15 0.002 - 0.006

A2 0.80 0.90 1.05 0.031 0.035 0.041

E 4.30 4.40 4.50 0.169 0.173 0.177

HE 6.40 BSC .252 BSC

D 6.40 6.50 6.60 0.252 0.256 0.260

L 0.50 0.60 0.75 0.020 0.024 0.030

L1 1.00 REF 0.039 REF

b 0.19 - 0.30 0.007 - 0.012

e 0.65 BSC 0.026 BSC

c 0.09 - 0.20 0.004 - 0.008

0 0º - 8º 0º - 8º

Y 0.10 BASIC 0.004 BASIC

W681310

- 34 -

13. ORDERING INFORMATION

Winbond Part Number Description

Product Family

W681310 Product

W681310_ _

Package Material:

Blank = Standard Package

G = Pb-free Package

Package Type:

S = 20-Lead Plastic Small Outline Package (SOG/SOP)

R = 20-Lead Plastic Small Outline Package (SSOP)

W = 20-Lead Plastic Thin Small Outline Package (TSSOP)

When ordering W681310 series devices, please refer to the following part numbers.

Part Number

W681310S

W681310R

W681310W

W681310SG

W681310RG

W681310WG

W681310

Publication Release Date: September 2005

- 35 - Revision B13

14. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 August 10, 2003 Draft version

A2 August 22, 2003 Update typo errors and parameters

B11 November,

2004

Added reference to TSSOP package and Pb-free

packaging.

Added reference to TSSOP package.

Added description of TSSOP package.

Added W and G package ordering code.

Extended conditions on Table 10.2.

Extended conditions on Table 10.3.

Corrected Idle Channel Noise min/max and units.

Improved Application Diagram

B12 April, 2005 36 Add Important Notice

B13 September,

2005

29,30

Various

Improved Application Diagram

Added Reference to VRMS

Capitalized logic HIGH/LOW

W681310

- 36 -

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

The information contained in this datasheet may be subject to change without

notice. It is the responsibility of the customer to check the Winbond USA website

(www.winbond-usa.com) periodically for the latest version of this document, and

any Errata Sheets that may be generated between datasheet revisions.

Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai,

Science-Based Industrial Park, CA 95134, U.S.A. 200336 China

Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999

TEL: 886-3-5770066 FAX: 1-408-5441798 FAX: 86-21-62356998

FAX: 886-3-5665577 http://www.winbond-usa.com/

http://www.winbond.com.tw/

Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG, 3-7-18 Unit 9-15, 22F, Millennium City,

Neihu District, Shinyokohama Kohoku-ku, No. 378 Kwun Tong Rd.,

Taipei, 114, Taiwan Yokohama, 222-0033 Kowloon, Hong Kong

TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100

FAX: 886-2-87153579 FAX: 81-45-4781800 FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.