MB91F467EAPMC-GS-N2E2 - CYPRESS SEMICONDUCTOR

The following document contains information on Cypress products.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use,

including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not

designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless

extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,

severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,

mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where

chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating conditions. If any products described in this document

represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law

of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the

respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion

product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without

notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,

completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other

warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of

the information in this document.

ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and

other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

FUJITSU SEMICONDUCTOR

DATA SHEET

2010.10

For the information for microcontroller supports, see the following web site.

This web site includes the "Customer Design Review Supplement" which provides the latest cautions on sys-

tem development and the minimal requirements to be checked to prevent problems before the system develop-

ment.

http://edevice.fujitsu.com/micom/en-support/

32-bit Microcontroller

CMOS

FR60 MB91460E Series

MB91F467EA

■DESCRIPTION

MB91460E series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control

applications which require high-speed real-time processing, such as consumer devices and on-board vehicle

systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs.

This series contains the LIN-USART and CAN controllers.

* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Semiconductor Limited.

■FEATURES

1. FR60 CPU core

• 32-bit RISC, load/store architecture, ﬁve-stage pipeline

• 16-bit ﬁxed-length instructions (basic instructions)

• Instruction execution speed: 1 instruction per cycle

• Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions

suitable for embedded applications

• Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C

language

• Register interlock function: Facilitating assembly-language coding

• Built-in multiplier with instruction-level support

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interrupts (save PC/PS) : 6 cycles (16 priority levels)

(Continued)

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MB91460E Series

2 DS705-00002-1v3-E

(Continued)

• Harvard architecture enabling program access and data access to be performed simultaneously

• Instructions compatible with the FR family

2. Internal peripheral resources

• General-purpose ports : Maximum 170 ports

• DMAC (DMA Controller)

Maximum of 5 channels able to operate simultaneously. (External to external : 1 channel)

3 transfer sources (external pin/internal peripheral/software)

Activation source can be selected using software.

Addressing mode speciﬁes full 32-bit addresses (increment/decrement/ﬁxed)

Transfer mode (demand transfer/burst transfer/step transfer/block transfer)

Transfer data size selectable from 8/16/32-bit

Multi-byte transfer enabled (by software)

DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)

• A/D converter (successive approximation type)

10-bit resolution: 24 channels

Conversion time: minimum 1 µs

• External interrupt inputs : 14 channels

8 channels shared with CAN RX or I2C pins

• Bit search module (for REALOS)

Function to search from the MSB (most signiﬁcant bit) for the position of the ﬁrst “0”, “1”, or changed bit in a word

• LIN-USART (full duplex double buffer): 5 channels

Clock synchronous/asynchronous selectable

Sync-break detection

Internal dedicated baud rate generator

•I

2C* bus interface (supports 400 kbps): 3 channels

Master/slave transmission and reception

Arbitration function, clock synchronization function

• CAN controller (C-CAN): 2 channels

Maximum transfer speed: 1 Mbps

32 transmission/reception message buffers

• Stepper motor controller : 6 channels

4 high current output to each channel

2 synchronized PWMs per channel (8/10-bit)

• Sound generator : 1 channel

Tone frequency : PWM frequency divide-by-two (reload value + 1)

• Alarm comparator : 1 channel

Monitor external voltage

Generate an interrupt in case of voltage lower/higher than the deﬁned thresholds (reference voltage)

• 16-bit PPG timer : 12 channels

• 16-bit PFM timer : 1 channel

• 16-bit reload timer: 8 channels

• 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU)

• Input capture: 8 channels (operates in conjunction with the free-run timer)

• Output compare: 4 channels (operates in conjunction with the free-run timer)

• Up/Down counter: 3 channels (3*8-bit or 1*16-bit + 1*8-bit)

• Watchdog timer

(Continued)

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MB91460E Series

DS705-00002-1v3-E 3

(Continued)

• Real-time clock

• Low-power consumption modes : Sleep/stop mode function

• Supply Supervisor: Low voltage detection circuit for external VDD5 and internal 1.8V core voltage

• Clock supervisor

Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator,

etc.) when the oscillations stop.

• Clock modulator

• Clock monitor

• Sub-clock calibration

Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator

• Main oscillator stabilization timer

Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization

wait time counter

• Sub-oscillator stabilization timer

Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization

wait time counter

3. Shutdown mode

• In low leakage shutdown mode, the internal main power supply is switched off. Only the following resources

and meories remain active:

- Standby RAM (16 KByte)

- Real Time Clock

- 4 MHz oscillator, 32 kHz oscillator, RC oscillator

- Power management logic

- Hardware Watchdog and Clock Supervisor

4. Package and technology

• Package : LQFP-208 (low proﬁle QFP)

• CMOS 0.18 µm technology

• Power supply range 3 V to 5 V (1.9V/1.8 V internal logic provided by a step-down voltage converter)

• Operating temperature range: between − 40˚C and + 105˚C

MB91460E-DS705-00002-1v3-E.fm Page 3 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

4 DS705-00002-1v3-E

■PRODUCT LINEUP

Feature MB91FV460B MB91F467DA

MB91F467DB MB91F467EA

Max. core frequency (CLKB) 100MHz 96MHz 100MHz

Max. resource frequency (CLKP) 50MHz 48MHz 50MHz

Max. external bus freq. (CLKT) 50MHz 48MHz 50MHz

Max. CAN frequency (CLKCAN) 50MHz 48MHz 50MHz

Technology 0.18um 0.18um 0.18um

Software-Watchdog yes yes yes

Hardware-Watchdog

(RC osc. based)

yes (disengageable),

can be activated in

SLEEP/STOP

yes

yes,

can be activated in

SLEEP/STOP

Bit Search yes yes yes

Reset input (INITX) yes yes yes

Clock Modulator yes yes yes

Clock Monitor yes yes yes

Low Power Mode yes yes yes

Shutdown Mode no,

emulation by software no yes

DMA 5 ch 5 ch 5 ch

MMU/MPU MPU (16 ch) 1) MPU (8 ch) 1) MPU (8 ch) 1)

Flash memory 2112 KByte or external

emulation SRAM 1088 KByte 1088 KByte

Flash Protection yes yes yes

D-RAM 64 KByte 32 KByte 64 KByte

ID-RAM 64 KByte 32 KByte 48 KByte

Standby RAM no no 16 KByte

Flash-Cache (F-cache) 16 KByte 8 KByte 8 KByte

Boot-ROM / BI-ROM 16 KByte Boot Flash 4 KByte 4 KByte

RTC 1 ch 1 ch 1 ch

Free Running Timer 8 ch 8 ch 8 ch

ICU 8 ch 8 ch 8 ch

OCU 8 ch 4 ch 4 ch

Reload Timer 8 ch 8 ch 8 ch

PPG 16-bit 16 ch 12 ch 12 ch

PFM 16-bit 1 ch 1 ch 1 ch

MB91460E-DS705-00002-1v3-E.fm Page 4 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 5

Sound Generator 1 ch 1 ch 1 ch

Up/Down Counter (8/16-bit) 4 ch (8-bit)/2ch(16-bit) 3 ch (8-bit) / 1 ch (16-bit) 3 ch (8-bit)/1ch(16-bit)

C_CAN 6 ch (128msg) 3 ch (32msg) 2 ch (32msg)

LIN-USART 16 ch FIFO 1 ch + 4 ch FIFO 1 ch + 4 ch FIFO

I2C (400k) 8 ch 3 ch 3 ch

FR external bus yes (32bit addr,

32bit data)

yes (26bit addr,

32bit data)

yes (26bit addr,

32bit data)

External Interrupts 32 ch 14 ch 14 ch

SMC 6 ch 6 ch 6 ch

ADC (10 bit) 32 ch, with

Range Comparator 24 ch 24 ch, with

Range Comparator

Alarm Comparator 2 ch 1 ch 1 ch

Supply Supervisor

(low voltage detection) yes yes yes

Clock Supervisor yes yes yes

Main clock oscillator 4MHz 4MHz 4MHz

Sub clock oscillator 32kHz 32kHz 32kHz

RC Oscillator 100kHz / 2MHz 100kHz / 2MHz 100kHz / 2MHz

PLL x 25 x 24 x 25

DSU4 yes - -

EDSU yes (32 BP) *1 yes (16 BP) *1 yes (16 BP) *1

Supply Voltage 1.8V + 3V / 5V 3V / 5V 3V / 5V

Regulator no yes yes

Power Consumption n.a. < 2 W < 1.3 W

Temperatur Range (Ta) 0..70 C -40..105 C -40..105 C

Package BGA896 QFP208 LQFP208

Feature MB91FV460B MB91F467DA

MB91F467DB MB91F467EA

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MB91460E Series

6 DS705-00002-1v3-E

*1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).

Power on to PLL run < 20 ms < 20 ms < 20 ms

Flash Download Time < 8 sec typical < 6 sec typical < 6 sec typical

Feature MB91FV460B MB91F467DA

MB91F467DB MB91F467EA

MB91460E-DS705-00002-1v3-E.fm Page 6 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 7

■PIN ASSIGNMENT

1. MB91F467EA

(TOP VIEW)

FPT-208P-M06

Note: Difference versus MB91460D series: At pins 95+96, RX2 and TX2 of CAN2 are removed.

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

VDD5

P29_7/AN7

P29_6/AN6

P29_5/AN5

P29_4/AN4

P29_3/AN3

P29_2/AN2

P29_1/AN1

P29_0/AN0

ALARM_0

AVCC5

AVRH5

AVSS5

P16_7/PPG15/ATGX

P16_6/PPG14/PFM

P16_5/PPG13/SGO

P16_4/PPG12/SGA

P16_3/PPG11

P16_2/PPG10

P16_1/PPG9

P16_0/PPG8

P17_7/PPG7

P17_6/PPG6

P17_5/PPG5

P17_4/PPG4

VSS5

VDD5

P14_7/ICU7/TIN7/TTG7/ 15

P14_6/ICU6/TIN6/TTG6/ 14

P14_5/ICU5/TIN5/TTG5/ 13

P14_4/ICU4/TIN4/TTG4/ 12

P14_3/ICU3/TIN3/TTG11

P14_2/ICU2/TIN2/TTG10

P14_1/ICU1/TIN1/TTG9

P14_0/ICU0/TIN0/TTG8

P15_3/OCU3/TOT3

P15_2/OCU2/TOT2

P15_1/OCU1/TOT1

P15_0/OCU0/TOT0

P18_6/SCK7/ZIN3/CK7

P18_5/SOT7/BIN3

P18_4/SIN7/AIN3

P18_2/SCK6/ZIN2/CK6

P18_1/SOT6/BIN2

P18_0/SIN6/AIN2

P19_6/SCK5/ CK5

P19_5/SOT5

P19_4/SIN5

P19_2/SCK4/ CK4

P19_1/SOT4

P19_0/SIN4

VSS5

P01_0/D16

P01_1/D17

P01_2/D18

P01_3/D19

P01_4/D20

P01_5/D21

P01_6/D22

P01_7/D23

P00_0/D24

P00_1/D25

P00_2/D26

P00_3/D27

P00_4/D28

P00_5/D29

P00_6/D30

P00_7/D31

P07_0/A0

P07_1/A1

P07_2/A2

P07_3/A3

P07_4/A4

P07_5/A5

P07_6/A6

P07_7/A7

VDD35

VSS5

P06_0/A8

P06_1/A9

P06_2/A10

P06_3/A11

P06_4/A12

P06_5/A13

P06_6/A14

P06_7/A15

P05_0/A16

P05_1/A17

P05_2/A18

P05_3/A19

P05_4/A20

P05_5/A21

P05_6/A22

P05_7/A23

P04_0/A24

P04_1/A25

P08_0/WRX0

P08_1/WRX1

P08_2/WRX2

P08_3/WRX3

P08_4/RDX

P08_5/BGRNTX

VDD35

100

101

102

103

104

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

VDD35

P02_7/D15

P02_6/D14

P02_5/D13

P02_4/D12

P02_3/D11

P02_2/D10

P02_1/D9

P02_0/D8

P03_7/D7

P03_6/D6

P03_5/D5

P03_4/D4

P03_3/D3

P03_2/D2

P03_1/D1

P03_0/D0

P13_2/DEOTX0/DEOP

P13_1/DACKX0

P13_0/DREQ0

VSS5

P25_7/SMC2M5

P25_6/SMC2P5

P25_5/SMC1M5

P25_4/SMC1P5

HVSS5

HVDD5

P25_3/SMC2M4

P25_2/SMC2P4

P25_1/SMC1M4

P25_0/SMC1P4

P26_7/SMC2M3/AN31

P26_6/SMC2P3/ AN30

P26_5/SMC1M3/AN29

P26_4/SMC1P3/ AN28

HVSS5

HVDD5

P26_3/SMC2M2/AN27

P26_2/SMC2P2/ AN26

P26_1/SMC1M2/AN25

P26_0/SMC1P2/ AN24

P27_7/SMC2M1/AN23

P27_6/SMC2P1/ AN22

P27_5/SMC1M1/AN21

P27_4/SMC1P1/ AN20

HVSS5

HVDD5

P27_3/SMC2M0/AN19

P27_2/SMC2P0/ AN18

P27_1/SMC1M0/AN17

P27_0/SMC1P0/ AN16

VSS5

P08_6/BRQ

P08_7/RDY

P09_0/CSX0

P09_1/CSX1

P09_2/CSX2

P09_3/CSX3

P09_6/CSX6

P09_7/CSX7

P10_1/ASX

P10_2/BAAX

P10_3/WEX

P10_4/MCLKO

P10_5/MCLKI

P10_6/MCLKE

MONCLK

VSS5

MD_2

MD_1

MD_0

INITX

X1A

X0A

VDD5

VSS5

VCC18C

VDD5R

P24_0/INT0

P24_1/INT1

P24_2/INT2

P24_3/INT3

P24_4/INT4/SDA2

P24_5/INT5/SCL2

P24_6/INT6/SDA3

P24_7/INT7/SCL3

P23_0/RX0/INT8

P23_1/TX0

P23_2/RX1/INT9

P23_3/TX1

P23_4/INT10

P23_5

P22_0/INT12

P22_2/INT13

P22_4/SDA0/INT14

P22_5/SCL0

P20_0/SIN2/AIN0

P20_1/SOT2/BIN0

P20_2/SCK2/ZIN0/CK2

VDD5

QFP-208

MB91460E-DS705-00002-1v3-E.fm Page 7 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

8 DS705-00002-1v3-E

■PIN DESCRIPTION

1. MB91F467EA

(Continued)

Pin no. Pin name I/O I/O circuit

type *1Function

2 to 9 P01_0 to P01_7 I/O A General-purpose input/output ports

D16 to D23 Signal pins of external data bus (bit16 to bit23)

10 to 17 P00_0 to P00_7 I/O A General-purpose input/output ports

D24 to D31 Signal pins of external data bus (bit24 to bit31)

18 to 25 P07_0 to P07_7 I/O A General-purpose input/output ports

A0 to A7 Signal pins of external address bus (bit0 to bit7)

28 to 35 P06_0 to P06_7 I/O A General-purpose input/output ports

A8 to A15 Signal pins of external address bus (bit8 to bit15)

36 to 43 P05_0 to P05_7 I/O A General-purpose input/output ports

A16 to A23 Signal pins of external address bus (bit16 to bit23)

44, 45 P04_0, P04_1 I/O A General-purpose input/output ports

A24, A25 Signal pins of external address bus (bit24, bit25)

46 to 49 P08_0 to P08_3 I/O A General-purpose input/output ports

WRX0 to WRX3 External write strobe output pins

50 P08_4 I/O A General-purpose input/output port

RDX External read strobe output pin

51 P08_5 I/O A General-purpose input/output port

BGRNTX External bus release reception output pin

54 P08_6 I/O A General-purpose input/output port

BRQ External bus release request input pin

55 P08_7 I/O A General-purpose input/output port

RDY External ready input pin

56 to 59 P09_0 to P09_3 I/O A General-purpose input/output ports

CSX0 to CSX3 Chip select output pins

60, 61 P09_6, P09_7 I/O A General-purpose input/output ports

CSX6, CSX7 Chip select output pins

62 P10_1 I/O A General-purpose input/output port

ASX Address strobe output pin

63 P10_2 I/O A General-purpose input/output port

BAAX Burst address advance output pin

64 P10_3 I/O A General-purpose input/output port

WEX Write enable output pin

65 P10_4 I/O A General-purpose input/output port

MCLKO Clock output pin for memory

MB91460E-DS705-00002-1v3-E.fm Page 8 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 9

(Continued)

Pin no. Pin name I/O I/O circuit

type *1 Function

66 P10_5 I/O A General-purpose input/output port

MCLKI Clock input pin for memory

67 P10_6 I/O A General-purpose input/output port

MCLKE Clock enable signal pin for memory

68 MONCLK O M Clock monitor pin

70 MD_2 I G

Mode setting pins71 MD_1 I G

72 MD_0 I G

73 INITX I H External reset input pin

74 X1A ⎯J2 Sub clock (oscillation) output

75 X0A ⎯J2 Sub clock (oscillation) input

76 X1 ⎯J1 Clock (oscillation) output

77 X0 ⎯J1 Clock (oscillation) input

83 to 86 P24_0 to P24_3 I/O A General-purpose input/output ports

INT0 to INT3 External interrupt input pins

P24_4

I/O C

General-purpose input/output port

INT4 External interrupt input pin

SDA2 I2C bus DATA input/output pin

P24_5

I/O C

General-purpose input/output port

INT5 External interrupt input pin

SCL2 I2C bus clock input/output pin

P24_6

I/O C

General-purpose input/output port

INT6 External interrupt input pin

SDA3 I2C bus DATA input/output pin

P24_7

I/O C

General-purpose input/output port

INT7 External interrupt input pin

SCL3 I2C bus clock input/output pin

P23_0

I/O A

General-purpose input/output port

RX0 RX input pin of CAN0

INT8 External interrupt input pin

92 P23_1 I/O A General-purpose input/output port

TX0 TX output pin of CAN0

P23_2

I/O A

General-purpose input/output port

RX1 RX input pin of CAN1

INT9 External interrupt input pin

MB91460E-DS705-00002-1v3-E.fm Page 9 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

10 DS705-00002-1v3-E

(Continued)

Pin no. Pin name I/O I/O circuit

type *1 Function

94 P23_3 I/O A General-purpose input/output port

TX1 TX output pin of CAN1

95 *2 P23_4 I/O A General-purpose input/output port

INT10 External interrupt input pin

96 *2 P23_5 I/O A General-purpose input/output port

97 P22_0 I/O A General-purpose input/output port

INT12 External interrupt input pin

98 P22_2 I/O A General-purpose input/output port

INT13 External interrupt input pin

P22_4

I/O C

General-purpose input/output port

SDA0 I2C bus data input/output pin

INT14 External interrupt input pin

100 P22_5 I/O C General-purpose input/output port

SCL0 I2C bus clock input/output pin

101

P20_0

I/O A

General-purpose input/output port

SIN2 Data input pin of USART2

AIN0 Up/down counter input pin

102

P20_1

I/O A

General-purpose input/output port

SOT2 Data output pin of USART2

BIN0 Up/down counter input pin

103

P20_2

I/O A

General-purpose input/output port

SCK2 Clock input/output pin of USART2

ZIN0 Up/down counter input pin

CK2 External clock input pin of free-run timer 2

106 P19_0 I/O A General-purpose input/output port

SIN4 Data input pin of USART4

107 P19_1 I/O A General-purpose input/output port

SOT4 Data output pin of USART4

108

P19_2

I/O A

General-purpose input/output port

SCK4 Clock input/output pin of USART4

CK4 External clock input pin of free-run timer 4

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MB91460E Series

DS705-00002-1v3-E 11

(Continued)

Pin no. Pin name I/O I/O circuit

type *1 Function

109 P19_4 I/O A General-purpose input/output port

SIN5 Data input pin of USART5

110 P19_5 I/O A General-purpose input/output port

SOT5 Data output pin of USART5

111

P19_6

I/O A

General-purpose input/output port

SCK5 Clock input/output pin of USART5

CK5 External clock input pin of free-run timer 5

112

P18_0

I/O A

General-purpose input/output port

SIN6 Data input pin of USART6

AIN2 Up/down counter input pin

113

P18_1

I/O A

General-purpose input/output port

SOT6 Data output pin of USART6

BIN2 Up/down counter input pin

114

P18_2

I/O A

General-purpose input/output port

SCK6 Clock input/output pin of USART6

ZIN2 Up/down counter input pin

CK6 External clock input pin of free-run timer 6

115

P18_4

I/O A

General-purpose input/output port

SIN7 Data input pin of USART7

AIN3 Up/down counter input pin

116

P18_5

I/O A

General-purpose input/output port

SOT7 Data output pin of USART7

BIN3 Up/down counter input pin

117

P18_6

I/O A

General-purpose input/output port

SCK7 Clock input/output pin of USART7

ZIN3 Up/down counter input pin

CK7 External clock input pin of free-run timer 7

118 to 121

P15_0 to P15_3

I/O A

General-purpose input/output ports

OCU0 to OCU3 Output compare output pins

TOT0 to TOT3 Reload timer output pins

122 to 129

P14_0 to P14_7

I/O A

General-purpose input/output ports

ICU0 to ICU7 Input capture input pins

TIN0 to TIN7 External trigger input pins of reload timer

TTG8 to TTG11,

TTG4/12 to

TTG7/15

External trigger input pins of PPG timer

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MB91460E Series

12 DS705-00002-1v3-E

(Continued)

Pin no. Pin name I/O I/O circuit

type *1 Function

132 to 135 P17_4 to P17_7 I/O A General-purpose input/output ports

PPG4 to PPG7 Output pins of PPG timer

136 to 139 P16_0 to P16_3 I/O A General-purpose input/output ports

PPG8 to PPG11 PPG timer output pins

140

P16_4

I/O A

General-purpose input/output port

PPG12 Output pin of PPG timer

SGA SGA output pin of sound generator

141

P16_5

I/O A

General-purpose input/output port

PPG13 Output pin of PPG timer

SGO SGO output pin of sound generator

142

P16_6

I/O A

General-purpose input/output port

PPG14 Output pin of PPG timer

PFM Pulse frequency modulator output pin

143

P16_7

I/O A

General-purpose input/output port

PPG15 PPG timer output pin

ATGX A/D converter external trigger input pin

147 ALARM_0 I N Alarm comparator input pin

148 to 155 P29_0 to P29_7 I/O B General-purpose input/output ports

AN0 to AN7 Analog input pins of A/D converter

158

P27_0

I/O F

General-purpose input/output port

SMC1P0 Controller output pin of Stepper motor

AN16 Analog input pin of A/D converter

159

P27_1

I/O F

General-purpose input/output port

SMC1M0 Controller output pin of Stepper motor

AN17 Analog input pin of A/D converter

160

P27_2

I/O F

General-purpose input/output port

SMC2P0 Controller output pin of Stepper motor

AN18 Analog input pin of A/D converter

161

P27_3

I/O F

General-purpose input/output port

SMC2M0 Controller output pin of Stepper motor

AN19 Analog input pin of A/D converter

164

P27_4

I/O F

General-purpose input/output port

SMC1P1 Controller output pin of Stepper motor

AN20 Analog input pin of A/D converter

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MB91460E Series

DS705-00002-1v3-E 13

(Continued)

Pin no. Pin name I/O I/O circuit

type *1 Function

165

P27_5

I/O F

General-purpose input/output port

SMC1M1 Controller output pin of Stepper motor

AN21 Analog input pin of A/D converter

166

P27_6

I/O F

General-purpose input/output port

SMC2P1 Controller output pin of Stepper motor

AN22 Analog input pin of A/D converter

167

P27_7

I/O F

General-purpose input/output port

SMC2M1 Controller output pin of Stepper motor

AN23 Analog input pin of A/D converter

168

P26_0

I/O F

General-purpose input/output port

SMC1P2 Controller output pin of Stepper motor

AN24 Analog input pin of A/D converter

169

P26_1

I/O F

General-purpose input/output port

SMC1M2 Controller output pin of Stepper motor

AN25 Analog input pin of A/D converter

170

P26_2

I/O F

General-purpose input/output port

SMC2P2 Controller output pin of Stepper motor

AN26 Analog input pin of A/D converter

171

P26_3

I/O F

General-purpose input/output port

SMC2M2 Controller output pin of Stepper motor

AN27 Analog input pin of A/D converter

174

P26_4

I/O F

General-purpose input/output port

SMC1P3 Controller output pin of Stepper motor

AN28 Analog input pin of A/D converter

175

P26_5

I/O F

General-purpose input/output port

SMC1M3 Controller output pin of Stepper motor

AN29 Analog input pin of A/D converter

176

P26_6

I/O F

General-purpose input/output port

SMC2P3 Controller output pin of Stepper motor

AN30 Analog input pin of A/D converter

177

P26_7

I/O F

General-purpose input/output port

SMC2M3 Controller output pin of Stepper motor

AN31 Analog input pin of A/D converter

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MB91460E Series

14 DS705-00002-1v3-E

(Continued)

*1 : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.

*2 : Difference versus MB91460D series: At pins 95+96, RX2 and TX2 of CAN2 are removed.

Pin no. Pin name I/O I/O circuit

type *1 Function

178 P25_0 I/O E General-purpose input/output port

SMC1P4 Controller output pin of Stepper motor

179 P25_1 I/O E General-purpose input/output port

SMC1M4 Controller output pin of Stepper motor

180 P25_2 I/O E General-purpose input/output port

SMC2P4 Controller output pin of Stepper motor

181 P25_3 I/O E General-purpose input/output port

SMC2M4 Controller output pin of Stepper motor

184 P25_4 I/O E General-purpose input/output port

SMC1P5 Controller output pin of Stepper motor

185 P25_5 I/O E General-purpose input/output port

SMC1M5 Controller output pin of Stepper motor

186 P25_6 I/O E General-purpose input/output port

SMC2P5 Controller output pin of Stepper motor

187 P25_7 I/O E General-purpose input/output port

SMC2M5 Controller output pin of Stepper motor

189 P13_0 I/O A General-purpose input/output port

DREQ0 DMA external transfer request input

190 P13_1 I/O A General-purpose input/output port

DACKX0 DMA external transfer acknowledge output pin

191

P13_2

I/O A

General-purpose input/output port

DEOTX0 DMA external transfer EOT (End of Track) output pin

DEOP0 DMA external transfer EOP (End of Process) output pin

192 to 199 P03_0 to P03_7 I/O A General-purpose input/output ports

D0 to D7 Signal pins of external data bus (bit0 to bit7)

200 to 207 P02_0 to P02_7 I/O A General-purpose input/output ports

D8 to D15 Signal pins of external data bus (bit8 to bit15)

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MB91460E Series

DS705-00002-1v3-E 15

2. Power supply/Ground pins

Pin no. Pin name I/O Function

1, 27, 53, 69, 79, 105,

131, 157, 188 VSS5

Supply

Ground pins

163, 173, 183 HVSS5 Ground pins for Stepper motor controller

26, 52, 208 VDD35 Power supply pins for external data bus

78, 104, 130, 156 VDD5 Power supply pins

162, 172, 182 HVDD5 Power supply pins for Stepper motor controller

81, 82 VDD5R Power supply pins for internal regulator

144 AVSS5 Analog ground pin for A/D converter

146 AVCC5 Power supply pin for A/D converter

145 AVRH5 Reference power supply pin for A/D converter

80 VCC18C Capacitor connection pin for internal regulator

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MB91460E Series

16 DS705-00002-1v3-E

■I/O CIRCUIT TYPES

Type Circuit Remarks

A CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

B CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

Analog input

pull-up control

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

pull- down control

driver strength

control

data line

standby control for

input shutdown

analog input

pull-up control

pull- down control

driver strength

control

data line

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

standby control for

input shutdown

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MB91460E Series

DS705-00002-1v3-E 17

C CMOS level output (IOL = 3mA, IOH = -3mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

D CMOS level output (IOL = 3mA, IOH = -3mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

Analog input

Type Circuit Remarks

pull-up control

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

pull- down control

data line

standby control for

input shutdown

analog input

pull-up control

pull- down control

data line

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

standby control for

input shutdown

MB91460E-DS705-00002-1v3-E.fm Page 17 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

18 DS705-00002-1v3-E

E CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA,

and IOL = 30mA, IOH = -30mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

F CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA,

and IOL = 30mA, IOH = -30mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

Analog input

Type Circuit Remarks

pull-up control

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

pull- down control

driver strength

control

data line

standby control for

input shutdown

analog input

pull-up control

pull- down control

driver strength

control

data line

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

standby control for

input shutdown

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MB91460E Series

DS705-00002-1v3-E 19

G Mask ROM and EVA device:

CMOS Hysteresis input pin

Flash device:

CMOS input pin

12 V withstand (for MD [2:0])

H CMOS Hysteresis input pin

Pull-up resistor value: 50 kΩ approx.

J1 High-speed oscillation circuit:

• Programmable between oscillation mode

(external crystal or resonator connected

to X0/X1 pins) and

Fast external Clock Input (FCI) mode

(external clock connected to X0 pin)

• Feedback resistor = approx. 2 * 0.5 MΩ.

Feedback resistor is grounded in the center

when the oscillator is disabled or in FCI mode.

J2 Low-speed oscillation circuit:

• Feedback resistor = approx. 2 * 5 MΩ.

Feedback resistor is grounded in the center

when the oscillator is disabled.

Type Circuit Remarks

Hysteresis

inputs

Pull-up

Resistor

Hysteresis

inputs

Xout

FCI

FCI or osc disable

X1A

X0A

Xout

osc disable

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MB91460E Series

20 DS705-00002-1v3-E

K CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

LCD SEG/COM output

L CMOS level output

(programmable IOL = 5mA, IOH = -5mA

and IOL = 2mA, IOH = -2mA)

2 different CMOS hysteresis inputs with input

shutdown function

Automotive input with input shutdown function

TTL input with input shutdown function

Programmable pull-up resistor: 50kΩ approx.

Analog input

LCD Voltage input

Type Circuit Remarks

pull-up control

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

pull- down control

driver strength

control

data line

standby control for

input shutdown

LCD SEG/COM

pull-up control

pull- down control

driver strength

control

data line

CMOS hysteresis type1

Automotive inputs

TTL input

CMOS hysteresis type2

standby control for

input shutdown

VLCD

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MB91460E Series

DS705-00002-1v3-E 21

M CMOS level tri-state output

(IOL = 5mA, IOH = -5mA)

Analog input pin with protection

Type Circuit Remarks

tri-state control

data line

analog input line

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MB91460E Series

22 DS705-00002-1v3-E

■HANDLING DEVICES

1. Preventing Latch-up

Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5) or less than (VSS5orHVSS5)

is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins

and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal

breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum

ratings.

2. Handling of unused input pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected

to pull-up or pull-down resistor (2KΩto 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR)

before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5or

VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.

3. Power supply pins

In MB91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins

necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-up.

All of the power supply pins and ground pins must be externally connected to the power supply and ground

respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground

level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of

the MB91460 series must be connected to the current supply source via a low impedance.

It is also recommended to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between

power supply pin and ground pin near this device.

This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 µF (use a X7R ceramic

capacitator) to VCC18C pin for the regulator.

4. Crystal oscillator circuit

Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit

boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass

capacitors connected to ground, are located near the device and ground.

It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and

X1A pins are surrounded by ground plane for the stable operation.

Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this

device.

5. Notes on using external clock

When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In

the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to

the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible.

(Continued)

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MB91460E Series

DS705-00002-1v3-E 23

(Continued)

Example of using opposite phase supply

X0 (X0A)

X1 (X1A)

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MB91460E Series

24 DS705-00002-1v3-E

6. Mode pins (MD_x)

These pins should be connected directly to the power supply or ground pins. To prevent the device from entering

test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power

supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.

7. Notes on operating in PLL clock mode

If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may

continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-

running operation cannot be guaranteed.

8. Pull-up control

The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.

9. Notes on PS register

As the PS register is processed in advance by some instructions, when the debugger is being used, the exception

handling may result in execution breaking in an interrupt handling routine or the displayed values of the ﬂags in

the PS register being updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,

the operation before and after the EIT always proceeds according to speciﬁcation.

•The following behavior may occur if any of the following occurs in the instruction

immediately after a DIV0U/DIV0S instruction:

(a) a user interrupt or NMI is accepted;

(b) single-step execution is performed;

1. D0 and D1 flags are updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed

and the D0 and D1 ﬂags are updated to the same values as those in 1.

• The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed

to enable a user interrupt or NMI source while that interrupt is in the active state.

1. The PS register is updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the above instructions are executed and the PS register

is updated to the same value as in 1.

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MB91460E Series

DS705-00002-1v3-E 25

■NOTES ON DEBUGGER

1. Execution of the RETI Command

If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding

interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the

main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base

timer interrupt is enabled, stepping over the RETI instruction will always break on the ﬁrst line of the time-base

timer interrupt handler).

Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debug-

ging.

2. Break function

If the range of addresses that cause a hardware break (including event breaks) is set to the address of the

current system stack pointer or to an area that contains the stack pointer, execution will break after each

instruction regardless of whether the user program actually contains data access instructions.

To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the

target of the hardware break (including an event breaks).

3. Operand break

It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not

set the access to the areas containing the address of system stack pointer as a target of data event break.

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MB91460E Series

26 DS705-00002-1v3-E

■BLOCK DIAGRAM

1. MB91F467EA

DREQ0

DACKX0

DEOP0

DEOTX0

AIN0,AIN2,AIN3

BIN0,BIN2,BIN3

ZIN0,ZIN2,ZIN3

TTG8 to TTG11, TTG4/12 to TTG7/15

PPG4 to PPG15

TIN0 to TIN7

TOT0 to TOT3

CK2,CK4 to CK7

ICU0 to ICU7

OCU0 to OCU3

ALARM_0

PFM

SDA0,SDA2,SDA3

SCL0,SCL2,SCL3

AN0 to AN7,

AN16 to AN31

ATGX

SGA

SGO

SIN2,SIN4 to SIN7

SOT2,SOT4 to SOT7

SCK2,SCK4 to SCK7

SMC1P0 to SMC1P5

SMC1M0 to SMC1M5

SMC2M0 to SMC2M5

SMC2P0 to SMC2P5

ASX

RDX

WRX0 to WRX3

MCLKI

BGRNTX

CSX0 to CSX3,CSX6,CSX7

A0 to A25

D0 to D31

RX0 to RX1

TX0 to TX1

R-bus

I-bus

D-bus

FR60 CPU

core

Flash-Cache

8 KByte

Flash memory

1088 KByte (MB91F467EA)

ID-RAM

48 KByte

(MB91F467EA)

D-RAM

64 KByte

Bit search

CAN

2 channels

32 <-> 16

bus adapter

External

bus

interface

DMAC

5 channels

BRQ

MCLKE

MCLKO

WEX

BAAX

Clock modulator

Clock monitor MONCLK

Interrupt controller

INT0 to INT10,

INT12 to INT14

External interrupt

14 channels

Clock supervisor

Clock control

Reload timer

8 channels

Free-run timer

8 channels

Input capture

8 channels

Output compare

4 channels

Up/down counter

3 channels

PFM timer

1 channel

Alarm comparator

1 channel

LIN-USART

5 channels

3 channels

Real time clock

A/D converter

24 channels

Stepper motor controller

6 channels

Sound generator

1 channel

Standby-RAM

16 KByte

(MB91F467EA)

Hardware Watchdog

Shutdown / Recovery

Control

INT0 to INT3,

INT6 to INT9

Always ON Logic

PPG timer

12 channels

Always ON Logic

Bus converter

Extended D-bus

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MB91460E Series

DS705-00002-1v3-E 27

■A/D CONVERTER / RANGE COMPARATOR

The new A/D Converter with Range Comparator is available on MB91FV460B and some new ﬂash devices and

is backward compatible to the A/D converter used on older devices. Beside the Range Comparator, 32 separated

result data registers, a second interrupt ﬂag and a new behaviour regarding reading the ADCS0.ACH[5:0] bits

have been implemented.

There is one software incompatibility: Read-modify-write operation to the register ADCS0 is not allowed. See

the description of the ADCS0.ACH[5:0] bits on 35ff.

This chapter provides an overview of the A/D converter, describes the register structure and functions, and

describes the operation of the A/D converter.

1. Overview of A/D Converter and A/D Range Comparator

The A/D converter converts analog input voltages into digital values and provides the following features. Any

ADC cannel can be assigned to one of 4 Range Comparators.

1.1. Features of the A/D converter:

• Conversion time: minimum 1us per channel.

• RC type successive approximation conversion with sample & hold circuit

• 10-bit or 8-bit resolution

• Program section analog input from 32 channels

• 1 common result data register and 32 dedicated channel result data registers

• Single conversion mode: Convert the speciﬁed channel(s) only once.

• Continuous mode: Repeatedly convert the speciﬁed channels.

• Scan conversion mode: Continuous conversion of multiple channels, programmable for up to 32 channels

• Stop mode: Convert one channel, then temporarily halt until the next activation.

(Enables synchronization of the conversion start timing.)

• A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that

is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to

memory.

• A/D conversion of all enabled channels (scan conversion) can be followed by an A/D End of Scan interrupt

request to CPU. The data is stored into dedicated channel result registers, which can be read out using DMA

transfer.

• Conversion startup may be by software, external trigger (falling edge) or timer (rising edge).

1.2. Features of the A/D Range Comparator (RCO):

• 4 conversion result Range Comparator channels, comparing the upper 8 bit of the conversion result with an

upper and a lower threshold. The thresholds are programmable for the 4 comparators independendly.

• Any ADC channel can be assigned to one of the 4 range comparators.

• The comparision results will set “overﬂow” and “interrupt” ﬂags per ADC channel, depending on the conﬁgu-

ration. It is possible to conﬁgure the comparision for:

- “out of range”: The ﬂags are set if the A/D result is below the lower OR above the upper threshold.

- “inside range”: The ﬂags are set if the A/D result is above the lower AND below the upper threshold.

• The conﬁguration can be set individually per ADC channel.

• Range comparision can be followed by an A/D Range Comparator interrupt request to CPU.

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MB91460E Series

28 DS705-00002-1v3-E

2. A/D Converter Input Impedance

The following ﬁgure shows the sampling circuit of the A/D converter:

Analog

signal

source

Rext Rin

Cin

ADC

ANx

Analog SW

Do not set Rext over maximum sampling time (Tsamp).

Rext = Tsamp / (7*Cin) - Rin

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MB91460E Series

DS705-00002-1v3-E 29

3. Block Diagram of A/D Converter

The following ﬁgure shows block diagram of A/D converter.

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN1 0

AN1 1

AN1 2

AN1 3

AN1 4

AN1 5

AN1 6

AN1 7

AN1 8

AN1 9

AN2 0

AN2 1

AN2 2

AN2 3

AN2 4

AN2 5

AN2 6

AN2 7

AN2 8

AN2 9

AN3 0

AN3 1

MPX

Input Circuit

D/ A con vert e r

A/ D d a t a re g is t e r

Se q u e n t ia l

comparison register

R - Bus

Comparator

Samp le & Hold

circuit

A/D control register 0

A/D control register 1

Prescaler

ADC S 0/ 1

Operating

Clock

AVCC AVRH AVRL AVSS

ATGX

16- b it

Re lo a d Tim e r

CLKP

Decoder

A/D control register 2

A/D channel

data registers

ADCD00

ADCD31

ADC

Range

Comparator

4 digital

comparators

with upper

and lower

threshold

32 * 2 flags

(2 flags per

ADC channel)

RCO INT

INT2

INT

RCO Flags

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30 DS705-00002-1v3-E

4. Registers of the A/D Converter

The A/D converter with Range Comparator has the following registers:

Address

(ADC0)

Address

(ADC1 *1)

x=0 or 1 for ADC0, ADC1 *1 respectively Register

+0 +1 +2 +3

0001A0H0005E0HADxERH ADxERL A/D channel Enable register

0001A4H0005E4HADxCS1 ADxCS0 ADxCR1 ADxCR0 A/D Control / Status register 0 + 1,

A/D Conversion Result register

0001A8H0005E8HADxCT1 ADxCT0 ADxSCH ADxECH

Sampling timer setting register,

Start Channel setting register,

End Channel setting register

0006B0H0006DCHADxCS2 - - - A/D Control / Status register 2

000688H0006B4HRCOxH0 RCOxL0 RCOxH1 RCOxL1 Range Comparator 0,1 High/Low threshold

registers

00068CH0006B8HRCOxH2 RCOxL2 RCOxH3 RCOxL3 Range Comparator 2,3 High/Low threshold

registers

000690H0006BCHRCOxIRS Range Comparator Inverted Range Select

control

000694H0006C0HRCOxOF Range Comparator Overflow flags

000698H0006C4HRCOxINT Range Comparator Interrupt flags

0006A0H0006CCHADxCC0 ADxCC1 ADxCC2 ADxCC3 Channel control for ch 0 to 7

0006A4H0006D0HADxCC4 ADxCC5 ADxCC6 ADxCC7 Channel control for ch 8 to 16

0006A8H0006D4HADxCC8 ADxCC9 ADxCC10 ADxCC11 Channel control for ch 16 to 23

0006ACH0006D8HADxCC12 ADxCC13 ADxCC14 ADxCC15 Channel control for ch 24 to 31

0006E0H000720HADCxD0 ADCxD1 ADC Channel Data register, channel 0,1

0006E4H000724HADCxD2 ADCxD3 ADC Channel Data register, channel 2,3

0006E8H000728HADCxD4 ADCxD5 ADC Channel Data register, channel 4,5

0006ECH00072CHADCxD6 ADCxD7 ADC Channel Data register, channel 6,7

0006F0H000730HADCxD8 ADCxD9 ADC Channel Data register, channel 8,9

0006F4H000734HADCxD10 ADCxD11 ADC Channel Data register, channel 10,11

0006F8H000738HADCxD12 ADCxD13 ADC Channel Data register, channel 12,13

0006FCH00073CHADCxD14 ADCxD15 ADC Channel Data register, channel 14,15

000700H000740HADCxD16 ADCxD17 ADC Channel Data register, channel 16,17

000704H000744HADCxD18 ADCxD19 ADC Channel Data register, channel 18,19

000708H000748HADCxD20 ADCxD21 ADC Channel Data register, channel 20,21

00070CH00074CHADCxD22 ADCxD23 ADC Channel Data register, channel 22,23

000710H000750HADCxD24 ADCxD25 ADC Channel Data register, channel 24,25

000714H000754HADCxD26 ADCxD27 ADC Channel Data register, channel 26,27

000718H000758HADCxD28 ADCxD29 ADC Channel Data register, channel 28,29

00071CH00075CHADCxD30 ADCxD31 ADC Channel Data register, channel 30,31

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4.1. A/D Input Enable Register (ADER)

This register enables the analog input functions of the A/D converter. On MB91FV460B, additionally the bit

ADCHE in PORTEN register inﬂuences the enabling of analog input.

•ADERH : Access: Word, Half-word, Byte

•ADERL : Access: Word, Half-word, Byte

[ADE31-0]: A/D Input Enable

• Software reset (RST) clears ADEn and PORTEN.ADCHE to 0.

• Be sure to set start channel and end channel to cover all enabled channels.

1. On MB91F467E, ADC1 does not exist.

31 30 29 28 27 26 25 24 Bit

ADE31 ADE30 ADE29 ADE28 ADE27 ADE26 ADE25 ADE24

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

23 22 21 20 19 18 17 16 Bit

ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

15 14 13 12 11 10 9 8 Bit

ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

76543210Bit

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

ADEn PORTEN.

ADCHE Function

0 [initial] X Analog input of A/D channel n is disabled.

The ADC will not sample/convert this channel.

0 [initial]

Analog input of the channel n is enabled. Additionally, the port function register

(PFR,EPFR) of the corresponding port must be set . The PFR/EPFR will switch

the port to input direction (output driver = HiZ) and disable the digital input lines.

Analog input of the channel n is enabled. Setting the port function register(s) is

not necessary. ADEn will disable the digital input lines of the ports, but it does

not change the port’s direction.

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4.1. A/D Control Status Registers (ADCS2, ADCS1, ADCS0)

The A/D control status registers control and show the status of A/D converter. Do not overwrite ADCS0 register

during A/D converting.

•ADCS2 : Access: Byte

[bits 15:12] BUSY, INT, INTE, PAUS

These bits are a mirror of the corresponding bits in ADCS1, intended to quickly read out all status and interrupt

information using only one register access. To write the bits, access them via ADCS1.

[bits 11:10] -

These bits do not exist. Read operation returns 0.

[bit 9] INT2 (End of Scan Flag)

The End of Scan ﬂag is set when conversion data of the last channel is stored in ADCR, whereas the last channel

is deﬁned by ADECH register setting.

• If bit 8 (INTE2) is "1" when this bit is set, and the ADC runs in continous conversion mode, an End of Scan

interrupt request is generated or, if activation of DMA is enabled, DMA is activated.

• Only clear this bit by writing "0" when A/D conversion is halted.

• Initialized to "0" by a reset.

• If DMA is used, this bit is cleared at the end of DMA transfer.

• Read-modify-write operations read this bit as “1”.

[bit 8] INTE2 (Enable End of Scan Interrupt)

INTE2 enables the End of Scan interrupt in continous conversion mode. In the other conversion modi, this bit

has no effect.

Additionally, setting INTE2 changes the protect function of converted data (see description of ADCS1.PAUS).

15 14 13 12 11 10 9 8 Bit

BUSY INT INTE PAUS - - INT2 INTE2

0 0 0 0 0 0 0 0 Initial value

R R R R R0 R0 R/W R/W Attribute

INTE2 Function

0 [initial] Disable End of Scan interrupt,

ADC result protection protects the ADCR register data.

Enable End of Scan interrupt,

ADC result protection protects the ADCD0...ADCD31 register data

(in continous conversion mode only)

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•ADCS1 : Access: Half-word, Byte

[bit 15] BUSY (busy ﬂag and stop)

• Read-modify-write instructions read the bit as "1".

• Cleared on the completion of A/D conversion in single conversion mode.

• In continuous and stop mode, the ﬂag is not cleared until conversion is terminated by writing "0".

• Initialized to "0" by a software reset (RST).

• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.

[bit 14] INT (End of Conversion Interrupt ﬂag)

This bit is set when conversion data is stored in ADCR.

• If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is enabled,

DMA is activated.

• Only clear this bit by writing "0" when A/D conversion is halted.

• Initialized to "0" by a software reset (RST).

• If DMA is used, this bit is cleared at the end of DMA transfer.

[bit 13] INTE (End of Conversion Interrupt enable)

This bit is enables or disables the conversion completion interrupt.

• Cleared by a software reset (RST).

15 14 13 12 11 10 9 8 Bit

BUSY INT INTE PAUS STS1 STS0 STRT reserved

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

BUSY Function

Reading A/D converter operation indication bit. Set on activation of A/D con-

version and cleared on completion.

Writing Writing "0" to this bit during A/D conversion forcibly terminates con-

version. Use to forcibly terminate in continuous and stop modes.

INTE Function

0 Disable interrupt [Initial value]

1 Enable interrupt

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[bit 12] PAUS (A/D converter pause)

This bit is set when A/D conversion temporarily halts.

The A/D converter has one register to store the conversion result (ADCR) and additionally 32 ADC channel data

registers. If a conversion is ﬁnished and the data of the previous conversion has not been read out before,

previous data would be overwritten.

To avoid this problem, the next conversion data is not stored in the data registers until the previous value has

been read out (e.g. by DMA). A/D conversion halts during this time. A/D conversion resumes when the ADC

interrupt ﬂag ADCR1.INT is cleared.

The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:

• In continous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for

writing to the registers, but IRQ2 (End of Scan interrupt) is active.

• In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,

but IRQ (End of Conversion) is active.

• PAUS is cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting

condition of DMA transfer, this bit cannot be cleared.

• Regarding protect function of converted data, see Section “6. Operation of A/D Converter".

[bit 11, 10] STS1, STS0 (Start source select)

These bits select the A/D activation source.

• These bits are initialized "00" by software reset (RST).

• In multiple-activation modes, the ﬁrst activation to occur starts A/D conversion.

• The activation source changes immediately on writing to the register. Therefore care is required when switching

activation mode during A/D operation.

• The A/D converter detects falling edges on the external trigger pin. When external trigger level is "L" and if

these bits are changed to external trigger activation mode, A/D converting may starts.

• Selecting the timer selects the 16-bit reload timer 7.

Mode INTE2 Function

Single,

Stop X Protect ADCR (the common result register)

Continous 0 Protect ADCR (the common result register)

1 Protect ADCD0...ADCD31 (the dedicated channel data registers)

STS1 STS0 Function

0 0 Software activation [Initial value]

0 1 External trigger pin activation and software activation

1 0 Timer activation and software activation

1 1 External trigger pin activation, timer activation and software activation

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[bit 9] STRT (Start)

Writing "1" to this bit starts A/D conversion (software activation).

• Write "1" again to restart conversion.

• Initialized to "0" by a software reset (RST).

• In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate conver-

sion after clearing.)

• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.

[bit 8] reserved bit

Always write "0" to this bit.

•ADCS0 : Access: Half-word, Byte. Read-modify-write access is not allowed

[bit 7, 6] MD1, MD0 (A/D converter mode set)

These bits the operation mode.

• Single mode: A/D conversion is continously performed from the selected start channel (ADSCH)

to the selected end channel (ADECH). The conversion stops once it has been done

for all these channels.

• Continuous mode:A/D conversion is repeatedly performed from the selected start channel (ADSCH)

to the selected end channel (ADECH) in a row.

• Stop mode: A/D conversion is performed from the selected start channel (ADSCH) to

the selected end channel (ADECH), followed by a pause after each channel.

The conversion is resumed upon activation.

When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped

by the BUSY bit.

Conversion is stopped by writing "0" to the BUSY bit.

On activation after forcibly stopping, conversion starts from the start channel, selected by ADSCH register.

Reactivation during A/D conversion is disabled for any of the timer, external trigger and software start sources

in single mode 2, continuous and stop mode.

76543210Bit

MD1 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 /

ACHMD

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R R R R R,W *1

1. ACHMD is a new, control bit, see “[bit 0] ACHMD (ACH register mode, write-only)” on page 36.

Attribute

MD1 MD0 Operating mode

0 0 Single mode 1 (Reactivation during A/D conversion is allowed)

0 1 Single mode 2 (Reactivation during A/D conversion is not allowed)

1 0 Continuous mode (Reactivation during A/D conversion is not allowed)

1 1 Stop mode (Reactivation during A/D conversion is not allowed)

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[bit 5] S10

This bit deﬁnes resolution of A/D conversion. If this bit set "0", the resolution is 10-bit. In the other case, resolution

is 8-bit and the conversion result is stored to ADCR0 and in the lower 8 bits of the dedicated ADC result registers.

• Initialized to "0" by a reset.

[bit 4 to 0] ACH4-0 (Analog convert select channel, read-only)

These bits show the number of the currently or previously converted analog channel, depending on bit ACHMD

(see below).

• Writing these bits has no effect (bit 0 is writeable with special function ADCHMD).

• Initialized to "0000" by software reset (RST).

[bit 0] ACHMD (ACH register mode, write-only)

For reading out the ACH4-0 register bits (see below), there is a direct mode and a latched mode.

In direct mode, ACH4-0 shows the number of the ADC channel which is currently in conversion, e.g. the internal

conversion channel pointer. This pointer is incremented immediately after a conversion is ﬁnished. On MB91460

series devices having the old ADC macro, ACH4-0 always show this mode.

In the new latched mode, ACH4-0 shows the number of the ADC channel whose conversion was ﬁnished

previously. After a conversion is ﬁnished, the conversion channel pointer is latched and the latched data can be

read in this mode. At the end of the next conversion, the latch is overwritten if no PAUSE condition exists.

• ACHMD is a write-only bit.

• Read- or read-modify-write access returns the value of bit ACH0, that’s why read-modify-write access is not

allowed.

• Initial value is 0.

ACH4 ACH3 ACH2 ACH1 ACH0 Converted channel

00000 AN0

00001 AN1

... ...

11110 AN30

11111 AN31

ACHMD Function

0 Direct ACH register mode [Initial value]

1 Latched ACH register mode

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4.2. Common Data Register (ADCR1, ADCR0)

These registers store the conversion results of the A/D converter. ADCR0 stores lower 8-bit. ADCR1 stores

upper 2-bit. The register values are updated at the completion of each conversion. The registers normally store

the results of the previous conversion.

•ADCR1 : Access: Word, Half-word, Byte

•ADCR0 : Access: Word, Half-word, Byte

• Bit 15 to 10 of ADCR1 are read as "0".

• The A/D converter has a conversion data protection function. See the "Operation" section for further informa-

tion.

4.3. Dedicated A/D Channel Data Register (ADCD0 to ADCD31)

There are 32 ADC result data registers, one per channel. The registers are written by hardware at the end of

conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.

•ADCD0 ... ADCD31 : Access: Word, Half-word, Byte

• Bit 15 to 10 of the ADCD registers are read as "0".

• The A/D converter has a conversion data protection function. In continous conversion mode, the protection

function can be changed to protect the A/D Channel Data registers rather then the A/D Data Register (ADCR1).

See section “6.6. Protection of the ADC Channel Data Registers" for further information.

15 14 13 12 11 10 9 8 Bit

------D9D8

0 0 0 0 0 0 X X Initial value

R0, W0 R0, W0 R0, W0 R0, W0 R0, W0 R0, W0 R R Attribute

76543210Bit

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X Initial value

R R R R R R R R Attribute

15 14 13 12 11 10 9 8 Bit

------D9D8

0 0 0 0 0 0 X X Initial value

R0 R0 R0 R0 R0 R0 R R Attribute

76543210Bit

D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X Initial value

R R R R R R R R Attribute

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4.4. Sampling Timer Setting Register (ADCT)

ADCT register controls the sampling time and comparison time of analog input. This register sets A/D conversion

time. Do not update value of this register during A/D conversion operation.

•ADCT1: Access: Word, Half-word, Byte

•ADCT0: Access: Word, Half-word, Byte

[bit 15 to 10] CT5-0 (A/D comparison time set)

These bits specify clock division of comparison time.

• Setting "000001" means one division (=CLKP).

• Do not set these bits "000000".

• Initialized these bits to "000100" by software reset (RST).

• Comparison time = CT value * CLKP cycle * 10 + (4 * CLKP)

• Do not set comparison time over 500 us.

[bit 9 to 0] ST9-0 (Analog input sampling time set)

These bits specify sampling time of analog input.

• Initialized these bits to "0000101100" by software reset (RST).

• Sampling time = ST value * CLKP cycle

• Do not set sampling time below 1.2 us when AVCC is below 4.5 V.

Necessary sampling time and ST value are calculated by following.

• Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7

• ST9 to ST0 = Tsamp / CLKP cycle

ST has to be set that sampling time is over Tsamp.

Example: CLKP = 32MHz, AVCC >= 4.5V, Rext = 200K

Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [us]

ST = 15.17-6 / 31.25-9 = 485.44

ST has to be set over 486D (111100110B).

Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.

15 14 13 12 11 10 9 8 Bit

CT5 CT4 CT3 CT2 CT1 CT0 ST9 ST8

0 0 0 1 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

76543210Bit

ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

0 0 1 0 1 1 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

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4.5. A/D Channel Setting Register (ADSCH, ADECH)

These registers specify the channels for the A/D converter to convert. Do not update these registers while the

A/D converting is operating.

•ADSCH: Access: Word, Half-word, Byte

•ADECH : Access: Word, Half-word, Byte

These bits set the start and end channel for A/D converter.

• Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 speciﬁes conversion for that channel only.

(Single conversion)

• In continuous or stop mode, conversion is performed up to the channel speciﬁed by ANE4 to ANE0. Conversion

then starts again from the start channel speciﬁed by ANS4 to ANS0.

• If ANS > ANE, conversion starts with the channel speciﬁed by ANS, continuous up to channel 31, starts again

from channel 0, and ends with the channel speciﬁed by ANE.

• Initialized to ANS="00000", ANE="00000" by a software reset (RST).

Example: Channel Setting ANS=30ch, ANE=3ch, single conversion mode

Operation : Conversion channel 30ch -> 31ch -> 0ch -> 1ch -> 2ch -> 3ch end

[bit 12 to 8] ANS4-0 (Analog start channel set)

[bit 4 to 0] ANE4-0 (Analog end channel set)

15 14 13 12 11 10 9 8 Bit

- - - ANS4 ANS3 ANS2 ANS1 ANS0

- - - 0 0 0 0 0 Initial value

RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Attribute

76543210Bit

- - - ANE4 ANE3 ANE2 ANE1 ANE0

- - - 0 0 0 0 0 Initial value

RX, W0 RX, W0 RX, W0 R/W R/W R/W R/W R/W Attribute

ANS4

ANE4

ANS3

ANE3

ANS2

ANE2

ANS1

ANE1

ANS0

ANE0 Start / End Channel

00000 AN0

00001 AN1

00010 AN2

00011 AN3

... ...

11101 AN29

11110 AN30

11111 AN31

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5. Range Comparator

5.1. Range Comparator Structure

The Range Comparator has 4 comparsion groups with an upper and a lower threshold register each. The 32

ADC channels can be enabled for range comparision and assigned to one of the 4 comparators individually. If

enabled, the comparsision will set up to 2 ﬂags for this ADC channel:

• An interrupt ﬂag RCOINT, signalling that the ADC result is outside the range or, by “inverted” conﬁguration,

inside the range.

• An overﬂow ﬂag RCOOF, showing that the range violation was an overﬂow and no underﬂow.

Furthermore, each ADC channel can be enabled to send an interrupt request to the CPU, if the RCOINT ﬂag is set.

RCOH0[7:0]

RCOL0[7:0]

Upper/lower threshold regs Comparators

Flag

setting

logic

RCOH1[7:0]

RCOL1[7:0]

RCOH2[7:0]

RCOL2[7:0]

RCOH3[7:0]

RCOL3[7:0]

A/D Conversion result SAR[9:2]

AS[4:0] A/D Conversion current channel number

A/D Conversion result register load pulse (strobe)

ADCC0 : RCOIE, RCOE, RCOS[1:0]

A/D Channel Control registers (per ADC channel)

ADCC1 : RCOIE, RCOE, RCOS[1:0]

ADCC2 : RCOIE, RCOE, RCOS[1:0]

ADCC3 : RCOIE, RCOE, RCOS[1:0]

ADCC30 : RCOIE, RCOE, RCOS[1:0]

ADCC31 : RCOIE, RCOE, RCOS[1:0]

...

RCOS[1:0]: Select one of the 4 comparators for this channel

RCOE : Enable Comparision for this ADC channel

RCOIE: Enable Comparision Interrupt for this ADC channel

RCOOF

[0:31]

Overflow

flags

RCOINT

[0:31]

Interrupt

flags

OR RCOIRQ

to R-Bus

RCOIE[0:31]

ADE[31:0] A/D Channel Enable AND

RCOIRS[0:31]

Inverted Range Selection register:

Set the ags, if the ADC result is

inside upper and lower threshold,

instead of outside upper or lower

threshold (default).

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5.2. Range Comparator Registers

The Range Comparator (RCO) has the following registers:

• RCOHx[7:0] : Upper threshold register, one register per comparator block (x = 0...3)

• RCOLx[7:0] : Lower threshold register, one register per comparator block (x = 0...3)

• ADCCm[7:0] : ADC channel control, one register per 2 ADC channels (m = 0...15)

• RCOIRS[0:31] : RCO Inverted Range Selection, one bit per ADC channel

• RCOOF[0:31] : RCO Overﬂow Flags, one bit per ADC channel, read-only

• RCOINT[0:31] : RCO Interrupt Flags, one bit per ADC channel

5.2.1. Range Comparator Threshold registers (RCOH0/L0 to RCOH3/L3)

•RCOH0-3 : Higher threshold, access: Word, Half-word, Byte

[bit 7:0] RCOH[7:0] (Range Comparator High threshold)

The RCOH bits deﬁne the higher comparision threshold of the Range Comparator channel.

The upper Range Comparator compares that the upper 8 bits of the ADC conversion result are higher then

RCOH[7:0]

•RCOL0-3 : Lower threshold, access: Word, Half-word, Byte

[bit 7:0] RCOL[7:0] (Range Comparator Low threshold)

The RCOL bits deﬁne the lower comparision threshold of the Range Comparator channel.

The lower Range Comparator compares that the upper 8 bits of the ADC conversion result are lower then

RCOL[7:0]

15 14 13 12 11 10 9 8 Bit

RCOH7 RCOH6 RCOH5 RCOH4 RCOH3 RCOH2 RCOH1 RCOH0

1 1 1 1 1 1 1 1 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

76543210Bit

RCOL7 RCOL6 RCOL5 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

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5.2.2. A/D Converter Channel Control registers (ADCC0 to ADCC15)

The A/D channel control registers serve 2 ADC channels per register and control the range comparision for

these channels.

ADCC0 register controls A/D channels 0 + 1,

ADCC1 register controls A/D channels 2 + 3,

...

ADCC15 register controls A/D channels 30 + 31

•ADCC0-15: Access: Word, Half-word, Byte

[bit 7,3] RCOIE1, RCOIE0 (Range Comparator Interrupt enable)

The RCOIE bits enable the Range Comparator interrupt for the corresponding ADC channel.

[bit 6,2] RCOE1, RCOE0 (Range Comparator operation enable)

The RCOE bits enable the Range Comparision for the corresponding ADC channel:

[bits 5:4,1:0] RCOS1[1:0], RCOS0[1:0] (converter channel select)

These bits select the A/D converter channel to be assigned to the Range Comparator channel:

76543210Bit

RCOIE1 RCOE1 RCOS11 RCOS10 RCOIE0 RCOE0 RCOS01 RCOS00

0 0 0 0 0 0 0 0 Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

Bits 7:4 control A/D channels 1,3,5,7,...31 Bits 3:0 control A/D channels 0,2,4,6,...,30

RCOIE Function

0 RCO interrupt for this ADC channel is disabled [default]

1 RCO interrupt for this ADC channel is enabled

RCOE Function

0RCO disabled,

RCO flags for this ADC channel will not be set [default]

1 RCO enabled for this ADC channel

RCOS[1:0] Function

00 Select range comparator channel 0 for this ADC channel [de-

fault]

01 Select range comparator channel 1 for this ADC channel

10 Select range comparator channel 2 for this ADC channel

11 Select range comparator channel 3 for this ADC channel

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MB91460E Series

DS705-00002-1v3-E 43

5.2.3. Inverted Range Selection register

The RCOIRS register controlles that the comparision should check for “out of range” or “inside range”.

The 32 bits of RCOIRS is organized “per ADC channel”. ADC channel 0 is located on the MSB of the register

and ADC channel 31 is on the LSB.

•RCOIRS : Access: Word, Half-word, Byte

Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.

[bits 31:0] RCOIRS[0:31] (Inverted Range Select)

The RCOIRS bits control how the Range Comparator result ﬂags are set.

• If the RCOIRS[n] is 0, the ﬂags are set when the ADC result is above the upper threshold

OR below the lower threshold. That is called “out of range” mode.

• If the RCOIRS[n] is 1, the ﬂags are set when the ADC result is below or equal the upper threshold

AND above or equal the lower threshold. That is called “inside range” mode.

31 30 29 28 27 26 259 24 Bit

RCOIRS0 RCOIRS1 RCOIRS2 RCOIRS3 RCOIRS4 RCOIRS5 RCOIRS6 RCOIRS7

00000000Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

23 22 21 20 19 18 17 16 Bit

RCOIRS8 RCOIRS9 RCOIRS10 RCOIRS11 RCOIRS12 RCOIRS13 RCOIRS14 RCOIRS15

00000000Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

15 14 13 12 11 10 9 8 Bit

RCOIRS16 RCOIRS17 RCOIRS18 RCOIRS19 RCOIRS20 RCOIRS21 RCOIRS22 RCOIRS23

00000000Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

76543210Bit

RCOIRS24 RCOIRS25 RCOIRS26 RCOIRS27 RCOIRS28 RCOIRS29 RCOIRS30 RCOIRS31

00000000Initial value

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

RCOIRS

nFunction

0 Range comparision for this ADC channel checks for “out of range” (default)

1 Range comparision for this ADC channel checks for “inside range”

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44 DS705-00002-1v3-E

5.2.4. Range Comparator Result Flags

The result of range comparision is stored in 2 ﬂag registers:

• RCOINT[0:31]: Range comparision interrupt ﬂags

• RCOOF[0:31]: Range comparision overﬂow ﬂags

The Range Comparator Result ﬂags are organized “per ADC channel”. There are 32 Range Comparator overﬂow

ﬂags and 32 interrupt ﬂags. In case of a RCO interrupt, all interrupt ﬂags can be read out by one 32-bit read

operation and analyzed using the Bit Search Unit. The Bit Search Unit will return the number of the interrupting

channel. Since bit search works from MSB to LSB (from left to right), ADC channel 0 is located on the MSB of

the registers and ADC channel 31 is on LSB.

•RCOINT[0:31] : Access: Word, Half-word, Byte

Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.

[bits 31:0] RCOINT[0:31] (Range Comparator Interrupt ﬂags)

The RCOINT ﬂags show that a “out of range” or “inside range” condition has been found on the ADC channel.

The bits are set under the following condition:

• the ADC channel is enabled ADER.ADE[i] is set and

• the range comparision for this channel is enabledADCCn.RCOE[i] is setand

• the conversion of the ADC channel is just ﬁnished and

• an interrupt condition was found (see the table on next page).

• The bits are cleared by writing 0 or by software reset (RST). Writing 1 has no effect.

• Read-modify-write operations read 1.

31 30 29 28 27 26 259 24 Bit

RCOINT0 RCOINT1 RCOINT2 RCOINT3 RCOINT4 RCOINT5 RCOINT6 RCOINT7

00000000Initial value

R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute

23 22 21 20 19 18 17 16 Bit

RCOINT8 RCOINT9 RCOINT10 RCOINT11 RCOINT12 RCOINT13 RCOINT14 RCOINT15

00000000Initial value

R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute

15 14 13 12 11 10 9 8 Bit

RCOINT16 RCOINT17 RCOINT18 RCOINT19 RCOINT20 RCOINT21 RCOINT22 RCOINT23

00000000Initial value

R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute

76543210Bit

RCOINT24 RCOINT25 RCOINT26 RCOINT27 RCOINT28 RCOINT29 RCOINT30 RCOINT31

00000000Initial value

R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 Attribute

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MB91460E Series

DS705-00002-1v3-E 45

The interrupt condition depends on the comparision results and the RCOIRS setting for this channel:

Note: The upper threshold comparator returns 1 if the upper 8 bits of the ADC result are greather then the threshold

value in RCOH[7:0].

The lower threshold comparator returns 1 if the upper 8 bits of the ADC result are smaller then the threshold

value in RCOL[7:0].

•RCOOF[0:31] : Access: Read-only, Word, Half-word, Byte

Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.

[bits 31:0] RCOOF[0:31] (Range Comparator Overﬂow ﬂag)

The RCOOF read-only ﬂags store the output signal of the upper threshold comparator at the time when an

interrupt condition (see above) appeared and the corresponding RCOINT ﬂag was not set. So the RCOOF ﬂags

indicate the upper comparator state when the RCOINT ﬂag had the last rising edge.

Mode RCOIRS

Upper

threshold

comparator

Lower

threshold

comparator

Interrupt condition

out of

range 0

1 x INT condition: above range, RCOOF is set

00-

x 1 INT condition: below range, RCOOF is cleared

inside

range 1

1x-

0 0 INT condition: inside range

x1-

31 30 29 28 27 26 259 24 Bit

RCOOF0 RCOOF1 RCOOF2 RCOOF3 RCOOF4 RCOOF5 RCOOF6 RCOOF7

00000000Initial value

RRRRRRRRAttribute

23 22 21 20 19 18 17 16 Bit

RCOOF8 RCOOF9 RCOOF10 RCOOF11 RCOOF12 RCOOF13 RCOOF14 RCOOF15

00000000Initial value

RRRRRRRRAttribute

15 14 13 12 11 10 9 8 Bit

RCOOF16 RCOOF17 RCOOF18 RCOOF19 RCOOF20 RCOOF21 RCOOF22 RCOOF23

00000000Initial value

RRRRRRRRAttribute

76543210Bit

RCOOF24 RCOOF25 RCOOF26 RCOOF27 RCOOF28 RCOOF29 RCOOF30 RCOOF31

00000000Initial value

RRRRRRRRAttribute

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MB91460E Series

46 DS705-00002-1v3-E

The RCOOF ﬂag for a ADC channel is loaded with the upper threshold comparator output signal under the

following condition:

• the corresponding RCOINT ﬂag is not yet setand

• the corresponding RCOINT ﬂag has a set condition in this cycle.

The ﬂags are initialized by software reset (RST).

5.3. Range Comparator Interrupt request

The Range Comparator has one interrupt output line RCOIRQ. The interrupt output line becomes active if at

least one of the Range Comparator interrupt ﬂags RCOINT[31:0] is set and the corrsponding interrupt enable

bit in the ADCC registers is set..

It is not possible to activate a DMA request from the range comparator interrupts.

RCOOFn Function

0 The output of the upper threshold comparator was 0 [default]

1 The output of the upper threshold comparator was 1

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6. Operation of A/D Converter

The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. There is

one 16-bit register provided to store conversion results (ADCR), which is updated each time conversion com-

pletes. Additionally, there is one ADC Channel Data register per channel (ADCD0...31), which is updated each

time the assigned channel is converted. The Channel Data registers especially improve the continous conversion

mode.

It is recommended to use the DMA service. The following describes the operation modes.

6.1. Single Mode

In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted in

order until the completion of conversion on the end channel determined by the ANE bits. A/D conversion then

ends. If the start channel and end channel are the same (ANS=ANE), only a single channel conversion is

performed.

Examples:

• ANS=00000b, ANE=00011b

Start -> AN0 -> AN1 -> AN2 -> AN3 -> End

• ANS=00010b, ANE=00010b

Start -> AN2 -> End

6.2. Continuous Mode

In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in order until

the completion of conversion on the end channel determined by the ANE bits, then the converter returns to the

ANS channel for analog input and repeats the process continuously. When the start and end channels are the

same (ANS=ANE), conversion is performed continuously for that channel.

Examples:

• ANS=00000b, ANE=00011b

Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 ... -> repeat

• ANS=00010b, ANE=00010b

Start -> AN2 -> AN2 -> AN2 ... -> repeat

In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit forcibly

stops the conversion operation.) Note that forcibly terminating operation halts the current conversion during mid-

conversion. (If operation is forcibly terminated, the value in the conversion register is the result of the most

recently completed conversion.)

6.3. Stop Mode

In stop mode the analog input signal selected by the ANS bits and ANE bits are converted in order, but conversion

operation pauses after each channel. The pause is released by applying another start signal.

At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the

ANS channel for analog input signal and repeats the conversion process continuously. When the start and end

channel are the same (ANS=ANE), only a signal channel conversion is performed.

Examples:

• ANS=00000b, ANE=00011b

Start -> AN0 -> stop -> start -> AN1 -> stop -> start -> AN2 -> stop -> start -> AN3 -> stop -> start -> AN0 ...

-> repeat

• ANS=00010b, ANE=00010b

Start -> AN2 -> stop -> start -> AN2 -> stop -> start -> AN2 ... -> repeat

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48 DS705-00002-1v3-E

In stop mode the startup source is the source determined by the STS1, STS0 bits. This mode enables synchro-

nization of the conversion start signal.

6.4. Single-shot Conversion

The following ﬁgure shows the operation of A/D converter in Single-shot conversion mode

(1) Channel selection

(2) A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)

(3) INT ﬂag clear, BUSY ﬂag set

(4) Sample hold

(5) Conversion (Conversion a + Conversion b + Conversion c)

(6) Conversion end, INT ﬂag set, BUSY ﬂag clear

(7) Buffers the conversion value. Buffered data storage

(8) Software-based INT ﬂag clear

Channel

selection

Activation

(trigger)

AN input

Internal level

Conversion

value

Conversion

aConversion

bConversion

Sample

hold

Buffer

(ADT)

Conversion end

(INT)

BUSY

Flag clear

(A/D conversion

activation,

or software)

(1)

(2)

(3)

(4) (5)

(6)

(7)

(8)

Flag clear on A/D conversion activation

Conversion time

Conversion in progress Finalized

Previous conversion value New conversion value

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6.5. Scan Conversion

The following ﬁgure shows the operation of A/D converter in Scan conversion mode

(1) Activation channel selection

(2) A/D activation (Trigger: Software trigger/Reload timer/External trigger)

(3) INT ﬂag clear, PAUS ﬂag clear

(4) AN0 conversion

a. Sample hold, conversion (conversion a + conversion b + conversion c)

b. Conversion end

c. Buffers the conversion value.

(5) AN1 conversion

(6) AN2 conversion

(7) AN3 conversion

(8) INT2 (End of Scan) ﬂag is set, AN0 conversion starts

(9) Because INT2 has not been cleared yet, the ADC protects the result register of AN0

against overwriting and enters PAUSE state.

(10)INT2 ﬂag cleared by DMA or by software, the ADC stores the result of AN0 and continues sampling AN1.

6.6. Protection of the ADC Channel Data Registers

There are 32 ADC result data registers, one register per channel. The registers are written by hardware at the

end of conversion of the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.

The CPU can read the data registers any time.

Scan start

channel

selection

Activation

(trigger)

AN input

Result registers

End of Scan INT

PAUS

AN1 AN2 AN3

ADCD0

ADCD1

ADCD2

ADCD3

a, b, c

AN0 AN1 AN2 AN3

AN0

(6)

(5)

(4)

(3)

(2)

(1)

(7)

(8)

(9)

(10)

AN1 conversion value

AN2 conversion value

AN3 conversion value

AN0 conversion value

Sample hold

AN0

(5)

(4)

AN0 next conversion value

AN1 next value

AN0

AN2 next value

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50 DS705-00002-1v3-E

If a conversion is ﬁnished and the data of the previous conversion has not been read out before, previous data

would be overwritten. To avoid this problem, the next conversion data is not stored in the data registers until the

previous value has been read out (e.g. by DMA). A/D conversion halts during this time and the PAUS ﬂag is set.

A/D conversion restarts when the ADC interrupt ﬂag ADCR1.INT is cleared.

The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:

6.6.1. Protection of ADCD0...31

In continous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for

writing to the registers, but IRQ2 (End of Scan interrupt) is already active.

Example: Start channel =4, end channel=7, continous mode, ADCS1.INTE=0, ADCS2.INTE2=1

Start by CPU --> convert channel 4 + safe data to ADCD4,

convert channel 5 + safe data to ADCD5,

convert channel 6 + safe data to ADCD6,

convert channel 7 + safe data to ADCD7 ---> End of Scan interrupt (IRQ2),

convert channel 4 + set PAUS (protect ADCD4...7).

After the CPU or DMA have read the data registers and cleared IRQ2, the scan conversion continues.

6.6.2. Protection of ADCR

In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers,

but IRQ (End of Conversion) is active. Because in this mode the protection function is active after each single

conversion, the ADCR register is protected.

7. ADC Interrupt Generation and DMA Access

There are 2 ADC interrupt sources: End of Conversion and End of Scan.

7.1. End of Conversion

The End of Conversion (EoC) interrupt is enabled by ADCS1.INTE bit and is compatible to the A/D convertes

in old devices of MB91460 series. If EoC is enabled, it appeares after any conversion cycle. It is recommended

to use DMA transfer to read out the data from ADCR.

7.2. End of Scan

The End of Scan (EoS) interrupt is enabled by ADCS2.INTE2 bit. If EoS is enabled, it appeares after the

conversion of the end channel, which is deﬁned by the setting of ADECH register.

If the End of Conversion interrupt is enabled in parallel, both interrupt bits are set. In this case it is recommended

that the interrupt routine reads out ADCS2 register (containing mirrored bits of ADCS1[7:4]) to check where the

interrupt comes from.

7.3. DMA Transfer

DMA transfer can be triggered by End of Conversion interrupt or by End of Scan interrupt. The interrupts are

assigned to separate DMA resource numbers (please refer to the Interrupt Vector Table).

Mode INTE2 Function

Single,

Stop X Protection of ADCR

Continous 0 Protection of ADCR

1 Protection of ADCD0...ADCD31

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The automatic interrupt clear after DMA transfer works for End of Conversion and for End of Scan separately.

■HARDWARE WATCHDOG (Extension)

This chapter describes a new feature of the Hardware Watchdog. For reference, please refer to

chapter 21 Hardware Watchdog in the MB91460 series hardware manual.

1. Enabling the Hardware Watchdog in SLEEP and STOP State

The Hardware Watchdog can now be enabled in SLEEP and STOP state by software. On old devices, the

watchdog is cleared in SLEEP and STOP and restarts counting at the transition to RUN mode.

Additionally, the restriction of MB91V460A about the settings ED1,ED0 = 01,10,11 has been removed.

1.1. HWWDE: Hardware watchdog timer duration register

The Hardware Watchdog Timer Duration register changes like following:

• Bit7-5: Reserved bits. Always write 0 to these bits.

• Bit4: STP_RUN (Run in SLEEP/STOP mode):

- STP_RUN = 1 enables that the Hardware Watchdog continues running in SLEEP and STOP mode.

The RC Oscillator will continue operation in SLEEP and STOP too.

- STP_RUN = 0 (default) the the Hardware Watchdog is cleared in SLEEP and STOP mode.

- STP_RUN can be set by CPU, but it cannot be cleared by the CPU

- STP_RUN is cleared by software reset (RST)

• Bit3-2: Reserved bits. Always write 0 to these bits.

• Bit1-0: ED (Elongate watchdog duration).

- These bits are cleared by software reset (RST) and can be written and read by CPU.

1.2. Caution

The section “Caution” changes as follows:

• Software disabling is not possible.

The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop the

counting.

• Hardware disabling is only possible on the evaluation device MB91V460A and MB91FV460B.

The watchdog timer can be permanently disabled by setting the corresponding jumper of the

7654 3210Bit

---STP_RUN - - ED1 ED0

X X X 0 X X 0 0 Initial value

RX, W0 RX, W0 RX, W0 R, W1 RX, W0 RX, W0 R, W R, W Attribute

ED1-0 Function

00 The watchdog period is 216 CLKRC cycles [initial setting]

01 The watchdog period is 217 CLKRC cycles

10 The watchdog period is 218 CLKRC cycles

11 The watchdog period is 219 CLKRC cycles

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52 DS705-00002-1v3-E

evaluation board (this is not possible on ﬂash devices with this watchdog timer). So always ensure

correct conﬁguration of the evaluation system to reﬂect the behaviour of the ﬂash device.

• Postponement of reset

In order to postpone the watchdog reset, the clearing of the watchdog timer is necessary. Whenever the CL

bit of register is set to ‘0’ (there is no minimum writing limitation), the timer is cleared and the occurrence of

reset is postponed. Just writing to the register without setting CL to ‘0’ does not clear the timer.

• Timer stop and clear

In modes where the CPU does not work (SLEEP state, STOP state or STOP with RTC active state), the timer

is cleared ﬁrst then the counting is stopped. If the bit HWWDE.STP_RUN is set, the counting continues,

and the RC oscillator will continue too.

• During DMA transfer

During DMA transfer between D-bus modules, the writing e0f to CL bit is not possible. Thus, if the transfer

timeis more than 328ms (calculated from the fastest frequency of the RC oscillator as minimum period), a

reset occurs.

• Duration setting

Unlike on MB91V460 Rev.A it is possible to elongate the duration of the watchdog reset.

• CLKRC frequency

Unlike on MB91V460 Rev.A it is possible to change the CLKRC frequency to 2MHz. Even though the watchdog

timer is always operated with a frequency of 100kHz (10us) typical.

• Difference between watchdog reset, external reset and Power-on reset

External reset pin (INITX), Clock Supervisor and Hardware Watchdog build a “reset chain”:

External reset pin / Power-On reset

→ Clock Supervisor

→ Hardware Watchdog

→ Shutdown Controller 1

→ CPU

Each module in the chain transferes the incoming reset signal to its reset output.

External reset pin or Power-On will clear all the modules in the chain, but the Hardware Watchdog reset will

not clear the Clock Supervisor.

■

1. Shutdown Controller is implemented on MB91F467E only.

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■CLOCK SUPERVISOR (New Feature)

This section gives an overview of the Clock Supervisor. Purpose of the Clock Supervisor is the supervision of the

Main- and Sub oscillators. In case of oscillation (OSCMAIN or OSCSUB) failure the Clock Supervisor control logic

will take action, i.e. switching to an internal RC-oscillation clock (CLKRC 100kHz), depending on the operation

mode set in the control register.

In MB91FV460B, MB91F467P and other new devices, an new Clock Supervisor version with extended functional-

ity is implemented. This new feature is marked with the keyword “New feature”.

1. Overview Clock Supervisor

Figure 0-1 Block diagram of the clock supervisor

The purpose of the clock supervisor is the supervision of the main and sub oscillation clocks. In case of a

oscillation failure (OSCMAIN and/or OSCSUB) it can be replaced by an on-chip RC-oscillation clock (CLKRC

100kHz), depending on the conﬁguration.

If a clock the MCU currently uses, fails for a certain time (20-80 s for Main clock / 160-640 s for Sub clock)

the MCU is reset by Setting Initialization Request (INIT) and the reset cause can be checked after reset vector

fetch.

If the Sub clock is failing while the MCU is in Main clock mode, reset can be delayed until the transition to Sub

clock mode or no reset will be initiated. The user can choose the behaviour with a control bit in the Clock

Supervisor Control Register.

There are two independent supervisors, one for the Main clock and one for the Sub clock. They can be enabled/

disabled separately.

Main clock and Sub clock supervisor are disabled and re-enabled automatically if the corresponding oscillator

is disabled and re-enabled.

If the MCU changes to STOP state, the RC-oscillator can be automatically disabled by a control bit. It will be

enabled again upon wake-up from STOP state.

There are two status bits in the Clock Supervisor Control Register which indicate the failure of the Main clock

and Sub clock. These bits can be available at two port pins (device dependent).

Single clock devices can use the CLKRC as Sub clock.

Ma in

Oscillator

4MHz

Sub

Oscillator

32kHz

Oscillator

2MHz

100kHz

Ct rl.

Lo g ic

Ma in Clo ck SV

Ct rl.

Lo g ic

Sub Clo ck SV

CSVCR_

MSVE

CSVCR_

SSVE

CSCFG_

RCSEL

CLKRC 100kHz

CLKM AIN

CLKS U B

CLKRC

OSCMAIN

OSCSUB

µµ

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MB91460E Series

54 DS705-00002-1v3-E

New feature: The two Clock Supervisor status bits can be cleared by CPU access, if the main and/or sub oscillator

has resumed oscillation. The clock is switched back to OSCMAIN and/or OSCSUB in this case.

New feature: The RC oscillator is enabled in STOP mode automatically, if the Hardware Watchdog is conﬁgured

to run during STOP. The RC oscillator can only be stopped in STOP mode, and then it depends on the Hardware

Watchdog and the control bit in the Clock Supervisor Control Register.

2. Clock Supervisor Register

This section lists the Clock Supervisor Control Register and describes the function of each bit in detail.

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MB91460E Series

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2.1. Clock Supervisor Control Register (CSVCR)

The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor. Figure 0-2

shows the conﬁguration of the Clock Supervisor Control Register.

Figure 0-2 Conﬁguration Clock Supervisor Control Register (CSVCR)

76543210

R/W R

R/W

R/W R/W R/W

bit0

OUTE Output enable

0Do not enable ports for MCLK_MISSING and

SCLK_MISSING output pins

1Enable ports for MCLK_MISSING and

SCLK_MISSING output pins

bit1

SRST Sub clock mode reset

0do not perform reset upon transition from Main clock to

Sub clock modes if Sub clock is already missing

1perform reset upon transition from Main clock to Sub

clock modes if Sub clock is already missing

bit2

SSVE Sub clock supervisor enable

0 disable Sub clock supervisor

1 enable Sub clock supervisor

bit3

MSVE Main clock supervisor enable

0 disable Main clock supervisor

1 enable Main clock supervisor

bit4

RCE RC oscillator enable

0 disable RC-oscillator in STOP mode

1 enable RC-oscillator in STOP mode

bit5

SM Sub clock missing

0 Missing Sub clock has not been detected

1 Missing Sub clock has been detected

bit6

MM Main clock missing

0 Missing Main clock has not been detected

1 Missing Main clock has been detected

bit7

SCKS Sub clock select (in single clock devices always 0)

0 32k oscillation used as Sub clock

1 RC oscillation used as Sub clock

0 0 0 1 1 1 0 0

OUTE

SCKS

MM SM RCE

MSVE

SSVE SRST

Initial Value

0004AD

W0 W0

New feature

R/W0 : Readable and writeable (0 only)

R/W : Readable and writable

R : Read only

: Initial value

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Table 0-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR).

Table 0-1 Functional Description of each bit of the Clock Supervisor Control Register

Bit Name Function

SCKS

(Sub clock se-

lect)

This bit is to select between 32 kHz external oscillation and internal RC oscillation as

Sub clock. If this bit is ‘0’ then the external 32 kHz oscillation is used as Sub clock, if it’s

‘1’ then the internal RC oscillation is used as Sub clock. This bit is cleared to ’0’ by Pow-

er-On reset or external reset. Other types of reset will not affect this bit.

Note: Don’t change this bit while the CPU runs on Sub clock. First switch back to Main

clock and then change SCKS!

(Main clock

missing)

If this bit is 1, the Main clock supervisor has detected that the Main oscillation clock com-

ing from X0, X1 is missing, e.g. by a broken crystal. If this bit is ‘0’, a missing Main clock

has not been detected. This bit is cleared to ’0’ by Power-On reset or external reset. Oth-

er types of reset will not affect this bit.

New feature: This bit can be cleared by CPU access, if the main oscillator has resumed

oscillation. If the main oscillator is still failing, the write access is ignored.

(Sub clock

missing)

If this bit is 1, the Sub clock supervisor has detected that the sub oscillation clock coming

from X0A, X1A is missing, e.g. by a broken crystal. If this bit is ‘0’, a missing Sub clock

has not been detected. This bit is cleared to ’0’ by Power-On reset or external reset. Oth-

er types of reset will not affect this bit.

New feature: This bit can be cleared by CPU access, if the sub oscillator has resumed

oscillation. If the sub oscillator is still failing, the write access is ignored.

RCE

(RC-oscillator

enable)

Setting this bit to ‘1’ enables the RC-oscillator in STOP mode. Outside STOP mode, the

RC-oscillator is always enabled. This bit is set to ’1’ by Power-On reset or external reset.

Other types of reset will not affect this bit.

New feature: If HWWDE.STP_RUN (=HWWDE[4]) is set in the Hardware Watchdog,

then the RC oscillator is enabled and read and read-modify-write operations will return

‘1’ independendly of RCE register setting.

Effective RCE = RCE_Register or HWWDE.STP_RUN

MSVE

(Main clock

supervisor en-

able)

Setting this bit to ‘1’ enables the Main clock supervisor. This bit is set to ’1’ by Power-On

reset only. Other types of reset will not affect this bit.

SSVE

(Sub clock su-

pervisor en-

able)

Setting this bit to ‘1’ enables the Sub clock supervisor. This bit is set to ’1’ by Power-On

reset only. Other types of reset will not affect this bit.

SRST

(Sub clock

mode reset)

If this bit is set to ‘1’, a reset is performed upon transition from Main/PLL clock mode to

Sub clock mode if the Sub clock is already missing. If this bit is set to ‘0’, no reset is per-

formed in this case. This bit is cleared to ’0’ by Power-On reset or external reset. Other

types of reset will not affect this bit.

OUTE

(Output en-

able)

This bit can be used as an output enable to output the signals MCLK_MISSING (bit 3 of

CSVCR) and SCLK_MISSING (bit 4 of CSVCR) to port pins. For more information about

the pins see the corresponding Datasheet. If this bit is set to ’1’, the ports are enabled

for MCLK_MISSING and SCLK_MISSING output. This bit is cleared to ’0’ by Power-On

reset or external reset. Other types of reset will not affect this bit.

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3. Block Diagram Clock Supervisor

This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock Supervisor are:

• Main Clock Supervisor

• Sub Clock Supervisor

• Control Logic

• RC-Oscillator

3.1. Block Diagram Clock Supervisor

Figure 0-3 Bock Diagram of Clock Supervisor

SCLK_OUT and MCLK_OUT can be observed using the Clock Monitor Module. SCLK_MISSING and

MCLK_MISSING can be programmed to device speciﬁc outputs (see the datasheet of the used device for the

information which pins are used) by setting OUTE=1.

R-Bus

Clock Supervisor

Main Clock

Supervisor

MCLK

STBY

RC_CLK

NO_MCLK

Sub Clock

Supervisor

SCLK

STBY

RC_CLK

NO_SCLK

Control Logic

NO_MCLK

NO_SCLK

SCLK_STBY

SSEN

MCLK_STBY

MSEN

RC_CLK

Clock Supervisor Control Register

CSVCR

CLK

RC_CLK

01234567

RCESMMM

OUTE

SCKS

MSVE

SSVE

SRST

RCE

TO_MCLK

TO_SCLK

Timeout Counter

RC-Oscillator

STBY RC_CLK RC_CLK

ERSXOERSX

PONR

TB_ST

RC_CLK

EXT_RST_OUT

OUTE

SCLK_MISSING

MCLK_MISSING

CLKMAIN

CLKSUB

EXT_RST_IN

PONR

OSC_STAB

OSCMAIN

MCLK_STBY

OSCSUB

SCLK_STBY

MUX

SCKS

f/2

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Signal EXT_RST_IN is the reset input, connected to the external INITX pin.

Signal EXT_RST_OUT is the reset output and causes Setting Initialization Request (INIT).

4. Operation Modes

This section describes all operation modes of the Clock Supervisor.

4.1. Operation mode with initial settings

In case the clock supervisor control register (CSVCR) is not conﬁgured at the beginning of the user program,

the RC-oscillator, the Main clock supervisor and the Sub clock supervisor is enabled.

• The RC-oscillator is enabled at power-on.

• The Main clock supervisor is enabled after the ’oscillation stabilization wait time’ or in case the Main clock is

missing before the completion of the ’oscillation stabilization wait time’, after the ’Main clock timeout’

(TO_MCLK) from the timeout counter. The timeout counter is clocked with CLKRC. If the Main clock is missing

from power-on, the power-on reset state is never left, which in this case is a safe state. The user must make

sure with external pull-up/pull-down resistors that all relevant signal are pulled to the correct level.

• The Sub clock supervisor is enabled after the completion of the ’Sub clock timeout’ (TO_SCLK) from the

timeout counter. The timeout counter is clocked with CLKRC.

• If the Main clock stops while the Main clock supervisor is enabled, the Main clock is replaced with CLKRC

100kHz, the MM bit is set to ’1’ and reset (EXT_RST_OUT) is asserted.

• If the Sub clock stops and the Sub clock supervisor is enabled, the behaviour depend on whether the MCU is

in Main clock mode or in Sub clock mode. If the Sub clock stops in Sub clock mode, CLKRC divided by two

substitutes the Sub clock, the SM bit is set to ’1’ and reset (EXT_RST_OUT) is asserted. If the Sub clock stops

in Main clock mode, CLKRC divided by two substitutes the Sub clock, the SM bit is set to ’1’ and no reset

occurs upon transition to Sub clock mode, since the SRST bit has its initial value of ’0’. If the SRST bit is ‘1’ a

reset (INIT) occurs.

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Figure 0-4 Timing Diagram: Initial settings, Main clock missing during power-on reset

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

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Figure 0-5 Timing Diagram: Initial settings, Main clock missing during ’oscillation stabilization wait time’

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

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Figure 0-6 Timing Diagram: Initial settings, Main clock missing after ’oscillation stabilization wait time’

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

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Figure 0-7 Timing Diagram: Initial settings, Sub clock missing before timeout

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

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Figure 0-8 Timing Diagram: Initial settings, Sub clock missing after timeout

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

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4.2. Disabling the RC-oscillator and the clock supervisors

The initial point of this scenario is that the RC-oscillator and Main clock or Sub clock supervisor is enabled.

• The RC-oscillator can be disabled only in STOP mode.

First check that both SM and MM (bit 5 and bit 6 of CSVCR) are ’0’.

Then disable the RC-oscillator by setting RCE to ’0’. If either SM or MM bit is ’1’, RCE must not be set to ’0’.

•New feature: If the Hardware Watchdog is to run in STOP mode (HWWDE.STP_RUN=’1’) then the RC-

oscillator is enabled by hardware.

• The Main clock supervisor is disabled by setting MSVE (bit 3 of CSVCR) to ’0’.

• The Sub clock supervisor is disabled by setting SSVE (bit 2 of CVSVR) to ’0’.

Figure 0-9 Timing Diagram: Disabling the RC-oscillator and the clock supervisors

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

RCE

STOP

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4.3. Re-enabling the RC-oscillator and the clock supervisors

The initial point of this scenario is that the RC-oscillator and both Main clock and Sub clock supervisor are

disabled.

• The RC-oscillator is always enabled in RUN state. It can only be disabled in STOP, and after wakeup from

STOP it will re-start automatically.

• The Main clock supervisor is enabled by setting MSVE (bit 3 of CSVCR) to ’1’.

• The Sub clock supervisor is enabled by setting SSVE (bit 2 of CSVCR) to ’1’.

Figure 0-10 Timing Diagram: Re-enabling the RC-oscillator and the clock supervisors

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

RCE

STOP

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4.4. New feature: Switching back from RC to Main Oscillation

The initial point of this scenario is that the Main clock was missing, the Main clock supervisor has set the MM

ﬂag and switched to RC clock. The CPU already got reset (INIT) from clock supervisor and has detected MM=1

as reset source (See "Check if reset was asserted by the Clock Supervisor" on P. 73). The user is quite sure

that the Main clock returned meanwhile or will return soon and wants to switch back to Main clock.

• The MM ﬂag can be cleared by writing ‘0’ (bit 6 of CSVCR).

• If the Main clock is still missing during the write access, the write operation has no effect, the MM ﬂag keeps

‘1’ value and the clock supervisor continues giving out RC clock.

• If the Main clock is operating during the write access, the MM ﬂag is cleared and the clock is switched back

to Main clock.

• It is possible to poll the MM ﬂag until the Main clock is resumed:

ldi #_csvcr,r1

clear_CSV_loop:

bandh #0b1001,@r1 ;; Clear MM+SM

btsth #0b0110,@r1 ;; Check: Is one of them 1?

bne clear_CSV_loop

4.5. New feature: Switching back from RC to Sub Oscillation

The initial point of this scenario is that the CPU is running on Sub clock and Sub clock was missing. The Sub

clock supervisor has set the SM ﬂag and switched to RC clock (divided by 2). A clock supervisor reset was not

generated because of CSVCR.SRST was ‘0’. Now the CPU is running user software on RC clock. The ﬂag

SM=1 was found by polling. The user is quite sure that the Sub oscillation returned meanwhile or will return

soon and wants to switch back to Sub oscillation.

• The SM ﬂag can be cleared by writing ‘0’ (bit 5 of CSVCR).

• If the Sub clock is still missing during the write access, the write operation has no effect, the SM ﬂag keeps

‘1’ value and the clock supervisor continues giving out RC clock.

• If the Sub clock is operating during the write access, the SM ﬂag is cleared and the clock is switched back to

Sub clock.

• It is possible to poll the SM ﬂag like described in the Main clock example above.

4.6. Sub clock modes

The Main clock supervisor is automatically disabled in Sub clock modes. The enable bit MSVE remains un-

changed. At transition from Sub clock mode to Main clock mode the Main clock supervisor is enabled after the

’oscillation stabilization wait time’ or in case the Main clock is missing before the completion of the ’oscillation

stabilization wait time’, after the ’Main clock timeout’ (TO_MCLK) from the timeout counter. The timeout counter

is clocked with CLKRC.

4.7. Changing the behaviour upon transition to Sub clock mode if the Sub clock has already

stopped in Main clock mode

If the Sub clock has stopped in Main clock mode and this was detected by the Sub clock supervisor, the behaviour

upon transition to Sub clock mode depends on the state of the SRST bit.

• If SRST is set to ’0’ (initial value), reset is not asserted at the transition to Sub clock mode. The transition is

performed using the RC-oscillation clock as Sub clock. In this case it is recommended to check the SM bit

before the transition to Sub clock mode to get the information if Sub clock or CLKRC is used.

• If SRST is set to ’1’, reset is asserted at the transition to Sub clock mode.

The following timing diagrams (Figure 0-11,Figure 0-12, ) illustrate this behaviour.

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Figure 0-11 Timing Diagram: Sub clock missing in Main clock mode, SRST=0

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

Clock Mode

Main Sub

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Figure 0-12 Timing Diagram: Sub clock missing in Main clock mode, SRST=1

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

Clock Mode

Main Main

Sub

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Timing Diagram: Waking up from Sub clock mode

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

Main Sub Main

Clock Mode

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4.8. STOP mode (with both oscillators disabled)

In this section, “STOP mode” means that the CPU is in STOP state and both oscillators are disabled by setting

STCR.OSCD1=’1’ and STCR.OSCD2=’1’. The Clock Supervisor’s inputs MCLK_SBY and SCLK_SBY are con-

nected to the oscillator disable lines OCSD1 and OSCD2, respectively.

If Main clock and Sub clock supervisors are enabled, they will be automatically disabled at transition into STOP

state. The corresponding enable bits in the clock supervisor control register remain unchanged. So after wake-

up from STOP mode the clock supervisors will be enabled again. If the corresponding enable bits are set to ’0’,

the clock supervisors will stay disabled after wake-up from STOP mode.

The RC-oscillator is disabled in STOP, if the RCE bit in the CSVCR register is cleared.

New feature: If the Hardware Watchdog is enabled in STOP state (HWWDE.STP_RUN=’1’), then the RC-

oscillator is enabled by hardware during STOP. The RCE bit is unchanged, but read and read-modify-write

operations return ‘1’.

• The RC-oscillator is enabled immediately after wake-up from STOP mode.

• The Main clock supervisor is enabled after the ’oscillation stabilization wait time’ or in case the Main clock is

missing after wake-up from STOP mode, after the ’Main clock timeout’ (TO_MCLK) from the timeout counter.

The timeout counter is clocked with CLKRC.

• The Sub clock supervisor is enabled after the ’Sub clock timeout’ (TO_SCLK) from the timeout counter which

is clocked with the CLKRC.

Figure 0-13 Timing Diagram: Waking up from STOP state

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

RCE

Clock Mode

Main Stop Main

Sub

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4.9. RTC mode (STOP mode with Real Time Clock enabled)

In this section, “RTC mode” means that the CPU is in STOP state and one of the quartz oscillators is enabled

by setting STCR.OSCD1=’0’ or STCR.OSCD2=’0’. The enabled oscillator clock is switched to the Real Time

Clock to keep it running during STOP. The behavoiur of the Clock Supervisor depends on several settings.

• If the RTC is connected to Main clock, the behaviour of the main clock supervisor is like described in Table 0-2

Note New feature: RCE setting is valid if HWWDE.STP_RUN (HWWDE[4]) is ‘0’. Otherwise, RCE is overwritten to ‘1’.

• If the RTC is connected to Sub clock, the behaviour of the sub clock supervisor is like described in Table 0-3

Note New feature: RCE setting is valid if HWWDE.STP_RUN (HWWDE[4]) is ‘0’. Otherwise, RCE is overwritten to ‘1’.

• The RC-oscillator is enabled immediately after wake-up from STOP state.

Table 0-2 Main Clock Supervisor in RTC mode.

oscillator

enable

CSVCR.RCE

Main

Oscillator

disable

STCR.OSCD1

Main clock

supervisor

enable

SVCR.MSVE

Behaviour in STOP mode if Main clock fails and the RTC

is connected to Main clock

11X

Main clock fail cannot be seen because the Main oscillator is

disabled. The Main clock supervisor is disabled because of the Main

oscillator is disabled. The RTC will not run because of the same

reason. Note: This is no RTC mode.

101

The clock supervisor will set MM ﬂag, switch the Main clock to RC

clock and generate an reset (INIT) to CPU. The STOP mode is

cancelled by the reset. The RTC is initialized by the reset.

100

Main clock supervisor is disabled by MSVE=0. In case of Main clock

fail, the RTC clock simply stopps.

0XX

Main clock supervisor is disabled because of it does not get RC

clock. In case of Main clock fail, the RTC clock simply stopps.

Table 0-3 Sub Clock Supervisor in RTC mode.

oscillator

enable

CSVCR.RCE

Sub

Oscillator

disable

STCR.OSCD2

Sub clock

supervisor

enable

SVCR.SSVE

Behaviour in STOP mode if Sub clock fails and the RTC is

connected to Sub clock

11X

Sub clock fail cannot be seen because the Sub oscillator is disabled.

The Sub clock supervisor is disabled because of the Sub oscillator is

disabled. The RTC will not run because of the same reason. Note:

This is no RTC mode.

101

The clock supervisor will set SM ﬂag and switch the Sub clock to RC

clock.The RTC continues running on RC clock. A reset is not

generated because there is no transition from Main clock to Sub

clock during STOP mode.

100

Sub clock supervisor is disabled by SSVE=0. In case of Sub clock

fail, the RTC clock simply stopps.

0XX

Sub clock supervisor is disabled because of it does not get RC clock.

In case of Sub clock fail, the RTC clock simply stopps.

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• If the Main clock was disabled in STOP: The Main clock supervisor is enabled after the ’oscillation stabilization

wait time’ or in case the Main clock is missing after wake-up from STOP state, after the ’Main clock timeout’

(TO_MCLK) from the timeout counter. The timeout counter is clocked with CLKRC.

• IF the Sub clock was disabled in STOP: The Sub clock supervisor is enabled after the ’Sub clock timeout’

(TO_SCLK) from the timeout counter which is clocked with the CLKRC.

4.10. RC-Clock as Sub Clock

The Sub clock supervisor can provide the CLKRC as Sub clock. To enable this feature, SCKS bit (bit7 of CSVCR)

must be set to ’1’.

Figure 0-14 Timing Diagram: Sub clock mode with single clock device

PONR

MCLK

SCLK

RC_CLK

OSC_STAB

MSVE

MSEN

SSVE

SSEN

MCLK_STBY

SCLK_STBY

TO_MCLK

TO_SCLK

EXT_RST

EXT_RST_OUT

MCLK_OUT

SCLK_OUT

MCLK_MISSING

SCLK_MISSING

SRST

RCE

SCKS

Main Sub

Clock Mode

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4.11. Check if reset was asserted by the Clock Supervisor

To ﬁnd out whether the Clock Supervisor has asserted reset, the software must check the reset cause by reading

the RSRR register (see the hardware manual "RSRR: Reset Cause Register" on P. 229). On the most ﬂash

devices, the RSRR register is read and cleared by the Boot ROM software. The content of RSRR can be found

in CPU register R4[7:0] after Boot ROM is done.

If INIT (bit 7 of RSRR) is set, the cause was either external reset at the INITX pin or the clock supervisor or the

hardware watchdog (HWWD). If neither SM bit nor MM bit (bit 5 and bit 6 of CSVCR) is set, reset cause was

the external reset or the hardware watchdog. If SM is ’1’ the reset cause is a missing Sub clock and if MM is ’1’

the reset cause is a missing Main clock.

5. Cautions

After a Clock Supervisor reset, the CLKPLL is not usable as clk source, if the clock supervisor reset was

caused by a missing OSCMAIN.

■USART LIN/FIFO (Extension)

This chapter describes an extension of the USART (LIN/FIFO USART).

For reference, please refer to chapter 32 USART (LIN/FIFO) in the MB91460 series hardware manual.

1. USART End of Transmission Interrupt (ET)

The USART macros have been extended to generate an “End of Transmission” (ET) interrupt after the last bit

of a transmission has been sent. If ET is enabled and there is no FIFO installed, the interrupt is generated after

each transmission. If FIFO is installed, ET appeares after the transmission while the FIFO is empty.

The ET interrupt cannot request a DMA transfer.

The ET can be enabled and observed in the FSR (FIFO Status Register). Therefore, also USART modules which

are not equipped with FIFO, have the FIFO Status Register.

1.1. USART Interrupts

With the ET interrupt, the list of USART interrupts extends to:

Reception/

transmis-

sion/

ICU

Inter-

rupt

request

ﬂag

Flag

Operation

mode Interrupt

cause

Interrupt

cause

enable bit

How to clear

the Interrupt

Request

01 2 3

Reception

RDRF SSR x x x x

receive data is writ-

ten to RDR

(FIFO level reached)

SSR:RIE

Receive data

is read

ORE SSR x x x x Overrun error "1" is written to

clear rec. error

bit (SCR: CRE)

FRE SSR x x *1x Framing error

PE SSR x *2Parity error

LBD ESCR x x LIN synch break

detected

ESCR:

LBIE

"0" is written to

ESCR:LBD

TBI &

RBI ESCR x x x no bus activity ECCR:BIE Receive data /

Send data

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1.2. FSR: FIFO Status register for ET interrupt control

The FSR register ontrols and observes the ET interrupt and displays FIFO status (if FIFO is installed).

• bit15: TDRE Transmission Data Register Empty ﬂag (shadow)

- This is a read-only shadow of TDRE ﬂag. Interrupt routines can determine the interrupt source

(TDRE or ET) by just reading the FSR register.

• bit 14: ETINT End of Transmission interrupt ﬂag

- This ﬂag is set when the ET condition has appeared:

If no FIFO is installed, after the last bit of a transmission has been sent,

if FIFO is installed, after the last bit of a transmission has been sent and the FIFO is empty.

- This ﬂag is cleared by software reset (RST) or by writing 0.

- Writing 1 has no effect.

- Read - modify - write access always reads 1.

• bit13: ETIE End of Transmission interrupt enable

- ETIE = 1 enables that the ET interrupt request is sent to the CPU when ETINT is set.

- ETIE = 0 (default) disables the ET interrupt request.

- This bit is cleared by software reset (RST) and can be written and read by CPU.

• bit12-8: NVFD[4:0] Number of valid FIFO data

- These bits indicate the number of stored receptions (SVD=0) or pending transmissions (SVD=1)

in the FIFO buffer.

- If no FIFO is installed, these bits return 0x00.

Transmission

TDRE SSR or

FSR *3xxx xEmpty transmission

written

ET FSR xxx xEnd of transmission

[and FIFO empty *4]FSR:ETIE "0" is written to

FSR:ETINT

Input Cap-

ture Unit

ICP4 IPCP x x 1st falling edge of LIN

synch field IPCP:ICE disable ICE

temporary

ICP4 IPCP x x 5th falling edge of

LIN synch field IPCP:ICE disable ICE

1. Only available if ECCR04/SSM = 1

2. Only available if ECCR04/SSM = 1

3. FSR:TDRE is a read-only mirror of the SSR:TDRE bit

4. if FIFO is installed

X: Used

15 14 13 12 11 10 9 8 Bit

TDRE ETINT ETIE NVFD (Number of valid FIFO data)

XX000000Initial value

R R,W0 R,W R RRRRAttribute

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■

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■SHUTDOWN MODE

1. Overview

In Shutdown mode, the power supply of more then 80% of the internal logic and the main memories is switched

off to minimize leakage.

This mode is a type of STOP state.

The device can enter this mode if it goes to STOP state when Shutdown is enabled.

During this mode, the oscillators can stop oscillating and the power is not supplied except for some logic.

The power continues to be supplied to the following circuits even in shutdown state:

• Standby RAM 16 KByte for data (address FFFAC000H to FFFAFFFH)

• Shutdown / recovery control circuit

• Clock control logic

• Real Time Clock

• 4 MHz oscillator + 32 kHz oscillator + RC oscillator

• Hardware Watchdog + Clock Supervisor

In the “BLOCK DIAGRAM” on page 26, this part of the device is called “Always ON Logic”:

The device will recover from Shutdown mode after the following events:

• Reset assertion by the INITX pin 1

• External interrupt (8 sources)

• Real Time Clock interrupt

• Hardware watchdog reset

• Main Clock Supervisor reset

1. Reset by the INITX pin will kill the ShutDown state and restart the device like at power-on.

DEOP0

DEOTX0

TTG8 to TTG11, TTG4/12 to TTG

PPG4 to PPG15

TIN0 to TIN7

TOT0 to TOT3

5 channels

Clock

modulator

Clock monitor MONCLK

INT0 to INT10,

INT12 to INT14

External interrupt

14 channels

Clock supervisor

Clock control

Reload timer

8 channels

Real time clock

Standby-RAM

16 KByte

(MB91F467EA)

Hardware Watchdog

Shutdown / Recovery

Control

INT0 to INT3,

INT6 to INT9

Always ON Logic

PPG timer

12 channels

Always ON Logic

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2. Standby RAM

MB91F467E containes a 16 KByte low-leakage RAM used as Standby RAM. The power supply of this RAM is

not switched off in Shutdown state.

The Standby RAM is located at addresses FFFAC000H to FFFAFFFH.

To access it, to the RAM must be enabled by setting RAMEN bit in SHDE register. RAMEN is initialized by

Software Reset (RST). If the RAM is to be accessed, make sure that no external bus Chip Select area overlaps

the Standby RAM addresses.

The bit RAMEN is written using CLKP, while the Standby RAM is accessed with CLKB. If CLKP is slower then

CLKB, make sure to have some wait time (at least 2 CLKP periods) between setting of RAMEN and ﬁrst RAM

access.

For the Standby RAM, low-leakage macros have been implemented. Read and write acces are performed with

1 wait cycle.

3. Shutdown Registers

3.1. Notes About the Reset Signals

The following register description mentiones different reset signals, which are explained shortly here. For more

information, please refer to the MB91460 series hardware manual, “Chapter 9 Reset”.

• Settings Initialization Reset (INIT):

initializes all the device’s control and clock settings. INIT can be triggered

- by low level on external INITX pin

- by low level on external HSTX pin (no hardware standby pin available in MB91460E series)

- by Hardware Watchdog Timer

- by Clock Supervisor

- by Software Watchdog Timer

- by Low Voltage Detection

• Operation Initialization Reset (RST, “Software Reset”):

initializes CPU and peripherals and restarts the software. RST can be triggered

- by low level on external RSTX pin (not available in MB91460E series)

- by INIT (INIT always causes RST)

- by software (STCR.SRST=0)

• Shutdown Recovery: The Shutdown state is released when a valid recovery factor is found. Shutdown recovery

causes a Settings Initialization Reset (INIT) with some exceptions. For details, please refer to “Recovery from

shutdown mode” on page 88.

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3.2. SHDE: Shutdown control register

This register enables/disables the shutdown state as well as the Standby RAM.

•SHDE : Address 0004D4H Access: Byte

[bit 7] SDENB : Shutdown enable

[bit 6 to bit 1] Reserved bits

• The read value is undeﬁned.

• Always write 0 to these bits.

[bit 0] RAMEN : Standby RAM enable

Note: RAMEN is cleared by INIT and by Software Reset because the chip select control registers (CSER,

ACR0-7, ASR0-7, AWR0-7) are initialized by the same conditions. After both kinds of reset, chip select CS0

is enabled to cover all addresses of external bus area, which would overlap the Standby RAM address space.

Note: The bit RAMEN is written using CLKP, while the Standby RAM is accessed with CLKB. If CLKP is slower then

CLKB, make sure to have some wait time (at least 2 CLKP periods) between setting of RAMEN and ﬁrst

RAM access.

76543210

SDENB - - - - - - RAMEN

0 X X X X X X 0 Initial value 1

1. Initial value after external pin INITX=0 or Shutdown Recovery

retained X X X X X X 0 Initial value 2

2. Initial value after Software Reset (RST)

R/W - - - - - - R/W Attribute

SDENB Function

1 Enable shutdown state: On transition to STOP mode, the device enters Shutdown state.

0 Disable shutdown state: On transition to STOP mode, the device enters the normal STOP mode.

RAMEN Function

1 Enable the Standby RAM 1: Read and write access to the Standby RAM is possible

1. The Standby RAM is located inside the address space of External Bus. If the Standby RAM is

enabled, make sure that no chip select area of the External Bus overlaps the standby RAM area.

0 Disable the Standby RAM: Read and write access to the Standby RAM is disabled.

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3.3. EXTE: Shutdown recovery external interrupt enable register

This register enables external interrupts as the source for recovering from the shutdown state.

•EXTE : Address 0004D6H Access: Byte

Eight external interrupts that can be set as recovery sources are allocated to each bit, as shown in the table

below:

[bit 7 to bit 0] Interrupt enable bits

• These bits can be read and written.

• External pin INITX=0 or Shutdown recovery clear these bits.

76543210

RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0

0 0 0 0 0 0 0 0 Initial value 1

1. Initial value after external pin INITX=0 or Shutdown Recovery

retained retained retained retained retained retained retained retained Initial value 2

2. Initial value after Software Reset (RST)

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

bit Pin No Pin Name

7 93 P32_2/RX1/INT9

6 91 P23_0/RX0/INT8

5 90 P24_7/SCL3/INT7

4 89 P24_6/SDA3/INT6

3 86 P24_3/INT3

2 85 P24_2/INT2

1 84 P24_1/INT1

0 83 P24_0/INT0

Value Function

1 Enable recovery interrupt

0 Disable recovery interrupt

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3.4. SHDINT: Shutdown recovery internal interrupt control and status register

The SHDINT register containes control bits and ﬂags for enabling and indicating internal interrupts for recovery

from shutdown mode.

•SHDINT : Address 0004DBH Access: Byte

[bit 7 to bit 4] Reserved bits

• The read value is undeﬁned.

• Always write 0 to these bits.

[bit 3] HWWDF: Hardware Watchdog recovery ﬂag

• This bit is set in Shutdown mode, if HWWDE is set and if an INITX signal from Hardware Watchdog is detected.

• Writing "1" to this bit does not affect the operation.

• Writing "0" cleares the bit, external pin INITX=0 cleares the bit.

• "1" is read by a read-modify-write instruction.

[bit 2] HWWDE: Hardware Watchdog recovery enable (mirror of HWWDE.STP_RUN 1)

• This bit is a read-only mirror of HWWDE.STP_RUN, which can be set only once after reset and cannot be

cleared by CPU access.

• This bit is cleared by Software Reset (RST). Note that external pin INITX=0 or Shutdown recovery are always

followed by a Software Reset RST.

76543210

- - - - HWWDF HWWDE RTCF RTCE

X X X X 0 0 0 0 Initial value 1

1. Initial value after external pin INITX=0

X X X X retain 0 retain 0 Initial value 2

2. Initial value after Shutdown Recovery

X X X X retain 0 retain retain Initial value 3

3. Initial value after Software Reset (RST)

----

R(RM1)/

W0 RR(RM1)/

W0 R/W Attribute

HWWDF Function

1 Recovery factor from Hardware Watchdog found

0 No recovery factor from Hardware Watchdog found

1. STP_RUN is bit HWWDE[4]

HWWDE Function

1Recovery reset from Hardware Watchdog is enabled,

RC clock is enabled in STOP/Shutdown mode by hardware

0Recovery reset from Hardware Watchdog is disabled,

RC clock depends on CSVCR.RCE setting in STOP/Shutdown mode

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[bit 1] RTCF: Real Time Clock recovery ﬂag

• This bit is set in Shutdown mode, if RTCE is set and an interrupt signal from Real Time Clock is detected.

• Writing "1" to this bit does not affect the operation.

• Writing "0" cleares the bit, external pin INITX=0 cleares the bit.

• "1" is read by a read-modify-write instruction.

[bit 0] RTCE: Real Time Clock recovery enable

• This bit can be read and written.

• External pin INITX=0 or Shutdown recovery clear this bit.

RTCF Function

1 Recovery factor from Real Time Clock found

0 No recovery factor from Real Time Clock found

RTCE Function

1 Recovery reset from Real Time Clock is enabled

0 Recovery reset from Real Time Clock is disabled

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3.5. EXTF: Shutdown recovery external interrupt source ﬂags

This register indicates the recovery source for when a shutdown recovery external interrupt is used to recover.

•EXTF : Address 0004D7H Access: Byte

The bit conﬁguration is the same as for the EXTE register.

[bit 7 to bit 0] Interrupt factor ﬂag bits

The bit corresponding to any input signal found to be valid as a recovery factor is set to "1."

• These bits are set in Shutdown mode, when the attached external interrupt channel is enabled by EXTE=1

and a recovery factor (level / edge) from the external interrupt channel is detected.

• Writing "1" to these bits does not affect the operation.

• Writing "0" cleares the bits, external pin INITX=0 cleares the bits.

• "1" is read by a read-modify-write instruction.

76543210

RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0

0 0 0 0 0 0 0 0 Initial value 1

1. Initial value after external pin INITX=0

retained retained retained retained retained retained retained retained Initial value 2

2. Initial value after Shutdown Recovery

retained retained retained retained retained retained retained retained Initial value 3

3. Initial value after Software Reset (RST)

R(RM1)/

W0 Attribute

Value Function

1 Recovery factor found

0 No recovery factor found

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3.6. EXTLV1/2: Shutdown recovery external interrupt level selection register

This register sets the pin level for recovering from the shutdown state using an external interrupt.

•EXTLV1 : Address 0004D8H Access: Halfword, Byte

•EXTLV2 : Address 0004D9H Access: Halfword, Byte

Source levels of eight external interrupts that can be set as recovery sources are allocated to each bit, as shown

in the table below.

[bit15 to bit0]: Interrupt level setting register

Please refer to “External Interrupts: Level or Edge Setting” on page 87.

15 14 13 12 11 10 9 8

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

0 0 0 0 0 0 0 0 Initial value 1

1. Initial value after external pin INITX=0 or Shutdown Recovery

retained retained retained retained retained retained retained retained Initial value 2

2. Initial value after Software Reset (RST)

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

76543210

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

0 0 0 0 0 0 0 0 Initial value 1

1. Initial value after external pin INITX=0 or Shutdown Recovery

retained retained retained retained retained retained retained retained Initial value 2

2. Initial value after Software Reset (RST)

R/W R/W R/W R/W R/W R/W R/W R/W Attribute

bit Pin No Pin Name

15,14 93 P23_2/RX1/INT9

13,12 91 P23_0/RX0/INT8

11,10 90 P24_7/SCL3/INT7C

9,8 89 P24_6/SDA3/INT6D

7,6 86 P24_3/INT3

5,4 85 P24_2/INT2

3,2 84 P24_1/INT1

1,0 83 P24_0/INT0

LBx LAx Interrupt Level

0 0 "L" level (initial value)

0 1 "H" level

1 0 Rising edge

1 1 Falling edge

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4. Shutdown Operation

4.1. Transition to shutdown state

Shutdown state is a special kind of the STOP state. During Shutdown, the settings in the STCR register for

Oscillation Disable (STCR.OSCD1, STCR.OSCD2), Hi-Z mode (STCR.HIZ) and Oscillation Stabilization time

(STCR.OS[1:0]) are valid the same kind as in normal STOP state. At recovery from Shutdown, STCR.OS[1:0]

are not cleared to maintain the oscillator stabilisation time, while STCR.OSCD1, STCR.OSCD2 and STCR.HIZ

are initialized by the recovery.

For transition into Shutdown, do the following:

• Enable at least one recovery condition (otherwise, recovery is only possible by external INITX pin)

• Enable the Shutdown mode

• Switch the device to STOP mode

The details are explained below.

4.1.1. Precautions

Before enabling Shutdown, consider the following:

• Data, which is needed after recovery from Shutdown, should be copied into the Standby RAM.

• The CPU should run on Main- or Sub-Oscillation, not on PLL. The PLL should be disabled.

• The Sub-Regulator can be set to 1.2V in STOP mode by setting REGSEL.SUBSEL = 0x00

• Specify the levels of external interrupt signals used for recovery in EXTLV1/2 registers

• Enable the channels of external interrupt signals for recovery in EXTE register

4.1.2. Deep Shutdown Settings for maximal power saving

The following settings generate Shutdown without any activity on the device:

• Disable all pin pull-up/pull-down settings which are not required, or set the STCR.HIZ 1bit when going to STOP.

• Set external bus pins to port mode / input direction (otherwise some pins will output constant values,

see “I/O Behaviour in Shutdown” on page 91).

• Don’t set Hardware Watchdog Run in STOP mode (HWWDE.STP_RUN 2 =0, this is default setting)

• Disable the RC oscillator in STOP mode (CSVCR.RCE=0)

• Disable the Low Voltage Detection in STOP mode (LVDET.LVEPD=1, LVDET.LVIPD=1)

• Disable the Main and the Sub oscillators in STOP mode (STCR.OSCD1=1, STCR.OSCD2=1)

• Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode

• Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times.

1. With STCR.HIZ=1, all pull-ups and pull-downs are disabled in STOP/Shutdown.

2. STP_RUN is bit [4] of HWWDE register. It enables running the Hardware Watchdog in STOP mode.

STP_RUN can only be set by software, but not cleared. STP_RUN is cleared by INIT.

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4.1.3. Shutdown with Real Time Clock running

The following settings generate Shutdown with the RTC running on Main-Oscillation, Sub-Oscillation or RC

clock, and with recovery by RTC enabled:

• Set the RTC prescaler values depending on the clock speed (WTBR register)

• If recovery by the RTC is needed:

- Enable at least one of the the RTC interrupts (half-second, second, minute, hour or day) in WTCR and/or

WTCE register

- Enable RTC recovery: set SHDINT.RTCE=1

• If RTC uses Main Oscillation:

- Disable the RC oscillator in STOP mode (CSVCR.RCE=0)

- Disable the Sub oscillator in STOP mode (STCR.OSCD2=1) and keep Main oscillator running (OSCD1=0)

- The RTC is connected to Main oscillation by default.

• If RTC uses Sub Oscillation:

- Disable the RC oscillator in STOP mode (CSVCR.RCE=0)

- Disable the Main oscillator in STOP mode (STCR.OSCD1=1) and keep Sub oscillator running (OSCD2=0)

- Connect the RTC to Sub oscillator: set CSCFG.CSC[1:0]=01

• If RTC uses RC clock:

- Enable the RC oscillator in STOP mode (CSVCR.RCE=1, this is default setting)

- Disable the Main and the Sub oscillators in STOP mode (STCR.OSCD1=1, STCR.OSCD2=1)

- Connect the RTC to RC oscillator: set CSCFG.CSC[1:0]=10

• Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode

• Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times.

4.1.4. Hardware Watchdog in Shutdown

The Hardware Watchdog can run in STOP mode, if the bit HWWDE.STP_RUN 1 is set.

• Outside STOP mode, the Hardware Watchdog timeout will send an INIT signal to the CPU via the Shutdown

control.

• In STOP mode without Shutdown, the Hardware Watchdog timeout will send an INIT signal to the CPU via

the (inactive) Shutdown control, which cancelles the STOP mode immediately.

• In STOP mode with Shutdown enabled, the Hardware Watchdog timeout will set the SHDINT.HWWDF ﬂag,

causing a recovery from Shutdown.

The Hardware Watchdog can be enabled in Shutdown state like follows:

• Enable the Hardware Watchdog operation in STOP mode: set HWWDE.STP_RUN = 1

In parallel, this enables the RC oscillator by hardware, and the Hardware Watchdog recovery Enable bit

SHDINT.HWWDE is set by hardware too.

• If RTC is needed, enable it like described in 4.1.3. Shutdown with Real Time Clock running above.

• Specify the levels of external interrupt signals used for recovery in EXTLV1/2 registers

• Enable the channels of external interrupt signals for recovery in EXTE register

• Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode

• Clear/restart the Hardware Watchdog: write 0 to bit HWWD.CL

• Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times.

1. STP_RUN is bit [4] of HWWDE register. It enables running the Hardware Watchdog in STOP mode.

STP_RUN can only be set by software, but not cleared. STP_RUN is cleared by INIT.

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If the timeout is reached, the Hardware Watchdog generates INIT, which cancelles the Shutdown state and

forces recovery. The CPU will run on Main Oscillation after this recovery.

WARNING: If a Hardware Watchdog timeout INIT signal appeares just at the transition to Standby Mode, the device

may enter an unpredictable state. Always make sure that the hardware Watchdog has been cleared

just before entering Shutdown.

4.1.5. Clock Supervisor in Shutdown

The INITX pin, Clock Supervisor and Hardware Watchdog form the “external INIT chain”, like shown in the ﬁgure

in section “Determining the Reset Source after Shutdown” on page 89. The Shutdown control is part of this chain.

An INIT signal from the Clock Supervisor will pass the Hardware Watchdog and arrive at the same Shutdown

control input line as the INIT signal from Hardware Watchdog. Therefore, clock supervision in Shutdown mode

is only possible if the Hardware Watchdog is operating in parallel.

If the Hardware Watchdog is disabled in Shutdown mode, an INIT signal from the Clock Supervisor is ignored

in Shutdown.

The Clock Supervisor is enabled by default. In Shutdown mode, as long as the Main- and/or Sub-oscillator is

running and the RC clock is not stopped, the CSV is supervising the Main- or Sub-oscillator, respectively.

• The Clock Supervisor needs the RC clock, so set CSVCR.RCE=1, this is default setting.

• If the Main-oscillator is not stopped (STCR.OSCD1=0), the Main clock supervisor is running.

• If the Main-oscillator fails, the Main Clock Supervisor generates INIT, which can cancel the Shutdown state

and force recovery. The CPU runs on RC clock during and after the recovery.

• If the Sub-oscillator is not stopped (STCR.OSCD2=0), the Sub Clock Supervisor is running.

• If the Sub-oscillator fails, the Sub clock is switched to RC clock divided by 2. An INIT is not generated, and

the Real Time Clock continues running on on RC clock divided by 2, if RTC is enabled.

To disable the Clock Supervisor, clear the bits CSVCR.MSVE and CSVCR.SSVE.

4.1.6. Low Voltage Detection in Shutdown

Low Voltage Detection is not supported in Shutdown mode. Always set the Low Voltage Detection into power

down mode (LVDET.LVEPD=1, LVDET.LVIPD=1) before enabling Shutdown.

4.1.7. External Interrupts: Input Voltage Setting

The input voltages (CMOS-Schmitt, Automotive, TTL, CMOS-2) of the external interrupt lines are deﬁned by the

setting of PILR and EPILR of the appropriate ports. The PILR and EPILR settings for the 8 external recovery

interrupt lines are maintained during Shutdown mode until they are cleared by the Software reset following the

Recovery INIT.

EPILR PILR Pin No Pin Name

EPILR23[2] PILR23[2] 93 P23_2/RX1/INT9

EPILR23[0] PILR23[0] 91 P23_0/RX0/INT8

EPILR24[7] PILR24[7] 90 P24_7/SCL3/INT7C

EPILR24[6] PILR24[6] 89 P24_6/SDA3/INT6D

EPILR24[3] PILR24[3] 86 P24_3/INT3

EPILR24[2] PILR24[2] 85 P24_2/INT2

EPILR24[1] PILR24[1] 84 P24_1/INT1

EPILR24[0] PILR24[0] 83 P24_0/INT0

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4.1.8. External Interrupts: Level or Edge Setting

The registers EXTLV1 and EXTLV2 are used to set the interrupt level or edge for recovery per interrupt channel.

The settings “level” and “edge” generate different behaviour if the external source line is not changed back after

recovery of if it changes to the sensitive level before Shutdown.

Examples:

• INT0 is enabled for recovery on risong edge. If a rising edge appeares during Shutdown state, recovery is

performed. If a rising edge is outside Shutdown state, there will be no recovery:

• INT0 is enabled for recovery on high level. If INT0 changes to high level during Shutdown state, recovery is

performed. If INT0 changes to high level already before Shutdown state, the Shutdown is recovered immedi-

ately because the high level on INT0 is valid. Note that, in this case, a complete shut-down/power-up sequence

with recovery INIT is performed:

Note: If “H” level or “L” level is enabled for recovery, the level must be active for minimum 500 µs.

LBx LAx Interrupt Level

0 0 "L" level (initial value)

0 1 "H" level

1 0 Rising edge

1 1 Falling edge

INT0

STOP/ShutDown state

Recovery INIT

INT0

STOP/ShutDown state

Recovery INIT

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4.2. Recovery from shutdown mode

The following factors are available to recover from the shutdown state:

• Assert the reset signal at the INITX terminal for minimum 10 ms 12

• Input of a valid recovery request via an external interrupt terminal

• Real Ttime Clock Interrupt (when RTC interrupt is enabled)

• Hardware Watchdog reset (when HWWD is enabled in STOP mode)

• Main Clock Supervisor reset (when Main oscillator is running and Main Clock Supervisor is enabled and

recovery by HWWD is enabled)

Shutdown state is released when a valid recovery factor is permitted. After the Shutdown state release, the

device restarts with a settings initialization reset (INIT), just like power-up operation. Only the Real Time Clock,

the Oscillation Stabilization settings in STCR register, and the recovery source ﬂags in the Shutdown registers

EXTF and SHDINT are not cleared.

The internal restart sequence is as follows:

1. Resume the internal power supply.

2. Reset and assert the initialization reset (INIT).

3. Wait for oscillation stabilization.

4. Start the reset sequence.

As the external interrupt source ﬂags and the RTC ﬂag are retained in EXTF and SHDINT registers, it is possible

to determine whether it is power-up operation or recovery from shutdown state by checking the ﬂags.

4.2.1. The Real Time Clock at Recovery from Shutdown

In normal operation, the registers and settings of the Real Rime Clock are initialized by Software Reset (RST).

At recovery from Shutdown, the RTC is not initialized:

• The prescaler, second, minute and hour counters continue counting also during the recovery INIT state.

• The clock selection for the RTC (by CSCFG.OSC1, CSCFG.OSC0) remains unchanged.

• The RTC interrupt enable bits and interrupt ﬂags (in WTCR and WTCE registers) remain unchanged.

So at each recovery from Shutdown, the RTC continues running and the current time as well as the interrupt

ﬂags can be read from the RTC after recovery.

Note: The Interrupt Control Register for RTC (ICR58), the Interrupt Level Mask (ILM) register as well as the Condition

Code Register (CCR, containing the I-Flag) are cleared by the recovery INIT, so that all interrupt processing

is disabled.

If the software re-enables interrupt processing by setting ICR58, ILM and I-Flag, the software will process

the pending RTC interrrupt immediately.

1. The minimum INTX=0 pulse length is determined by the time the main oscillator needs for stabilization.

2. Reset by INITX=0 will kill the ShutDown state and restart the device like at power-on.

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4.3. Determining the Reset Source after Shutdown

The recovery from Shutdown is followed by an Setting Initialization Reset (INIT). Because INIT is always followed

by a Software Reset (RST), the CPU fetches the Mode- and Reset-Vectors and jumps to the Reset Vector, which

is located in the Boot ROM.

The following drawing shows how the Shutdown Control is located in the external INIT chain:

The following table lists the registers and ﬂags for determination of the reset source, including Shutdown:

Note: RSRR: Reset Source register

EXTF: External shutdown recovery ﬂags, see page 82

SHDINT: Hardware Watchdog/ Real Time Clock recovery ﬂags, see page 80

CSVCR: CLock Supervisor Control / Status register

HWWD: Hardware Watchdog register

For details about RSRR, CSVCR and HWWD, please refer to the hardware manual.

Recovery from Shutdown will set the INIT bit in RSRR register. Because the INIT bit can also be set by external

INIT (low level at INITX pin), Clock Supervisor or Hardware Watchdog, the ﬂags in EXTF, SHDINT, CSVCR and

HWWD should be checked for determining the reset source.

RSRR 480H1

1. RSRR is read and cleared by the Boot ROM software. After Boot ROM, the content of RSRR can be

found in CPU register R4[7:0] and in a variable in memory.

INIT HSTB WDOG ERST SRST LINIT WT1 WT0

EXTF 4D7HRX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0

SHDINT 4DBH----HWWDF HWWDE RTCF RTCE

CSVCR 4ADHSCKS MM SM RCE MSVE SSVE SRST OUTE

HWWD 4C7H----CL --CPUF

INITX

Noise

filter

Clock

Supervisor

MM SM

Hardware

Watchdog

CPUF RX1, RX0, INT7, INT6,

INT3, INT2, INT1, INT0

INIT

Reset

Source

CL CL

PR SINIT

Low Volt

Detection

LINIT

HWWDF RTCF

External interrupts Real Time Clock

Shutdown State

No Shutdown

Recovery flags

Control

Regs and

State

Machine

CL Recover!

Shutdown Control

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The recovery ﬂags in EXTF and SHDINT are set only in Shutdown mode and only if recovery by this channel

is enabled.

4.4. Registers which are not initialized by Shutdwon Recovery

As described above, recovery from Shutdown performes a settings initialization reset (INIT) followed by software

reset (RST). This sequence will initialize the complete device with some exceptions, explained in the following

table.

Registers which are not initialized by Shutdown Recovery:

Note: If the ShutDown state is killed by external pin INITX=0, these registers are initialized like at normal power-on.

STCR 481HOS1, OS0 Keep oscillation stabilization time setting

CSVCR 4ADHall bits Clock Supervisor is not initialized by recovery

CSCFG 4AEHall bits Keep RTC and Calibration clock source settings

CMCFG 4AFHall bits Keep Clock Monitor settings

WTCER 4A1H

all bits Real Time Clock to continue running

WTCR 4A2H - 4A3H

WTBR 4A5H - 4A7H

WTHR 4A8H

WTMR 4A9H

WTSR 4AAH

CUCR 4B0H - 4B1H

all bits Subclock Calibration unit is part of RTC module

CUTD 4B2H - 4B3H

CUTR1 4B4H - 4B5H

CUTR2 4B6H - 4B7H

HWWDE 4C6Hall bits Hardware Watchdog is not initialized by recovery

HWWD 4C7Hall bits

EXTF 4D7Hall bits Keep external recovery flags

SHDINT 4DBHHWWDF, RTCF Keep hardware watchdog and RTC recovery ﬂags

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4.5. I/O Behaviour in Shutdown

During Shutdown mode, the I/O pins are switched into dedicated states:

Ports/Pins Port function Setting

P00_0 to P00_7,

P01_0 to P01_7,

P02_0 to P02_7,

P03_0 to P03_7.

D[31:0] External bus

data I/O The pins are switched to input direction, but it is not possible

to input signals on these pins.

If STCR.HIZ (HiZ mode in STOP) is not set, the pull-up/pull-

down settings are maintained during shutdown.

If STCR.HIZ is set, the pull-up and pull-down resistors are

disabled.

P08_6, P08_7,

P10_5, P13_0

BRQ, RDY,

MCLKI, DREQ0

External bus

control inputs

P04_0 to P04_1,

P05_0 to P05_7,

P06_0 to P06_7,

P07_0 to P07_7.

A[25:0]

External bus

address out-

puts

P08_0 to P08_5,

P09_0 to P09_7,

P10_1 to P10_4,

P10_6,

P13_1, P13_2

WRnX, RDX,

BGRNTX,

CSnX, ASX,

BAAX, WEX,

MCLKO, MCLKE

External bus

control and

clock outputs

If the pins were switched to output direction before shutdown

(by PFR==1 or DDR==1), the pins will output ‘1’ value and

the driver strength is switched to 2 mA.

Otherwise, the pins keep input direction, but it is not possible

to input signals on these pins. If STCR.HIZ is not set, the

pull-up/pull-down settings are maintained. If STCR.HIZ is

set, the pull-up and pull-down resistors are disabled.

P24_0 to P24_3,

P24_6, P24_7,

P23_0,

P23_2

INT0 to INT3,

INT6, INT7,

RX0/INT8,

RX1/INT9

Pins used for

Shutdown

recovery

The pins are switched to input direction.

If STCR.HIZ is not set, the pull-up/pull-down settings are

maintained during shutdown. If STCR.HIZ is set, the pull-up

and pull-down resistors are disabled.

If external interrupt is enabled for recovery from Shutdown

(Shutdown INTE=1), the input threshold setting (PILR,

EPILR) is maintained during the shutdown mode and it is

possible to input signals for recovery. After the ﬁrst recovery

factor is accepted, the port settings are initialized when the

device proceeds to the reset (INIT/RST) sequence.

Pnn_m 1

1. nn = 14 to 29, m = 0 to 7

all other Ports not mentioned

above

All other pins are switched to input direction, but it is not pos-

sible to input signals on these pins. If STCR.HIZ is not set,

the pull-up/pull-down settings are maintained during Shut-

down. If STCR.HIZ is set, the pull-up and pull-down resistors

are disabled.

ALARM_0 ALARM analog input The state of ALARM input is not changed in Shutdown state.

MD_0 to MD_2 Mode inputs The state of MD[2:0] is not changed in Shutdown state

INITX External INIT

The state of INITX is not changed in Shutdown state. The

pull-up is enabled. It is possible to input external INITX signal

during Shutdown.

VCC18C Regulator capacitor pin The capacitor connection pin for internal regulator shows the

voltage which is applied to internal Always-ON domain.

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■CPU AND CONTROL UNIT

The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced

instructions for embedded applications.

1. Features

• Adoption of RISC architecture

Basic instruction: 1 instruction per cycle

• General-purpose registers: 32-bit 16 registers

• 4 Gbytes linear memory space

• Multiplier installed

32-bit 32-bit multiplication: 5 cycles

16-bit 16-bit multiplication: 3 cycles

• Enhanced interrupt processing function

Quick response speed (6 cycles)

Multiple-interrupt support

Level mask function (16 levels)

• Enhanced instructions for I/O operation

Memory-to-memory transfer instruction

Bit processing instruction

Basic instruction word length: 16 bits

• Low-power consumption

Sleep mode/stop mode

2. Internal architecture

• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent

of each other.

• A 32-bit ↔16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and

peripheral resources.

• A Harvard ↔Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between

the CPU and the bus controller.

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3. Programming model

3.1. Basic programming model

ILM SCR CCR

. . .

XXXX XXXXH

0000 0000H

XXXX XXXXH

. . .

R1 2

R1 3

R1 4

R1 5

TBR

SSP

USP

MDL

MDH

. . .

32 bits

Initial value

General-purpose registers

Program counter

Program status

Table base register

Return pointer

System stack pointer

User stack pointer

Multiply & divide registers

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4. Registers

4.1. General-purpose register

Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation

operations and as pointers for memory access.

Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular

applications.

R13 : Virtual accumulator

R14 : Frame pointer

R15 : Stack pointer

Initial values at reset are undeﬁned for R0 to R14. The value for R15 is 00000000H (SSP value).

4.2. PS (Program Status)

This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.

All undeﬁned bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these

bits is invalid.

. . .

XXXX XXXXH

0000 0000H

XXXX XXXXH

. . .

R12

R13

R14

R15

. . .

32 bits

Initial value

Bit position →bit 20 bit 0bit 7bit 8bit 10bit 16

ILM SCR CCR

bit 31

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4.3. CCR (Condition Code Register)

SV : Supervisor ﬂag

S : Stack ﬂag

I : Interrupt enable ﬂag

N : Negative enable ﬂag

Z : Zero ﬂag

V : Overﬂow ﬂag

C : Carry ﬂag

4.4. SCR (System Condition Register)

Flag for step division (D1, D0)

This ﬂag stores interim data during execution of step division.

Step trace trap ﬂag (T)

This ﬂag indicates whether the step trace trap is enabled or disabled.

The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution

of user programs.

4.5. ILM (Interrupt Level Mask register)

This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.

The register is initialized to value “01111B” at reset.

4.6. PC (Program Counter)

The program counter indicates the address of the instruction that is being executed.

The initial value at reset is undeﬁned.

- 000XXXXB

bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7

CVZNISSV

Initial value

bit 10 bit 8bit 9

D1 D0 T XX0B

Initial value

bit 18bit 16bit 17

ILM2 ILM1 ILM0 01111B

ILM3ILM4

bit 20 bit 19 Initial value

bit 0bit 31

XXXXXXXXH

Initial value

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4.7. TBR (Table Base Register)

The table base register stores the starting address of the vector table used in EIT processing.

The initial value at reset is 000FFC00H.

4.8. RP (Return Pointer)

The return pointer stores the address for return from subroutines.

During execution of a CALL instruction, the PC value is transferred to this RP register.

During execution of a RET instruction, the contents of the RP register are transferred to PC.

The initial value at reset is undeﬁned.

4.9. USP (User Stack Pointer)

The user stack pointer, when the S ﬂag is “1”, this register functions as the R15 register.

•The USP register can also be explicitly speciﬁed.

The initial value at reset is undeﬁned.

•This register cannot be used with RETI instructions.

4.10. Multiply & divide registers

These registers are for multiplication and division, and are each 32 bits in length.

The initial value at reset is undeﬁned.

bit 0bit 31

000FFC00H

Initial value

bit 0bit 31

XXXXXXXXH

Initial value

bit 0bit 31

XXXXXXXXH

Initial value

bit 0

MDL

bit 31

MDH

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■EMBEDDED PROGRAM/DATA MEMORY (FLASH)

1. Flash features

• MB91F467EA: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes) = 8.5 Mbits

• Programmable wait state for read/write access

• Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F

• Boot security

• Basic speciﬁcation: Same as MBM29LV400TC (except size and part of sector conﬁguration)

2. Operation modes

(1) 64-bit CPU mode:

• CPU reads and executes programs in word (32-bit) length units.

• Flash writing is not possible.

• Actual Flash Memory access is performed in d-word (64-bit) length units.

(2) 32-bit CPU mode :

• CPU reads, writes and executes programs in word (32-bit) length units.

• Actual Flash Memory access is performed in word (32-bit) length units.

(3) 16-bit CPU mode :

• CPU reads and writes in half-word (16-bit) length units.

• Program execution from the Flash is not possible.

• Actual Flash Memory access is performed in half-word (16-bit) length units.

Note: The operation mode of the ﬂash memory can be selected using a Boot-ROM function. The function start

address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash

Access Mode Switching".

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3. Flash access in CPU mode

3.1. Flash conﬁguration

3.1.1. Flash memory map MB91F467EA

ROMS1

ROMS0

addr+6

ROMS5

ROMS4

ROMS6

ROMS7

ROMS3

ROMS2

dat[31:16]

dat[15:0]

dat[31:0]

dat[31:16]

dat[15:0]

16bit read/write

32bit read/write

dat[63:0]

64bit read

addr+7

addr+2

SA0 (8KB)

SA16 (64KB)

SA10 (64KB)

SA21 (64KB)

SA19 (64KB)

Address

0014:FFFFh

0014:C000h

0014:BFFFh

0014:8000h

SA7 (8KB)

SA5 (8KB)

SA3 (8KB)

SA1 (8KB)

SA23 (64KB)

SA6 (8KB)

SA4 (8KB)

SA2 (8KB)

SA22 (64KB)

SA20 (64KB)

0013:FFFFh

0012:0000h

0011:FFFFh

0010:0000h

SA18 (64KB)

0014:7FFFh

0014:4000h

0014:3FFFh

0014:0000h

000F:FFFFh

000E:0000h

SA15 (64KB)

000D:FFFFh

000C:0000h

000B:FFFFh

000A:0000h

addr+5

SA11 (64KB)

SA8 (64KB)

SA9 (64KB)

addr+0

addr+1

addr+3

addr+4

0009:FFFFh

0008:0000h

0007:FFFFh

0006:0000h

0005:FFFFh

0004:0000h

SA17 (64KB)

SA14 (64KB)

SA12 (64KB)

SA13 (64KB)

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3.2. Flash access timing settings in CPU mode

The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or

maximum clock modulation) for Flash read and write access.

3.2.1. Flash read timing settings (synchronous read)

3.2.2. Flash write timing settings (synchronous write)

Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark

to 24 MHz 0 0 0 - 1

to 48 MHz 0 0 1 - 2

to 80 MHz 1 1 3 - 4

Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark

to 32 MHz 1 - - 0 4

to 48 MHz 1 - - 0 5

to 64 MHz 1 - - 0 6

to 80 MHz 1 - - 0 7

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3.3. Address mapping from CPU to parallel programming mode

The following tables show the calculation from CPU addresses to ﬂash macro addresses which are used in

parallel programming.

3.3.1. Address mapping MB91F467EA

Note: FA result is without 20:0000h offset for parallel Flash programming .

Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.

CPU Address

(addr) Condition Flash

sectors FA (ﬂash address) Calculation

14:0000h

14:FFFFh

addr[2]==0 SA0, SA2, SA4, SA6

(8 Kbyte)

FA := addr - addr%00:4000h + (addr%00:4000h)/2

- (addr/2)%4 + addr%4 - 05:0000h

14:0000h

14:FFFFh

addr[2]==1 SA1, SA3, SA5, SA7

(8 Kbyte)

FA := addr - addr%00:4000h + (addr%00:4000h)/2

- (addr/2)%4 + addr%4 - 05:0000h

+ 00:2000h

04:0000h

13:FFFFh

addr[2]==0

SA8, SA10, SA12, SA14,

SA16, SA18, SA20, SA22

(64 Kbyte)

FA := addr - addr%02:0000 + (addr%02:0000h)/2

- (addr/2)%4 + addr%4 + 0C:0000h

04:0000h

13:FFFFh

addr[2]==1

SA9, SA11, SA13, SA15,

SA17, SA19, SA21, SA23

(64 Kbyte)

FA := addr - addr%02:0000h + (addr%02:0000h)/2

- (addr/2)%4 + addr%4 + 0C:0000h

+ 01:0000h

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4. Parallel Flash programming mode

4.1. Flash conﬁguration in parallel Flash programming mode

Parallel Flash programming mode (MD[2:0] = 111):

MB91F467EA

16bit write mode

DQ[15:0]

SA20 (64KB)

SA19 (64KB)

SA18 (64KB)

FA[21:0]

003E:FFFFh

003E:0000h

003D:FFFFh

003D:0000h

003F:FFFFh

003F:0000h

SA23 (64KB)

SA22 (64KB)

SA21 (64KB)

003C:FFFFh

003C:0000h

003B:FFFFh

003B:0000h

003A:FFFFh

003A:0000h

0039:FFFFh

0039:0000h

SA17 (64KB)

0038:FFFFh

0038:0000h

0037:FFFFh

0037:0000h

SA16 (64KB)

SA15 (64KB)

0036:FFFFh

0036:0000h

0035:FFFFh

0035:0000h

SA14 (64KB)

SA13 (64KB)

0034:FFFFh

0034:0000h

0033:FFFFh

0033:0000h

SA12 (64KB)

SA11 (64KB)

0032:FFFFh

0032:0000h

0031:FFFFh

0031:0000h

SA10 (64KB)

SA9 (64KB)

0030:FFFFh

0030:0000h

002F:FFFFh

002F:E000h

SA8 (64KB)

SA7 (8KB)

002F:7FFFh

002F:6000h

SA4 (8KB)

SA3 (8KB)

002F:DFFFh

002F:C000h

002F:BFFFh

002F:A000h

SA6 (8KB)

SA5 (8KB)

002F:1FFFh

002F:0000h

SA0 (8KB)

FA[1:0]=00

FA[1:0]=10

002F:5FFFh

002F:4000h

002F:3FFFh

002F:2000h

SA2 (8KB)

SA1 (8KB)

002F:9FFFh

002F:8000h

Remark: Always keep FA[0] = 0 and FA[21] = 1

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4.2. Pin connections in parallel programming mode

Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s

interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of

the signals to General Purpose Ports. Please see table below for signal mapping.

In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set

when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash

memory’s Auto Algorithms are available.

Correspondence between MBM29LV400TC and Flash Memory Control Signals

MBM29LV400TC

External pins FR-CPU mode

MB91F467EA external pins

Comment

Flash memory

mode Normal function Pin number

⎯INITX ⎯INITX 73

RESET ⎯FRSTX P09_6 60

⎯⎯MD_2 MD_2 70 Set to ‘1’

⎯⎯MD_1 MD_1 71 Set to ‘1’

⎯⎯MD_0 MD_0 72 Set to ‘1’

RY/BY FMCS:RDY bit RY/BYX P09_0 56

BYTE Internally ﬁxed to ’H’ BYTEX P09_2 58

Internal control signal

+ control via interface

circuit

WEX P13_2 191

OE OEX P13_1 190

CE CEX P13_0 189

⎯ATDIN P25_7 187 Set to ‘0’

⎯EQIN P25_6 186 Set to ‘0’

⎯TESTX P09_3 59 Set to ‘1’

⎯RDYI P09_1 57 Set to ‘0’

A-1

Internal address bus

FA0 P25_5 185 Set to ‘0’

A0 to A3 FA1 to FA4 P27_0 to P27_3 158 to 161

A4 to A7 FA5 to FA8 P27_4 to P27_7 164 to 167

A8 to A11 FA9 to FA12 P26_0 to P26_3 168 to 171

A12 to A15 FA13 to FA16 P26_4 to P26_7 174 to 177

A16 to A19 FA17 to FA20 P25_0 to P25_3 178 to 181

⎯FA21 P25_4 184 Set to ‘1’

DQ0 to DQ7 Internal data bus DQ0 to DQ7 P03_0 to P03_7 192 to 199

DQ8 to DQ15 DQ8 to DQ15 P02_0 to P02_7 200 to 207

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5. Poweron Sequence in parallel programming mode

The ﬂash memory can be accessed in programming mode after a certain wait time, which is needed for Security

Vector fetch:

• Minimum wait time after VDD5/VDD5R power on: 2.76 ms

• Minimum wait time after INITX rising: 1.0 ms

6. Flash Security

6.1. Vector addresses

Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)

controlling the protection functions of the Flash Security Module:

FSV1: 0x14:8000 BSV1: 0x14:8004

FSV2: 0x14:8008 BSV2: 0x14:800C

6.2. Security Vector FSV1

The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the

individual write protection of the 8 Kbytes sectors.

6.2.1. FSV1 (bit31 to bit16)

The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.

Explanation of the bits in the Flash Security Vector FSV1 [31:16]

FSV1[31:19]

FSV1[18]

WriteProtection

Level

FSV1[17]

Write Protection

FSV1[16]

Read Protection Flash Security Mode

set all to “0” set to “0” set to “0” set to “1” Read Protection (all device modes,

except INTVEC mode MD[2:0] =“000”)

set all to “0” set to “0” set to “1” set to “0” Write Protection (all device modes,

without exception)

set all to “0” set to “0” set to “1” set to “1”

Read Protection (all device modes,

except INTVEC mode MD[2:0] =“000”)

and Write Protection (all device modes)

set all to “0” set to “1” set to “0” set to “1” Read Protection (all device modes,

except INTVEC mode MD[2:0] =“000”)

set all to “0” set to “1” set to “1” set to “0” Write Protection (all device modes,

except INTVEC mode MD[2:0] =“000”)

set all to “0” set to “1” set to “1” set to “1”

Read Protection (all device modes,

except INTVEC mode MD[2:0] =“000”)

and Write Protection (all device modes

except INTVEC mode MD[2:0] =“000”)

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6.2.2. FSV1 (bit15 to bit0)

The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the

8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set.

Explanation of the bits in the Flash Security Vector FSV1 [15:0]

Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to

write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where

it is possible to either read out the Flash content or manipulate data by writing.

See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash

Memory.

FSV1 bit Sector Enable Write

Protection

Disable Write

Protection Comment

FSV1[0] SA0 set to “0” set to “1”

FSV1[1] SA1 set to “0” set to “1”

FSV1[2] SA2 set to “0” set to “1”

FSV1[3] SA3 set to “0” set to “1”

FSV1[4] SA4 set to “0” ⎯Write protection is mandatory!

FSV1[5] SA5 set to “0” set to “1”

FSV1[6] SA6 set to “0” set to “1”

FSV1[7] SA7 set to “0” set to “1”

FSV1[8] ⎯set to “0” set to “1” not available

FSV1[9] ⎯set to “0” set to “1” not available

FSV1[10] ⎯set to “0” set to “1” not available

FSV1[11] ⎯set to “0” set to “1” not available

FSV1[12] ⎯set to “0” set to “1” not available

FSV1[13] ⎯set to “0” set to “1” not available

FSV1[14] ⎯set to “0” set to “1” not available

FSV1[15] ⎯set to “0” set to “1” not available

MB91460E-DS705-00002-1v3-E.fm Page 104 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 105

6.3. Security Vector FSV2

The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the

64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set.

Explanation of the bits in the Flash Security Vector FSV2[31:0]

Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.

FSV2 bit Sector Enable Write

Protection

Disable Write

Protection Comment

FSV2[0] SA8 set to “0” set to “1”

FSV2[1] SA9 set to “0” set to “1”

FSV2[2] SA10 set to “0” set to “1”

FSV2[3] SA11 set to “0” set to “1”

FSV2[4] SA12 set to “0” set to “1”

FSV2[5] SA13 set to “0” set to “1”

FSV2[6] SA14 set to “0” set to “1”

FSV2[7] SA15 set to “0” set to “1”

FSV2[8] SA16 set to “0” set to “1”

FSV2[9] SA17 set to “0” set to “1”

FSV2[10] SA18 set to “0” set to “1”

FSV2[11] SA19 set to “0” set to “1”

FSV2[12] SA20 set to “0” set to “1”

FSV2[13] SA21 set to “0” set to “1”

FSV2[14] SA22 set to “0” set to “1”

FSV2[15] SA23 set to “0” set to “1”

FSV2[31:16] ⎯set to “0” set to “1” not available

MB91460E-DS705-00002-1v3-E.fm Page 105 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

106 DS705-00002-1v3-E

■MEMORY SPACE

The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.

• Direct addressing area

The following address space area is used for I/O.

This area is called direct addressing area, and the address of an operand can be speciﬁed directly in an

instruction.

The size of directly addressable area depends on the length of the data being accessed as shown below.

Byte data access : 000H to 0FFH

Half word access : 000H to 1FFH

Word data access : 000H to 3FFH

MB91460E-DS705-00002-1v3-E.fm Page 106 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 107

■MEMORY MAPS

1. MB91F467EA

MB91F467EA

00000000

00000400

I/O (direct addressing area)

I/O

00002000

00004000

Flash-Cache (8 KByte)

00001000

DMA

00006000

00007000

Flash memory control

00008000

0000B000

Boot ROM (4 KByte)

0000C000

CAN

0000D000

00020000

D-RAM (0 wait, 64 KByte)

00030000

ID-RAM (48 KByte)

0003C000

00040000

Flash memory (1088 KByte)

00150000

00180000

External bus area

00500000

External data bus

FFFFFFFF

Note: Access prohibited areas

FFFAC000

FFFB0000

Standby-RAM (16 KByte)

MB91460E-DS705-00002-1v3-E.fm Page 107 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

108 DS705-00002-1v3-E

■I/O MAP

1. MB91F467EA

Note : Initial values of register bits are represented as follows:

“ 1 ” : Initial value “ 1 ”

“ 0 ” : Initial value “ 0 ”

“ X ” : Initial value “ undefined ”

“ - ” : No physical register at this location

Access is barred with an undeﬁned data access attribute.

Address Register Block

+ 0 + 1 + 2 + 3

000000HPDR0 [R/W]

XXXXXXXX

PDR1 [R/W]

XXXXXXXX

PDR2 [R/W]

XXXXXXXX

PDR3 [R/W]

XXXXXXXX

T-unit

port data register

Read/write attribute

address 4n + 1...)

Leftmost register address (for word access, the register in column 1

becomes the MSB side of the data.)

MB91460E-DS705-00002-1v3-E.fm Page 108 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 109

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000000HPDR00 [R/W]

XXXXXXXX

PDR01 [R/W]

XXXXXXXX

PDR02 [R/W]

XXXXXXXX

PDR03 [R/W]

XXXXXXXX

R-bus

Port Data

000004HPDR04 [R/W]

- - - - - - XX

PDR05 [R/W]

XXXXXXXX

PDR06 [R/W]

XXXXXXXX

PDR07 [R/W]

XXXXXXXX

000008HPDR08 [R/W]

XXXXXXXX

PDR09 [R/W]

XX - - XXXX

PDR10 [R/W]

- XXXXXX - Reserved

00000CHReserved PDR13 [R/W]

- - - - - XXX

PDR14 [R/W]

XXXXXXXX

PDR15 [R/W]

- - - - XXXX

000010HPDR16 [R/W]

XXXXXXXX

PDR17 [R/W]

XXXX - - - -

PDR18 [R/W]

- XXX - XXX

PDR19 [R/W]

- XXX - XXX

000014HPDR20 [R/W]

- - - - - XXX Reserved PDR22 [R/W]

- - XX - X - X

PDR23 [R/W]

- - XXXXXX

000018HPDR24 [R/W]

XXXXXXXX

PDR25 [R/W]

XXXXXXXX

PDR26 [R/W]

XXXXXXXX

PDR27 [R/W]

XXXXXXXX

00001CHReserved PDR29 [R/W]

XXXXXXXX Reserved

000020H

00002CH

Reserved Reserved

000030HEIRR0 [R/W]

XXXXXXXX

ENIR0 [R/W]

00000000

ELVR0 [R/W]

00000000 00000000

External interrupt

(INT 0 to INT 7)

000034HEIRR1 [R/W]

XXXXXXXX

ENIR1 [R/W]

00000000

ELVR1 [R/W]

00000000 00000000

External interrupt

(INT 8 to INT 10,

INT 12 to INT 14)

000038HDICR [R/W]

- - - - - - - 0

HRCL [R/W]

0 - - 11111 Reserved Delay Interrupt

00003CH

00004CH

Reserved Reserved

000050HSCR02 [R/W, W]

00000000

SMR02 [R/W, W]

00000000

SSR02 [R/W, R]

00001000

RDR02/TDR02

[R/W]

00000000 LIN-USART

000054HESCR02 [R/W]

00000X00

ECCR02

[R/W, R, W]

-00000XX

FSR02 [RW/R]

xx00 0000 Reserved

000058H,

00005CHReserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 109 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

110 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000060HSCR04 [R/W, W]

00000000

SMR04 [R/W, W]

00000000

SSR04 [R/W, R]

00001000

RDR04/TDR04

[R/W]

00000000 LIN-USART

with FIFO

000064HESCR04 [R/W]

00000X00

ECCR04

[R/W, R, W]

-00000XX

FSR04 [RW/R]

xx00 0000

FCR04 [R/W]

0001 - 000

000068HSCR05 [R/W, W]

00000000

SMR05 [R/W, W]

00000000

SSR05 [R/W, R]

00001000

RDR05/TDR05

[R/W]

00000000 LIN-USART

with FIFO

00006CHESCR05 [R/W]

00000X00

ECCR05

[R/W, R, W]

-00000XX

FSR05 [RW/R]

xx00 0000

FCR05 [R/W]

0001 - 000

000070HSCR06 [R/W, W]

00000000

SMR06 [R/W, W]

00000000

SSR06 [R/W, R]

00001000

RDR06/TDR06

[R/W]

00000000 LIN-USART

with FIFO

000074HESCR06 [R/W]

00000X00

ECCR06

[R/W, R, W]

-00000XX

FSR06 [RW/R]

xx00 0000

FCR06 [R/W]

0001 - 000

000078HSCR07 [R/W, W]

00000000

SMR07 [R/W, W]

00000000

SSR07 [R/W, R]

00001000

RDR07/TDR07

[R/W]

00000000 LIN-USART

with FIFO

00007CHESCR07 [R/W]

00000X00

ECCR07

[R/W, R, W]

-00000XX

FSR07 [RW/R]

xx00 0000

FCR07 [R/W]

0001 - 000

000080HReserved Reserved

000084HBGR102 [R/W]

00000000

BGR002 [R/W]

00000000 Reserved

Baud rate

Generator

LIN-USART

2,4 to 7

000088HBGR104 [R/W]

00000000

BGR004 [R/W]

00000000

BGR105 [R/W]

00000000

BGR005 [R/W]

00000000

00008CHBGR106 [R/W]

00000000

BGR006 [R/W]

00000000

BGR107 [R/W]

00000000

BGR007 [R/W]

00000000

000090HPWC20 [R/W]

- - - - - - XX XXXXXXXX

PWC10 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 0

000094HReserved PWS20 [R/W]

-0000000

PWS10 [R/W]

- -000000

000098HPWC21 [R/W]

- - - - - - XX XXXXXXXX

PWC11 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 1

00009CHReserved PWS21 [R/W]

-0000000

PWS11 [R/W]

- -000000

MB91460E-DS705-00002-1v3-E.fm Page 110 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 111

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

0000A0HPWC22 [R/W]

- - - - - - XX XXXXXXXX

PWC12 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 2

0000A4HReserved PWS22 [R/W]

-0000000

PWS12 [R/W]

- -000000

0000A8HPWC23 [R/W]

- - - - - - XX XXXXXXXX

PWC13 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 3

0000ACHReserved PWS23 [R/W]

-0000000

PWS13 [R/W]

- -000000

0000B0HPWC24 [R/W]

- - - - - - XX XXXXXXXX

PWC14 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 4

0000B4HReserved PWS24 [R/W]

-0000000

PWS14 [R/W]

- -000000

0000B8HPWC25 [R/W]

- - - - - - XX XXXXXXXX

PWC15 [R/W]

- - - - - - XX XXXXXXXX Stepper Motor 5

0000BCHReserved PWS25 [R/W]

-0000000

PWS15 [R/W]

- -000000

0000C0HReserved PWC0 [R/W]

-00000-- Reserved PWC1 [R/W]

-00000--

Stepper Motor Control

0 to 5

0000C4HReserved PWC2 [R/W]

-00000-- Reserved PWC3 [R/W]

-00000--

0000C8HReserved PWC4 [R/W]

-00000-- Reserved PWC5 [R/W]

-00000--

0000CCHReserved Reserved

0000D0HIBCR0 [R/W]

00000000

IBSR0 [R]

00000000

ITBAH0 [R/W]

- - - - - - 00

ITBAL0 [R/W]

00000000

I2C 00000D4HITMKH0 [R/W]

00 - - - - 11

ITMKL0 [R/W]

11111111

ISMK0 [R/W]

01111111

ISBA0 [R/W]

- 0000000

0000D8HReserved IDAR0 [R/W]

00000000

ICCR0 [R/W]

00011111 Reserved

0000DCH

000100H

Reserved Reserved

000104HGCN11 [R/W]

00110010 00010000 Reserved GCN21 [R/W]

- - - - 0000

PPG Control

4 to 7

000108HGCN12 [R/W]

00110010 00010000 Reserved GCN22 [R/W]

- - - - 0000

PPG Control

8 to 11

000110H

00012CH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 111 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

112 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000130HPTMR04 [R]

11111111 11111111

PCSR04 [R/W]

XXXXXXXX XXXXXXXX PPG 4

000134HPDUT04 [R/W]

XXXXXXXX XXXXXXXX

PCNH04 [R/W]

0000000 -

PCNL04 [R/W]

000000 - 0

000138HPTMR05 [R]

11111111 11111111

PCSR05 [R/W]

XXXXXXXX XXXXXXXX PPG 5

00013CHPDUT05 [R/W]

XXXXXXXX XXXXXXXX

PCNH05 [R/W]

0000000 -

PCNL05 [R/W]

000000 - 0

000140HPTMR06 [R]

11111111 11111111

PCSR06 [R/W]

XXXXXXXX XXXXXXXX PPG 6

000144HPDUT06 [R/W]

XXXXXXXX XXXXXXXX

PCNH06 [R/W]

0000000 -

PCNL06 [R/W]

000000 - 0

000148HPTMR07 [R]

11111111 11111111

PCSR07 [R/W]

XXXXXXXX XXXXXXXX PPG 7

00014CHPDUT07 [R/W]

XXXXXXXX XXXXXXXX

PCNH07 [R/W]

0000000 -

PCNL07 [R/W]

000000 - 0

000150HPTMR08 [R]

11111111 11111111

PCSR08 [R/W]

XXXXXXXX XXXXXXXX PPG 8

000154HPDUT08 [R/W]

XXXXXXXX XXXXXXXX

PCNH08 [R/W]

0000000 -

PCNL08 [R/W]

000000 - 0

000158HPTMR09 [R]

11111111 11111111

PCSR09 [R/W]

XXXXXXXX XXXXXXXX PPG 9

00015CHPDUT09 [R/W]

XXXXXXXX XXXXXXXX

PCNH09 [R/W]

0000000 -

PCNL09 [R/W]

000000 - 0

000160HPTMR10 [R]

11111111 11111111

PCSR10 [R/W]

XXXXXXXX XXXXXXXX PPG 10

000164HPDUT10 [R/W]

XXXXXXXX XXXXXXXX

PCNH10 [R/W]

0000000 -

PCNL10 [R/W]

000000 - 0

000168HPTMR11 [R]

11111111 11111111

PCSR11 [R/W]

XXXXXXXX XXXXXXXX PPG 11

00016CHPDUT11 [R/W]

XXXXXXXX XXXXXXXX

PCNH11 [R/W]

0000000 -

PCNL11 [R/W]

000000 - 0

000170H

P0TMCSRH

[R/W]

- 0 - 000 - 0

P0TMCSRL

[R/W]

- - - 00000

P1TMCSRH

[R/W]

- 0 - 000 - 0

P1TMCSRL

[R/W]

- - - 00000

PFM

000174HP0TMRLR [W]

XXXXXXXX XXXXXXXX

P0TMR [R]

XXXXXXXX XXXXXXXX

000178HP1TMRLR [W]

XXXXXXXX XXXXXXXX

P1TMR [R]

XXXXXXXX XXXXXXXX

00017CHReserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 112 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 113

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000180HReserved ICS01 [R/W]

00000000 Reserved ICS23 [R/W]

00000000

Input

Capture

0 to 3

000184HIPCP0 [R]

XXXXXXXX XXXXXXXX

IPCP1 [R]

XXXXXXXX XXXXXXXX

000188HIPCP2 [R]

XXXXXXXX XXXXXXXX

IPCP3 [R]

XXXXXXXX XXXXXXXX

00018CHOCS01 [R/W]

- - - 0 - - 00 0000 - - 00

OCS23 [R/W]

- - - 0 - - 00 0000 - - 00

Output

Compare

0 to 3

000190HOCCP0 [R/W]

XXXXXXXX XXXXXXXX

OCCP1 [R/W]

XXXXXXXX XXXXXXXX

000194HOCCP2 [R/W]

XXXXXXXX XXXXXXXX

OCCP3 [R/W]

XXXXXXXX XXXXXXXX

000198HSGCRH [R/W]

0000 - - 00

SGCRL [R/W]

- - 0 - - 000

SGFR [R/W, R]

XXXXXXXX XXXXXXXX Sound

Generator

00019CHSGAR [R/W]

00000000 Reserved SGTR [R/W]

XXXXXXXX

SGDR [R/W]

XXXXXXXX

0001A0HADERH [R/W]

00000000 00000000

ADERL [R/W]

00000000 00000000

A/D

Converter 0

0001A4 ADCS1 [R/W]

00000000

ADCS0 [R/W]

00000000 [R]

- - - - - - - 0 [W]

ADCR1 [R]

000000XX

ADCR0 [R]

XXXXXXXX

0001A8HADCT1 [R/W]

00010000

ADCT0 [R/W]

00101100

ADSCH [R/W]

- - - 00000

ADECH [R/W]

- - - 00000

0001ACHReserved ACSR0 [R/W]

- 11XXX00 Reserved Alarm Comparator 0

0001B0HTMRLR0 [W]

XXXXXXXX XXXXXXXX

TMR0 [R]

XXXXXXXX XXXXXXXX

Reload Timer 0

0001B4HReserved

TMCSRH0

[R/W]

- - - 00000

TMCSRL0

[R/W]

0 - 000000

0001B8HTMRLR1 [W]

XXXXXXXX XXXXXXXX

TMR1 [R]

XXXXXXXX XXXXXXXX

Reload Timer 1

0001BCHReserved

TMCSRH1

[R/W]

- - - 00000

TMCSRL1

[R/W]

0 - 000000

0001C0HTMRLR2 [W]

XXXXXXXX XXXXXXXX

TMR2 [R]

XXXXXXXX XXXXXXXX Reload Timer 2

(PPG 4, PPG 5)

0001C4HReserved

TMCSRH2

[R/W]

- - - 00000

TMCSRL2

[R/W]

0 - 000000

MB91460E-DS705-00002-1v3-E.fm Page 113 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

114 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

0001C8HTMRLR3 [W]

XXXXXXXX XXXXXXXX

TMR3 [R]

XXXXXXXX XXXXXXXX Reload Timer 3

(PPG 6, PPG 7)

0001CCHReserved

TMCSRH3

[R/W]

- - - 00000

TMCSRL3

[R/W]

0 - 000000

0001D0HTMRLR4 [W]

XXXXXXXX XXXXXXXX

TMR4 [R]

XXXXXXXX XXXXXXXX Reload Timer 4

(PPG 8, PPG 9)

0001D4HReserved

TMCSRH4

[R/W]

- - - 00000

TMCSRL4

[R/W]

0 - 000000

0001D8HTMRLR5 [W]

XXXXXXXX XXXXXXXX

TMR5 [R]

XXXXXXXX XXXXXXXX Reload Timer 5

(PPG 10, PPG 11)

0001DCHReserved

TMCSRH5

[R/W]

- - - 00000

TMCSRL5

[R/W]

0 - 000000

0001E0HTMRLR6 [W]

XXXXXXXX XXXXXXXX

TMR6 [R]

XXXXXXXX XXXXXXXX Reload Timer 6

(PPG 12, PPG 13)

0001E4HReserved

TMCSRH6

[R/W]

- - - 00000

TMCSRL6

[R/W]

0 - 000000

0001E8HTMRLR7 [W]

XXXXXXXX XXXXXXXX

TMR7 [R]

XXXXXXXX XXXXXXXX Reload Timer 7

(PPG 14, PPG 15)

(A/D Converter)

0001ECHReserved

TMCSRH7

[R/W]

- - - 00000

TMCSRL7

[R/W]

0 - 000000

0001F0HTCDT0 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS0 [R/W]

00000000

Free Running

Timer 0

(ICU 0, ICU 1)

0001F4HTCDT1 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS1 [R/W]

00000000

Free Running

Timer 1

(ICU 2, ICU 3)

0001F8HTCDT2 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS2 [R/W]

00000000

Free Running

Timer 2

(OCU 0, OCU 1)

0001FCHTCDT3 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS3 [R/W]

00000000

Free Running

Timer 3

(OCU 2, OCU 3)

MB91460E-DS705-00002-1v3-E.fm Page 114 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 115

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000200HDMACA0 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

000204HDMACB0 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000208HDMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00020CHDMACB1 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000210HDMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000214HDMACB2 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000218HDMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

00021CHDMACB3 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000220HDMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

000224HDMACB4 [R/W]

00000000 00000000 XXXXXXXX XXXXXXXX

000228H

00023CH

Reserved

000240HDMACR [R/W]

00 - - 0000 Reserved

000244H

0002CCH

Reserved Reserved

0002D0HReserved ICS045 [R/W]

00000000 Reserved ICS67 [R/W]

00000000

Input

Capture

4 to 7

0002D4HIPCP4 [R]

XXXXXXXX XXXXXXXX

IPCP5 [R]

XXXXXXXX XXXXXXXX

0002D8HIPCP6 [R]

XXXXXXXX XXXXXXXX

IPCP7 [R]

XXXXXXXX XXXXXXXX

0002DCH

0002ECH

Reserved Reserved

0002F0HTCDT4 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS4 [R/W]

00000000

Free Running

Timer 4

(ICU 4, ICU 5)

MB91460E-DS705-00002-1v3-E.fm Page 115 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

116 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

0002F4HTCDT5 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS5 [R/W]

00000000

Free Running

Timer 5

(ICU 6, ICU 7)

0002F8HTCDT6 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS6 [R/W]

00000000

Free Running

Timer 6

0002FCHTCDT7 [R/W]

XXXXXXXX XXXXXXXX Reserved TCCS7 [R/W]

00000000

Free Running

Timer 7

000300HReserved UDRC0 [W]

00000000 Reserved UDCR0 [R]

00000000 Up/Down

Counter

000304HUDCCH0 [R/W]

00000000

UDCCL0 [R/W]

00001000 Reserved UDCS0 [R/W]

00000000

000308H,

00030CHReserved Reserved

000310HUDRC3 [W]

00000000

UDRC2 [W]

00000000

UDCR3 [R]

00000000

UDCR2 [R]

00000000

Up/Down

Counter

2 to 3

000314HUDCCH2 [R/W]

00000000

UDCCL2 [R/W]

00001000 Reserved UDCS2 [R/W]

00000000

000318HUDCCH3 [R/W]

00000000

UDCCL3 [R/W]

00001000 Reserved UDCS3 [R/W]

00000000

00031CHReserved Reserved

000320HGCN13 [R/W]

00110010 00010000 Reserved GCN23 [R/W]

- - - - 0000

PPG Control

12 to 15

000324H

00032CH

Reserved Reserved

000330HPTMR12 [R]

11111111 11111111

PCSR12 [R/W]

XXXXXXXX XXXXXXXX PPG 12

000334HPDUT12 [R/W]

XXXXXXXX XXXXXXXX

PCNH12 [R/W]

0000000 -

PCNL12 [R/W]

000000 - 0

000338HPTMR13 [R]

11111111 11111111

PCSR13 [R/W]

XXXXXXXX XXXXXXXX PPG 13

00033CHPDUT13 [R/W]

XXXXXXXX XXXXXXXX

PCNH13 [R/W]

0000000 -

PCNL13 [R/W]

000000 - 0

000340HPTMR14 [R]

11111111 11111111

PCSR14 [R/W]

XXXXXXXX XXXXXXXX PPG 14

000344HPDUT14 [R/W]

XXXXXXXX XXXXXXXX

PCNH14 [R/W]

0000000 -

PCNL14 [R/W]

000000 - 0

MB91460E-DS705-00002-1v3-E.fm Page 116 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 117

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000348HPTMR15 [R]

11111111 11111111

PCSR15 [R/W]

XXXXXXXX XXXXXXXX PPG 15

00034CHPDUT15 [R/W]

XXXXXXXX XXXXXXXX

PCNH15 [R/W]

0000000 -

PCNL15 [R/W]

000000 - 0

000350H

000364H

Reserved Reserved

000368HIBCR2 [R/W]

00000000

IBSR2 [R]

00000000

ITBAH2 [R/W]

- - - - - - 00

ITBAL2 [R/W]

00000000

I2C 200036CHITMKH2 [R/W]

00 - - - - 11

ITMKL2 [R/W]

11111111

ISMK2 [R/W]

01111111

ISBA2 [R/W]

- 0000000

000370HReserved IDAR2 [R/W]

00000000

ICCR2 [R/W]

00011111 Reserved

000374HIBCR3 [R/W]

00000000

IBSR3 [R]

00000000

ITBAH3 [R/W]

- - - - - - 00

ITBAL3 [R/W]

00000000

I2C 3000378HITMKH3 [R/W]

00 - - - - 11

ITMKL3 [R/W]

11111111

ISMK3 [R/W]

01111111

ISBA3 [R/W]

- 0000000

00037CHReserved IDAR3 [R/W]

00000000

ICCR3 [R/W]

00011111 Reserved

000380H

00038CH

Reserved Reserved

000390HROMS [R]

11111111 00000000 (MB91F467EA) Reserved ROM Select Register

000394H

0003ECH

Reserved Reserved

0003F0HBSD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module

0003F4HBSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8HBSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FCHBSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400H

00043CH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 117 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

118 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000440HICR00 [R/W]

---11111

ICR01 [R/W]

---11111

ICR02 [R/W]

---11111

ICR03 [R/W]

---11111

Interrupt

Controller

000444HICR04 [R/W]

---11111

ICR05 [R/W]

---11111

ICR06 [R/W]

---11111

ICR07 [R/W]

---11111

000448HICR08 [R/W]

---11111

ICR09 [R/W]

---11111

ICR10 [R/W]

---11111

ICR11 [R/W]

---11111

00044CHICR12 [R/W]

---11111

ICR13 [R/W]

---11111

ICR14 [R/W]

---11111

ICR15 [R/W]

---11111

000450HICR16 [R/W]

---11111

ICR17 [R/W]

---11111

ICR18 [R/W]

---11111

ICR19 [R/W]

---11111

000454HICR20 [R/W]

---11111

ICR21 [R/W]

---11111

ICR22 [R/W]

---11111

ICR23 [R/W]

---11111

000458HICR24 [R/W]

---11111

ICR25 [R/W]

---11111

ICR26 [R/W]

---11111

ICR27 [R/W]

---11111

00045CHICR28 [R/W]

---11111

ICR29 [R/W]

---11111

ICR30 [R/W]

---11111

ICR31 [R/W]

---11111

000460HICR32 [R/W]

---11111

ICR33 [R/W]

---11111

ICR34 [R/W]

---11111

ICR35 [R/W]

---11111

000464HICR36 [R/W]

---11111

ICR37 [R/W]

---11111

ICR38 [R/W]

---11111

ICR39 [R/W]

---11111

000468HICR40 [R/W]

---11111

ICR41 [R/W]

---11111

ICR42 [R/W]

---11111

ICR43 [R/W]

---11111

00046CHICR44 [R/W]

---11111

ICR45 [R/W]

---11111

ICR46 [R/W]

---11111

ICR47 [R/W]

---11111

000470HICR48 [R/W]

---11111

ICR49 [R/W]

---11111

ICR50 [R/W]

---11111

ICR51 [R/W]

---11111

000474HICR52 [R/W]

---11111

ICR53 [R/W]

---11111

ICR54 [R/W]

---11111

ICR55 [R/W]

---11111

000478HICR56 [R/W]

---11111

ICR57 [R/W]

---11111

ICR58 [R/W]

---11111

ICR59 [R/W]

---11111

00047CHICR60 [R/W]

---11111

ICR61 [R/W]

---11111

ICR62 [R/W]

---11111

ICR63 [R/W]

---11111

000480HRSRR [R/W]

10000000

STCR [R/W]

00110011

TBCR [R/W]

00XXX - 00

CTBR [W]

XXXXXXXX Clock

Control

000484HCLKR [R/W]

---- 0000

WPR [W]

XXXXXXXX

DIVR0 [R/W]

00000011

DIVR1 [R/W]

00000000

000488HReserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 118 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 119

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00048CHPLLDIVM [R/W]

- - - - 0000

PLLDIVN [R/W]

- - 000000

PLLDIVG [R/W]

- - - - 0000

PLLMULG [W]

00000000 PLL Interface

000490HPLLCTRL [R/W]

- - - - 0000 Reserved

000494HOSCC1 [R/W]

- - - - - 010

OSCS1 [R/W]

00001111

OSCC2 [R/W]

- - - - - 010

OSCS2 [R/W]

00001111

Main/Sub

Oscillator

Control

000498HPORTEN [R/W]

- - - - - - 00 Reserved Port Input Enable

Control

00049CHReserved Reserved

0004A0HReserved WTCER [R/W]

- - - - - - 00

WTCR [R/W]

00000000 000 - 00 - 0

Real Time Clock

(Watch Timer)

0004A4HReserved WTBR [R/W]

- - - XXXXX XXXXXXXX XXXXXXXX

0004A8HWTHR [R/W]

- - - 00000

WTMR [R/W]

- - 000000

WTSR [R/W]

- - 000000 Reserved

0004ACHCSVTR [R/W]

- - - 00010

CSVCR

[R/W/W0]

00011100

CSCFG [R/W]

0X000000

CMCFG [R/W]

00000000

Clock-

Supervisor / Selector /

Monitor

0004B0HCUCR [R/W]

- - - - - - - - - - - 0 - - 00

CUTD [R/W]

10000000 00000000 Calibration of Sub

Clock

0004B4HCUTR1 [R]

- - - - - - - - 00000000

CUTR2 [R]

00000000 00000000

0004B8HCMPR [R/W]

- - 000010 11111101 Reserved CMCR [R/W]

- 001 - - 00 Clock

Modulator

0004BCHCMT1 [R/W]

00000000 1 - - - 0000

CMT2 [R/W]

- - 000000 - - 000000

0004C0HCANPRE [R/W]

0 - - - 0000

CANCKD [R/W]

- - - - - - 00 *1

1. Depends on the number of available CAN channels.

Reserved CAN Clock Control

MB91460E-DS705-00002-1v3-E.fm Page 119 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

120 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

0004C4HLVSEL [R/W]

00000111

LVDET [R/W]

0000 0 - 00

HWWDE [R/W]

- - - 0 - - 00 *1

1. HWWDE[4] is STP_RUN, see “HARDWARE WATCHDOG (Extension)” on page 51

HWWD [R/W, W]

00011000

Low Voltage Detection/

Hardware Watchdog

0004C8HOSCRH [R/W]

000 - - 001

OSCRL [R/W]

- - - - - 000

WPCRH [R/W]

00 - - - 000

WPCRL [R/W]

- - - - - - 00

Main-/Sub-Oscillation

Stabilisation Timer

0004CCHOSCCR [R/W]

- - - - - - 00*2

2. OSCCR[1] is OSCDS2, see MB91460 series hardware manual

Reserved REGSEL [R/W]

- - 11 0110*3

3. Main regulator default is 1.9V, sub regulator 1.8V (MB91F467D regulator defaults are 1.8V/1.6V)

REGCTR [R/W]

- - - 0 - - 00

Main- Oscillation

Standby Control

Main-/Subregulator

Control

0004D0HReserved Reserved

0004D4HSHDE [R/W]

0 - - - - - - 0 reserved EXTE [R/W]

0000 0000

EXTF [R/W0]

0000 0000 Shutdown Control

0004D8HEXTLV [R/W]

0000 0000 0000 0000 reserved SHDINT [R/W]

- - - - 0000

0004DCH

00063CH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 120 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 121

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000640HASR0 [R/W]

00000000 00000000

ACR0 [R/W]

1111**00 00100000 *1

External Bus

000644HASR1 [R/W]

XXXXXXXX XXXXXXXX

ACR1 [R/W]

XXXXXXXX XXXXXXXX

000648HASR2 [R/W]

XXXXXXXX XXXXXXXX

ACR2 [R/W]

XXXXXXXX XXXXXXXX

00064CHASR3 [R/W]

XXXXXXXX XXXXXXXX

ACR3 [R/W]

XXXXXXXX XXXXXXXX

000650HASR4 [R/W]

XXXXXXXX XXXXXXXX

ACR4 [R/W]

XXXXXXXX XXXXXXXX

000654HASR5 [R/W]

XXXXXXXX XXXXXXXX

ACR5 [R/W]

XXXXXXXX XXXXXXXX

000658HASR6 [R/W]

XXXXXXXX XXXXXXXX

ACR6 [R/W]

XXXXXXXX XXXXXXXX

00065CHASR7 [R/W]

XXXXXXXX XXXXXXXX

ACR7 [R/W]

XXXXXXXX XXXXXXXX

000660HAWR0 [R/W]

01001111 11111011

AWR1 [R/W]

XXXXXXXX XXXXXXXX

000664HAWR2 [R/W]

XXXXXXXX XXXXXXXX

AWR3 [R/W]

XXXXXXXX XXXXXXXX

000668HAWR4 [R/W]

XXXXXXXX XXXXXXXX

AWR5 [R/W]

XXXXXXXX XXXXXXXX

00066CHAWR6 [R/W]

XXXXXXXX XXXXXXXX

AWR7 [R/W]

XXXXXXXX XXXXXXXX

000670HMCRA [R/W]

XXXXXXXX

MCRB [R/W]

XXXXXXXX Reserved

000674HReserved

000678HIOWR0 [R/W]

XXXXXXXX

IOWR1 [R/W]

XXXXXXXX

IOWR2 [R/W]

XXXXXXXX

IOWR3 [R/W]

XXXXXXXX

00067CHReserved

000680HCSER [R/W]

00000001

CHER [R/W]

11111111 Reserved TCR [R/W]

0000**** *2

000684HRCRH [R/W]

00XXXXXX

RCRL [R/W]

XXXX0XXX Reserved

MB91460E-DS705-00002-1v3-E.fm Page 121 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

122 DS705-00002-1v3-E

000688HRCO0H0 [R/W]

11111111

RCO0L0 [R/W]

0000 0000

RCO0H1 [R/W]

1111111

RCO0L1 [R/W]

0000 0000

A/D Converter 0

Range Comparator

00068CHRCO0H2 [R/W]

1111111

RCO0L2 [R/W]

0000 0000

RCO0H3 [R/W]

1111111

RCO0L3 [R/W]

0000 0000

000690HRCO0IRS [R/W]

00000000 00000000 00000000 00000000

000694HRCO0OF [R]

00000000 00000000 00000000 00000000

000698HRCO0INT [R/W0]

00000000 00000000 00000000 00000000

00069CHreserved

0006A0HAD0CC0 [R/W]

0000 0000

AD0CC1 [R/W]

0000 0000

AD0CC2 [R/W]

0000 0000

AD0CC3 [R/W]

0000 0000

A/D Converter 0 Chan-

nel Control

0006A4HAD0CC4 [R/W]

0000 0000

AD0CC5 [R/W]

0000 0000

AD0CC6 [R/W]

0000 0000

AD0CC7 [R/W]

0000 0000

0006A8HAD0CC8 [R/W]

0000 0000

AD0CC9 [R/W]

0000 0000

AD0CC10 [R/W]

0000 0000

AD0CC11 [R/W]

0000 0000

0006ACHAD0CC12 [R/W]

0000 0000

AD0CC13 [R/W]

0000 0000

AD0CC14 [R/W]

0000 0000

AD0CC15 [R/W]

0000 0000

0006B0HAD0CS2 [RW]

0000 - - 00 reserved A/D Converter 0 Con-

trol register 2

0006B4H

0006DCH

Reserved

0006E0HADC0D0 [R]

- - - - - - XX XXXXXXXX

ADC0D1 [R]

- - - - - - XX XXXXXXXX

A/D Converter 0 Chan-

nel Data registers

0006E4HADC0D2 [R]

- - - - - - XX XXXXXXXX

ADC0D3 [R]

- - - - - - XX XXXXXXXX

0006E8HADC0D4 [R]

- - - - - - XX XXXXXXXX

ADC0D5 [R]

- - - - - - XX XXXXXXXX

0006ECHADC0D6 [R]

- - - - - - XX XXXXXXXX

ADC0D7 [R]

- - - - - - XX XXXXXXXX

0006F0HADC0D8 [R]

- - - - - - XX XXXXXXXX

ADC0D9 [R]

- - - - - - XX XXXXXXXX

0006F4HADC0D10 [R]

- - - - - - XX XXXXXXXX

ADC0D11 [R]

- - - - - - XX XXXXXXXX

0006F8HADC0D12 [R]

- - - - - - XX XXXXXXXX

ADC0D13 [R]

- - - - - - XX XXXXXXXX

0006FCHADC0D14 [R]

- - - - - - XX XXXXXXXX

ADC0D015 [R]

- - - - - - XX XXXXXXXX

000700HADC0D16 [R]

- - - - - - XX XXXXXXXX

ADC0D17 [R]

- - - - - - XX XXXXXXXX

Address Register Block

+ 0 + 1 + 2 + 3

MB91460E-DS705-00002-1v3-E.fm Page 122 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 123

000704HADC0D18 [R]

- - - - - - XX XXXXXXXX

ADC0D19 [R]

- - - - - - XX XXXXXXXX

A/D Converter 0 Chan-

nel Data registers

000708HADC0D20 [R]

- - - - - - XX XXXXXXXX

ADC0D21 [R]

- - - - - - XX XXXXXXXX

00070CHADC0D22 [R]

- - - - - - XX XXXXXXXX

ADC0D23 [R]

- - - - - - XX XXXXXXXX

000710HADC0D24 [R]

- - - - - - XX XXXXXXXX

ADC0D25 [R]

- - - - - - XX XXXXXXXX

000714HADC0D26 [R]

- - - - - - XX XXXXXXXX

ADC0D27 [R]

- - - - - - XX XXXXXXXX

000718HADC0D28 [R]

- - - - - - XX XXXXXXXX

ADC0D29 [R]

- - - - - - XX XXXXXXXX

00071CHADC0D30 [R]

- - - - - - XX XXXXXXXX

ADC0D31 [R]

- - - - - - XX XXXXXXXX

000720H

0007F8H

Reserved

0007FCHReserved MODR [W]

XXXXXXXX Reserved Mode Register

1. ACR0 [11 : 10] depends on bus width setting in Mode vector fetch information.

2. TCR [3 : 0] INIT value = 0000, keeps value after RST

Address Register Block

+ 0 + 1 + 2 + 3

MB91460E-DS705-00002-1v3-E.fm Page 123 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

124 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000800H

000CFCH

Reserved Reserved

000D00HPDRD00 [R]

XXXXXXXX

PDRD01 [R]

XXXXXXXX

PDRD02 [R]

XXXXXXXX

PDRD03 [R]

XXXXXXXX

R-bus

Port Data

Direct Read

000D04HPDRD04 [R]

- - - - - - XX

PDRD05 [R]

XXXXXXXX

PDRD06 [R]

XXXXXXXX

PDRD07 [R]

XXXXXXXX

000D08HPDRD08 [R]

XXXXXXXX

PDRD09 [R]

XX - - XXXX

PDRD10 [R]

- XXXXXX - Reserved

000D0CHReserved PDRD13 [R]

- - - - - XXX

PDRD14 [R]

XXXXXXXX

PDRD15 [R]

- - - - XXXX

000D10HPDRD16 [R]

XXXXXXXX

PDRD17 [R]

XXXX - - - -

PDRD18 [R]

- XXX - XXX

PDRD19 [R]

- XXX - XXX

000D14HPDRD20 [R]

- - - - - XXX Reserved PDRD22 [R]

- - XX - X - X

PDRD23 [R]

- - XXXXXX

000D18HPDRD24 [R]

XXXXXXXX

PDRD25 [R]

XXXXXXXX

PDRD26 [R]

XXXXXXXX

PDRD27 [R]

XXXXXXXX

000D1CHReserved PDRD29 [R]

XXXXXXXX Reserved

000D20H

000D3CH

Reserved Reserved

000D40HDDR00 [R/W]

00000000

DDR01 [R/W]

00000000

DDR02 [R/W]

00000000

DDR03 [R/W]

00000000

R-bus

Port Direction

000D44HDDR04 [R/W]

- - - - - - 00

DDR05 [R/W]

00000000

DDR06 [R/W]

00000000

DDR07 [R/W]

00000000

000D48HDDR08 [R/W]

00000000

DDR09 [R/W]

00 - - 0000

DDR10 [R/W]

- 000000 - Reserved

000D4CHReserved DDR13 [R/W]

- - - - - 000

DDR14 [R/W]

00000000

DDR15 [R/W]

- - - - 0000

000D50HDDR16 [R/W]

00000000

DDR17 [R/W]

0000 - - - -

DDR18 [R/W]

- 000 - 000

DDR19 [R/W]

- 000 - 000

000D54HDDR20 [R/W]

- - - - - 000 Reserved DDR22 [R/W]

- - 00 - 0 - 0

DDR23 [R/W]

- - 000000

000D58HDDR24 [R/W]

00000000

DDR25 [R/W]

00000000

DDR26 [R/W]

00000000

DDR27 [R/W]

00000000

000D5CHReserved DDR29 [R/W]

00000000 Reserved

000D60H

000D7CH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 124 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 125

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000D80HPFR00 [R/W]

00000000 *1

1. In internal vector fetch mode (MD[2:0]=000) PFR00 to PFR13 are initialized to 0x00 for GPIO mode.

In external vector fetch mode (MD[2:0]=001) PFR00 to PFR13 are initialized to 0xFF to enable the

external bus.

PFR01 [R/W]

00000000 *1

PFR02 [R/W]

00000000 *1

PFR03 [R/W]

00000000 *1

R-bus

Port Function

000D84HPFR04 [R/W]

- - - - - - 00 *1

PFR05 [R/W]

00000000 *1

PFR06 [R/W]

00000000 *1

PFR07 [R/W]

00000000 *1

000D88HPFR08 [R/W]

00000000 *1

PFR09 [R/W]

00 - - 0000 *1

PFR10 [R/W]

-000 000 - *1 Reserved

000D8CHReserved PFR13 [R/W]

- - - - - 000 *1

PFR14 [R/W]

00000000

PFR15 [R/W]

- - - - 0000

000D90HPFR16 [R/W]

00000000

PFR17 [R/W]

0000 - - - -

PFR18 [R/W]

- 000 - 000

PFR19 [R/W]

- 000 - 000

000D94HPFR20 [R/W]

- - - - - 000 Reserved PFR22 [R/W]

- - 00 - 0 - 0

PFR23 [R/W]

- - 000000

000D98HPFR24 [R/W]

00000000

PFR25 [R/W]

00000000

PFR26 [R/W]

00000000

PFR27 [R/W]

00000000

000D9CHReserved PFR29 [R/W]

00000000 Reserved

000DA0H

000DBCH

Reserved Reserved

000DC0HEPFR00 [R/W]

- - - - - - - -

EPFR01 [R/W]

- - - - - - - -

EPFR02 [R/W]

- - - - - - - -

EPFR03 [R/W]

- - - - - - - -

R-bus Extra

Port Function

000DC4HEPFR04 [R/W]

- - - - - - - -

EPFR05 [R/W]

- - - - - - - -

EPFR06 [R/W]

- - - - - - - -

EPFR07 [R/W]

- - - - - - - -

000DC8HEPFR08 [R/W]

- - - - - - - -

EPFR09 [R/W]

- - - - - - - -

EPFR10 [R/W]

- - 00 - - - - Reserved

000DCCHReserved EPFR13 [R/W]

- - - - - 0 - -

EPFR14 [R/W]

00000000

EPFR15 [R/W]

- - - - 0000

000DD0HEPFR16 [R/W]

0000 - - - -

EPFR17 [R/W]

- - - - - - - -

EPFR18 [R/W]

- 00 - - 00 -

EPFR19 [R/W]

- 0 - - - 0 - -

000DD4HEPFR20 [R/W]

- - - - - 00 - Reserved EPFR22 [R/W]

- - - - - - - -

EPFR23 [R/W]

- - - - - - - -

000DD8HEPFR24 [R/W]

- - - - - - - -

EPFR25 [R/W]

- - - - - - - -

EPFR26 [R/W]

00000000

EPFR27 [R/W]

00000000

000DDCHReserved EPFR29 [R/W]

- - - - - - - - Reserved

000DE0H

000DFCH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 125 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

126 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000E00HPODR00 [R/W]

00000000

PODR01 [R/W]

00000000

PODR02 [R/W]

00000000

PODR03 [R/W]

00000000

R-bus Port

Output Drive Select

000E04HPODR04 [R/W]

- - - - - - 00

PODR05 [R/W]

00000000

PODR06 [R/W]

00000000

PODR07 [R/W]

00000000

000E08HPODR08 [R/W]

00000000

PODR09 [R/W]

00 - - 0000

PODR10 [R/W]

- 000000 - Reserved

000E0CHReserved PODR13 [R/W]

- - - - - 000

PODR14 [R/W]

00000000

PODR15 [R/W]

- - - - 0000

000E10HPODR16 [R/W]

00000000

PODR17 [R/W]

0000 - - - -

PODR18 [R/W]

- 000 - 000

PODR19 [R/W]

- 000 - 000

000E14HPODR20 [R/W]

- - - - - 000 Reserved PODR22 [R/W]

- - 00 - 0 - 0

PODR23 [R/W]

- - 000000

000E18HPODR24 [R/W]

00000000

PODR25 [R/W]

00000000

PODR26 [R/W]

00000000

PODR27 [R/W]

00000000

000E1CHReserved PODR29 [R/W]

00000000 Reserved

000E20H

000E3CH

Reserved Reserved

000E40HPILR00 [R/W]

00000000

PILR01 [R/W]

00000000

PILR02 [R/W]

00000000

PILR03 [R/W]

00000000

R-bus Port

Input Level Select

000E44HPILR04 [R/W]

- - - - - - 00

PILR05 [R/W]

00000000

PILR06 [R/W]

00000000

PILR07 [R/W]

00000000

000E48HPILR08 [R/W]

00000000

PILR09 [R/W]

00 - - 0000

PILR10 [R/W]

- 000000 - Reserved

000E4CHReserved PILR13 [R/W]

- - - - - 000

PILR14 [R/W]

00000000

PILR15 [R/W]

- - - - 0000

000E50HPILR16 [R/W]

00000000

PILR17 [R/W]

0000 - - - -

PILR18 [R/W]

- 000 - 000

PILR19 [R/W]

- 000 - 000

000E54HPILR20 [R/W]

- - - - - 000 Reserved PILR22 [R/W]

- - 00 - 0 - 0

PILR23 [R/W]

- - 000000

000E58HPILR24 [R/W]

00000000

PILR25 [R/W]

00000000

PILR26 [R/W]

00000000

PILR27 [R/W]

00000000

000E5CHReserved PILR29 [R/W]

00000000 Reserved

000E60H

000E7CH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 126 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 127

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000E80HEPILR00 [R/W]

00000000

EPILR01 [R/W]

00000000

EPILR02 [R/W]

00000000

EPILR03 [R/W]

00000000

R-bus Extra

Port Input Level

Select Register

000E84HEPILR04 [R/W]

- - - - - - 00

EPILR05 [R/W]

00000000

EPILR06 [R/W]

00000000

EPILR07 [R/W]

00000000

000E88HEPILR08 [R/W]

00000000

EPILR09 [R/W]

00 - - 0000

EPILR10 [R/W]

- 000000 - Reserved

000E8CHReserved EPILR13 [R/W]

- - - - - 000

EPILR14 [R/W]

00000000

EPILR15 [R/W]

- - - - 0000

000E90HEPILR16 [R/W]

00000000

EPILR17 [R/W]

0000 - - - -

EPILR18 [R/W]

- 000 - 000

EPILR19 [R/W]

- 000 - 000

000E94HEPILR20 [R/W]

- - - - - 000 Reserved EPILR22 [R/W]

- - 00 - 0 - 0

EPILR23 [R/W]

- - 000000

000E98HEPILR24 [R/W]

00000000

EPILR25 [R/W]

00000000

EPILR26 [R/W]

00000000

EPILR27 [R/W]

00000000

000E9CHReserved EPILR29 [R/W]

00000000 Reserved

000EA0H

000EBCH

Reserved Reserved

000EC0HPPER00 [R/W]

00000000

PPER01 [R/W]

00000000

PPER02 [R/W]

00000000

PPER03 [R/W]

00000000

R-bus Port

Pull-Up/Down Enable

000EC4HPPER04 [R/W]

- - - - - - 00

PPER05 [R/W]

00000000

PPER06 [R/W]

00000000

PPER07 [R/W]

00000000

000EC8HPPER08 [R/W]

00000000

PPER09 [R/W]

00 - - 0000

PPER10 [R/W]

- 000000 - Reserved

000ECCHReserved PPER13 [R/W]

- - - - - 000

PPER14 [R/W]

00000000

PPER15 [R/W]

- - - - 0000

000ED0HPPER16 [R/W]

00000000

PPER17 [R/W]

0000 - - - -

PPER18 [R/W]

- 000 - 000

PPER19 [R/W]

- 000 - 000

000ED4HPPER20 [R/W]

- - - - - 000 Reserved PPER22 [R/W]

- - 00 - 0 - 0

PPER23 [R/W]

- - 000000

000ED8HPPER24 [R/W]

00000000

PPER25 [R/W]

00000000

PPER26 [R/W]

00000000

PPER27 [R/W]

00000000

000EDCHReserved PPER29 [R/W]

00000000 Reserved

000EE0H

000EFCH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 127 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

128 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

000F00HPPCR00 [R/W]

11111111

PPCR01 [R/W]

11111111

PPCR02 [R/W]

11111111

PPCR03 [R/W]

11111111

R-bus Port

Pull-Up/Down Control

000F04HPPCR04 [R/W]

- - - - - - 11

PPCR05 [R/W]

11111111

PPCR06 [R/W]

11111111

PPCR07 [R/W]

11111111

000F08HPPCR08 [R/W]

11111111

PPCR09 [R/W]

11 - - 1111

PPCR10 [R/W]

- 111111 - Reserved

000F0CHReserved PPCR13 [R/W]

- - - - - 111

PPCR14 [R/W]

11111111

PPCR15 [R/W]

- - - - 1111

000F10HPPCR16 [R/W]

11111111

PPCR17 [R/W]

1111 - - - -

PPCR18 [R/W]

- 111 - 111

PPCR19 [R/W]

- 111 - 111

000F14HPPCR20 [R/W]

- - - - - 111 Reserved PPCR22 [R/W]

- - 11 - 1 - 1

PPCR23 [R/W]

- - 111111

000F18HPPCR24 [R/W]

11111111

PPCR25 [R/W]

11111111

PPCR26 [R/W]

11111111

PPCR27 [R/W]

11111111

000F1CHReserved PPCR29 [R/W]

11111111 Reserved

000F20H

000F3CH

Reserved Reserved

001000HDMASA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

001004HDMADA0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001008HDMASA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00100CHDMADA1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001010HDMASA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001014HDMADA2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001018HDMASA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00101CHDMADA3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001020HDMASA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001024HDMADA4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001028H

001FFCH

Reserved Reserved

MB91460E-DS705-00002-1v3-E.fm Page 128 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 129

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

002000H

006FFCH

MB91F467EA Flash-cache size is 8 Kbytes : 004000H to 005FFCHFlash-cache /

I-RAM area

007000HFMCS [R/W]

01101000

FMCR [R]

- - - 00000

FCHCR [R/W]

- - - - - - 00 10000011 Flash Memory/

Flash-cache/

I-RAM Control

007004HFMWT [R/W]

11111111 11111111

FMWT2 [R]

- 001 - - - -

FMPS [R/W]

- - - - - 000

007008HFMAC [R]

00000000 00000000 00000000 00000000

00700CHFCHA0 [R/W]

- - - - - - - - - - - 00000 00000000 00000000 Flash-cache Non-

cacheable area setting

007010HFCHA1 [R/W]

- - - - - - - - - - - 00000 00000000 00000000

007014H

007FFCH

Reserved Reserved

008000H

00BFFCH

MB91F467EA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH

(instruction access is 1 wait cycle, data access is 1 wait cycle) Boot ROM area

00C000HCTRLR0 [R/W]

00000000 00000001

STATR0 [R/W]

00000000 00000000

CAN 0

Control

00C004HERRCNT0 [R]

00000000 00000000

BTR0 [R/W]

00100011 00000001

00C008HINTR0 [R]

00000000 00000000

TESTR0 [R/W]

00000000 X0000000

00C00CHBRPE0 [R/W]

00000000 00000000 Reserved

00C010HIF1CREQ0 [R/W]

00000000 00000001

IF1CMSK0 [R/W]

00000000 00000000

CAN 0

IF 1 Register

00C014HIF1MSK20 [R/W]

11111111 11111111

IF1MSK10 [R/W]

11111111 11111111

00C018HIF1ARB20 [R/W]

00000000 00000000

IF1ARB10 [R/W]

00000000 00000000

00C01CHIF1MCTR0 [R/W]

00000000 00000000 Reserved

MB91460E-DS705-00002-1v3-E.fm Page 129 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

130 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00C020HIF1DTA10 [R/W]

00000000 00000000

IF1DTA20 [R/W]

00000000 00000000

CAN 0

IF 1 Register

00C024HIF1DTB10 [R/W]

00000000 00000000

IF1DTB20 [R/W]

00000000 00000000

00C028H,

00C02CHReserved

00C030HIF1DTA20 [R/W]

00000000 00000000

IF1DTA10 [R/W]

00000000 00000000

00C034HIF1DTB20 [R/W]

00000000 00000000

IF1DTB10 [R/W]

00000000 00000000

00C038H,

00C03CHReserved

00C040HIF2CREQ0 [R/W]

00000000 00000001

IF2CMSK0 [R/W]

00000000 00000000

CAN 0

IF 2 Register

00C044HIF2MSK20 [R/W]

11111111 11111111

IF2MSK10 [R/W]

11111111 11111111

00C048HIF2ARB20 [R/W]

00000000 00000000

IF2ARB10 [R/W]

00000000 00000000

00C04CHIF2MCTR0 [R/W]

00000000 00000000 Reserved

00C050HIF2DTA10 [R/W]

00000000 00000000

IF2DTA20 [R/W]

00000000 00000000

00C054HIF2DTB10 [R/W]

00000000 00000000

IF2DTB20 [R/W]

00000000 00000000

00C058H,

00C05CHReserved

00C060HIF2DTA20 [R/W]

00000000 00000000

IF2DTA10 [R/W]

00000000 00000000

00C064HIF2DTB20 [R/W]

00000000 00000000

IF2DTB10 [R/W]

00000000 00000000

00C068H

00C07CH

Reserved

MB91460E-DS705-00002-1v3-E.fm Page 130 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 131

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00C080HTREQR20 [R]

00000000 00000000

TREQR10 [R]

00000000 00000000

CAN 0

Status Flags

00C084H

00C08CH

Reserved

00C090HNEWDT20 [R]

00000000 00000000

NEWDT10 [R]

00000000 00000000

00C094H

00C09CH

Reserved

00C0A0HINTPND20 [R]

00000000 00000000

INTPND10 [R]

00000000 00000000

00C0A4H

00C0ACH

Reserved

00C0B0HMSGVAL20 [R]

00000000 00000000

MSGVAL10 [R]

00000000 00000000

00C0B4H

00C0FCH

Reserved Reserved

00C100HCTRLR1 [R/W]

00000000 00000001

STATR1 [R/W]

00000000 00000000

CAN 1

Control

00C104HERRCNT1 [R]

00000000 00000000

BTR1 [R/W]

00100011 00000001

00C108HINTR1 [R]

00000000 00000000

TESTR1 [R/W]

00000000 X0000000

00C10CHBRPE1 [R/W]

00000000 00000000 Reserved

00C110HIF1CREQ1 [R/W]

00000000 00000001

IF1CMSK1 [R/W]

00000000 00000000

CAN 1

IF 1 Register

00C114HIF1MSK21 [R/W]

11111111 11111111

IF1MSK11 [R/W]

11111111 11111111

00C118HIF1ARB21 [R/W]

00000000 00000000

IF1ARB11 [R/W]

00000000 00000000

00C11CHIF1MCTR1 [R/W]

00000000 00000000 Reserved

00C120HIF1DTA11 [R/W]

00000000 00000000

IF1DTA21 [R/W]

00000000 00000000

00C124HIF1DTB11 [R/W]

00000000 00000000

IF1DTB21 [R/W]

00000000 00000000

MB91460E-DS705-00002-1v3-E.fm Page 131 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

132 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00C128H,

00C12CHReserved

CAN 1

IF 1 Register

00C130HIF1DTA21 [R/W]

00000000 00000000

IF1DTA11 [R/W]

00000000 00000000

00C134HIF1DTB21 [R/W]

00000000 00000000

IF1DTB11 [R/W]

00000000 00000000

00C138H,

00C13CHReserved

00C140HIF2CREQ1 [R/W]

00000000 00000001

IF2CMSK1 [R/W]

00000000 00000000

CAN 1

IF 2 Register

00C144HIF2MSK21 [R/W]

11111111 11111111

IF2MSK11 [R/W]

11111111 11111111

00C148HIF2ARB21 [R/W]

00000000 00000000

IF2ARB11 [R/W]

00000000 00000000

00C14CHIF2MCTR1 [R/W]

00000000 00000000 Reserved

00C150HIF2DTA11 [R/W]

00000000 00000000

IF2DTA21 [R/W]

00000000 00000000

00C154HIF2DTB11 [R/W]

00000000 00000000

IF2DTB21 [R/W]

00000000 00000000

00C158H,

00C15CHReserved

00C160HIF2DTA21 [R/W]

00000000 00000000

IF2DTA11 [R/W]

00000000 00000000

00C164HIF2DTB21 [R/W]

00000000 00000000

IF2DTB11 [R/W]

00000000 00000000

00C168H

00C17CH

Reserved

00C180HTREQR21 [R]

00000000 00000000

TREQR11 [R]

00000000 00000000

CAN 1

Status Flags

00C184H

00C18CH

Reserved

00C190HNEWDT21 [R]

00000000 00000000

NEWDT11 [R]

00000000 00000000

00C194H

00C19CH

Reserved

MB91460E-DS705-00002-1v3-E.fm Page 132 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 133

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00C1A0HINTPND21 [R]

00000000 00000000

INTPND11 [R]

00000000 00000000

CAN 1

Status Flags

00C1A4H

00C1ACH

Reserved

00C1B0HMSGVAL21 [R]

00000000 00000000

MSGVAL11 [R]

00000000 00000000

00C1B4H

00C1FCH

Reserved

00C200H

00EFFCH

Reserved Resedved

MB91460E-DS705-00002-1v3-E.fm Page 133 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

134 DS705-00002-1v3-E

(Continued)

Address Register Block

+ 0 + 1 + 2 + 3

00F000HBCTRL [R/W]

- - - - - - - - - - - - - - - - 11111100 00000000

EDSU / MPU

00F004HBSTAT [R/W]

- - - - - - - - - - - - - 000 00000000 10 - - 0000

00F008HBIAC [R]

- - - - - - - - - - - - - - - - 00000000 00000000

00F00CHBOAC [R]

- - - - - - - - - - - - - - - - 00000000 00000000

00F010HBIRQ [R/W]

- - - - - - - - - - - - - - - - 00000000 00000000

00F014H

00F01CH

Reserved

00F020HBCR0 [R/W]

- - - - - - - - 00000000 00000000 00000000

00F024HBCR1 [R/W]

- - - - - - - - 00000000 00000000 00000000

00F028HBCR2 [R/W]

- - - - - - - - 00000000 00000000 00000000

00F02CHBCR3 [R/W]

- - - - - - - - 00000000 00000000 00000000

00F030H

00F07CH

Reserved Reserved

00F080HBAD0 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDSU / MPU

00F084HBAD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F088HBAD2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F08CHBAD3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F090HBAD4 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F094HBAD5 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F098HBAD6 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

MB91460E-DS705-00002-1v3-E.fm Page 134 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 135

Address Register Block

+ 0 + 1 + 2 + 3

00F09CHBAD7 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDSU / MPU

00F0A0HBAD8 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0A4HBAD9 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0A8HBAD10 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0ACHBAD11 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0B0HBAD12 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0B4HBAD13 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0B8HBAD14 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0BCHBAD15 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0C0H

01FFFCH

Reserved Reserved

020000H

02FFFCH

MB91F467EA D-RAM size is 64 Kbytes : 020000H to 02FFFCH

(data access is 0 wait cycles) D-RAM area

030000H

03FFFCH

MB91F467EA ID-RAM size is 48 Kbytes : 030000H to 03BFFCH

(instruction access is 0 wait cycles, data access is 1 wait cycle) ID-RAM area

MB91460E-DS705-00002-1v3-E.fm Page 135 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

136 DS705-00002-1v3-E

2. Flash memory and external bus area

32bit read/write dat[31:0] dat[31:0]

16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0]

Address Register Block

+ 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7

040000H

05FFF8H

SA8 (64KB) SA9 (64KB) ROMS0

060000H

07FFF8H

SA10 (64KB) SA11 (64KB) ROMS1

080000H

09FFF8H

SA12 (64KB) SA13 (64KB) ROMS2

0A0000H

0BFFF8H

SA14 (64KB) SA15 (64KB) ROMS3

0C0000H

0DFFF8H

SA16 (64KB) SA17 (64KB) ROMS4

0E0000H

0FFFF0H

SA18 (64KB)

FMV [R] 1

06 00 00 00H

SA19 (64KB)

FRV [R] 2

00 00 BF F8H

ROMS5

0FFFF8H

100000H

11FFF8H

SA20 (64KB) SA21 (64KB)

ROMS6

120000H

13FFF8H

SA22 (64KB) SA23 (64KB)

140000H

143FF8H

SA0 (8KB) SA1 (8KB)

ROMS7

144000H

147FF8H

SA2 (8KB) SA3 (8KB)

148000H

14BFF8H

SA4 (8KB) SA5 (8KB)

14C000H

14FFF8H

SA6 (8KB) SA7 (8KB)

150000H

17FFF8H

Reserved

MB91460E-DS705-00002-1v3-E.fm Page 136 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 137

32bit read/write dat[31:0] dat[31:0]

16bit read/write dat[31:16] dat[15:0] dat[31:16] dat[15:0]

Address Register Block

+ 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7

180000H

1BFFF8H

External Bus Area

ROMS8

1C0000H

1FFFF8H

ROMS9

200000H

27FFF8H

ROMS10

280000H

2FFFF8H

ROMS11

300000H

37FFF8H

ROMS12

380000H

3FFFF8H

ROMS13

400000H

47FFF8H

ROMS14

480000H

4FFFF8H

ROMS15

500000H

FFFABFF8H

External Bus Area

FFFAC000H

FFFAFFF8H

MB91F467EA Standby-RAM 16 KBytes (1 wait cycle) Standby RAM

FFFB0000H

FFFFFFF8H

External Bus Area

1. Write operations to address 0FFFF8H is not possible. When reading these addresses, the values

shown above will be read.

2. Write operations to address 0FFFFCH is not possible. When reading these addresses, the values

shown above will be read.

MB91460E-DS705-00002-1v3-E.fm Page 137 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

138 DS705-00002-1v3-E

■INTERRUPT VECTOR TABLE

(Continued)

Interrupt

number Interrupt level *1Interrupt vector *2 DMA

Resource

number

Deci-

mal

Hexa-

decimal

Setting

address Offset Default Vector

address

Reset 0 00 ⎯⎯3FCH000FFFFCH⎯

Mode vector 1 01 ⎯⎯3F8H000FFFF8H⎯

System reserved 2 02 ⎯⎯3F4H000FFFF4H⎯

System reserved 3 03 ⎯⎯3F0H000FFFF0H⎯

System reserved 4 04 ⎯⎯3ECH000FFFECH⎯

CPU supervisor mode

(INT #5 instruction) *5 505 ⎯⎯3E8H000FFFE8H⎯

Memory Protection exception *5 606 ⎯⎯3E4H000FFFE4H⎯

System reserved 7 07 ⎯⎯3E0H000FFFE0H⎯

System reserved 8 08 ⎯⎯3DCH000FFFDCH⎯

System reserved 9 09 ⎯⎯3D8H000FFFD8H⎯

System reserved 10 0A ⎯⎯3D4H000FFFD4H⎯

System reserved 11 0B ⎯⎯3D0H000FFFD0H⎯

System reserved 12 0C ⎯⎯3CCH000FFFCCH⎯

System reserved 13 0D ⎯⎯3C8H000FFFC8H⎯

Undefined instruction exception 14 0E ⎯⎯3C4H000FFFC4H⎯

NMI request 15 0F FH fixed 3C0H000FFFC0H⎯

External Interrupt 0 16 10 ICR00 440H

3BCH000FFFBCH0, 16

External Interrupt 1 17 11 3B8H000FFFB8H1, 17

External Interrupt 2 18 12 ICR01 441H

3B4H000FFFB4H2, 18

External Interrupt 3 19 13 3B0H000FFFB0H3, 19

External Interrupt 4 20 14 ICR02 442H

3ACH000FFFACH20

External Interrupt 5 21 15 3A8H000FFFA8H21

External Interrupt 6 22 16 ICR03 443H

3A4H000FFFA4H22

External Interrupt 7 23 17 3A0H000FFFA0H23

External Interrupt 8 24 18 ICR04 444H

39CH000FFF9CH⎯

External Interrupt 9 25 19 398H000FFF98H⎯

External Interrupt 10 26 1A ICR05 445H

394H000FFF94H⎯

Reserved 27 1B 390H000FFF90H⎯

External Interrupt 12 28 1C ICR06 446H

38CH000FFF8CH⎯

External Interrupt 13 29 1D 388H000FFF88H⎯

External Interrupt 14 30 1E ICR07 447H

384H000FFF84H⎯

Reserved 31 1F 380H000FFF80H⎯

MB91460E-DS705-00002-1v3-E.fm Page 138 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 139

(Continued)

Interrupt

number Interrupt level *1 Interrupt vector *2 DMA

Resource

number

Deci-

mal

Hexa-

decimal

Setting

address Offset Default Vector

address

Reload Timer 0 32 20 ICR08 448H

37CH000FFF7CH4, 32

Reload Timer 1 33 21 378H000FFF78H5, 33

Reload Timer 2 34 22 ICR09 449H

374H000FFF74H34

Reload Timer 3 35 23 370H000FFF70H35

Reload Timer 4 36 24 ICR10 44AH

36CH000FFF6CH36

Reload Timer 5 37 25 368H000FFF68H37

Reload Timer 6 38 26 ICR11 44BH

364H000FFF64H38

Reload Timer 7 39 27 360H000FFF60H39

Free Run Timer 0 40 28 ICR12 44CH

35CH000FFF5CH40

Free Run Timer 1 41 29 358H000FFF58H41

Free Run Timer 2 42 2A ICR13 44DH

354H000FFF54H42

Free Run Timer 3 43 2B 350H000FFF50H43

Free Run Timer 4 44 2C ICR14 44EH

34CH000FFF4CH44

Free Run Timer 5 45 2D 348H000FFF48H45

Free Run Timer 6 46 2E ICR15 44FH

344H000FFF44H46

Free Run Timer 7 47 2F 340H000FFF40H47

CAN 0 48 30 ICR16 450H

33CH000FFF3CH⎯

CAN 1 49 31 338H000FFF38H⎯

Reserved 50 32 ICR17 451H

334H000FFF34H⎯

Reserved 51 33 330H000FFF30H⎯

Reserved 52 34 ICR18 452H

32CH000FFF2CH⎯

Reserved 53 35 328H000FFF28H⎯

Reserved 54 36 ICR19 453H

324H000FFF24H6, 48

Reserved 55 37 320H000FFF20H7, 49

Reserved 56 38 ICR20 454H

31CH000FFF1CH8, 50

Reserved 57 39 318H000FFF18H9, 51

LIN-USART 2 RX 58 3A

ICR21 455H

314H000FFF14H52

LIN-USART 2 TX

LIN-USART (FIFO) 2 EoT 59 3B 310H000FFF10H53

Reserved 60 3C ICR22 456H

30CH000FFF0CH54

Reserved 61 3D 308H000FFF08H55

Reserved 62 3E ICR23 *3457H

304H000FFF04H⎯

Delayed Interrupt 63 3F 300H000FFF00H⎯

MB91460E-DS705-00002-1v3-E.fm Page 139 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

140 DS705-00002-1v3-E

(Continued)

Interrupt

number Interrupt level *1 Interrupt vector *2 DMA

Resource

number

Deci-

mal

Hexa-

decimal

Setting

address Offset Default Vector

address

System reserved *464 40 (ICR24) (458H)2FCH000FFEFCH⎯

System reserved *465 41 2F8H000FFEF8H⎯

LIN-USART (FIFO) 4 RX 66 42

ICR25 459H

2F4H000FFEF4H10, 56

LIN-USART (FIFO) 4 TX

LIN-USART (FIFO) 4 EoT 67 43 2F0H000FFEF0H11, 57

LIN-USART (FIFO) 5 RX 68 44

ICR26 45AH

2ECH000FFEECH12, 58

LIN-USART (FIFO) 5 TX

LIN-USART (FIFO) 5 EoT 69 45 2E8H000FFEE8H13, 59

LIN-USART (FIFO) 6 RX 70 46

ICR27 45BH

2E4H000FFEE4H60

LIN-USART (FIFO) 6 TX

LIN-USART (FIFO) 6 EoT 71 47 2E0H000FFEE0H61

LIN-USART (FIFO) 7 RX 72 48

ICR28 45CH

2DCH000FFEDCH62

LIN-USART (FIFO) 7 TX

LIN-USART (FIFO) 7 EoT 73 49 2D8H000FFED8H63

I2C 0 / I2C 2 74 4A ICR29 45DH

2D4H000FFED4H⎯

I2C 3 75 4B 2D0H000FFED0H⎯

Reserved 76 4C ICR30 45EH

2CCH000FFECCH64

Reserved 77 4D 2C8H000FFEC8H65

Reserved 78 4E ICR31 45FH

2C4H000FFEC4H66

Reserved 79 4F 2C0H000FFEC0H67

Reserved 80 50 ICR32 460H

2BCH000FFEBCH68

Reserved 81 51 2B8H000FFEB8H69

Reserved 82 52 ICR33 461H

2B4H000FFEB4H70

Reserved 83 53 2B0H000FFEB0H71

Reserved 84 54 ICR34 462H

2ACH000FFEACH72

Reserved 85 55 2A8H000FFEA8H73

Reserved 86 56 ICR35 463H

2A4H000FFEA4H74

Reserved 87 57 2A0H000FFEA0H75

Reserved 88 58 ICR36 464H

29CH000FFE9CH76

Reserved 89 59 298H000FFE98H77

Reserved 90 5A ICR37 465H

294H000FFE94H78

Reserved 91 5B 290H000FFE90H79

MB91460E-DS705-00002-1v3-E.fm Page 140 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 141

(Continued)

Interrupt

number Interrupt level *1 Interrupt vector *2 DMA

Resource

number

Deci-

mal

Hexa-

decimal

Setting

address Offset Default Vector

address

Input Capture 0 92 5C ICR38 466H

28CH000FFE8CH80

Input Capture 1 93 5D 288H000FFE88H81

Input Capture 2 94 5E ICR39 467H

284H000FFE84H82

Input Capture 3 95 5F 280H000FFE80H83

Input Capture 4 96 60 ICR40 468H

27CH000FFE7CH84

Input Capture 5 97 61 278H000FFE78H85

Input Capture 6 98 62 ICR41 469H

274H000FFE74H86

Input Capture 7 99 63 270H000FFE70H87

Output Compare 0 100 64 ICR42 46AH

26CH000FFE6CH88

Output Compare 1 101 65 268H000FFE68H89

Output Compare 2 102 66 ICR43 46BH

264H000FFE64H90

Output Compare 3 103 67 260H000FFE60H91

Reserved 104 68 ICR44 46CH

25CH000FFE5CH92

Reserved 105 69 258H000FFE58H93

Reserved 106 6A ICR45 46DH

254H000FFE54H94

Reserved 107 6B 250H000FFE50H95

Sound Generator 108 6C ICR46 46EH

24CH000FFE4CH⎯

Phase Frequency Modulator 109 6D 248H000FFE48H⎯

Reserved 110 6E ICR47 *346FH

244H000FFE44H⎯

Reserved 111 6F 240H000FFE40H⎯

Reserved 112 70 ICR48 470H

23CH000FFE3CH15, 96

Reserved 113 71 238H000FFE38H97

Reserved 114 72 ICR49 471H

234H000FFE34H98

Reserved 115 73 230H000FFE30H99

PPG4 116 74 ICR50 472H

22CH000FFE2CH100

PPG5 117 75 228H000FFE28H101

PPG6 118 76 ICR51 473H

224H000FFE24H102

PPG7 119 77 220H000FFE20H103

PPG8 120 78 ICR52 474H

21CH000FFE1CH104

PPG9 121 79 218H000FFE18H105

PPG10 122 7A ICR53 475H

214H000FFE14H106

PPG11 123 7B 210H000FFE10H107

MB91460E-DS705-00002-1v3-E.fm Page 141 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

142 DS705-00002-1v3-E

(Continued)

*1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each

interrupt request. An ICR is provided for each interrupt request.

*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the

table base register value (TBR) . The TBR speciﬁes the top of the EIT vector table. The addresses listed in the

table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set

to 000FFC00H after the internal boot ROM is executed.

*3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])

*4 : Used by REALOS

*5 : Memory Protection Unit (MPU) support

Interrupt

number Interrupt level *1 Interrupt vector *2 DMA

Resource

number

Deci-

mal

Hexa-

decimal

Setting

address Offset Default Vector

address

PPG12 124 7C ICR54 476H

20CH000FFE0CH108

PPG13 125 7D 208H000FFE08H109

PPG14 126 7E ICR55 477H

204H000FFE04H110

PPG15 127 7F 200H000FFE00H111

Up/Down Counter 0 128 80 ICR56 478H

1FCH000FFDFCH⎯

Reserved 129 81 1F8H000FFDF8H⎯

Up/Down Counter 2 130 82 ICR57 479H

1F4H000FFDF4H⎯

Up/Down Counter 3 131 83 1F0H000FFDF0H⎯

Real Time Clock 132 84 ICR58 47AH

1ECH000FFDECH⎯

Calibration Unit 133 85 1E8H000FFDE8H⎯

A/D Converter 0 134 86 ICR59 47BH

1E4H000FFDE4H14, 112

Reserved 135 87 1E0H000FFDE0H⎯

Alarm Comparator 0 136 88 ICR60 47CH

1DCH000FFDDCH⎯

Reserved 137 89 1D8H000FFDD8H⎯

Low Voltage Detection 138 8A ICR61 47DH

1D4H000FFDD4H⎯

SMC Comparator 0 to 5 139 8B 1D0H000FFDD0H⎯

Timebase Overflow 140 8C ICR62 47EH

1CCH000FFDCCH⎯

PLL Clock Gear 141 8D 1C8H000FFDC8H⎯

DMA Controller 142 8E ICR63 47FH

1C4H000FFDC4H⎯

Main/Sub OSC stability wait 143 8F 1C0H000FFDC0H⎯

Security vector 144 90 ⎯⎯1BCH000FFDBCH⎯

Used by the INT instruction.

145

255

⎯⎯

1B8Hto

000H

000FFDB8H

000FFC00H

⎯

MB91460E-DS705-00002-1v3-E.fm Page 142 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 143

■RECOMMENDED SETTINGS

1. PLL and Clockgear settings

Please note that for MB91F467EA the core base clock frequencies are valid in the 1.9V operation mode of the

Main regulator and Flash.

Recommended PLL divider and clockgear settings

PLL

Input (CLK)

[MHz]

Frequency Parameter Clockgear Parameter

PLL

Output (X)

[MHz]

Core Base

Clock

[MHz] Remarks

DIVM DIVN DIVG MULG MULG

4 2 25 16 24 200 100

4 2 24 16 24 192 96 .

4 2 23 16 24 184 92

4 2 22 16 24 176 88

4 2 21 16 20 168 84

4 2 20 16 20 160 80

4 2 19 16 20 152 76

4 2 18 16 20 144 72

4 2 17 16 16 136 68

4 2 16 16 16 128 64

4 2 15 16 16 120 60

4 2 14 16 16 112 56

4 2 13 16 12 104 52

4 2 12 16 12 96 48

4 2 11 16 12 88 44

4 4 10 16 24 160 40

4 4 9 16 24 144 36

4 4 8 16 24 128 32

4 4 7 16 24 112 28

4 6 6 16 24 144 24

4 8 5 16 28 160 20

4 10 4 16 32 160 16

4 12 3 16 32 144 12

MB91460E-DS705-00002-1v3-E.fm Page 143 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

144 DS705-00002-1v3-E

2. Clock Modulator settings

The following table shows all possible settings for the Clock Modulator in a base clock frequency range from

32MHz up to 98MHz.

The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings

should be set according to base clock frequency.

Clock Modulator settings, frequency range and supported supply voltage

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

1 3 026F 88 79.5 98.5

1 3 026F 84 76.1 93.8

1 3 026F 80 72.6 89.1

1 5 02AE 80 68.7 95.8

2 3 046E 80 68.7 95.8

1 3 026F 76 69.1 84.5

1 5 02AE 76 65.3 90.8

1 7 02ED 76 62 98.1

2 3 046E 76 65.3 90.8

3 3 066D 76 62 98.1

1 3 026F 72 65.5 79.9

1 5 02AE 72 62 85.8

1 7 02ED 72 58.8 92.7

2 3 046E 72 62 85.8

3 3 066D 72 58.8 92.7

1 3 026F 68 62 75.3

1 5 02AE 68 58.7 80.9

1 7 02ED 68 55.7 87.3

1 9 032C 68 53 95

2 3 046E 68 58.7 80.9

2 5 04AC 68 53 95

3 3 066D 68 55.7 87.3

4 3 086C 68 53 95

1 3 026F 64 58.5 70.7

1 5 02AE 64 55.3 75.9

1 7 02ED 64 52.5 82

1 9 032C 64 49.9 89.1

1 11 036B 64 47.6 97.6

2 3 046E 64 55.3 75.9

2 5 04AC 64 49.9 89.1

MB91460E-DS705-00002-1v3-E.fm Page 144 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 145

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

3 3 066D 64 52.5 82

4 3 086C 64 49.9 89.1

5 3 0A6B 64 47.6 97.6

1 3 026F 60 54.9 66.1

1 5 02AE 60 51.9 71

1 7 02ED 60 49.3 76.7

1 9 032C 60 46.9 83.3

1 11 036B 60 44.7 91.3

2 3 046E 60 51.9 71

2 5 04AC 60 46.9 83.3

3 3 066D 60 49.3 76.7

4 3 086C 60 46.9 83.3

5 3 0A6B 60 44.7 91.3

1 3 026F 56 51.4 61.6

1 5 02AE 56 48.6 66.1

1 7 02ED 56 46.1 71.4

1 9 032C 56 43.8 77.6

1 11 036B 56 41.8 84.9

1 13 03AA 56 39.9 93.8

2 3 046E 56 48.6 66.1

2 5 04AC 56 43.8 77.6

2 7 04EA 56 39.9 93.8

3 3 066D 56 46.1 71.4

3 5 06AA 56 39.9 93.8

4 3 086C 56 43.8 77.6

5 3 0A6B 56 41.8 84.9

6 3 0C6A 56 39.9 93.8

1 3 026F 52 47.8 57

1 5 02AE 52 45.2 61.2

1 7 02ED 52 42.9 66.1

1 9 032C 52 40.8 71.8

1 11 036B 52 38.8 78.6

1 13 03AA 52 37.1 86.8

1 15 03E9 52 35.5 96.9

2 3 046E 52 45.2 61.2

MB91460E-DS705-00002-1v3-E.fm Page 145 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

146 DS705-00002-1v3-E

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

2 5 04AC 52 40.8 71.8

2 7 04EA 52 37.1 86.8

3 3 066D 52 42.9 66.1

3 5 06AA 52 37.1 86.8

4 3 086C 52 40.8 71.8

5 3 0A6B 52 38.8 78.6

6 3 0C6A 52 37.1 86.8

7 3 0E69 52 35.5 96.9

1 3 026F 48 44.2 52.5

1 5 02AE 48 41.8 56.4

1 7 02ED 48 39.6 60.9

1 9 032C 48 37.7 66.1

1 11 036B 48 35.9 72.3

1 13 03AA 48 34.3 79.9

1 15 03E9 48 32.8 89.1

2 3 046E 48 41.8 56.4

2 5 04AC 48 37.7 66.1

2 7 04EA 48 34.3 79.9

3 3 066D 48 39.6 60.9

3 5 06AA 48 34.3 79.9

4 3 086C 48 37.7 66.1

5 3 0A6B 48 35.9 72.3

6 3 0C6A 48 34.3 79.9

7 3 0E69 48 32.8 89.1

1 3 026F 44 40.6 48.1

1 5 02AE 44 38.4 51.6

1 7 02ED 44 36.4 55.7

1 9 032C 44 34.6 60.4

1 11 036B 44 33 66.1

1 13 03AA 44 31.5 73

1 15 03E9 44 30.1 81.4

2 3 046E 44 38.4 51.6

2 5 04AC 44 34.6 60.4

2 7 04EA 44 31.5 73

2 9 0528 44 28.9 92.1

MB91460E-DS705-00002-1v3-E.fm Page 146 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 147

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

3 3 066D 44 36.4 55.7

3 5 06AA 44 31.5 73

4 3 086C 44 34.6 60.4

4 5 08A8 44 28.9 92.1

5 3 0A6B 44 33 66.1

6 3 0C6A 44 31.5 73

7 3 0E69 44 30.1 81.4

8 3 1068 44 28.9 92.1

1 3 026F 40 37 43.6

1 5 02AE 40 34.9 46.8

1 7 02ED 40 33.1 50.5

1 9 032C 40 31.5 54.8

1 11 036B 40 30 59.9

1 13 03AA 40 28.7 66.1

1 15 03E9 40 27.4 73.7

2 3 046E 40 34.9 46.8

2 5 04AC 40 31.5 54.8

2 7 04EA 40 28.7 66.1

2 9 0528 40 26.3 83.3

3 3 066D 40 33.1 50.5

3 5 06AA 40 28.7 66.1

3 7 06E7 40 25.3 95.8

4 3 086C 40 31.5 54.8

4 5 08A8 40 26.3 83.3

5 3 0A6B 40 30 59.9

6 3 0C6A 40 28.7 66.1

7 3 0E69 40 27.4 73.7

8 3 1068 40 26.3 83.3

9 3 1267 40 25.3 95.8

1 3 026F 36 33.3 39.2

1 5 02AE 36 31.5 42

1 7 02ED 36 29.9 45.3

1 9 032C 36 28.4 49.2

1 11 036B 36 27.1 53.8

1 13 03AA 36 25.8 59.3

MB91460E-DS705-00002-1v3-E.fm Page 147 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

148 DS705-00002-1v3-E

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

1 15 03E9 36 24.7 66.1

2 3 046E 36 31.5 42

2 5 04AC 36 28.4 49.2

2 7 04EA 36 25.8 59.3

2 9 0528 36 23.7 74.7

3 3 066D 36 29.9 45.3

3 5 06AA 36 25.8 59.3

3 7 06E7 36 22.8 85.8

4 3 086C 36 28.4 49.2

4 5 08A8 36 23.7 74.7

5 3 0A6B 36 27.1 53.8

6 3 0C6A 36 25.8 59.3

7 3 0E69 36 24.7 66.1

8 3 1068 36 23.7 74.7

9 3 1267 36 22.8 85.8

1 3 026F 32 29.7 34.7

1 5 02AE 32 28 37.3

1 7 02ED 32 26.6 40.2

1 9 032C 32 25.3 43.6

1 11 036B 32 24.1 47.7

1 13 03AA 32 23 52.5

1 15 03E9 32 22 58.6

2 3 046E 32 28 37.3

2 5 04AC 32 25.3 43.6

2 7 04EA 32 23 52.5

2 9 0528 32 21.1 66.1

2 11 0566 32 19.5 89.1

3 3 066D 32 26.6 40.2

3 5 06AA 32 23 52.5

3 7 06E7 32 20.3 75.9

4 3 086C 32 25.3 43.6

4 5 08A8 32 21.1 66.1

5 3 0A6B 32 24.1 47.7

5 5 0AA6 32 19.5 89.1

6 3 0C6A 32 23 52.5

MB91460E-DS705-00002-1v3-E.fm Page 148 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 149

(Continued)

Modulation Degree

(k)

Random No

(N)

CMPR

[hex]

Baseclk

[MHz]

Fmin

[MHz]

Fmax

[MHz] Remarks

7 3 0E69 32 22 58.6

8 3 1068 32 21.1 66.1

9 3 1267 32 20.3 75.9

10 3 1466 32 19.5 89.1

MB91460E-DS705-00002-1v3-E.fm Page 149 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

150 DS705-00002-1v3-E

■ELECTRICAL CHARACTERISTICS

1. Absolute maximum ratings

Parameter Symbol Rating Unit Remarks

Min Max

Power supply slew rate ⎯⎯ 50 V/ms

Power supply voltage 1*1VDD5R − 0.3 + 6.0 V

Power supply voltage 2*1VDD5− 0.3 + 6.0 V

Power supply voltage 3*1HVDD5− 0.3 + 6.0 V

Power supply voltage 4*1VDD35 − 0.3 + 6.0 V

Relationship of the supply volt-

ages

HVDD5

VDD5-0.3 VDD5+0.3 V SMC mode

VSS5-0.3 VDD5+0.3 V General purpose port

mode

AVCC5

VDD5-0.3 VDD5+0.3 V

At least one pin of the

Ports 25 to 29 (SMC,

ANn) is used as digital

input or output.

VSS5-0.3 VDD5+0.3 V

All pins of the Ports 25 to

29 (SMC, ANn) follow the

condition of VIA

Analog power supply voltage*1AVCC5− 0.3 + 6.0 V *2

Analog reference

power supply voltage*1AVRH5 − 0.3 + 6.0 V *2

Input voltage 1*1VI1 Vss5 − 0.3 VDD5+ 0.3 V

Input voltage 2*1VI2 Vss5 − 0.3 VDD35 + 0.3 V External bus

Input voltage 3*1VI3 HVss5 − 0.3 HVDD5+ 0.3 V Stepper motor controller

Analog pin input voltage*1VIA AVss5 − 0.3 AVcc5 + 0.3 V

Output voltage 1*1VO1 Vss5 − 0.3 VDD5+ 0.3 V

Output voltage 2*1VO2 Vss5 − 0.3 VDD35 + 0.3 V External bus

Output voltage 3*1VO3 HVss5 − 0.3 HVDD5+ 0.3 V Stepper motor controller

Maximum clamp current ICLAMP − 4.0 + 4.0 mA *3

Total maximum clamp current Σ |ICLAMP|⎯ 20 mA *3

“L” level maximum

output current*4IOL

⎯10 mA

⎯40 mA Stepper motor controller

“L” level average

output current*5IOLAV

⎯8mA

⎯30 mA Stepper motor controller

“L” level total maximum

output current ΣIOL

⎯100 mA

⎯360 mA Stepper motor controller

“L” level total average

output current*6ΣIOLAV

⎯50 mA

⎯230 mA Stepper motor controller

“H” level maximum

output current*4IOH

⎯− 10 mA

⎯− 40 mA Stepper motor controller

MB91460E-DS705-00002-1v3-E.fm Page 150 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 151

*1 : The parameter is based on VSS5= HVSS5= AVSS5= 0.0 V.

*2 : AVCC5 and AVRH5 must not exceed VDD5+ 0.3 V.

*3 : •Use within recommended operating conditions.

•Use with DC voltage (current).

•+B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by

connecting a limiting resistor between the +B signal and the microcontroller.

•The value of the limiting resistor should be set so that the current input to the microcontroller pin does not

exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal

is input.

•Note that when the microcontroller drive current is low, such as in the low power consumption modes, the

+B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting

other devices.

•Note that if the +B signal is input when the microcontroller is off (not ﬁxed at 0 V), power is supplied through

the +B input pin; therefore, the microcontroller may partially operate.

•Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset

may not function in the power supply voltage.

“H” level average

output current*5IOHAV

⎯− 4mA

⎯− 30 mA Stepper motor controller

“H” level total maximum

output current ΣIOH

⎯− 100 mA

⎯− 360 mA Stepper motor controller

“H” level total average output

current*6ΣIOHAV

⎯− 25 mA

⎯− 230 mA Stepper motor controller

Permitted power dissipation *7 PD

⎯1100 *8 mW at TA≤ 85 °C

⎯1100 *8 mW at TA≤ 105 °C, no Flash

program/erase *9

⎯555 *8 mW at TA≤ 105 °C

Operating temperature TA− 40 + 105 °C

Storage temperature Tstg − 55 + 150 °C

Parameter Symbol Rating Unit Remarks

Min Max

MB91460E-DS705-00002-1v3-E.fm Page 151 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

152 DS705-00002-1v3-E

•Do not leave +B input pins open.

•Example of recommended circuit :

*4 : Maximum output current is deﬁned as the value of the peak current ﬂowing through any one of the corresponding

pins.

*5 : Average output current is deﬁned as the value of the average current ﬂowing through any one of the

corresponding pins for a 100 ms period.

*6 : Total average output current is deﬁned as the value of the average current ﬂowing through all of the

corresponding pins for a 100 ms period.

*7 : The maximum permitted power dissipation depends on the ambient temperature, the air ﬂow velocity and the

thermal conductance of the package on the PCB.

The actual power dissipation depends on the customer application and can be calculated as follows:

PD = PIO + PINT

PIO = Σ(|VSS-VOL| * IOL + |VDD-VOH| * IOH) (IO load power dissipation, sum is performed on all IO ports)

PINT = VDD5R * ICC + AVCC5 * IA + AVRH5 * IR (internal power dissipation)

*8 : Worst case value for the QFP package mounted on a 4-layer PCB at speciﬁed TA without air ﬂow.

*9 : Please contact Fujitsu for reliability limitations when using under these conditions.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

P-ch

N-ch

VCC

• Input/output equivalent circuit

+B input (0 V to 16 V)

Limiting

resistor

Protective diode

MB91460E-DS705-00002-1v3-E.fm Page 152 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

DS705-00002-1v3-E 153

2. Recommended operating conditions

(VSS5= AVSS5= 0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage

VDD5 3.0 ⎯5.5 V

VDD5R 3.0 ⎯5.5 V Internal regulator

VDD35 3.0 ⎯5.5 V External bus

HVDD5

4.5 ⎯5.5 V Stepper motor controller

3.0 ⎯5.5 V

Stepper motor controller

(when all pins are used as gen-

eral-purpose ports)

AVCC5 3.0 ⎯5.5 V A/D converter

Smoothing capacitor at

VCC18C pin CS⎯4.7 ⎯µF

Use a X7R ceramic capacitor or

a capacitor that has similar fre-

quency characteristics.

Power supply slew rate ⎯⎯50 V/ms

Operating temperature TA− 40 ⎯+ 105 °C

Stepper motor control

slew rate 40 ns Cload = 0 pF

Main Oscillation

stabilisation time 10 ms

Lock-up time PLL

(4 MHz ->16 ...100MHz) 0.6 ms

ESD Protection

(Human body model) Vsurge 2kV

Rdischarge = 1.5kΩ

Cdischarge = 100pF

RC Oscillator fRC100kHz 50 100 200 kHz VDDCORE ≥1.65V

fRC2MHz 1 2 4 MHz

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154 DS705-00002-1v3-E

AVSS5

VSS5

VCC18C

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MB91460E Series

DS705-00002-1v3-E 155

3. DC characteristics

Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or HVDD5 for SMC pins or VDD5 for other pins.

In the following tables, “VSS” means Hvss5 for ground Pins of the stepper motor and VSS5 for the other pins.

(VDD5=AVCC5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Condition Value Unit Remarks

Min Typ Max

Input “H”

voltage

VIH

⎯

Port inputs if CMOS

Hysteresis 0.8/0.2

input is selected

0.8 × VDD ⎯VDD + 0.3 V

CMOS

hysteresis

input

⎯

Port inputs if CMOS

Hysteresis 0.7/0.3

input is selected

0.7 × VDD ⎯VDD + 0.3 V 4.5 V ≤VDD ≤5.5 V

0.74 ×VDD ⎯VDD + 0.3 V 3 V ≤ VDD < 4.5 V

⎯

AUTOMOTIVE

Hysteresis input is

selected

0.8 × VDD ⎯VDD + 0.3 V

⎯Port inputs if TTL

input is selected 2.0 ⎯VDD + 0.3 V

VIHR INITX ⎯0.8 × VDD ⎯VDD + 0.3 V

INITX input pin

(CMOS

Hysteresis)

VIHM MD_2 to

MD_0 ⎯VDD − 0.3 ⎯VDD + 0.3 V Mode input pins

VIHX0S X0, X0A ⎯2.5 ⎯VDD + 0.3 V External clock in

“Oscillation mode”

VIHX0F X0 ⎯0.8 × VDD ⎯VDD + 0.3 V

External clock in

“Fast Clock Input

mode”

Input “L”

voltage

VIL

⎯

Port inputs if CMOS

Hysteresis 0.8/0.2

input is selected

VSS − 0.3 ⎯0.2 × VDD V

⎯

Port inputs if CMOS

Hysteresis 0.7/0.3

input is selected

VSS − 0.3 ⎯0.3 × VDD V

⎯

Port inputs if

AUTOMOTIVE

Hysteresis input is

selected

VSS − 0.3 ⎯0.5 × VDD V 4.5 V ≤VDD ≤5.5 V

VSS − 0.3 ⎯0.46 ×VDD V3 V≤ VDD < 4.5 V

⎯Port inputs if TTL

input is selected VSS − 0.3 ⎯0.8 V

VILR INITX ⎯VSS − 0.3 ⎯0.2 × VDD V

INITX input pin

(CMOS

Hysteresis)

VILM MD_2 to

MD_0 ⎯VSS − 0.3 ⎯VSS + 0.3 V Mode input pins

VILXDS X0, X0A ⎯VSS − 0.3 ⎯0.5 V External clock in

“Oscillation mode”

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MB91460E Series

156 DS705-00002-1v3-E

(VDD5=AVCC5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin

name Condition Value Unit Remarks

Min Typ Max

Input “L”

voltage VILXDF X0 ⎯VSS − 0.3 ⎯0.2 ×VDD V

External clock in

“Fast Clock Input

mode”

Output “H”

voltage

VOH2 Normal

outputs

4.5V VDD 5.5V,

IOH =− 2mA VDD − 0.5 ⎯⎯VDriving strength

set to 2 mA

3.0V VDD 4.5V,

IOH =− 1.6mA

VOH5 Normal

outputs

4.5V VDD 5.5V,

IOH =− 5mA VDD − 0.5 ⎯⎯VDriving strength

set to 5 mA

3.0V VDD 4.5V,

IOH =− 3mA

VOH3 I2C

outputs

3.0V VDD 5.5V,

IOH =− 3mA VDD − 0.5 ⎯⎯V

VOH30

High

current

outputs

4.5V VDD 5.5V,

TA = -40 °C,

IOH = -40mA

VDD − 0.5 V Driving strength

set to 30mA

4.5V VDD 5.5V,

IOH = -30mA

3.0V VDD 4.5V,

IOH = -20mA

Output “L“

voltage

VOL2 Normal

outputs

4.5V VDD 5.5V,

IOL =+ 2mA ⎯⎯0.4 V Driving strength

set to 2 mA

3.0V VDD 4.5V,

IOL =+ 1.6mA

VOL5 Normal

outputs

4.5V VDD 5.5V,

IOL =+ 5mA ⎯⎯0.4 V Driving strength

set to 5 mA

3.0V VDD 4.5V,

IOL =+ 3mA

VOL3 I2C

outputs

3.0V VDD 5.5V,

IOL =+ 3mA ⎯⎯0.4 V

VOL30

High

current

outputs

4.5V VDD 5.5V,

TA = -40 °C,

IOL = +40mA

0.5 V Driving strength

set to 30mA

4.5V VDD 5.5V,

IOL = +30mA

3.0V VDD 4.5V,

IOL = +20mA

Input leak-

age current IIL Pnn_m

3.0V VDD 5.5V

VSS5 < VI < VDD

TA=25 °C

− 1 ⎯+ 1

µA

3.0V VDD 5.5V

VSS5 < VI < VDD

TA=105 °C

− 3 ⎯+ 3

≤≤

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MB91460E Series

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(Continued)

Analog in-

put leak-

age current

IAIN ANn *2

3.0V VDD 5.5V

TA=25 °C− 1 ⎯+ 1 µA

3.0V VDD 5.5V

TA=105 °C− 3 ⎯+ 3 µA

Sum input

leakage

current

ΣIL

Pnn_m

*3,

ALARM

VDD5≥ VIN ≥ VSS5,

AVCC5≥VIN ≥AVSS5

Σ(1 to n)

[max(|ILHi|,

|ILLi|)]

−830µA

n = number of IO

= 65 GPIO + 1

ALARM

ILH: leakage at

high level input;

ILL: leakage at

low level input

Pull-up

resistance RUP

Pnn_m

INITX

3.0V VDD 3.6V 40 100 160

kΩ

4.5V VDD 5.5V 25 50 100

Pull-down

resistance RDOWN Pnn_m

3.0V VDD 3.6V 40 100 180 kΩ

4.5V VDD 5.5V 25 50 100

Input

capaci-

tance

CIN

All ex-

cept

VDD5,

VDD5R,

VSS5,

AVCC5,

AVSS,

AVRH5

f= 1 MHz - 5 15 pF

1. Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.

2. ANn includes all pins where AN channels are enabled.

3. Pnn_m includes all GPIO pins beside the external bus pins (P00 to P13) and Stepper Motor pins (P25,

P26, P27). Analog (AN) channels and PullUp/PullDown are disabled.

4. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and

the pins must be in input direction.

5. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and

the pins must be in input direction.

Parameter Symbol Pin

name Condition Value Unit Remarks

Min Typ Max

≤≤

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MB91460E Series

158 DS705-00002-1v3-E

(Continued)

(VDD5=AVCC5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Condition Value Unit Remarks

Min Typ Max

Power

supply

current

MB91

F467EA

ICC VDD5R

MB91F467EA:

CLKB: 100 MHz

CLKP: 50 MHz

CLKT: 50 MHz

CLKCAN: 50 MHz

⎯110 140 mA Code fetch from

Flash

ICCH VDD5R *1

1. Current on regulator supply pin VDD5R does not include IOSC and ICC of the I/O ring.

TA=+ 25 °C⎯10 30 µA ShutDown mode

with RTC running

on 32 kHz Sub

clock *2

2. ShutDown mode with standby RAM enabled, sub regulator set to 1.2V, Low voltage detection disabled.

Same current consumption if RTC and Sub oscillator are disabled.

TA=+ 85 °C⎯80 150 µA

TA=+ 105 °C⎯160 300 µA

TA=+ 25 °C⎯15 35 µA ShutDown mode

with RTC running

on 100 kHz RC

clock *3

3. ShutDown mode with standby RAM enabled, sub regulator set to 1.2V, Low voltage detection disabled,

RC oscillator enabled 100 kHz.

TA=+ 85 °C⎯85 160 µA

TA=+ 105 °C⎯170 320 µA

TA=+ 25 °C⎯30 100 µA

At STOP mode *4

4. STOP mode, sub regulator set to 1.2V, Low voltage detection disabled, RC oscillator disabled.

TA=+ 85 °C⎯450 1000 µA

TA=+ 105 °C⎯1000 2200 µA

TA=+ 25 °C⎯140 300 µA

RTC :

4 MHz mode *5

5. STOP mode, sub regulator set to 1.2V, Low voltage detection disabled, RC oscillator disabled,

Main oscillator enabled.

TA=+ 85 °C⎯500 1200 µA

TA=+ 105 °C⎯1000 2400 µA

TA=+ 25 °C⎯120 200 µA

RTC :

100 kHz mode *6

6. STOP mode, sub regulator set to 1.2V, Low voltage detection disabled, RC oscillator enabled 100 kHz.

TA=+ 85 °C⎯500 1100 µA

TA=+ 105 °C⎯1000 2300 µA

ILVE VDD5⎯⎯70 150 µAExternal low volt-

age detection

ILVI VDD5R ⎯⎯50 100 µAInternal low volt-

age detection

IOSC VDD5

⎯⎯250 500 µAMain clock

(4 MHz)

⎯⎯20 40 µASub clock

(32 kHz)

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MB91460E Series

DS705-00002-1v3-E 159

4. A/D converter characteristics

(VDD5=AVCC5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

(Continued)

Note : The accuracy gets worse as AVRH - AVRL becomes smaller

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Resolution ⎯⎯ ⎯ ⎯ 10 bit

Total error ⎯⎯ − 3 ⎯+ 3 LSB

Nonlinearity error ⎯⎯− 2.5 ⎯+ 2.5 LSB

Differential nonlinearity

error ⎯⎯− 1.9 ⎯+ 1.9 LSB

Zero reading voltage VOT ANn AVRL −

1.5 LSB

AVRL +

0.5 LSB

AVRL +

2.5 LSB V

Full scale reading voltage VFST ANn AVRH −

3.5 LSB

AVRH −

1.5 LSB

AVRH +

0.5 LSB V

Compare time Tcomp ⎯

0.6 ⎯t.b.d. 1

1. Paramater is under re-evaluation.

µs4.5 V ≤AVCC5≤

5.5 V

2.0 ⎯t.b.d. 1µs3.0 V ≤AVCC5≤

4.5 V

Sampling time Tsamp ⎯

0.4 ⎯⎯µs

4.5 V ≤AVCC5≤

5.5 V,

REXT < 2 kΩ

1.0 ⎯⎯µs

3.0 V ≤AVCC5≤

4.5 V,

REXT < 1 kΩ

Conversion time Tconv ⎯

1.0 ⎯⎯µs4.5 V ≤AVCC5≤

5.5 V

3.0 ⎯⎯µs3.0 V ≤AVCC5≤

4.5 V

Input capacitance CIN ANn ⎯⎯11 pF

Input resistance RIN ANn

⎯⎯2.6 kΩ4.5 V ≤AVCC5≤

5.5 V

⎯⎯12.1 kΩ3.0 V ≤AVCC5≤

4.5 V

Analog input leakage

current IAIN ANn − 1 ⎯+ 1 µATA=+ 25 °C

− 3 ⎯+ 3 µATA=+ 105 °C

Analog input voltage range VAIN ANn AVRL ⎯AVRH V

Offset between input chan-

nels ⎯ANn ⎯⎯ 4 LSB

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160 DS705-00002-1v3-E

(Continued)

*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating,

(VDD5 = AVCC5 = AVRH = 5.0 V)

*2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)

Sampling Time Calculation

Tsamp = ( 2.6 kOhm + REXT)× 11pF × 7; for 4.5V ≤ AVCC5≤ 5.5V

Tsamp = (12.1 kOhm + REXT)× 11pF × 7; for 3.0V ≤ AVCC5≤ 4.5V

Conversion Time Calculation

Tconv = Tsamp + Tcomp

Deﬁnition of A/D converter terms

• Resolution

Analog variation that is recognizable by the A/D converter.

• Nonlinearity error

Deviation between actual conversion characteristics and a straight line connecting the zero transition point

(00 0000 0000B↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B↔ 11 1111 1111B).

• Differential nonlinearity error

Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.

• Total error

This error indicates the difference between actual and theoretical values, including the zero transition error,

full scale transition error, and nonlinearity error.

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Reference voltage range

AVRH AVRH5 0.75 ×

AVCC5⎯AVCC5V

AVRL AVSS5AVSS5⎯AVCC5×

0.25 V

Power supply current

IAAVCC5⎯2.5 5 mA A/D Converter

active

IAH AVCC5⎯⎯ 5µAA/D Converter

not operated *1

Reference voltage current

IRAVRH5 ⎯0.7 1 mA A/D Converter

active

IRH AVRH5 ⎯⎯ 5µAA/D Converter

not operated *2

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(Continued)

3FFH

3FEH

3FDH

004H

003H

002H

001H

AVSS5AVRH

0.5 LSB'

{1 LSB’ (N − 1) + 0.5 LSB’}

1.5 LSB’

Analog input

Total error

Digital output

Actual conversion

characteristics

VNT

(

measurement value)

Ideal characteristics

Actual conversion

characteristics

Total error of digital output N =1 LSB'

VNT − {1 LSB' × (N − 1) + 0.5 LSB'}

N : A/D converter digital output value

VOT' (ideal value) = AVSS5+ 0.5 LSB' [V]

VFST' (ideal value) = AVRH − 1.5 LSB' [V]

VNT : Voltage at which the digital output changes from (N + 1) H to NH

1LSB' (ideal value) =1024

AVRH − AVSS5[V]

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162 DS705-00002-1v3-E

(Continued)

(N+1)H

(N-1)H

(N-2)H

AVSS5 AVRH

3FFH

3FEH

3FDH

004H

003H

002H

001H

AVSS5 AVRH

{1 LSB (N - 1) + VOT}

Analog inputAnalog input

Differential nonlinearity errorNonlinearity error

Digital output

Actual conversion characteristics

VFST

(measure-

ment value)

VNT

(measure-

ment value)

Actual conversion

characteristics

Ideal characteristics

VTO (measurement value)

Actual conversion characteristics

VNT

(measure-

ment value)

VFST

(measure-

ment value)

Nonlinearity error of digital output N =1LSB

VNT − {1LSB × (N − 1) + VOT}[LSB]

Differential nonlinearity error of digital output N =1LSB

V (N+1)T− VNT − 1 [LSB]

1LSB =1022

VFST − VOT [V]

N : A/D converter digital output value

VOT : Voltage at which the digital output changes from 000H to 001H.

VFST : Voltage at which the digital output changes from 3FEH to 3FFH.

Actual conversion

characteristics

Ideal

characteristics

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MB91460E Series

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5. Alarm comparator characteristics

Note: *1 : The fast Alarm Comparator mode is enabled by setting ACSR.MD=1

Setting ACSR.MD=0 sets the normal mode.

Parameter Symbol Pin name Value Unit Remarks

Min Typ Max

Power supply

current

IA5ALMF

AVCC5

⎯25 40 µA

Alarm compar-

ator enabled in

fast mode (per

channel) *1

IA5ALMS ⎯710µA

Alarm compar-

ator enabled in

normal mode

(per channel)

IA5ALMH ⎯⎯ 5µAAlarm compar-

ator disabled

ALARM pin in-

put current IALIN

ALARM_n

− 1 ⎯+ 1 µATA=25 °C

− 3 ⎯+ 3 µATA=105 °C

ALARM pin in-

put voltage

range

VALIN 0⎯AVCC5V

Alarm upper

limit

voltage

VIAH AVCC5× 0.78

− 3%AVCC5× 0.78 AVCC5× 0.78

+ 3%V

Alarm lower

limit

voltage

VIAL AVCC5× 0.36

− 5%AVCC5× 0.36 AVCC5× 0.36

+ 5%V

Alarm hystere-

sis

voltage

VIAHYS 50 ⎯250 mV

Alarm input

resistance RIN 5⎯⎯MΩ

Comparion

time

tCOMPF ⎯0.1 0.2 µs

Alarm compar-

ator enabled in

fast mode *1

tCOMPS ⎯12µs

Alarm compar-

ator enabled in

normal mode

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6. FLASH memory program/erase characteristics

6.1. MB91F467EA

(TA= 25oC,Vcc = 5.0V)

*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius

equation to convert high temperature measurements into normalized value at 85oC)

Parameter Value Unit Remarks

Min Typ Max

Sector erase time - 0.5 2.0 s Erasure programming time not

included

Chip erase time - n*0.5 n*2.0 s n is the number of Flash sector

of the device

Word (16 or 32-bit width)

programming time - 6 100 µsSystem overhead time not in-

cluded

Programme/Erase cycle 10 000 cycle

Flash data retention time 20 year *1

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7. AC characteristics

7.1. Clock timing

(VDD5=3.0 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

• Clock timing condition

Parameter Symbol Pin name Value Unit Condition

Min Typ Max

Clock frequency fC

3.5 4 16 MHz Opposite phase external

supply or crystal

3.5 4 8 MHz Opposite phase external

supply or ceramic resonator

X0A

X1A 32 32.768 100 kHz

0.8 VCC

0.2 VCC

PWH PWL

X0,

X1,

X0A,

X1A

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7.2. Reset input ratings

(VDD5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Condition Value Unit

Min Max

INITX input time

(at power-on) tINTL INITX ⎯

10 ⎯ms

INITX input time

(other than the above) 20 ⎯µs

0.2 VCC

tINTL

INITX

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7.3. LIN-USART Timings at VDD5 = 3.0 to 5.5 V

• Conditions during AC measurements

• All AC tests were measured under the following conditions:

• - IOdrive = 5 mA

• - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA

• - VSS5 = 0 V

• - Ta = -40 °C to +105 °C

• - Cl = 50 pF (load capacity value of pins when testing)

• - VOL = 0.2 x VDD5

• - VOH = 0.8 x VDD5

• - EPILR = 0, PILR = 1 (Automotive Level = worst case)

(VDD5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

* : Parameter m depends on tSCYCI and can be calculated as :

• if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2

• if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1

Notes : • The above values are AC characteristics for CLK synchronous mode.

• tCLKP is the cycle time of the peripheral clock.

Parameter Symbol Pin name Condition VDD5= 3.0 V to 4.5 V VDD5= 4.5 V to 5.5 V Unit

Min Max Min Max

Serial clock

cycle time tSCYCI SCKn

Internal

clock

operation

(master

mode)

4 tCLKP ⎯4 tCLKP ⎯ns

SCK ↓→ SOT

delay time tSLOVI SCKn

SOTn − 30 30 − 20 20 ns

SOT → SCK ↓

delay time tOVSHI SCKn

SOTn

m×

tCLKP − 30* ⎯m×

tCLKP −20* ⎯ns

Valid SIN →

SCK ↑ setup time tIVSHI SCKn

SINn tCLKP + 55 ⎯tCLKP + 45 ⎯ns

SCK ↑→valid

SIN hold time tSHIXI SCKn

SINn 0⎯0⎯ns

Serial clock

“H” pulse width tSHSLE SCKn

External

clock

operation

(slave

mode)

tCLKP + 10 ⎯tCLKP + 10 ⎯ns

Serial clock

“L” pulse width tSLSHE SCKn tCLKP + 10 ⎯tCLKP + 10 ⎯ns

SCK ↓→SOT

delay time tSLOVE SCKn

SOTn ⎯2tCLKP +55 ⎯2 tCLKP + 45 ns

Valid SIN →

SCK ↑ setup time tIVSHE SCKn

SINn 10 ⎯10 ⎯ns

SCK ↑→valid

SIN hold time tSHIXE SCKn

SINn tCLKP + 10 ⎯tCLKP + 10 ⎯ns

SCK rising time tFE SCKn ⎯20 ⎯20 ns

SCK falling time tRE SCKn ⎯20 ⎯20 ns

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MB91460E Series

168 DS705-00002-1v3-E

• Internal clock mode (master mode)

• External clock mode (slave mode)

tIVSHI

VIH

tSHIXI

tSLOVI

tSCYCI

VOL

SOTn

SCKn

for ESCR:SCES = 0

SCKn

for ESCR:SCES = 1

tOVSHI

VOL

VIL

VOL

VIL

VIH

VOH

VOH VOH

SINn

tIVSHE

VIH

tSHIXE

tSLOVE

tSLSHE

VOL

SOTn

SCKn

for ESCR:SCES = 0

SCKn

for ESCR:SCES = 1

VOL

VIL

VOL

VIL

VIH

VOH

VOL VOH

VOH

SINn

tSHSLE

VOL

tRE

VOH

tFE

VOL

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7.4. I2C AC Timings at VDD5 = 3.0 to 5.5 V

• Conditions during AC measurements

All AC tests were measured under the following conditions:

-IOdrive = 3 mA

-VDD5= 3.0 V to 5.5 V, Iload = 3 mA

-VSS5= 0 V

-Ta=− 40 °C to + 105 °C

-Cl= 50 pF

- VOL = 0.3 × VDD5

- VOH = 0.7 × VDD5

- EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)

Fast mode:

(VDD5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Note: tCLKP is the cycle time of the peripheral clock.

Parameter Symbol Pin name Value Unit Remark

Min Max

SCL clock frequency fSCL SCLn 0 400 kHz

Hold time (repeated) START

condition. After this period, the first

clock pulse is generated

tHD;STA SCLn, SDAn 0.6 ⎯µs

LOW period of the SCL clock tLOW SCLn 1.3 ⎯µs

HIGH period of the SCL clock tHIGH SCLn 0.6 ⎯µs

Setup time for a repeated START

condition tSU;STA SCLn, SDAn 0.6 ⎯µs

Data hold time for I2C-bus devices tHD;DAT SCLn, SDAn 0 0.9 µs

Data setup time tSU;DAT SCLn SDAn 100 ⎯ns

Rise time of both SDA and SCL

signals trSCLn, SDAn 20 + 0.1Cb 300 ns

Fall time of both SDA and SCL

signals tfSCLn, SDAn 20 + 0.1Cb 300 ns

Setup time for STOP condition tSU;STO SCLn, SDAn 0.6 ⎯µs

Bus free time between a STOP

and START condition tBUF SCLn, SDAn 1.3 ⎯µs

Capacitive load for each bus line CbSCLn, SDAn ⎯400 pF

Pulse width of spike suppressed

by input filter tSP SCLn, SDAn 0 (1..1.5) ×

tCLKP ns *1

1. The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of

peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral

clock

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SDA

SSr PS

SCL

tHD;STA

tSP tSU;STO

tSU;STA

tSU;DAT

tHD;DAT

tHD;STA

tLOW tHIGH

tBUF

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7.5. Free-run timer clock

(VDD5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Note : tCLKP is the cycle time of the peripheral clock.

7.6. Trigger input timing

(VDD5=3.0 V to 5.5 V, VSS5=AVSS5=0V,TA=−40 °Cto +105 °C)

Note : tCLKP is the cycle time of the peripheral clock.

Parameter Symbol Pin name Condition Value Unit

Min Max

Input pulse width tTIWH

tTIWL CKn ⎯4tCLKP ⎯ns

Parameter Symbol Pin name Condition Value Unit

Min Max

Input capture input trigger tINP ICUn ⎯5tCLKP ⎯ns

A/D converter trigger tATGX ATGX ⎯5tCLKP ⎯ns

tTIWH tTIWL

CKn

ICUn,

ATGX

tATGX, tINP

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7.7. External Bus AC Timings at VDD35 = 4.5 to 5.5 V

• Conditions during AC measurements

All AC tests were measured under the following conditions:

-IOdrive = 5 mA

-VDD35 = 4.5 V to 5.5 V, Iload = 5 mA

-VSS5= 0 V

-Ta=− 40 °C to + 105 °C

-Cl= 50 pF

- VOL = 0.5 × VDD35

- VOH = 0.5 × VDD35

- EPILR = 0, PILR = 1 (Automotive Level = worst case)

7.7.1. Basic Timing

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : tCLKT is the cycle time of the external bus clock.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO tCLCH MCLKO 1/2 x tCLKT − 2 1/2 × tCLKT + 2ns

tCHCL 1/2 × tCLKT − 2 1/2 × tCLKT + 2ns

MCLKO ↓ to CSXn delay time tCLCSL

MCLKO

CSXn

⎯7ns

tCLCSH ⎯7ns

MCLKO ↑ to CSXn delay time

(Addr → CS delay) tCHCSL − 1 + 6ns

MCLKO ↓ to ASX delay time tCLASL MCLKO

ASX

⎯7ns

tCLASH ⎯7ns

MCLKO ↓ to BAAX delay time tCLBAL MCLKO

BAAX

⎯7ns

tCLBAH 2⎯ns

MCLKO ↓ to Address valid delay time tCLAV MCLKO

A25 to A0 ⎯8ns

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MCLKO

CSXn

delayed CSXn

ASX

ADDRESS

BAAX

tCHCSL

tCLASL

tCLAV

tCLBAL

tCLASH

tCLCSL

tCLCH tCHCL tCYC

tCLCSH

tCLBAH

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7.7.2. Synchronous/Asynchronous read access with external MCLKI input

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note: The usage of the external feedback from MCLKO to MCLKI is not recommended.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↑ /MCLKI ↑ to RDX delay

time

tCHRL MCLKO

RDX − 1 6 ns

tCHRH MCLKI

RDX 816ns

Data valid to RDX ↑ setup time tDSRH RDX

D31 to D0 19 ⎯ns

RDX ↑ to Data valid hold time

(external MCLKI input) tRHDX RDX

D31 to D0 0⎯ns

Data valid to MCLKI ↑ setup time tDSCH MCLKI

D31 to D0 3⎯ns

MCLKI ↑ to Data valid hold time tCHDX MCLKI

D31 to D0 1⎯ns

MCLKO ↓to WRXn (as byte enable)

delay time

tCLWRL MCLKO

WRXn

⎯9ns

tCLWRH − 1 ⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯7ns

tCLCSH ⎯7ns

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MCLKO

MCLKI

CSXn

WRXn

(as byte enable)

RDX

DATA IN

tCLCSL

tCLWRL

tCHRL

tCHRH

tDSRH tRHDX

tCHDXtDSCH

tCLWRH

tCLCSH

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7.7.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↑ to RDX delay time tCHRL MCLKO RDX − 1 6 ns

tCHRH − 1 7 ns

Data valid to RDX ↑ setup time tDSRH RDX

D31 to D0 16 ⎯ns

RDX ↑ to Data valid hold time

(internal MCLKO → MCLKI /

/MCLKI feedback)

tRHDX RDX

D31 to D0 0⎯ns

MCLKO ↓ to WRXn

(as byte enable) delay time

tCLWRL MCLKO

WRXn

⎯9ns

tCLWRH − 1 ⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯7ns

tCLCSH ⎯7ns

MCLKO

CSXn

WRXn

(as byte enable)

RDX

DATA IN

tDSRH tRHDX

tCHRH

tCHRL

tCLWRL tCLWRH

tCLCSH

tCLCSL

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7.7.4. Synchronous write access - byte control type

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to WEX delay time tCLWL MCLKO

WEX

⎯7ns

tCLWH 2⎯ns

Data valid to WEX ↓ setup time tDSWL WEX

D31 to D0 − 4 ⎯ns

WEX ↑ to Data valid hold time tWHDH WEX

D31 to D0 tCLKT − 5 ⎯ns

MCLKO ↓ to WRXn (as byte enable)

delay time

tCLWRL MCLKO

WRXn

⎯9ns

tCLWRH − 1 ⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯7ns

tCLCSH ⎯7ns

MCLKO

CSXn

WRXn

(as byte enable)

WEX

DATA OUT

tCLWH

tCLWL

tCLWRL

tDSWL tWHDH

tCLWRH

tCLCSH

tCLCSL

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7.7.5. Synchronous write access - no byte control type

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to WRXn delay time tCLWRL MCLKO

WRXn

⎯9ns

tCLWRH − 1 ⎯ns

Data valid to WRXn ↓ setup time tDSWRL WRXn

D31 to D0 − 6 ⎯ns

WRXn ↑ to Data valid hold time tWRHDH WRXn

D31 to D0 tCLKT − 6 ⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯7ns

tCLCSH ⎯7ns

MCLKO

CSXn

WRXn

DATA OUT

tCLWRH

tCLWRL

tDSWRL tWRHDH

tCLCSH

tCLCSL

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7.7.6. Asynchronous write access - byte control type

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

WEX ↓ to WEX ↑ pulse width tWLWH WEX tCLKT − 2 ⎯ns

Data valid to WEX ↓ setup time tDSWL WEX

D31 to D0 1/2 ×tCLKT −16 ⎯ns

WEX ↑ to Data valid hold time tWHDH WEX

D31 to D0 1/2 × tCLKT − 6 ⎯ns

WEX to WRXn delay time tWRLWL WEX

WRXn

⎯1/2 × tCLKT + 2ns

tWHWRH 1/2 × tCLKT − 1 ⎯ns

WEX to CSXn delay time tCLWL WEX

CSXn

⎯1/2 × tCLKT + 1ns

tWHCH 1/2 × tCLKT − 1 ⎯ns

CSXn

WRXn

(as byte enable)

WEX

DATA OUT

tWHDH

tWHWRH

tWHCH

tWRLWL

tWLWH

tCLWL

tDSWL

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7.7.7. Asynchronous write access - no byte control type

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

WRXn ↓ to WRXn ↑ pulse width tWRLWRH WRXn tCLKT − 1 ⎯ns

Data valid to WRXn ↓setup time tDSWRL WRXn

D31 to D0 1/2 × tCLKT − 6 ⎯ns

WRXn ↑ to Data valid hold time tWRHDH WRXn

D31 to D0 1/2 × tCLKT − 6 ⎯ns

WRXn to CSXn delay time tCLWRL WRXn

CSXn

⎯1/2 × tCLKT − 1ns

tWRHCH 1/2 × tCLKT − 2 ⎯ns

CSXn

WRXn

DATA OUT

tWRHDH

tWRHCH

tCLWRL

tWRLWRH

tDSWRL

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7.7.8. RDY waitcycle insertion

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

RDY setup time tRDYS MCLKO

RDY 12 ⎯ns

RDY hold time tRDYH MCLKO

RDY 0⎯ns

MCLKO

RDY

tRDYS tRDYH

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7.7.9. Bus hold timing

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX).

It must be kept High as long as the bus shall be hold.

After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.

Note : Condition for tAXBGL and tBGHAV :

-VOL= 0.2 × VDD35

-VOH= 0.8 × VDD35

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to BGRNTX delay time tCLBGL MCLKO

BGRNTX

⎯5ns

tCLBGH ⎯6ns

Bus HIZ to BGRNTX ↓tAXBGL BGRNTX

MCLK*

A0 to An

RDX, ASX

WRXn,WEX

CSXn,BAAX

tCLKT + 5 ⎯ns

BGRNTX ↑ to Bus drive tBGHAV tCLKT + 6 ⎯ns

tAXBGL

tBGHAV

ADDR, RDX, WRX,

WEX, CSXn, ASX,

MCLKE, MCLKI,

MCLKO, BAAX

tCLBGL

tCLBGH

BGRNTX

MCLKO

BRQ

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7.7.10. Clock relationships

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to MCLKE (in sleep mode) tCLML MCLKO

MCLKE

⎯7ns

tCLMH − 1 ⎯ns

MCLKO

MCLKE(sleep)

tCLML

tCLMH

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7.7.11. DMA transfer

(VDD35 =4.5 V to 5.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : DREQ and DEOTX must be applied for at least 5 ×tCLKT to ensure that they are really sampled and evaluated.

Under best case conditions (DMA not busy) only setup and hold times are required.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to DACKX delay time tCLDAL MCLKO

DACKXn

⎯7ns

tCLDAH ⎯7ns

MCLKO ↓ to DEOP delay time tCLDEL MCLKO

DEOPn

⎯9ns

tCLDEH ⎯9ns

MCLKO ↑ to DACKX delay time

(ADDR → delayed CS) tCHDAL MCLKO

DACKXn 16ns

MCLKO ↑ to DEOP delay time

(ADDR → delayed CS) tCHDEL MCLKO

DEOPn 18ns

DREQ setup time tDRQS MCLKO

DREQn 12 ⎯ns

DREQ hold time tDRQH MCLKO

DREQn 0⎯ns

DEOTXn setup time tDTXS MCLKO

DEOTXn 12 ⎯ns

DEOTXn hold time tDTXH MCLKO

DEOTXn 0⎯ns

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MCLKO

DACKX

DEOP

delayed DACKX

delayed DEOP

DREQ

DEOTX

tCLDAL tCLDAH

tCLDEH

tCLDEL

tCHDAL

tCHDEL

tDRQH

tDTXH

tDTXS

tDRQS

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7.8. External Bus AC Timings at VDD35 = 3.0 to 4.5 V

• Conditions during AC measurements

All AC tests were measured under the following conditions:

-IOdrive = 5 mA

-VDD35 = 3.0 V to 4.5 V, Iload = 3 mA

-VSS5= 0 V

-Ta=− 40 °C to + 105 °C

-Cl= 50 pF

- VOL = 0.5 × VDD35

- VOH = 0.5 × VDD35

- EPILR = 0, PILR = 1 (Automotive Level = worst case)

7.8.1. Basic Timing

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : tCLKT is the cycle time of the external bus clock.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO tCLCH MCLKO 1/2 × tCLKT − 2 1/2 × tCLKT + 4ns

tCHCL 1/2 × tCLKT − 4 1/2 × tCLKT + 2ns

MCLKO ↓ to CSXn delay time tCLCSL

MCLKO

CSXn

⎯6ns

tCLCSH ⎯8ns

MCLKO ↑ to CSXn delay time

(Addr → CS delay) tCHCSL − 1 + 5 ns

MCLKO ↓ to ASX delay time tCLASL MCLKO

ASX

⎯7ns

tCLASH ⎯9ns

MCLKO ↓ to BAAX delay time tCLBAL MCLKO

BAAX

⎯7ns

tCLBAH 2⎯ns

MCLKO ↓to Address valid delay time tCLAV MCLKO

A25 to A0 ⎯13 ns

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MCLKO

CSXn

delayed CSXn

ASX

ADDRESS

BAAX

tCHCSL

tCLASL

tCLAV

tCLBAL

tCLASH

tCLCSL

tCLCH tCHCL tCYC

tCLCSH

tCLBAH

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7.8.2. Synchronous/Asynchronous read access with external MCLKI input

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note: The usage of the external feedback from MCLKO to MCLKI is not recommended.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↑/MCLKI ↑to RDX

delay time

tCHRL MCLKO

RDX − 1 5 ns

tCHRH MCLKI

RDX 816ns

Data valid to RDX ↑ setup time tDSRH RDX

D31 to D0 19 ⎯ns

RDX ↑ to Data valid hold time

(external MCLKI input) tRHDX RDX

D31 to D0 0⎯ns

Data valid to MCLKI ↑ setup time tDSCH MCLKI

D31 to D0 3⎯ns

MCLKI ↑ to Data valid hold time tCHDX MCLKI

D31 to D0 1⎯ns

MCLKO ↓ to WRXn

(as byte enable) delay time

tCLWRL MCLKO

WRXn

⎯12 ns

tCLWRH 0⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯6ns

tCLCSH ⎯9ns

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MCLKO

MCLKI

CSXn

WRXn

(as byte enable)

RDX

DATA IN

tCLCSL

tCLWRL

tCHRL

tCHRH

tDSRH tRHDX

tCHDXtDSCH

tCLWRH

tCLCSH

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7.8.3. Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↑ to RDX delay time tCHRL MCLKO RDX − 1 5 ns

tCHRH − 1 7 ns

Data valid to RDX ↑ setup time tDSRH RDX

D31 to D0 18 ⎯ns

RDX ↑ to Data valid hold time

(internal MCLKO → MCLKI /

/MCLKI feedback)

tRHDX RDX

D31 to D0 0⎯ns

MCLKO ↓ to WRXn

(as byte enable) delay time

tCLWRL MCLKO

WRXn

⎯12 ns

tCLWRH 0⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯6ns

tCLCSH ⎯8ns

MCLKO

CSXn

WRXn

(as byte enable)

RDX

DATA IN

tDSRH tRHDX

tCHRH

tCHRL

tCLWRL tCLWRH

tCLCSH

tCLCSL

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7.8.4. Synchronous write access - byte control type

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to WEX delay time tCLWL MCLKO

WEX

⎯7ns

tCLWH 1⎯ns

Data valid to WEX ↓ setup time tDSWL WEX

D31 to D0 − 11 ⎯ns

WEX ↑ to Data valid hold time tWHDH WEX

D31 to D0 tCLKT − 5 ⎯ns

MCLKO ↓to WRXn (as byte enable)

delay time

tCLWRL MCLKO

WRXn

⎯12 ns

tCLWRH 0⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯6ns

tCLCSH ⎯8ns

MCLKO

CSXn

WRXn

(as byte enable)

WEX

DATA OUT

tCLWH

tCLWL

tCLWRL

tDSWL tWHDH

tCLWRH

tCLCSH

tCLCSL

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7.8.5. Synchronous write access - no byte control type

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to WRXn delay time tCLWRL MCLKO

WRXn

⎯12 ns

tCLWRH 0⎯ns

Data valid to WRXn ↓setup time tDSWRL WRXn

D31 to D0 − 11 ⎯ns

WRXn ↑ to Data valid hold time tWRHDH WRXn

D31 to D0 tCLKT − 6 ⎯ns

MCLKO ↓ to CSXn delay time tCLCSL MCLKO

CSXn

⎯6ns

tCLCSH ⎯8ns

MCLKO

CSXn

WRXn

DATA OUT

tCLWRH

tCLWRL

tDSWRL tWRHDH

tCLCSH

tCLCSL

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7.8.6. Asynchronous write access - byte control type

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

WEX ↓ to WEX ↑ pulse width tWLWH WEX tCLKT − 2 ⎯ns

Data valid to WEX ↓setup time tDSWL WEX

D31 to D0 1/2 × tCLKT − 11 ⎯ns

WEX ↑ to Data valid hold time tWHDH WEX

D31 to D0 1/2 × tCLKT − 6 ⎯ns

WEX to WRXn delay time tWRLWL WEX

WRXn

⎯1/2 × tCLKT + 3 ns

tWHWRH 1/2 × tCLKT − 3 ⎯ns

WEX to CSXn delay time tCLWL WEX

CSXn

⎯1/2 × tCLKT − 3ns

tWHCH 1/2 × tCLKT − 3 ⎯ns

CSXn

WRXn

(as byte enable)

WEX

DATA OUT

tWHDH

tWHWRH

tWHCH

tWRLWL

tWLWH

tCLWL

tDSWL

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MB91460E Series

194 DS705-00002-1v3-E

7.8.7. Asynchronous write access - no byte control type

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

WRXn ↓ to WRXn ↑ pulse width tWRLWRH WRXn tCLKT − 2 ⎯ns

Data valid to WRXn ↓setup time tDSWRL WRXn

D31 to D0 1/2 × tCLKT − 11 ⎯ns

WRXn ↑ to Data valid hold time tWRHDH WRXn

D31 to D0 1/2 × tCLKT − 6 ⎯ns

WRXn to CSXn delay time tCLWRL WRXn

CSXn

⎯1/2 × tCLKT − 2ns

tWRHCH 1/2 × tCLKT − 3 ⎯ns

CSXn

WRXn

DATA OUT

tWRHDH

tWRHCH

tCLWRL

tWRLWRH

tDSWRL

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MB91460E Series

DS705-00002-1v3-E 195

7.8.8. RDY waitcycle insertion

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

RDY setup time tRDYS MCLKO

RDY 14 ⎯ns

RDY hold time tRDYH MCLKO

RDY 0⎯ns

MCLKO

RDY

tRDYS tRDYH

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MB91460E Series

196 DS705-00002-1v3-E

7.8.9. Bus hold timing

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX).

It must be kept High as long as the bus shall be hold.

After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.

Note : Condition for tAXBGL and tBGHAV :

-VOL= 0.2 × VDD35

-VOH= 0.8 × VDD35

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to BGRNTX delay time tCLBGL MCLKO

BGRNTX

⎯5ns

tCLBGH ⎯6ns

Bus HIZ to BGRNTX ↓tAXBGL BGRNTX

MCLK*

A0 to An

RDX, ASX

WRXn,WEX

CSXn,BAAX

tCLKT + 8 ⎯ns

BGRNTX ↑ to Bus drive tBGHAV tCLKT + 1 ⎯ns

tAXBGL

tBGHAV

ADDR, RDX, WRX,

WEX, CSXn, ASX,

MCLKE, MCLKI,

MCLKO, BAAX

tCLBGL

tCLBGH

BGRNTX

MCLKO

BRQ

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MB91460E Series

DS705-00002-1v3-E 197

7.8.10. Clock relationships

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to MCLKE

(in sleep mode)

tCLML MCLKO

MCLKE

⎯3ns

tCLMH 0⎯ns

MCLKO

MCLKE(sleep)

tCLML

tCLMH

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MB91460E Series

198 DS705-00002-1v3-E

7.8.11. DMA transfer

(VDD35 =3.0 V to 4.5 V, Vss5 =AVss5 =0V,TA=−40 °Cto +105 °C)

Note : DREQ and DEOTX must be applied for at least 5 ×tCLKT to ensure that they are really sampled and evaluated.

Under best case conditions (DMA not busy) only setup and hold times are required.

Parameter Symbol Pin name Value Unit

Min Max

MCLKO ↓ to DACKX delay time tCLDAL MCLKO

DACKXn

⎯7ns

tCLDAH ⎯8ns

MCLKO ↓ to DEOP delay time tCLDEL MCLKO

DEOPn

⎯7ns

tCLDEH ⎯11 ns

MCLKO ↑ to DACKX delay time

(ADDR → delayed CS) tCHDAL MCLKO

DACKXn − 1 4 ns

MCLKO ↑ to DEOP delay time

(ADDR → delayed CS) tCHDEL MCLKO

DEOPn − 1 6 ns

DREQ setup time tDRQS MCLKO

DREQn 16 ⎯ns

DREQ hold time tDRQH MCLKO

DREQn 0⎯ns

DEOTXn setup time tDTXS MCLKO

DEOTXn 16 ⎯ns

DEOTXn hold time tDTXH MCLKO

DEOTXn 0⎯ns

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MB91460E Series

DS705-00002-1v3-E 199

MCLKO

DACKX

DEOP

delayed DACKX

delayed DEOP

DREQ

DEOTX

tCLDAL tCLDAH

tCLDEH

tCLDEL

tCHDAL

tCHDEL

tDRQH

tDTXH

tDTXS

tDRQS

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MB91460E Series

200 DS705-00002-1v3-E

■ORDERING INFORMATION

Part number Package Remarks

MB91F467EAPMC-GSE2 208-pin low profile QFP

(FPT-208P-M06) Lead-free package

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MB91460E Series

DS705-00002-1v3-E 201

■PACKAGE DIMENSION

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

208-pin plastic LQFP Lead pitch 0.50 mm

Package width ×

package length 28.0 × 28.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm MAX

Weight 2.55g

Code

(Reference) P-LFQFP208-28×28-0.50

208-pin plastic LQFP

(FPT-208P-M06)

2003 FUJITSU LIMITED F208027S-c-3-3

Details of "A" part

0.25(.010)

(Stand off)

(.004±.002)

0.10±0.05

(.024±.006)

0.60±0.15

1.50 +0.20

–0.10

+.008

–.004

.059

0˚~8˚

"A"

0.08(.003)

(.006±.002)

0.145±0.055

INDEX

LEAD No. 52

104

105

156

157

208

0.50(.020) 0.08(.003)M

(.009±.002)

0.22±0.05

28.00±0.10(1.102±.004)SQ

30.00±0.20(1.181±.008)SQ

(Mounting height)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB91460E-DS705-00002-1v3-E.fm Page 201 Wednesday, September 29, 2010 9:47 AM

MB91460E Series
202 DS705-00002-1v3-E
■REVISION HISTORY
Version/
Date Page Section Change Results
Ver. 0.01
2009-04-16 - - Initial version based on MB91F467D
Ver. 0.2
2009-07-03
all all Various updates following the proof read results on
other MB91460 series datasheets
76 Shutdown Mode Chapter “Shutdown Mode” added
Ver. 0.3
2009-08-03
4Product Lineup Corrected that the software watchdog cannot be ac-
tivated in SLEEP/STOP
76-
92 Chapter Shutdown Mode Total update
120 IO Map; SHDINT register Removed bits [3:2]
151 ELECTRICAL CHARACTERISTICS,
Absolute maximum ratings Permitted power dissipation (calculated) added
157 DC Characteristics Added  Sum input leakage current
159
A/D converter characteristics;
  Zero reading voltage,
  Full scale reading voltage
Changed the units from “LSB” into “V” and the values
from <value>+<n> into <value>+<n LSB>
165 AC Characteristics Removed the AC specification temporary
201 Package Dimension Updated the the drawing of FPT-208P-M04 into
FPT-208P-M06, updated the URL for download
Ver. 0.4
2009-08-04 all Total update after first spec review No change bars in this revision!
Ver. 0.5
2009-08-19
73 USART LIN/FIFO (Extension) This chapter added for “End of Transmission” IRQ
108 I/O Map Marked all differences versus MB91F467D
with colors
138 Interrupt Vector Table Added the USART “End of Transmission” IRQs
Ver. 0.6
2009-09-08
87 Shutdown mode:  External Interrupts:
   Level or Edge Setting Added this section
86 Shutdown mode:  Input Voltage Selec-
tion Added this section
80 Shutdown mode: SHDINT register Re-added bits [3:2] HWWDF, HWWDE for hardware
watchdog
78 Shutdown mode: All registers Updated the bit descriptions of all flags, updated the
reset conditions of all registers
89 Shutdown mode: Determining the reset
source
Figure updated, Hardware watchdog + Clock super-
visor updated
85 Shutdown mode: Hardware watchdog Updated the parts about Hardware watchdog, Clock
Supervisor completely
86 Shutdown mode: Clock Supervisor
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MB91460E Series
DS705-00002-1v3-E 203
Ver. 0.8
2009-10-19
77 Shutdwon Mode: Standby RAM Changed: 1 wait cycle for read, 0 wait cycles for write
78 Hardware Watchdog: Caution Updated “Difference between watchdog reset, exter-
nal reset and Power-on reset”
84 Shutdown Mode: Precautions Add setting of EXTE and EXTLV; removed this from
Deep Shutdown settings
90 Shutdown Mode: Registers which are
not initialized by Shutdown Recovery Added this section
26 Block Diagram Corrected the connection of Standby RAM (to ex-
tended D-bus)
Ver. 0.9
2009-11-24 56 Clock Supervisor, CSVCR register Added note that bit SCKS must not be changed dur-
ing CPU runs in Sub clock.
Ver. 1.0
2009-12-15
all Header Changed from “Preliminary Short Specification” into
“Preliminary Datasheet”
3Features Removed the note about PHILIPS I2C license
15 Pin Description : Power supply/Ground
pins Added pin 208 to the list of VDD35 pins
77 Shutdown Mode: Standby RAM StandBy RAM 1 wait state for read and write
125 I/O Map Added note about external bus PFR initial values
137 I/O Map StandBy RAM 1 wait state for read and write
138 Interrupt Vector Table Re-arranged the table to set correct page breaks
201 Package Dimension Link to package database corrected
Ver. 1.1
2010-01-21
74
USART LIN/FIFO (Extension) :
 FIFO status register for
 End of Transmission interrupt control
Bits [12:8] of FSR register named NVFD[5:0]
(Number of valid FIFO data), name is needed for
Softune header file.
77 Shutdown Mode: Standby RAM Added notes that, if CLKP is slower then CLKB,
there must be a wait time between setting RAMEN
and Standby RAM access.
78 Shutdown Mode: SHDE Register
76 Shutdown Mode: Overview
Added notes that reset by external pin INITX=0 will
kill the Shutdown state and restart the device like at
power-on.
88 Shutdown Mode: Recovery
90 Shutdown Mode: Registers which are
not initialized by Shutdown Recovery
Ver 1.11
2010-06-02
4 Product Lineup Changed max. CLKB frequency to 100 MHz
143 Recommended Settings
 PLL and Clockgear settings Enabled / allowed the settings which reach
CLKB up to 100MHz
144 Recommended Settings
 Clock modulator settings
158 Electrical Characteristics
  DC Characteristics
Changed Icc max for
 CLKB:P:T:CAN = 100:50:50:50 MHz;
Updated all current consumption characteristics
165 Electrical Characteristics
  AC Characteristics Chapter AC Characteristics added
Version/
Date Page Section Change Results
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MB91460E Series
204 DS705-00002-1v3-E
DS705-00002-1v2-E 2010-08-15
Page Section Changes
1■ DESCRIPTION Fujitsu Microelectronics --> Fujitsu Semiconductor
22 ■ HANDLING DEVICES
3. Power supply pins Changed “MB91460D series” --> “MB91460 series”
55 ■ CLOCK SUPERVISOR
2.1. Clock Supervisor Control Register (CSVCR)
Description of SCKS bit:
On single clock devices always 0
57 ■ CLOCK SUPERVISOR
3. Block Diagram Clock Supervisor
Changed input EXT_RST ---> EXT_RST_IN in the
drawing
73
■ CLOCK SUPERVISOR
4.11. Check if reset was asserted by the Clock
Supervisor
Changed the cross reference text “RSRR: Reset Cause
Register" so that the hardware manual is mentioned.
157
■ ELECTRICAL CHARACTERISTICS
3. DC characteristics
    Sum input leakage current
Changed from max. 40µA to max. 30µA
158
■ ELECTRICAL CHARACTERISTICS
3. DC characteristics
    Power supply current MB91 F467EA
Updated all IccH values according to evaluation results
159
■ ELECTRICAL CHARACTERISTICS
4. A/D converter characteristics
 Compare time
Changed Tcomp max from 16,500 µs to “t.b.d.” because
this parameter is under re-evaluation.
172
186
■ ELECTRICAL CHARACTERISTICS
7. AC characteristics
7.7. External Bus AC Timings at VDD35 =4.5 to 5.5 V
7.8. External Bus AC Timings at VDD35 =3.0 to 4.5 V
Changed all symbol names from upper case strings to
the commonly used style.
Example: Changed TCLCH into tCLCH
172
■ ELECTRICAL CHARACTERISTICS
7. AC characteristics
7.7. External Bus AC Timings at VDD35 =4.5 to 5.5 V
Updated all timing information according to the evalua-
tion results
186
■ ELECTRICAL CHARACTERISTICS
7. AC characteristics
7.8. External Bus AC Timings at VDD35 =3.0 to 4.5 V
Updated all timing information according to the evalua-
tion results
200 ■ ORDERING INFORMATION Removed the remark that the "device is under develop-
ment"
MB91460E-DS705-00002-1v3-E.fm  Page 204  Wednesday, September 29, 2010  9:47 AM

MB91460E Series
DS705-00002-1v3-E 205
■CHANGES IN THIS EDITION
DS705-00002-1v3-E 2010-10-01
Page Section Changes
172
186
■ ELECTRICAL CHARACTERISTICS
7. AC characteristics
7.7. External Bus AC Timings at VDD35 =4.5 to 5.5 V
7.8. External Bus AC Timings at VDD35 =3.0 to 4.5 V
Corrected the condition of
 VOL from 0.2 × VDD35 into 0.5 × VDD35
 VOH from 0.8 × VDD35 into 0.5 × VDD35
182
196
■ ELECTRICAL CHARACTERISTICS
7. AC characteristics
7.7.9. Bus hold timing
7.8.9. Bus hold timing
Added note about condition for tAXBGL and tBGHAV :
- VOL =  0.2 × VDD35
- VOH =  0.8 × VDD35
200 ■ ORDERING INFORMATION
Corrected the product number
 from MB91F467EAPFVS-GSE2
 into  MB91F467EAPMC-GSE2
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MB91460E Series

206 DS705-00002-1v3-E

■MEMO AND DISCLAIMER

MEMO

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MB91460E Series

DS705-00002-1v3-E 207

MEMO

MB91460E-DS705-00002-1v3-E.fm Page 207 Wednesday, September 29, 2010 9:47 AM

MB91460E Series

208 DS705-00002-1v3-E

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Asia Paciﬁc

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

Thei

nformation,suchas descriptions offunction and application circuit examples,in this document are presented solelyfor the purpose

ofreference to showexamples ofoperations and uses of FUJITSU SEMICONDUCTORdevice; FUJITSU SEMICONDUCTOR does

not warrant proper operation ofthedevice withrespect to use based on suchinformation.When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Anyinformation in this document,including descriptions offunction and schematic diagrams,shall not be construed as license ofthe use

or exercise ofanyintellectual propertyright,suchaspatent rightor copyright,or anyother rightof FUJITSU SEMICONDUCTORorany

third partyor does FUJITSU SEMICONDUCTORwarrant non-infringement ofanythird-party's intellectual propertyrightorother right

by using suchinformation. FUJITSU SEMICONDUCTORassumes no liabilityfor anyinfringement ofthe intellectual propertyrights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed,developed and manufactured as contemplated for general use,including without

limitation,ordinaryindustrial use,generaloffice use,personal use,and household use,but are not designed,developed and manufactured

as contemplated (1) for use accompanying fatal risksordangers that,unless extremelyhighsafetyis secured,could haveaserious effect

to thepublic,and could lead directlyto death, personalinjury, severe physicaldamage or other loss (i.e., nuclearreaction control in

nuclearfacility, aircraftflight control,air traffic control,mass transport control,medicallife support system, missile launchcontrol in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note thatFUJITSU SEMICONDUCTORwill not beliable against you and/or anythird partyfor anyclaimsordamages aris-

ing in connection with above-mentioned uses of the products.

Anysemiconductor devices haveaninherent chance offailure.You must protect against injury, damage or loss fromsuchfailures

by incorporating safetydesign measures into your facilityand equipment suchas redundancy, fire protection,and prevention ofover-

current levels and other abnormal operating conditions.

Exportation/release ofanyproducts described in this document may require necessaryprocedures in accordance withthe regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Fujitsu Semiconductor Europe GmbH

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MB91460E Series

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