LP2902-N, LP324-N
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SNOSBX6C –SEPTEMBER 1999–REVISED MARCH 2013
LP324-N/LP2902-N Micropower Quad Operational Amplifier
Check for Samples: LP2902-N,LP324-N
1FEATURES DESCRIPTION
The LP324-N series consists of four independent,
2• Low Supply Current: 85μA (typ) high gain internally compensated micropower
• Low Offset Voltage: 2mV (typ) operational amplifiers. These amplifiers are specially
• Low Input Bias Current: 2nA (typ) suited for operation in battery systems while
maintaining good input specifications, and extremely
• Input Vommon Mode to GND low supply current drain. In addition, the LP324-N has
• Interfaces to CMOS Logic an input common mode range, and output source
• Wide Supply Range: 3V < V+< 32V range which includes ground, making it ideal in single
supply applications.
• Small Outline Package Available
• Pin-for-pin Compatible with LM324 These amplifiers are ideal in applications which
include portable instrumentation, battery backup
equipment, and other circuits which require good DC
performance and low supply current.
Connection Diagram
Figure 1. 14-Lead SOIC Figure 2. 14-Pin TSSOP
See NFF0014A or D Package See PW Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LP2902-N, LP324-N
SNOSBX6C –SEPTEMBER 1999–REVISED MARCH 2013
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Simplified Schematic
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage LP324-N 32V or ± 16V
LP2902-N 26V or ± 13V
Differential Input Voltage LP324-N 32V
LP2902-N 26V
Input Voltage(3) LP324-N −0.3V to 32V
LP2902-N −0.3V to 26V
Output Short-Circuit to GND (One Amplifier)(4) Continuous
V+≤15V and TA= 25°C ESD Susceptibility(5) ±500V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The input voltage is not allowed to go more than −0.3V below V−(GND) as this will turn on a parasitic transistor causing large currents
to flow through the device.
(4) Short circuits from the output to GND can cause excessive heating and eventual destruction. The maximum sourcing output current is
approximately 30 mA independent of the magnitude of V+. At values of supply voltage in excess of 15 VDC, continuous short-circuit to
GND can exceed the power dissipation ratings (particularly at elevated temperatures) and cause eventual destruction. Destructive
dissipation can result from simultaneous shorts on all amplifiers.
(5) The test circuit used consists of the human body model of 100 pF in series with 1500Ω.
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SNOSBX6C –SEPTEMBER 1999–REVISED MARCH 2013
Operating Conditions
TJMAX 150°C
θJA(1) PW Package 154°C/W
NFF014A Package 90°C/W
D Package 140°C/W
Operating Temp. Range See(2)
Storage Temp. Range −65°C≤TJ≤150°C
Soldering Information Wave Soldering(10sec) 260°C(lead temp.)
Convection or Infrared(20sec) 235°C
(1) For operation at elevated temperatures, these devices must be derated based on a thermal resistance of θJA and TJmax. TJ= TA+
θJAPD.
(2) The LP2902-N may be operated from −40°C ≤TA≤+85°C, and the LP324-N may be operated from 0°C ≤TA≤+70°C.
Electrical Characteristics(1)
Symbol Parameter Conditions LP2902-N(2) LP324-N
Typ Tested Design Typ Tested Design Units
Limit(3) Limit(4) Limit(3) Limit(4) Limits
VOS Input Offset 2 4 10 2 4 9mV
Voltage (Max)
IBInput Bias Current 2 20 40 2 10 20 nA
(Max)
IOS Input Offset Current 0.5 4 80.2 2 4nA
(Max)
AVOL Voltage Gain RL= 10k to GND 70 40 30 100 50 40 V/mV
V+= 30V (Min)
CMRR Common Mode Rej. V+= 30V, 0V ≤VCM 90 80 75 90 80 75 dB
Ratio VCM < V+−1.5 (Min)
PSRR Power Supply Rej. V+= 5V to 30V 90 80 75 90 80 75 dB
Ratio (Min)
ISSupply Current RL=∞85 150 250 85 150 250 μA
(Max)
VOOutput Voltage Swing IL= 350μA to GND 3.6 3.4 V+−1.9V 3.6 3.4 V+−1.9V V
VCM = 0V (Min)
IL= 350μA to V+0.7 0.8 1.0 0.7 0.8 1.0 V
VCM = 0V (Max)
IOUT Output Source VO= 3V 10 7 410 7 4mA
Source Current VIN (diff) = 1V (Min)
IOUT Output Sink Current VO= 1.5V 5 4 35 4 3mA
Sink VIN (diff) = 1V (Min)
IOUT Output Sink Current VO= 1.5V 4 2 14 2 1mA
Sink VCM = 0V (Min)
ISOURCE Output Short to GND VIN (diff) = 1V 20 25 35 20 25 35 mA
35 35 (Max)
ISINK Output Short to V+VIN (diff) = 1V 15 30 45 15 30 45 mA
(Max)
VOS Drift 10 10 μV/C°
IOS Drift 10 10 pA/C°
GBW Gain Bandwidth 100 100 KHz
Product
SR Slew Rate 50 50 V/mS
(1) Boldface numbers apply at temperature extremes. All other numbers apply only at TA= TJ= 25°C, V+= 5V, Vcm = V/2, and RL=100k
connected to GND unless otherwise specified.
(2) The LP2902-N operating supply range is 3V to 26V, and is not tested above 26V.
(3) Specified and 100% production tested.
(4) Specified (but not 100% production tested) over the operating supply voltage range (3.0V to 32V for the LP324-N, LP324-N, and 3.0V to
26V for the LP2902-N), and the common mode range (0V to V+−1.5V), unless otherwise specified. These limits are not used to
calculate outgoing quality levels.
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Typical Performance Curves
Input Voltage Range Input Current
Figure 3. Figure 4.
Supply Current Voltage Gain
Figure 5. Figure 6.
Open Loop Power Supply
Frequency Response Rejection Ratio
Figure 7. Figure 8.
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Typical Performance Curves (continued)
Voltage Follower Voltage Follower Pulse
Pulse Response Response (Small Signal)
Figure 9. Figure 10.
Common Mode Large Signal
Rejection Ratio Frequency Response
Figure 11. Figure 12.
Output Characteristics Output Characteristics
Current Sourcing Current Sinking
Figure 13. Figure 14.
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Typical Performance Curves (continued)
Current Limiting
Figure 15.
APPLICATION HINTS
The LP324-N series is a micro-power pin-for-pin equivalent to the LM324 op amps. Power supply current, input
bias current, and input offset current have all been reduced by a factor of 10 over the LM324. Like its
predecessor, the LP324-N series op amps can operate on single supply, have true-differential inputs, and remain
in the linear mode with an input common-mode voltage of 0 VDC.
The pinouts of the package have been designed to simplify PC board layouts. Inverting inputs are adjacent to
outputs for all of the amplifiers and the outputs have also been placed at the corners of the package (pins 1, 7, 8,
and 14).
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in
polarity or the unit is not inadvertently installed backwards in the test socket as an unlimited current surge
through the resulting forward diode within the IC could destroy the unit.
Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes
are not needed, no large input currents result from large differential input voltages. The differential input voltage
may be larger than V+without damaging the device. Protection should be provided to prevent the input voltages
from going negative more than −0.3 VDC (at 25°C). An input clamp diode with a resistor to the IC input terminal
can be used.
The amplifiers have a class B output stage which allows the amplifiers to both source and sink output currents. In
applications where crossover distortion is undesirable, a resistor should be used from the output of the amplifier
to ground. The resistor biases the output into class A operation.
The LP324-N has improved stability margin for driving capacitive loads. No special precautions are needed to
drive loads in the 50 pF to 1000 pF range. It should be noted however that since the power supply current has
been reduced by a factor of 10, so also has the slew rate and gain bandwidth product. This reduction can cause
reduced performance in AC applications where the LM324 is being replaced by an LP324-N. Such situations
usually occur when the LM324 has been operated near its power bandwidth.
Output short circuits either to ground or to the positive power supply should be of short time duration. Units can
be destroyed, not as a result of the short circuit current causing metal fusing, but rather due to the large increase
in IC chip dissipation which will cause eventual failure due to excessive junction temperatures. For example: If all
four amplifiers were simultaneously shorted to ground on a 10V supply the junction temperature would rise by
110°C.
Exceeding the negative common-mode limit on either input will cause a reversal of phase to the output and force
the amplifier to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs
will force the amplifier output to a high state. Exceeding the positive common-mode limit on a single input will not
change the phase of the output. However, if both inputs exceed the limit, the output of the amplifier will be forced
to a low state. In neither case does a latch occur since returning the input within the common mode range puts
the input stage and thus the amplifier in a normal operating mode.
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SNOSBX6C –SEPTEMBER 1999–REVISED MARCH 2013
The circuits presented in the section on typical applications emphasize operation on only a single power supply
voltage. If complementary power supplies are available, all of the standard op amp circuits can be used. In
general, introducing a pseudo-ground (a bias voltage reference to V+/2) will allow operation above and below this
value in single power supply systems. Many application circuits are shown which take advantage of the wide
input common-mode voltage range which includes ground. In most cases, input biasing is not required and input
voltages which range to ground can easily be accommodated.
Figure 16. Driving CMOS
Figure 17. Comparator with Hysteresis
Figure 18. Non-Inverting Amplifier
Figure 19. Adder/Subtractor
Figure 20. Unity Gain Buffer
Figure 21. Positive Integrator
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Figure 22. Differential Integrator
Figure 23. Howland Current Pump
Figure 24. Bridge Current Amplifier
Figure 25. μPower Current Source
Figure 26. Lowpass Filter
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SNOSBX6C –SEPTEMBER 1999–REVISED MARCH 2013
Figure 27. 1 kHz Bandpass Active Filter
Figure 28. Band-Reject Filter
Figure 29. Pulse Generator
Figure 30. Window Comparator
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LP2902M NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LP2902M
LP2902M/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LP2902M
LP2902MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LP2902M
LP2902N/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LP2902N
LP324M NRND SOIC D 14 55 TBD Call TI Call TI 0 to 70 LP324M
LP324M/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LP324M
LP324MT NRND TSSOP PW 14 94 TBD Call TI Call TI 0 to 70 LP324
MT
LP324MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LP324
MT
LP324MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LP324
MT
LP324MX NRND SOIC D 14 2500 TBD Call TI Call TI 0 to 70 LP324M
LP324MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LP324M
LP324N/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LP324N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LP2902MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LP324MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1
LP324MX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LP324MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP2902MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LP324MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LP324MX SOIC D 14 2500 367.0 367.0 35.0
LP324MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
N0014A
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N14A (Rev G)
NFF0014A
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