MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Functional Diagram
19-0196; Rev 1; 3/12
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX187.related.
EVALUATION KIT AVAILABLE
General Description
The MAX187/MAX189 serial 12-bit analog-to-digital con-
verters (ADCs) operate from a single +5V supply and
accept a 0 to 5V analog input. Both parts feature an 8.5Fs
successive-approximation ADC, a fast track/hold (1.5Fs),
an on-chip clock, and a high-speed 3-wire serial interface.
The MAX187/MAX189 digitize signals at a 75ksps
throughput rate. An external clock accesses data from
the interface, which communicates without external
hardware to most digital signal processors and micro-
controllers. The interface is compatible with SPI, QSPIK,
and MICROWIREM.
The MAX187 has an on-chip buffered reference, and
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin PDIP and
16-pin SO packages. Power consumption is 7.5mW and
reduces to only 10FW in shutdown.
Excellent AC characteristics and very low power con-
sumption combined with ease of use and small package
size make these converters ideal for remote DSP and
sensor applications, or for circuits where power con-
sumption and space are crucial.
Features
S 12-Bit Resolution
S ±½ LSB Integral Nonlinearity (MAX187A/MAX189A)
S Internal Track/Hold, 75kHz Sampling Rate
S Single +5V Operation
S Low Power: 2µA Shutdown Current
1.5mA Operating Current
S Internal 4.096V Buffered Reference (MAX187)
S 3-Wire Serial Interface, Compatible with SPI, QSPI,
and MICROWIRE
S Small-Footprint 8-Pin PDIP and 16-Pin SO
Applications
Portable Data Logging
Remote Digital Signal Processing
Isolated Data Acquisition
High-Accuracy Process Control
QSPI is a trademark of Motorola.
MICROWIRE is a registered trademark of National Semiconductor Corp.
GND 5
REF 4
AIN 2
VDD 1
T/H
BANDGAP
REFERENCE
+2.5V
(MAX187 ONLY)
10kI
AV = 1.638
(4.096V)
REF-
REF+
DAC
OUTPUT
SHIFT
REGISTER
DOUT6
SCLK
8
CS7
3
CONTROL
AND
TIMING
12-BIT
SAR
COMPARATOR
BUFFER ENABLE/DISABLE
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY
SHDN
MAX187
MAX189
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
2Maxim Integrated
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND.................................-0.3V to (VDD + 0.3V)
Digital Outputs to GND..............................-0.3V to (VDD + 0.3V)
SHDN to GND.............................................-0.3V to (VDD + 0.3V)
REF Load Current (MAX187) .........................4.0mA Continuous
REF Short-Circuit Duration (MAX187)......................... ... .......20s
DOUT Current..................................................................Q20mA
Continuous Power Dissipation (TA = +70NC)
8-Pin PDIP (derate 9.1mW/NC above +70NC)..............727mW
16-Pin Wide SO (derate 14.5mW/NC above 70NC).....1157mW
Operating Temperature Ranges
MAX187_C_ _/MAX189_C_ _..............................0NC to +70NC
MAX187_E_ _/MAX189_E_ _...........................-40NC to +85NC
Storage Temperature Range.............................-60NC to +150NC
Lead Temperature (soldering, 10s) .................................+300NC
Soldering Temperature (reflow) .......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal refer-
ence: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 12 Bits
Relative Accuracy (Note 2)
MAX18_A Q½
LSBMAX18_B Q1
MAX18_C Q2
Differential Nonlinearity DNL No missing codes over temperature Q1LSB
Offset Error MAX18_A Q1½ LSB
MAX18_B/C Q3
Gain Error (Note 3)
MAX187 Q3
LSBMAX189A Q1
MAX189B/C Q3
Gain Temperature Coefficient External reference, 4.096V Q0.8 ppm/NC
DYNAMIC SPECIFICATIONS (10kHz Sine Wave Input, 0 to 4.096VP-P, 75ksps)
Signal-to-Noise Plus
Distortion Ratio SINAD 70 dB
Total Harmonic Distortion
(Up to the 5th Harmonic) THD -80 dB
Spurious-Free Dynamic Range SFDR 80 dB
Small-Signal Bandwidth Rolloff -3dB 4.5 MHz
Full-Power Bandwidth 0.8 MHz
CONVERSION RATE
Conversion Time tCONV 5.5 8.5 Fs
Track/Hold Acquisition Time tACQ 1.5 Fs
Throughput Rate External clock, 4MHz, 13 clocks 75 ksps
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
3Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal refer-
ence: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Aperture Delay tAPR 10 ns
Aperture Jitter < 50 ps
ANALOG INPUT
Input Voltage Range 0 to VREF V
Input Capacitance (Note 4) 16 pF
INTERNAL REFERENCE (MAX187 Only, Reference Buffer Enabled)
REF Output Voltage VREF
TA = +25NC4.076 4.096 4.116
V
TA = TMIN to
TMAX
MAX187_C 4.060 4.132
MAX187_E 4.050 4.140
REF Short-Circuit Current Q30 mA
REF Tempco
MAX187AC/BC Q30 Q50
ppm/NC
MAX187AE/BE Q30 Q60
MAX187C Q30
Load Regulation (Note 5) 0 to 6mA output load 1 mV
EXTERNAL REFERENCE AT REF (Buffer Disabled, VREF = 4.096V)
Input Voltage Range 2.50 VDD + 50mV V
Input Current 200 350 µA
Input Resistance 12 20 kI
Shutdown REF Input Current 1.5 10 µA
DIGITAL INPUTS (SCLK, CS, SHDN)
SCLK, CS Input High Voltage VINH 2.4 V
SCKL, CS Input Low Voltage VINL 0.8 V
SCLK, CS Input Hysteresis VHYST 0.15 V
SCLK, CS Input Leakage IIN VIN = 0V or VDD ±1 µA
SCLK, CS Input Capacitance CIN (Note 4) 15 pF
SHDN Input High Voltage VINSH VDD - 50mV V
SHDN Input Low Voltage VINSL 0.5 V
SHDN Input Current IINS VSHDN = VDD or 0V ±4.0 µA
SHDN Input Mid voltage VIM 1.5 VDD - 1.5 V
SHDN Voltage, Floating VFLT SHDN = Open 2.75 V
SHDN Maximum Allowed
Leakage, Mid-Input SHDN = Open -100 100 nA
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal refer-
ence: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
TIMING CHARACTERISTICS
(VDD = +5V ±5%, TA = TMIN to TMAX; unless otherwise noted.)
Note 1: Tested at VDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum-
time needed for the signal to be acquired.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (DOUT)
Output Voltage Low VOL
ISINK = 5mA 0.4 V
ISINK = 16mA 0.3
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current ILVCS = 5V Q10 FA
Three-State Output Capacitance COUT VCS = 5V (Note 4) 15 pF
POWER REQUIREMENTS
Supply Voltage VDD 4.75 5.25 V
Supply Current IDD
Operating mode MAX187 1.5 2.5 mA
MAX189 1.0 2.0
Power-down mode 2 10 FA
Power-Supply Rejection PSR VDD = +5V Q5%; external reference,
4.096V; full-scale input (Note 6) Q0.06 Q0.5 mV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Track/Hold Acquisition Time tACQ CS = high (Note7) 1.5 µs
SCLK Fall to Output Data Valid tDQ CLOAD = 100pF MAX18_ _C/E 20 150 ns
MAX18_ _M 20 200
CS Fall to Output Enable tDV CLOAD = 100pF 100 ns
CS Rise to Output Disable tTR CLOAD = 100pF 100 ns
SCLK Clock Frequency tSCLK 5 MHz
SCLK Pulse Width High tCH 100 ns
SCLK Pulse Width Low tCL 100 ns
SCLK Low to CS Fall Setup Time tCSO 50 ns
CS Pulse Width tCS 500 ns
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
5Maxim Integrated
Typical Operating Characteristics
POWER-SUPPLY REJECTION
vs. TEMPERATURE
MAX187 toc01
TEMPERATURE (°C)
POWER-SUPPLY REJECTION (mV)
100-20 6020
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0
-60 140
VREF vs. TEMPERATURE
MAX187 toc02
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
1006020-20
4.081
4.082
4.083
4.084
4.085
4.086
4.087
4.088
4.089
4.090
4.080
-60 140
SUPPLY vs. TEMPERATURE
MAX187 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
10060-20 20
0.2
0.6
1.0
1.4
1.8
2.2
-60 140
MAX187
MAX189
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX187 toc04
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
10060-20 20
1
2
3
4
5
6
7
0
-60 140
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
6Maxim Integrated
Pin Description
Pin Configurations
PIN NAME FUNCTION
PDIP WIDE SO
1 1 VDD Supply Voltage. +5V, Q5%
2 3 AIN Sampling Analog Input. 0V to VREF range
3 6 SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX187/MAX189 down to 10FA
(max) supply current. Both MAX187 and MAX189 are fully operational with either SHDN
high or unconnected. For the MAX187, pulling SHDN high enables the internal reference,
and letting SHDN unconnected disables the internal reference and allows for the use of an
external reference.
4 8 REF
Reference Voltage—sets analog voltage range and functions as a 4.096V output for the
MAX187 with enabled internal reference. REF also serves as a +2.5V to VDD input for a
precision reference for both MAX187 (disabled internal reference) and MAX189. Bypass
with 4.7FF if internal reference is used, and with 0.1FF if an external reference is applied.
5 — GND Analog and Digital Ground
— 10 AGND Analog Ground
— 11 DGND Digital Ground
6 12 DOUT Serial Data Output. Data changes state at SCLK’s falling edge.
7 15 CS Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is
high impedance.
8 16 SCLK Serial Clock Input. Clocks data out with rates up to 5MHz.
—2, 4, 5, 7,
9, 13. 14 N.C. No Connection. Not internally connected. Connect to AGND for best noise performance.
REF GND
1
2
8
7
VDD
AIN
DOUT
SCLK
PDIP
TOP VIEW
3
4
6
5
MAX187
MAX189
MAX187
MAX189
SHDN
CS
+
N.C.
N.C.N.C.
1
2
16
15
SCLK
+
CSN.C.
AIN
VDD
Wide SO
3
4
14
13
DGND
AGNDN.C.
512 DOUTN.C.
SHDN 6
7
11
10
N.C.REF 89
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
7Maxim Integrated
Detailed Description
Converter Operation
The MAX187/MAX189 use input track/hold (T/H) and suc-
cessive approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. No exter-
nal hold capacitor is needed for the T/H. Figures 3a and
3b show the MAX187/MAX189 in their simplest configu-
ration. The MAX187/MAX189 convert input signals in the
0V to VREF range in 10µs, including T/H acquisition time.
The MAX187’s internal reference is trimmed to 4.096V,
while the MAX189 requires an external reference. Both
devices accept external reference voltages from +2.5V to
VDD. The serial interface requires only three digital lines,
SCLK, CS, and DOUT, and provides easy interface to
microprocessors (µPs).
Both converters have two modes: normal and shutdown.
Pulling SHDN low shuts the device down and reduces
supply current to below 10µA, while pulling SHDN high or
leaving it floating puts the device into the operational mode.
A conversion is initiated by CS falling. The conversion result
is available at DOUT in unipolar serial format. A high bit,
signaling the end of conversion (EOC), followed by the data
bits (MSB first), make up the serial data stream.
The MAX187 operates in one of two states: (1) internal
reference and (2) external reference. Select internal
reference operation by forcing SHDN high, and external
reference operation by floating SHDN.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s analog comparator. The full-scale input voltage
depends on the voltage at REF.
REFERENCE ZERO SCALE FULL SCALE
Internal Reference
(MAX187 only) 0V +4.096V
External Reference 0V VREF
For specified accuracy, the external reference voltage
range spans from +2.5V to VDD.
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
DOUT DOUT
3kICLOAD = 100pF CLOAD = 100pF
3kI
DGND
+5V
B. HIGH-Z TO VOL AND VOH TO VOL
A. HIGH-Z TO VOH AND VOL TO VOH
DGND
DOUT DOUT
3kICLOAD = 100pF CLOAD = 100pF
3kI
DGND
+5V
B. VOL TO HIGH-ZA. VOH TO HIGH-Z
DGND
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
8Maxim Integrated
Figure 3a. MAX187 Operational Diagram
Figure 4. Equivalent Input Circuit
Figure 3b. MAX189 Operational Diagram
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges capaci-
tor CHOLD. Bringing CS low ends the acquisition interval.
At this instant, the T/H switches the input side of CHOLD
to GND. The retained charge on CHOLD represents a
sample of the input, unbalancing the node ZERO at the
comparator’s input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of a 12-bit resolution. This action
is equivalent to transferring a charge from CHOLD to the
binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal. At the
conversion’s end, the input side of CHOLD switches back
to AIN, and CHOLD charges to the input signal again.
The time required for the T/H to acquire an input sig-
nal is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is calcu-
lated by:
tACQ = 9 (RS + RIN) 16pF
where RIN = 5kI, RS = the source impedance of the
input signal, and tACQ is never less than 1.5Fs. Source
impedances below 5kI do not significantly affect the AC
performance of the ADC.
Input Bandwidth
The ADCs’ input tracking circuitry has a 4.5MHz small-
signal bandwidth, and an 8V/Fs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is rec-
ommended. See the MAX274/MAX275 continuous-time
filters data sheet.
ON
OFF
SHUTDOWN
INPUT
ANALOG INPUT
0 TO +5V
+5V 1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
DOUT
GND
SERIAL
INTERFACE
4.7µF
4.7µF
0.1µF
CS
MAX187
AIN TRACK INPUT
HOLD
CPACKAGE
GND
TRACK HOLD
RIN
5kI
CHOLD
16pF
-+
CSWITCH
COMPARATOR
ZERO
REF
12-BIT CAPACITIVE DAC
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
ON
OFF
SHUTDOWN
INPUT
ANALOG INPUT
0 TO +5V
REFERENCE
INPUT
+5V 1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
DOUT
GND
SERIAL
INTERFACE
0.1µF
4.7µF
0.1µF
CS
MAX189
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
9Maxim Integrated
Figure 5. MAX187/MAX189 Shutdown Sequence
Input Protection
Internal protection diodes that clamp the analog input
allow the input to swing from GND - 0.3V to VDD + 0.3V
without damage. However, for accurate conversions near
full scale, the input must not exceed VDD by more than
50mV, or be lower than GND by 50mV.
If the analog input exceeds the supplies by more than
50mV beyond the supplies, limit the input current
to 2mA, since larger currents degrade conversion
accuracy.
Driving the Analog Input
The input lines to AIN and GND should be kept as short
as possible to minimize noise pickup. Shield longer
leads. Also see the Input Protection section.
Because the MAX187/MAX189 incorporate a T/H, the
drive requirements of the op amp driving AIN are less
stringent than those for a successive-approximation ADC
without a T/H. The typical input capacitance is 16pF. The
amplifier bandwidth should be sufficient to handle the
frequency of the input signal. The MAX400 and OP07
work well at lower frequencies. For higher-frequency
operation, the MAX427 and OP27 are practical choices.
The allowed input frequency range is limited by the
75ksps sample rate of the MAX187/MAX189. Therefore,
the maximum sinusoidal input frequency allowed is
37.5kHz. Higher-frequency signals cause aliasing prob-
lems unless undersampling techniques are used.
Reference
The MAX187 can be used with an internal or external ref-
erence, while the MAX189 requires an external reference.
Internal Reference
The MAX187 has an on-chip reference with a buff-
ered temperature-compensated bandgap diode, laser-
trimmed to +4.096V Q0.5%. Its output is connected to
REF and also drives the internal DAC. The output can be
used as a reference voltage source for other components
and can source up to 0.6mA. Decouple REF with a 4.7FF
capacitor. The internal reference is enabled by pulling
the SHDN pin high. Letting SHDN float disables the inter-
nal reference, which allows the use of an external refer-
ence, as described in the External Reference section.
External Reference
The MAX189 operates with an external reference at the
REF pin. To use the MAX187 with an external reference,
disable the internal reference by letting SHDN float. Stay
within the voltage range +2.5V to VDD to achieve speci-
fied accuracy. The minimum input impedance is 12kI for
DC currents. During conversion, the external reference
must be able to deliver up to 350FA DC load current and
have an output impedance of 10I or less. The recom-
mended minimum value for the bypass capacitor is 0.1FF.
If the reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7FF capacitor.
DOUT
CS
SHDN
CONVERSION 1CONVERSION 1
tWAKE
COMPLETE CONVERSION SEQUENCE
POWERED DOWNPOWERED UP POWERED UP
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
10Maxim Integrated
Figure 6. Average Supply Current vs. Conversion Rate Figure 7. tWAKE vs. Time in Shutdown (MAX187 Only)
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, it takes the fully discharged
4.7FF reference bypass capacitor up to 20ms to provide
adequate charge for specified accuracy. With SHDN
not pulled low, the MAX187/MAX189 are now ready to
convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated.
After an internally timed 8.5Fs conversion period, the end
of conversion is signaled by DOUT pulling high. Data can
then be shifted out serially with the external clock.
Using SHDN to Reduce
Supply Current
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver-
sions. This is shown in Figure 6, a plot of average supply
current vs. conversion rate. Because the MAX189 uses
an external reference voltage (assumed to be present
continuously), it “wakes up” from shutdown more quickly,
and therefore provides lower average supply currents.
The wakeup-time, tWAKE, is the time from SHDN deas-
serted to the time when a conversion may be initiated.
For the MAX187, this time is 2Fs. For the MAX189, this
time depends on the time in shutdown (see Figure 7)
because the external 4.7FF reference bypass capacitor
loses charge slowly during shutdown (see the specifica-
tions for shutdown, REF Input Current = 10FA max).
External Clock
The actual conversion does not require the external
clock. This frees the FP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the FP’s convenience at any clock rate
from 0 to 5MHz. The clock duty cycle is unrestricted if
each clock phase is at least 100ns. Do not run the clock
while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline the operation of the serial
interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to convert,
and DOUT changes from high impedance to logic low.
SCLK must be kept inactive during the conversion. An
internal register stores the data when the conversion is
in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing sig-
nal. SCLK shifts the data out of this register any time after
the conversion is complete. DOUT transitions on SCLK’s
falling edge. The next falling clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits. Since there are 12 data bits and one leading
high bit, at least 13 falling clock edges are needed to
shift out these bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to a
rising edge of CS, produce trailing 0s at DOUT and have
no effect on converter operation.
CONVERSIONS PER SECOND
SUPPLY CURRENT (µA)
10k1k100101
10
100
1000
10,000
1
0.1 100k
MAX187
MAX189*
*REF CONNECTED TO VDD
TIME IN SHUTDOWN (s)
tWAKE (ms)
10.10.010.001
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0001 10
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
11Maxim Integrated
Figure 8. MAX187/MAX189 Interface Timing Sequence
Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing
CS
SCLK
DOUT
INTERFACE IDLE
CONVERSION
IN PROGRESS
EOC
A/D
STATE
TRACK
CONVERSION
0
TRAILING
ZEROS IDLE
0.5µs
(tCS)
TOTAL = 12.25µs
CONV. 1
CLOCK OUTPUT DATA
TRACK
12 x 0.250µs = 3.25µs
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
14 812
MINIMUM
CYCLE TIME
8.5µs
(tCONV)0µs
EOC
0µs
CS
SCLK
DOUT
INTERNAL
T/H
(TRACK)
tCS0
tDV
tAPR
(HOLD) (TRACK)
B2 B1 B0
tCH
tDO tCL tTR
tCONV
tCS
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
12Maxim Integrated
Minimum cycle time is accomplished by using DOUT’s
rising edge as the EOC signal. Clock out the data with
13 clock cycles at full speed. Raise CS after the conver-
sion’s LSB has been read. After the specified minimum
time, tACQ, CS can be pulled low again to initiate the next
conversion.
Output Coding and Transfer Function
The data output from the MAX187/MAX189 is binary, and
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive integer
LSB values. If VREF = +4.096V, then 1 LSB = 1.00mV or
4.096V/4096.
Dynamic Performance
High-speed sampling capability and a 75ksps throughput
make the MAX187/MAX189 ideal for wideband signal pro-
cessing. To support these and other related applications,
Fast Fourier Transform (FFT) test techniques are used
to guarantee the ADC’s dynamic frequency response,
distortion, and noise at the rated throughput. Specifically,
this involves applying a low-distortion sine wave to the
ADC input and recording the digital conversion results for
a specified time. The data is then analyzed using an FFT
algorithm that determines its spectral content. Conversion
errors are then seen as spectral elements outside of the
fundamental input frequency. ADCs have traditionally
been evaluated by specifications such as Zero and Full-
Scale Error, Integral Nonlinearity (INL), and Differential
Nonlinearity (DNL). Such parameters are widely accepted
for specifying performance with DC and slowly varying
signals, but are less useful in signal-processing applica-
tions, where the ADC’s impact on the system transfer
function is the main concern. The significance of various
DC errors does not translate well to the dynamic case, so
different tests are required.
Signal-to-Noise Ratio and
Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS amplitude of all other ADC output signals. The input
bandwidth is limited to frequencies above DC and below
one-half the ADC sample (conversion) rate.
The theoretical minimum ADC noise is caused by quanti-
zation error and is a direct result of the ADC’s resolution:
SINAD = (6.02N + 1.76)dB, where N is the number of bits
of resolution. An ideal 12-bit ADC can, therefore, do no
better than 74dB. An FFT plot of the output shows the out-
put level in various spectral bands. Figure 11 shows the
result of sampling a pure 10kHz sine wave at a 75ksps
rate with the MAX187/MAX189.
Figure 10. MAX187/MAX189 UnipolarTransfer Function, 4.096V
= Full Scale
Figure 11. MAX187/MAX189 FFT plot
11...111
11...110
11...101
00...011
00...010
00...01
00...000
01
2F
S
OUTPUT CODE
FS - 3/2 LSBINPUT VOLTAGE (LSBs)
FS = +4.096V
1 LSB = FS
4096
FULL-SCALE
TRANSITION
3
AMPLITUDE (dB)
20
0
-20
-40
-60
-80
-100
-120
-140
0 18.75 37.5
fS = 75ksps
fT = 10kHz
TA = +25°C
FREQUENCY (kHz)
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
13Maxim Integrated
Figure 12. Effective Bits vs. Input Frequency
The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured SINAD:
N = (SINAD - 1.76)/6.02. Figure 12 shows the effective
number of bits as a function of the input frequency for the
MAX187/MAX189.
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater than
the Nyquist frequency, the nonlinearities in the ADC’s
transfer function create harmonics of the input frequency
present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including
the DC component) to the RMS amplitude of the funda-
mental frequency. This is expressed as follows:
222 2
234 N
1
VVV V
THD 20log V
+ + +…
=
where V1 is the fundamental RMS amplitude, and V2
through VN are the amplitudes of the 2nd through
Nth harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th harmonics.
Applications Information
Connection to Standard Interfaces
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and MICROWIRE standard serial inter-
faces.
If a serial interface is available, set the CPU’s serial inter-
face in master mode so the CPU generates the serial
clock. Choose a clock frequency up to 2.5MHz.
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
3) Activate SCLK for a minimum of 13 clock cycles.
The first falling clock edge will produce the MSB of
the DOUT conversion. DOUT output data transitions
on SCLK’s falling edge and is available in MSB-first
format. Observe the SCLK to DOUT valid timing char-
acteristic. Data can be clocked into the FP on SCLK’s
rising edge.
4) Pull CS high at or after the 13th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the LSB.
5) With CS = high, wait the minimum specified time, tCS,
before launching a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversions end, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of the
conversion padded with one leading 1, and trailing 0s if
SCLK is still active with CS kept low.
SPI and MICROWIRE
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until DOUT
goes high or the maximum specified 8.5Fs conversion
time. Two consecutive 1-byte reads are required to get
the full 12 bits from the ADC. DOUT output data transi-
tions on SCLK’s falling edge and is clocked into the FP
on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conver-
sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections and
Figure 14 for timing.
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
110 100 1000
EFFECTIVE BITS
INPUT FREQUENCY (kHz)
12.0
12.2
(UNDERSAMPLED)
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
14Maxim Integrated
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX187/MAX189 require
13 clock cycles from the FP to clock out the 12 bits of
data with no trailing 0s (Figure 15). The maximum clock
frequency to ensure compatibility with QSPI is 2.77MHz.
Opto-Isolated Interface,
Serial-to-Parallel Conversion
Many industrial applications require electrical isolation to
separate the control electronics from hazardous electri-
cal conditions, provide noise immunity, or prevent exces-
sive current flow where ground disparities exist between
the ADC and the rest of the system. Isolation amplifiers
typically used to accomplish these tasks are expensive.
In cases where the signal is eventually converted to a
digital form, it is cost effective to isolate the input using
opto-couplers in a serial link.
The MAX187 is ideal in this application because it includes
both T/H amplifier and voltage reference, operates from a
single supply, and consumes very little power (Figure 16).
The ADC results are transmitted across a 1500V isolation
barrier provided by three 6N136 opto-isolators. Isolated
power must be supplied to the converter and the isolated
side of the opto-couplers. 74HC595 three-state shift reg-
isters are used to construct a 12-bit parallel data output.
The timing sequence is identical to the timing shown
in Figure 8. Conversion speed is limited by the delay
through the opto-isolators. With a 140kHz clock, conver-
sion time is 100Fs.
The universal 12-bit parallel data output can also be used
without the isolation stage when a parallel interface is
required. Clock frequencies up to 2.9MHz are possible
without violating the 20ns shift-register setup time. Delay or
invert the clock signal to the shift registers beyond 2.9MHz.
Figure 14. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
HI-Z
tCONV
DOUT
CS
SCLK
HI-Z
EOC
2ND BYTE READ
1ST BYTE READ
MAX187
MAX189
CS
SCLK
DOUT
I/O
SCK
MISO
+5V
SS
A. SPI
MAX187
MAX189
CS
SCLK
DOUT
CS
SCK
MISO
+5V
SS
B. QSPI
MAX187
MAX189
CS
SCLK
DOUT
I/O
SK
SI
C. MICROWIRE
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
15Maxim Integrated
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
Figure 16. 12-Bit Isolated ADC
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
HI-Z
tCONV
DOUT
CS
SCLK
HI-Z
EOC
MAX187
6N136
ANALOG
INPUT
SIGNAL
GROUND
4.7µF
5
4
2
1
6
8
7
3
10µF
0.1µF
GND
REF
AIN
VDD
DOUT
SCLK
CS
SHDN
+5V +5V ON THIS SIDE OF
BARRIER MUST BE ISOLATED POWER
7
8
1
+5V
2
6
5
3
4
3kI
200I
6N136
74HC04
74HC04
7
8
2
3
6
5
4
1
200I
8.2kI
6N136
1
2
6
7
3
5
4
8
3kI
470I
14
11
12
10
7
6
5
4
3
2
1
15
16
D11 (MSB)
D10
D9
D8
+5V
0.1µF
SER
SCK
RCK
SCLR
QH
SCLK/INPUT CLOCK
QG
QF
QE
QD
QC
QB
QA
13 8
9
74HC595
14
11
12
10
6
7
5
4
3
2
1
15
16
D3
D7
D6
D5
D4
D10
D1
D0 (LSB)
+5V
+5V
0.1µF
SER
SCK
RCK
SCLR
QH
QH’
QG
QF
QE
QD
QC
QB
QA
13 8
74HC595
CS/START
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
16Maxim Integrated
Layout, Grounding, Bypassing
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially
clock) lines parallel to one another, or digital lines under-
neath the ADC package.
Figure 17 shows the recommended system ground con-
nections. A single-point analog ground (“star” ground
point) should be established at GND, separate from the
logic ground. All other analog grounds should be con-
nected to this ground. The 16-pin versions also have a
dedicated DGND pin available. Connect DGND to this
star ground point for further noise reduction. No other
digital system ground should be connected to this single-
point analog ground. The ground return to the power
supply for this ground should be low impedance and as
short as possible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01FF
and 4.7FF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection. If the +5V power
supply is very noisy, a 10I resistor can be connected
as a lowpass filter to attenuate supply noise (Figure 17).
Figure 17. Power-Supply Grounding Condition
SUPPLIES
+5V GND
DGND+5V
DIGITAL
CIRCUITRY
DGNDAGNDVDD
MAX187
MAX189
*OPTIONAL
R* = 10I
4.7µF
0.01µF
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
17Maxim Integrated
Ordering Information
*Denotes a lead(Pb)–free/RoHS–compliant package.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS
status.
Chip Information
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 PDIP P8+3 21-0043 —
16 SO W16+3 21-0042 90-0107
PART TEMP RANGE PIN-
PACKAGE
ERROR
(LSB)
MAX187ACPA+ 0NC to +70NC8 PDIP ±1/2
MAX187BCPA+ 0NC to +70NC8 PDIP ±1
MAX187CCPA+ 0NC to +70NC8 PDIP ±2
MAX187ACWE+ 0NC to +70NC16 Wide SO ±1/2
MAX187BCWE+ 0NC to +70NC16 Wide SO ±1
MAX187CCWE+ 0NC to +70NC16 Wide SO ±2
MAX187AEPA+ -40NC to +85NC8 PDIP ±1/2
MAX187BEPA+ -40NC to +85NC8 PDIP ±1
MAX187CEPA+ -40NC to +85NC8 PDIP ±2
MAX187AEWE+ -40NC to +85NC16 Wide SO ±1/2
MAX187BEWE+ -40NC to +85NC16 Wide SO ±1
MAX187CEWE+ -40NC to +85NC16 Wide SO ±2
MAX189ACPA+ 0NC to +70NC8 PDIP ±1/2
MAX189BCPA+ 0NC to +70NC8 PDIP ±1
MAX189CCPA+ 0NC to +70NC8 PDIP ±2
MAX189ACWE+ 0NC to +70NC16 Wide SO ±1/2
MAX189BCWE+ 0NC to +70NC16 Wide SO ±1
MAX189CCWE+ 0NC to +70NC16 Wide SO ±2
MAX189AEPA+ -40NC to +85NC8 PDIP ±1/2
MAX189BEPA+ -40NC to +85NC8 PDIP ±1
MAX189CEPA+ -40NC to +85NC8 PDIP ±2
MAX189AEWE+ -40NC to +85NC16 Wide SO ±1/2
MAX189BEWE+ -40NC to +85NC16 Wide SO ±1
MAX189CEWE+ -40NC to +85NC16 Wide SO ±2
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 18
© 2012 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/93 Initial release —
1 3/12 Updated the Electrical Characteristics and Ordering Information.1, 3, 18
