LP3906SQ-VPFP/NOPB - NATIONAL SEMICONDUCTOR

VINLDO12

SYNC

VIN1

SW1

FB1

GND_SW1

VIN2

SW2

2.2 PH

10 PF

1 PF

10 PF

FB2

GND_SW2

AVDD

10 PF

1 PF

0.47 PF

1 PF

0.47 PF

GND_C

GND_L

SCL

SDA

LDO2

LDO1

VINLDO2

VINLDO1

ENSW2

ENSW1

ENLDO2

ENLDO1

EN_T

LP3906

DAP

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible

Interface

Check for Samples: LP3906

1FEATURES KEY SPECIFICATIONS

2• Compatible with Advanced Applications • DC/DC Converter (Buck)

Processors and FPGAs – 1.5A Output Current

• 2 LDOs for Powering Internal Processor – Programmable VOUT from:

Functions and I/Os – Buck1 : 0.8V–2.0V

• High Speed Serial Interface for Independent – Buck2 : 1.0V–3.5V

Control of Device Functions and Settings – Up to 96% Efficiency

• Precision Internal Reference – 2 MHz PWM Switching Frequency

• Thermal Overload Protection – ±3% Output Voltage Accuracy

• Current Overload Protection – Automatic Soft Start

• 24-lead 5 × 4 × 0.8 mm WQFN Package • Linear Regulators (LDO)

• Software Programmable Regulators – Programmable VOUT of 1.0V–3.5V

– ±3% Output Voltage Accuracy

APPLICATIONS – 300 mA Output Currents

• FPGA, DSP Core Power – 25 mW (Typ) Dropout

• Applications Processors

• Peripheral I/O Power DESCRIPTION

The LP3906 is a multi-function, programmable Power

Management Unit, optimized for low power FPGAs,

Microprocessors and DSPs.

Typical Application Circuits

Figure 1. Typical Application Circuit

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

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For information about how schottky diodes can reduce noise in high load, high Vin applications, see Buck Output

Ripple Management.

DESCRIPTION (CONTINUED)

This device integrates two highly efficient 1.5A Step-Down DC/DC converters with dynamic voltage management

(DVM), two 300mA Linear Regulators and a 400kHz I2C compatible interface to allow a host controller access to

the internal control registers of the LP3906. The LP3906 additionally features programmable power-on

sequencing and is offered in a tiny 5 x 4 x 0.8mm WQFN-24 pin package.

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OSC

Logic

Control

and

registers

I2C

GND_SW1

SW2

FB2

vref

GND_SW2

Cvdd

4.7 PF

VIN1

VIN2

SYNC

BUCK1

BUCK2

Lsw2 2.2 PH

SW1

FB1

LDO2

RESET

Clock

divider

LDO2

GND_C

BIAS

Thermal

Shutdown

Power On

Reset

Lsw1 2.2 PH

VINLDO1

20 19 23

VINLDO1

5417

AVDD

SDA

SCL

VBUCK2

LDO1LDO1

14 Cldo1

0.47 PF

VinLDO12

Csw2

10 PF

Csw1

10 PF

Cldo2

0.47 PF

Power

ON-OFF

Logic

FPGA

LP3906 PMIC

Flash

VBUCK1

EN_T10

ENLDO115

ENLDO216

GND_L

VINLDO2

VINLDO12

ENSW1

ENSW224

CPU

CORE

I/O

1.8V

1.2V

3.3V

VBUCK2 3.3V

VINLDO2

AVDD

10 PF

1 PF

DC SOURCE

4.5 ± 5.5V

Li-ion/polymer cell 3.6V - 4.2V

Programmable

Application

Processor

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

Figure 2. Typical Application Circuit

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1 2 3 4 5 6 7

13141516171819

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

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Connection Diagram

Figure 3. 24-Lead WQFN Package (Top View)

See Package Number NHZ0024B

Table 1. Default Voltage Options(1)(2)

Part Number Package Buck1 Buck2 LDO1 LDO2

Marking

LP3906SQ-DJXI/NOPB 06-DJXI 0.9V 1.8V 3.3V 1.8V

LP3906SQ-FXPI/NOPB 06-FXPI 1.0V 3.3V 2.5V 1.8V

LP3906SQ-JXXI/NOPB 06-JXXI 1.2V 3.3V 3.3V 1.8V

LP3906SQ-PPXP/NOPB 06-PPXP 1.5V 2.5V 3.3V 2.5V

LP3906SQ-TKXII/NOPB(3) 06-TKXII(3) 1.25V 3.3V 1.8V 1.8V

LP3906SQ-VPFP/NOPB 06-VPFP 1.8V 2.5V 1.5V 2.5V

LP3906SQE-PPXP/NOPB 06-PPXP 1.5V 2.5V 3.3V 2.5V

LP3906SQE-VPFP/NOPB 06-VPFP 1.8V 2.5V 1.5V 2.5V

LP3906SQX-DJXI/NOPB 06-DJXI 0.9V 1.8V 3.3V 1.8V

LP3906SQX-FXPI/NOPB 06-FXPI 1.0V 3.3V 2.5V 1.8V

LP3906SQX-JXXI/NOPB 06-JXXI 1.2V 3.3V 3.3V 1.8V

LP3906SQX-PPXP/NOPB 06-PPXP 1.5V 2.5V 3.3V 2.5V

LP3906SQX-TKXII/NOPB(3) 06-TKXII(3) 1.25V 3.3V 1.8V 1.8V

LP3906SQX-VPFP/NOPB 06-VPFP 1.8V 2.5V 1.5V 2.5V

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Option only available with default EN_T of 001; all other options use 010.

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Pin Descriptions(1)

Pin Name Pin No. I/O Type Description

VIN2 1 I PWR Power in from either DC source or Battery to Buck 2

SW2 2 O PWR Buck2 switcher output pin

GND_SW2 3 G G Buck2 NMOS Power Ground

GND_C 4 G G Non switching core ground pin

GND_SW1 5 G G Buck1 NMOS Power Ground

SW1 6 O PWR Buck1 switcher output pin

VIN1 7 I PWR Power in from either DC source or Battery to buck 1

SDA 8 I/O D I2C Data (Bidirectional)

SCL 9 I D I2C Clock

EN_T 10 I D Enable for preset power on sequence.

FB1 11 I A Buck1 input feedback terminal

AVDD 12 I PWR Analog Power for Buck converters.

VINLDO1 13 I PWR Power in from either DC source or Battery to input terminal of LDO1

LDO1 14 O PWR LDO1 Output

ENLDO1 15 I D LDO1 enable pin, a logic HIGH enables the LDO1

ENLDO2 16 I D LDO2 enable pin, a logic HIGH enables the LDO2

GND_L 17 G G LDO Ground

LDO2 18 O PWR LDO2 Output

VINLDO2 19 I PWR Power in from either DC source or battery to input terminal to LDO2

VinLDO12 20 I PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)

FB2 21 I A Buck2 input feedback terminal

ENSW1 22 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1

SYNC 23 I D Frequency Synchronization pin which allows the user to connect an external

clock signal PLL to synchronize the PMIC internal oscillator.

ENSW2 24 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2

DAP DAP GND GND Connection isn't necessary for electrical performance, but it is recommended

for better thermal dissipation.

(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)

VIN, SDA, SCL −0.3V to +6V

GND to GND SLUG ±0.3V

Power Dissipation (PD_MAX)

(TA=85°C, TMAX=125°C, )(4) 1.43 W

Junction Temperature (TJ-MAX) 150°C

Storage Temperature Range −65°C to +150°C

Maximum Lead Temperature (Soldering) 260°C

ESD Ratings

Human Body Model (5) 2 kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP −(θJA × PD-MAX). See APPLICATION

NOTES.

(5) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. (MILSTD - 883 3015.7)

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OPERATING RATINGS(1)(2)(3)

Bucks

VIN 2.7V to 5.5V

VEN 0 to (VIN + 0.3V)

Junction Temperature (TJ) Range −40°C to +125°C

Ambient Temperature (TA) Range(4) −40°C to +85°C

Thermal Properties(5)(6) (4)

Junction-to-Ambient Thermal Resistance

(θJA)NHZ0024B 28°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(4) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(5) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 160°C (typ.) and

disengages at TJ= 140°C (typ.)

(6) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP −(θJA × PD-MAX). See APPLICATION

NOTES.

GENERAL ELECTRICAL CHARACTERISTICS(1)(2)(3)(4)

Unless otherwise noted, VIN = 3.6V, Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.

Parameter Test Conditions Min Typ Max Units

VPOR Power-On Reset Threshold VDD Falling Edge 1.9 V

TSD Thermal Shutdown Threshold 160 °C

TSDH Themal Shutdown Hysteresis 20 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most

likely norm.

(4) This specification is ensured by design.

I2C COMPATIBLE INTERFACE ELECTRICAL SPECIFICATIONS(1)

Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C

Parameter Test Conditions Min Typ Max Units

FCLK Clock Frequency 400 kHz

tBF Bus-Free Time Between Start and Stop See(1) 1.3 µs

tHOLD Hold Time Repeated Start Condition See(1) 0.6 µs

tCLKLP CLK Low Period See(1) 1.3 µs

tCLKHP CLK High Period See(1) 0.6 µs

tSU Set Up Time Repeated Start Condition See(1) 0.6 µs

tDATAHLD Data Hold time See(1) 0 µs

tDATASU Data Set Up Time See(1) 100 ns

TSU Set Up Time for Start Condition See(1) 0.6 µs

TTRANS Maximum Pulse Width of Spikes that See(1)

Must be Suppressed by the Input Filter of 50 ns

Both DATA & CLK Signals.

(1) This specification is ensured by design.

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LOW DROP OUT REGULATORS, LDO1 AND LDO2

Unless otherwise noted, VIN = 3.6, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for

TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

+125°C. (1)(2) (3)(4)(5)(6) (7)

Parameter Test Conditions Min Typ Max Units

VIN Operational Voltage Range VINLDO1 and VINLDO2 PMOS 1.74 5.5 V

pins(8)

VOUT Accuracy Output Voltage Accuracy (Default VOUT) Load current = 1 mA −3 3 %

ΔVOUT Line Regulation VIN = (VOUT + 0.3V) to 5.0V, 0.15 %/V

(7), Load Current = 1 mA

Load Regulation VIN = 3.6V, 0.011 %/mA

Load Current = 1 mA to IMAX

ISC Short Circuit Current Limit LDO1-2, VOUT = 0V 500 mA

VIN – VOUT Dropout Voltage Load Current = 50 mA(5) 25 200 mV

PSRR Power Supply Ripple Rejection F = 10 kHz, Load Current = IMAX 45 dB

θn Supply Output Noise 10 Hz < F < 100 KHz 80 µVrms

IQ(6) (9) Quiescent Current “On” IOUT = 0 mA 40 µA

Quiescent Current “On” IOUT = IMAX 60 µA

Quiescent Current “Off” EN is de-asserted(10) 0.03 µA

TON Turn On Time Start up from shut-down 300 µs

COUT Output Capacitor Capacitance for stability 0°C ≤TJ0.33 0.47 µF

≤125°C

−40°C ≤TJ≤125°C 0.68 1.0 µF

ESR 5 500 mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(7) VIN minimum for line regulation values is 1.8V.

(8) Pins 13, 19 can operate from Vin min of 1.74 to a Vin max of 5.5V this rating is only for the series pass pmos power fet. It allows the

system design to use a lower voltage rating if the input voltage comes from a buck output.

(9) The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to

disable each block of the IC please contact the factory applications for IQ details.

(10) The Iq exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2µA

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SNVS456M –AUGUST 2006–REVISED MAY 2013

BUCK CONVERTERS SW1, SW2

Unless otherwise noted, VIN = 3.6, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in

normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

operation, −40°C to +125°C. (1) (2) (3) (4) (5)

Parameter Test Conditions Min Typ Max Units

VOUT Output Voltage Accuracy Default VOUT −3 +3 %

Line Regulation 2.7< VIN < 5.5 0.089 %/V

IO=10 mA

Load Regulation 100 mA < IO< IMAX 0.0013 %/mA

Eff Efficiency Load Current = 250 mA 96 %

ISHDN Shutdown Supply Current EN is de-asserted 0.01 µA

fOSC Sync Mode Clock Frequency Synchronized from 13 MHz system 2.0 MHz

clock

Internal Oscillator Frequency 2.0 MHz

IPEAK Peak Switching Current Limit 2.0 A

IQ(5) Quiescent Current “On” No load PFM Mode 33 µA

RDSON (P) Pin-Pin Resistance PFET 200 mΩ

RDSON (N) Pin-Pin Resistance NFET 180 mΩ

TON Turn On Time Start up from shut-down 500 µs

CIN Input Capacitor Capacitance for stability 10 µF

COOutput Capacitor Capacitance for stability 10 µF

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to

disable each block of the IC please contact the factory applications for IQ details.

I/O ELECTRICAL CHARACTERISTICS

Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface

type apply over the entire junction temperature range for operation, TJ= 0°C to +125°C. (1)

Limit

Parameter Test Conditions Units

Min Max

VIL Input Low Level 0.4 V

VIH Input High Level 1.2 V

(1) This specification is ensured by design.

Product Folder Links: LP3906

TEMPERATURE (°C)

VOUT CHANGE (%)

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

VOUT CHANGE (%)

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO

TA= 25°C unless otherwise noted

Output Voltage Change Output Voltage Change

vs vs

Temperature (LDO1) Temperature (LDO2)

Vin = 4.3V, Vout = 3.3V, 100 mA load Vin = 4.3V, Vout = 1.8V, 100 mA load

Figure 4. Figure 5.

Load Transient (LDO1) Load Transient (LDO2)

3.6 Vin, 3.3 Vout, 0 – 100 mA load 3.6 Vin, 1.8 Vout, 0 – 100 mA load

Figure 6. Figure 7.

Line Transient (LDO1) Line Transient (LDO2)

3.6 - 4.5 Vin, 3.3 Vout, 150 mA load 3 – 4.2 Vin, 1.8 Vout, 150 mA load

Figure 8. Figure 9.

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued)

TA= 25°C unless otherwise noted

Enable Start-up time (LDO1) ) Enable Start-up time (LDO2)

0-3.6 Vin, 3.3 Vout, 1mA load 0 – 3.6 Vin, 1.8 Vout, 1 mA load

Figure 10. Figure 11.

Product Folder Links: LP3906

10-3 10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 3.6V

VIN = 2.8V

10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 2.8V

VIN = 3.6V

VIN = 5.5V

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

1.835

1.830

1.825

1.820

1.815

1.810

1.805

1.800

2.5 3.0 3.5 4.0 4.5 5.0 5.5

IOUT = 20 mA

IOUT = 750 mA

IOUT = 1.5 A

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.550

3.540

3.530

3.520

3.510

3.500

3.490

4.0 4.5 5.0 5.5

IOUT = 20 mA

IOUT = 750 mA

IOUT = 1.5A

TEMPERATURE (°C)

SHUTDOWN CURRENT (éA)

0.15

0.12

0.09

0.06

0.03

0.00

-40 -20 0 20 40 60 80

VIN = 2.7V

VIN = 3.6V

VIN = 5.5V

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

1.040

1.035

1.030

1.025

1.020

1.015

1.010

1.005

1.000

0.995

0.990

2.5 3.0 3.5 4.0 4.5 5.0 5.5

IOUT = 20 mA

IOUT = 750 mA

IOUT = 1.5A

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK

TA= 25°C unless otherwise noted

Output Voltage

Shutdown Current vs.

vs. Supply Voltage

Temp (Vout = 1.0 V)

Figure 12. Figure 13.

Output Voltage Output Voltage

vs. vs.

Supply Voltage Supply Voltage

(Vout = 1.8V) (Vout = 3.5V)

Figure 14. Figure 15.

Buck 1 Efficiency Buck 1 Efficiency

vs vs

Output Current Output Current

(Forced PWM Mode, Vout =1.2V, L= 2.2µH) (Forced PWM Mode, Vout =2.0V, L= 2.2µH)

Figure 16. Figure 17.

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10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 4.3V

10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 4.3V

10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 4.3V

10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 4.3V

10-3 10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 5.5V

VIN = 3.6V

VIN = 2.8V

10-2 10-1 100101102103104

OUTPUT CURRENT (mA)

100

EFFICIENCY (%)

VIN = 2.8V

VIN = 5.5V

VIN = 3.6V

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SNVS456M –AUGUST 2006–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

TA= 25°C unless otherwise noted

Buck 1 Efficiency Buck 1 Efficiency

vs vs

Output Current Output Current

(PFM to PWM mode, Vout =1.2V, L= 2.2µH) (PFM to PWM mode, Vout =2.0V, L= 2.2µH)

Figure 18. Figure 19.

Buck 2 Efficiency Buck 2 Efficiency

vs vs

Output Current Output Current

(Forced PWM Mode, Vout =1.8V, L= 2.2µH) (Forced PWM Mode, Vout =3.3V, L= 2.2µH)

Figure 20. Figure 21.

Buck 2 Efficiency Buck 2 Efficiency

vs vs

Output Current Output Current

(PFM to PWM Mode, Vout =1.8V, L= 2.2µH) (PFM to PWM Mode, Vout =3.3V, L= 2.2µH)

Figure 22. Figure 23.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

TA= 25°C unless otherwise noted

Load Transient Response Mode Change by Load Transient

Vout = 1.2 (PWM Mode) Vout = 1.2V (PWM to PFM)

Figure 24. Figure 25.

Line Transient Response Line Transient Response

Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load Vin = 3 – 3.6 V, Vout = 3.3 V, 250 mA load

Figure 26. Figure 27.

Start up into PWM Mode Start up into PWM Mode

Vout = 1.8 V, 1.2 A load Vout = 3.3 V, 1.2 A load

Figure 28. Figure 29.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

TA= 25°C unless otherwise noted

Start up into PFM Mode Start up into PFM Mode

Vout = 1.8 V, 30 mA load Vout = 3.3 V, 30 mA load

Figure 30. Figure 31.

Product Folder Links: LP3906

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HIGH VIN-HIGH LOAD OPERATION

Additional information is provided when the IC is operated at extremes of Vin and regulator loads. These are

described in terms of the Junction Temperature and Buck Output Ripple Management.

Junction Temperature

The maximum junction temperature TJ-MAX-OP of 125ºC of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and

Total chip power must be controlled to keep TJ below this maximum:

TJ-MAX-OP = TA-MAX + (θJA) [ °C/ Watt] * (PD-MAX) [Watts]

Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a

minor amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.

PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * Vin) [Watts].

Power dissipation of LDO1

PLDO1 = (VinLDO1- VoutLDO1) * IoutLDO1 [V*A]

Power dissipation of LDO2

PLDO2 = (VinLDO2 - VoutLDO2) * IoutLDO2 [V*A]

Power dissipation of Buck1

PBuck1 = PIN – POUT =

VoutBuck1* IoutBuck1 * (1 -η1) / η1[V*A]

η1= efficiency of buck 1

Power dissipation of Buck2

PBuck2 = PIN – POUT =

VoutBuck2 * IoutBuck2 * (1 - η2) / η2[V*A]

η2= efficiency of buck 2

ηis the efficiency for the specific condition taken from efficiency graphs.

Buck Output Ripple Management

If Vin and ILoad increase, the output ripple associated with the Buck Regulators also increases. Figure 32 shows

the safe operating area. To ensure operation in the area of concern it is recommended that the system designer

circumvents the output ripple issues to install schottky diodes on the Bucks(s) that are expected to perform under

these extreme corner conditions.

(Schottky diodes are recommended to reduce the output ripple if the system requirements include this shaded

area of operation. Vin > 5.2 V and Iload > 1.24 A)

Product Folder Links: LP3906

0 0.5 1.0 1.5

LOAD CURRENT (A)

3.0

3.5

4.0

4.5

5.0

5.5

VIN (V)

LP3906

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Figure 32. LP3906 Buck Converter

VIN vs ILOAD Operating Ranges

Thermal Performance of the WQFN Package

The LP3906 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (θJA) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although

thicker copper may be used to further improve thermal performance. The LP3906 die attach pad is connected to

the substrate of the IC and therefore, the thermal land and vias on the PCB board need to be connected to

ground (GND pin).

For more information on board layout techniques, refer to Application Note AN–1187 (Literature Number

SNOA401) “Leadless Lead frame Package (WQFN).” This application note also discusses package handling,

solder stencil and the assembly process.

DC/DC Converters

OVERVIEW

The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators

LDO1 and LDO2 and two Buck converters SW1 and SW2. The table here under lists the output characteristics of

the various regulators.

Product Folder Links: LP3906

VIN

ENLDO

VLDO

GND

Vref

LDO

controlled

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Table 2. SUPPLY SPECIFICATION

Output

Supply Load IMAX

VOUT Range(V) Resolution (mV) Maximum Output Current (mA)

LDO1 analog 1.0 to 3.5 100 300

LDO2 analog 1.0 to 3.5 100 300

SW1 digital 0.8 to 2.0 50 1500

SW2 digital 1.0 to 3.5 100 1500

LINEAR LOW DROP-OUT REGULATORS (LDOS)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

programmed during Final Test, which can be tailored to the specific needs of the system designer.

NO-LOAD STABILITY

The LDOs will remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example CMOS RAM keep-alive applications.

LDO1 AND LDO2 CONTROL REGISTERS

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both

LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is

also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the

SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters

FUNCTIONAL DESCRIPTION

The LP3906 incorporates two high efficiency synchronous switching buck regulators, SW1 and SW2 that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1500mA depending on the

input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability).

There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70mA or higher, delivering voltage precision of +/-3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (IQ= 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering

the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced

through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

Product Folder Links: LP3906

VIN

160:

IMODE < 66 mA )

(Typically +

-VOUT

VIN - VOUT

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Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload

protection.

CIRCUIT OPERATION DESCRIPTION

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

(1)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

PWM OPERATION

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input

voltage is introduced.

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

CURRENT LIMITING

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is

shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration

until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby

preventing runaway.

A current limit feature allows the buck to protect itself and external components during overload conditions PWM

mode implements cycle-by-cycle current limiting using an internal comparator that trips at 2000mA (typical).

PFM OPERATION

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

1. The inductor current becomes discontinuous

2. The peak PMOS switch current drops below the IMODE level

(3)

Product Folder Links: LP3906

High PFM Threshold

~1.016 * Vout

Low1 PFM Threshold

~1.008 * Vout

PFM Mode at Light Load

PWM Mode at

Moderate to Heavy

Loads

Pfet on

until

Ipfm limit

reached

Nfet on

drains

inductor

current

until

I inductor = 0

High PFM

Voltage

Threshold

reached,

go into

sleep mode

Low PFM

Threshold,

turn on

PFET

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

Low2 PFM Threshold,

switch back to PWMmode

Load current

increases

Low2 PFM Threshold

Vout

Z-

Axis

VIN

80:

IPFM = 66 mA +

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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output

voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level

set for PFM mode. The typical peak current in PFM mode is:

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the ‘high’ PFM comparator threshold (see Figure 33), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM

threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output

switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage

to ~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see Figure 33) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

SW1, SW2 OPERATION

SW1 and SW2 have selectable output voltages ranging from 0.8V to 3.5V (typ.). Both SW1 and SW2 in the

LP3906 are I2C register controlled and are enabled by default through the internal state machine of the LP3906

following a Power-On event that moves the operating mode to the Active state. (see POWER ON). The SW1 and

SW2 output voltages revert to default values when the power on sequence has been completed. The default

output voltage for each buck converter is factory programmable. (See APPLICATION NOTES).

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I2C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

Figure 33.

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SHUTDOWN MODE

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended to disable the converter during the system power up and under voltage conditions

when the supply is less than 2.8V.

SOFT START

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing start-up stresses and surges. The two LP3906 buck converters have a soft-start circuit that limits in-

rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated

only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch current limit). The start-up time

thereby depends on the output capacitor and load current demanded at start-up.

LOW DROPOUT OPERATION

The LP3906 can operate at 100% duty cycle (noswitching; PMOS switch completely on) for low drop out support

of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum

input voltage needed to support the output voltage is:

VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT

Where:

ILOAD Load current

RDSON, PFET Drain to source resistance of

PFET switch in the triode region

RINDUCTOR Inductor resistance

FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES

The LP3906 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, all four enables should be tied LOW so that the regulators don’t

automatically enable when power is supplied. The user can then program the chip through I2C and raise EN_T

from LOW to HIGH to activate the power on sequencing.

POWER ON

EN_T assertion causes the LP3906 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks are internally pulled up, which causes the part to turn

ON automatically. If the user wishes to have a preset timing sequence to power on the regulators, the external

regulator enables must be tied LOW. Otherwise, simply tie the enables of each specific regulator HIGH.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the

default is set at 1 ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power on sequence, while

a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators will have no effect on the chip.

Table 3. Default Power ON Sequence:

t1(ms) t2(ms) t3(ms) t4(ms)

1.5 2.0 3 6

Product Folder Links: LP3906

EN_T

Vout Buck1

Vout Buck2

Vout LDO1

Vout LDO2

I2C

EN_T

Ext Enable

Pins

Regulator ON

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NOTE

LP3906 The default Power on delays can be reprogrammed at final test or by using I2C

registers to 1, 1.5, 2, 3, 6, or 11 ms.

The regulators can also be programmed through I2C to turn on and off. By default, the I2C enables for the

regulators are ON.

The regulators are on following the pattern below:

Regulators on = (I2C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after VIN is applied to

the device. However, VIN must be stable for approximately 8ms minimum before EN_T be

asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power-on for

power sequencing function to operate properly.

LP3906 Default Power-Up Sequence

Table 4. Power-On Timing Specification

Symbol Description Min Typ Max Units

t1Programmable Delay from EN_T assertion to VCC_Buck1 On 1.5 ms

t2Programmable Delay from EN_T assertion to VCC_Buck2 On 2 ms

t3Programmable Delay from EN_T assertion to VCC_LDO1 On 3 ms

t4Programmable Delay from EN_T assertion to VCC_LDO2 On 6 ms

Product Folder Links: LP3906

EN_T

Vout Buck1

Vout Buck2

Vout LDO1

Vout LDO2

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NOTE

LP3906 The default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2,

3, 6, or 11 ms.

LP3906 Default Power-Off Sequence

Symbol Description Min Typ Max Units

t1Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms

t2Programmable Delay from EN_T deassertion to VCC_Buck2 Off 2 ms

t3Programmable Delay from EN_T deassertion to VCC_LDO1 Off 3 ms

t4Programmable Delay from EN_T deassertion to VCC_LDO2 Off 6 ms

NOTE

LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or

10 ms. Default setting is the same as the on sequence.

Power-On-Reset

The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD <

VPOR. This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of

the Logic and the internal oscillator that clocks the Sequential Logic in the Control section.

I2C Compatible Serial Interface

I2C SIGNALS

The LP3906 features an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock

and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3906

interface is an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See

I2C specification from Philips for further details.

Product Folder Links: LP3906

ADR6

bit7

MSB

ADR5

bit6 ADR4

bit5 ADR3

I2C SLAVE address (chip address)

ADR2

bit3 ADR1

bit2 ADR0

bit1 R/W

bit0

LSB

1 1 0 0 0 0 0

bit4

SDA

SCL S P

START condition STOP condition

SCL

SDA

data

change

allowed

data

valid data

change

allowed

data

valid data

change

allowed

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I2C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

Figure 34. I2C Signals: Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 35. START and STOP Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been

addressed must generate an acknowledgement (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). Please note that according to industry I2C standards for 7-bit

addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most

significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte

selects the register to which the data will be written. The third byte contains data to write to the selected register.

LP3906 has a chip address of 60’h, which is factory programmed.

Figure 36. I2C Chip Address

Product Folder Links: LP3906

ack from slave

w ackstart msb Chip Address lsb msb Register Add lsb msb DATA lsback ack stop

ack from slave ack from slave

SCL

start id = K¶60 w ack register addr = K¶10 GDWDDGGUK¶6Aack ack stop

SDA

rs msb Chip Address lsb r ack

repeated start data from slave ack from master

rid = K¶60ack rs

SCL

SDA

start id = K¶60 w ack addr = K¶02 DGGUHVVK¶$$GDWDack ack stop

ack from slave

w ackstart msb Chip Address lsb msb Register Add lsb msb DATA lsback ack stop

ack from slave ack from slave

123 4 5 6 7 8 9 1 2 3 ...

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w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3906 chip address : 0x60

Figure 37. I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 38. I2C Read Cycle

LP3906 Control Registers

0x02 ICRA R Interrupt Status Register A

0x07 SCR1 R/W System Control 1 Register

0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register

0x11 BKLDOSR R Buck and LDO Output Voltage Status Register

0x20 VCCR R/W Voltage Change Control Register 1

0x23 B1TV1 R/W Buck 1 Target Voltage 1 Register

0x24 B1TV2 R/W Buck 1 Target Voltage 2 Register

0x25 B1RC R/W Buck 1 Ramp Control

0x29 B2TV1 R/W Buck 2 Target Voltage 1 Register

0x2A B2TV2 R/W Buck 2 Target Voltage 2 Register

0x2B B2RC R/W Buck 2 Ramp Control

0x38 BFCR R/W Buck Function Register

0x39 LDO1VCR R/W LDO1 Voltage control Registers

0x3A LDO2VCR R/W LDO2 Voltage control Registers

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INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the user of the temperature status of the chip.

D7-2 D1 D0

Name — Temp 125°C —

Access — R —

Data Reserved Status bit for thermal warning PMIC T>125°C Reserved

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reset 0 0 0

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through

assertion of the EN_T pin.

D7 D6-4 D3 D2 D1 D0

Name — EN_DLY — FPWM2 FPWM1 ECEN

Access — R/W — R/W R/W R/W

Data Reserved Selects the preset Reserved Buck 2 PWM /PFM Buck 1 PWM /PFM External Buck Clock

delay sequence from Mode select Mode select Select

EN_T assertion 0 – Auto Switch PFM - 0 – Auto Switch PFM - 0 – Internal 2 MHz

(shown below) PWM operation PWM operation Oscillator clock

1 – PWM Mode Only 1 – PWM Mode Only 1 – External 13 MHz

Oscillator clock

Reset 0 010 1 0 0 0

EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0> Buck1 Buck2 LDO1 LDO2

000 1111

001 1 1.5 2 2

010 1.5 2 3 6

011 1.5 2 1 1

100 1.5 2 3 6

101 1.5 1.5 2 2

110 3 2 1 1.5

111 2 3 6 11

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

D7 D6 D5 D4 D3 D2 D1 D0

Name — LDO2EN — LDO1EN — BK2EN — BK1EN

Access — R/W — R/W — R/W — R/W

Data Reserved 0 – Disable Reserved 0 – Disable Reserved 0 – Disable Reserved 0 – Disable

1 – Enable 1 – Enable 1 – Enable 1 – Enable

Reset01110101

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BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7 D6 D5 D4 D3 D2 D1 D0

Name BKS_OK LDOS_OK LDO2_OK LDO1_OK — BK2_OK — BK1_OK

Access R R R R — R — R

Data 0 – Buck 1-2 0 – LDO 1-2 0 – LDO2 Not 0 – LDO1 Not Reserve 0 – Buck2 Not Reserve 0 – Buck1 Not

Not Valid Not Valid Valid Valid d Valid d Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid 1 – Buck2 Valid 1 – Buck1 Valid

Reset 0 0 0 0 0 0 0 0

BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20

This register selects and controls the output target voltages for the buck regulators.

D7-6 D5 D4 D3-2 D1 D0

Name — B2VS B2GO — B1VS B1GO

Access — R/W R/W — R/W R/W

Data Reserved Buck2 Target Voltage Buck2 Voltage Ramp Reserved Buck1 Target Voltage Buck1 Voltage Ramp

Select CTRL Select CTRL

0 – B2VT1 0 – Hold 0 – B1VT1 0 – Hold

1 – B2VT2 1 – Ramp to B2VS 1 – B1VT2 1 – Ramp to B1VS

selection selection

Reset 00 0 0 00 0 0

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BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23

This register allows the user to program the output target voltage of Buck 1.

D7-5 D4-0

Name — BK1_VOUT1

Access — R/W

Data Reserved Buck1 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 0.80

5’h02 0.85

5’h03 0.90

5’h04 0.95

5’h05 1.00

5’h06 1.05

5’h07 1.10

5’h08 1.15

5’h09 1.20

5’h0A 1.25

5’h0B 1.30

5’h0C 1.35

5’h0D 1.40

5’h0E 1.45

5’h0F 1.50

5’h10 1.55

5’h11 1.60

5’h12 1.65

5’h13 1.70

5’h14 1.75

5’h15 1.80

5’h16 1.85

5’h17 1.90

5’h18 1.95

5’h19 2.00

5’h1A–5’h1F 2.00

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

BUCK 1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24

This register allows the user to program the output target voltage of Buck 1.

D7-5 D4-0

Name — BK1_VOUT2

Access — R/W

Data Reserved Buck1 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 0.80

5’h02 0.85

5’h03 0.90

5’h04 0.95

5’h05 1.00

5’h06 1.05

5’h07 1.10

5’h08 1.15

5’h09 1.20

5’h0A 1.25

5’h0B 1.30

5’h0C 1.35

5’h0D 1.40

5’h0E 1.45

5’h0F 1.50

5’h10 1.55

5’h11 1.60

5’h12 1.65

5’h13 1.70

5’h14 1.75

5’h15 1.80

5’h16 1.85

5’h17 1.90

5’h18 1.95

5’h19 2.00

5’h1A–5’h1F 2.00

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

LP3906

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BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck 1.

D7 D6-4 D3-0

Name - - - - - - - - B1RS

Access - - - - - - - - R/W

Data Reserved Reserved Data Code Ramp Rate mV/us

4h'0 Instant

4h'1 1

4h'2 2

4h'3 3

4h'4 4

4h'5 5

4h'6 6

4h'7 7

4h'8 8

4h'9 9

4h'A 10

4h'B - 4h'F 10

Reset 0 010 1000

Product Folder Links: LP3906

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29

This register allows the user to program the output target voltage of Buck 2.

D7-5 D4-0

Name — BK2_VOUT1

Access — R/W

Data Reserved Buck2 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 1.0

5’h02 1.1

5’h03 1.2

5’h04 1.3

5’h05 1.4

5’h06 1.5

5’h07 1.6

5’h08 1.7

5’h09 1.8

5’h0A 1.9

5’h0B 2.0

5’h0C 2.1

5’h0D 2.2

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

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BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A

This register allows the user to program the output target voltage of Buck 2.

D7-5 D4-0

Name — BK2_VOUT2

Access — R/W

Data Reserved Buck2 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 1.0

5’h02 1.1

5’h03 1.2

5’h04 1.3

5’h05 1.4

5’h06 1.5

5’h07 1.6

5’h08 1.7

5’h09 1.8

5’h0A 1.9

5’h0B 2.0

5’h0C 2.1

5’h0D 2.2

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

2 MHz

Clock Frequency

Time

Spread Spectrum

frequency

10 kHz triangle

wave

Peak frequency deviation

2 kHz triangle

wave

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

BUCK 2 RAMP CONTROL REGISTER (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck 2

D7 D6-4 D3-0

Name - - - - - - - - B2RS

Access - - - - - - - - R/W

Data Reserved Reserved Data Code Ramp Rate mV/us

4h'0 Instant

4h'1 1

4h'2 2

4h'3 3

4h'4 4

4h'5 5

4h'6 6

4h'7 7

4h'8 8

4h'9 9

4h'A 10

4h'B - 4h'F 10

Reset 0 010 1000

BUCK FUNCTION REGISTER (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2 MHz.

D7-2 D1 D0

Name — BK_SLOMOD BK_SSEN

Access — R/W R/W

Data Reserved Buck Spread Spectrum Modulation Spread Spectrum Function Output

0 – 10 kHz triangular wave 0 – Disabled

1 – 2 kHz triangular wave 1 – Enabled

Reset 000010 1 0

Product Folder Links: LP3906

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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39

This register allows the user to program the output target voltage of LDO 1.

D7-5 D4-0

Name — LDO1_OUT

Access — R/W

Data Reserved LDO1 Output voltage (V)

5’h00 1.0

5’h01 1.1

5’h02 1.2

5’h03 1.3

5’h04 1.4

5’h05 1.5

5’h06 1.6

5’h07 1.7

5’h08 1.8

5’h09 1.9

5’h0A 2.0

5’h0B 2.1

5’h0C 2.2

5’h0D 2.3

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A

This register allows the user to program the output target voltage of LDO 2.

D7-5 D4-0

Name — LDO2_OUT

Access — R/W

Data Reserved LDO2 Output voltage (V)

5’h00 1.0

5’h01 1.1

5’h02 1.2

5’h03 1.3

5’h04 1.4

5’h05 1.5

5’h06 1.6

5’h07 1.7

5’h08 1.8

5’h09 1.9

5’h0A 2.0

5’h0B 2.1

5’h0C 2.2

5’h0D 2.3

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory Programmed Default

Product Folder Links: LP3906

where Iripple = VIN - VOUT

x x VOUT

VIN ¹

§¹

·©

§¹

Isat > Ioutmax + Iripple

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

www.ti.com

APPLICATION NOTES

SYSTEM CLOCK INPUT (SYNC) PIN

Pin 23 of the chip allows for a system clock input in order to synchronize the buck converters in PWM mode. This

is useful if the user wishes to force the bucks to work synchronously with the system. Otherwise, the user should

tie the pin to GND and the bucks will operate on an internal 2 MHz clock.

The signal applied to the SYNC pin must be 13 MHz as per application processor specifications, but we can be

contacted to modify that specification if so desired. Upon inputting the 13 MHz clock signal, the bucks will scale it

down and continue to run at 2 MHz based off the 13 MHz clock.

ANALOG POWER SIGNAL ROUTING

All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from

another source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.7 and 5.5 V, as specified on pg. 6 of the datasheet.

The other VINs (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.7V, as long as it's higher

than the programmed output (+0.3V, to be safe).

The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.

COMPONENT SELECTION

Inductors for SW1 and SW2

There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

Method 1

The saturation current is greater than the sum of the maximum load current and the worst case average to peak

inductor current. This can be written as follows:

(5)

IRIPPLE:Average to peak inductor current

IOUTMAX:Maximum load current

VIN:Maximum input voltage to the buck

L: Min inductor value including worse case tolerances (30% drop can be considered for method 1)

f: Minimum switching frequency (1.6 MHz)

VOUT:Buck Output voltage

Method 2

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 2375 mA.

Given a peak-to-peak current ripple (IPP) the inductor needs to be at least:

Product Folder Links: LP3906

L tVIN - VOUT

IPP xx VOUT

VIN ¹

§f

§¹

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

(6)

Inductor Value Unit Description Notes

LSW1,2 2.2 µH SW1,2 inductor D.C.R. 70 mΩ

External Capacitors

The regulators on the LP3906 require external capacitors for regulator stability. These are specifically designed

for portable applications requiring minimum board space and smallest components. These capacitors must be

correctly selected for good performance.

LDO CAPACITOR SELECTION

Input Capacitor

An input capacitor is required for stability. It is recommended that a 1.0 μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

approximately 1.0 μF over the entire operating temperature range.

Output Capacitor

The LDOs on the LP3906 are designed specifically to work with very small ceramic output capacitors. A 1.0 µF

ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩto 500 mΩ, are suitable in the

application circuit.

It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩto 500 mΩfor stability.

Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩto 40 mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, the graph below shows a typical graph comparing different

capacitor case sizes in a Capacitance vs. DC Bias plot.

Product Folder Links: LP3906

(Vin ± Vout) x Vout

L x f x Ioutmax x Vin

where r =

Irms = Ioutmax VOUT

VIN 12

+1 - ¹

§VOUT

VIN

0402, 6.3V, X5R

0603, 10V, X5R

0 1.0 2.0 3.0 4.0 5.0

DC BIAS (V)

20%

40%

60%

80%

100%

CAP VALUE (% of NOMINAL 1 PF)

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

www.ti.com

Figure 39. Graph Showing a Typical Variation in Capacitance vs. DC Bias

As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R

has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic

capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance

can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over

Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Input Capacitor Selection for SW1 and SW2

A ceramic input capacitor of 10 µF, 6.3V is sufficient for the magnetic dc/dc converters. Place the input capacitor

as close as possible to the input of the device. A large value may be used for improved input voltage filtering.

The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the dc/dc converter in the first half of each cycle and

reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series

Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor

with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:

(7)

The worse case is when VIN = 2VOUT

Product Folder Links: LP3906

Vpp-rms = Vpp-c2 + Vpp-esr2

Iripple

4 x f x C

Vpp-c =

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

Output Capacitor Selection for SW1, SW2

A 10 µF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters.

The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic dc/dc converter smoothes out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these

functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

(8)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

VPP–ESR = 2 × IRIPPLE × RESR (9)

Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

(10)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent.

The RESR should be calculated with the applicable switching frequency and ambient temperature.

Capacitor Min Value Unit Description Recommended Type

CLDO1 0.47 µF LDO1 output capacitor Ceramic, 6.3V, X5R

CLDO2 0.47 µF LDO2 output capacitor Ceramic, 6.3V, X5R

CSW1 10.0 µF SW1 output capacitor Ceramic, 6.3V, X5R

CSW2 10.0 µF SW2 output capacitor Ceramic, 6.3V, X5R

I2C Pullup Resistor

Both I2C_SDA and I2C_SCL terminals need to have pullup resistors connected to VINLDO12 or to the power

supply of the I2C master. The values of the pull-up resistors (typ. ∼1.8kΩ) are determined by the capacitance of

the bus. Too large of a resistor combined with a given bus capacitance will result in a rise time that would violate

the max. rise time specification. A too small resistor will result in a contention with the pull-down transistor on

either slave(s) or master.

Operation without I2C Interface

Operation of the LP3906 without the I2C interface is possible if the system can operate with default values for the

LDO and Buck regulators. (See Factory Programmable Options .) The I2C-less system must rely on the correct

default output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final test of the LP3906. The system designer that needs

specific options is advised to contact the local Texas Instruments sales office.

Factory programmable options Current value

Enable delay for power on code 010 (see BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20)

SW1 ramp speed 8 mV/µs

SW2 ramp speed 8 mV/µs

Product Folder Links: LP3906

03.5 4.0 4.5

VIN (V)

1.0

1.5

2.0

2.5

3.0

3.5

VOUT (V)

5.5

5.0

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

www.ti.com

The I2C Chip ID address is offered as a metal mask option. The current value equals 0x60.

MODE BOUNCE

PFM-PWM transition at low load current.

To improve efficiency at lower load currents LP3906 buck converters employ an automatically invoked PFM

mode for the low load operation. The PFM mode operates with a much lower value quiescent current (IQ) than

the PWM mode of operation that is used in the higher load currents.

As shown in the datasheet section about SW operation, there is a DC voltage difference between the two modes

of operation, with Vout PFM being typically 1.2% higher than Vout PWM. So there is a DC voltage level transition

and some associated dynamic perturbation at the mode transition point.

The transition between the two modes of operation has an associated hysterisis in the transition current value,

That is, the transition point for increasing current (PFM to PWM) is at a higher value that the decreasing current

(PWM to PFM). This hysterisis is to ensure that in the event that the load current values equals the PFM PWM

transition value, the device will not make multiple transitions between modes; this reduces the noise at this load

by eliminating multiple transitions between modes (also known as mode bounce).

Under some conditions of high Vin and Low Vout the hystersis value is reduced and some amount of mode

bounce can occur. Under these conditions, the regulator still maintains DC regulation, however the output ripple

is more pronounced. Refer to the attached Vout vs Vin chart below that shows the operational area that may

exhibit this increased output ripple. If the application is expected to be operated in the area of concern AND have

a static load current of the transition current value, the user can avoid the possible noise increase by invoking the

components’ “Force PWM mode”.

Figure 40. LP3906 Buck Converter

VOUT vs VIN Operating Range

during PFM-PWM-PPM Transition

Product Folder Links: LP3906

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

REVISION HISTORY

Changes from Revision L (May 2013) to Revision M Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 40

Product Folder Links: LP3906

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3906SQ-DJXI/NOPB ACTIVE WQFN NHZ 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 06-DJXI

LP3906SQ-FXPI/NOPB ACTIVE WQFN NHZ 24 1000 RoHS & Green SN Level-1-260C-UNLIM 06-FXPI

LP3906SQ-JXXI/NOPB ACTIVE WQFN NHZ 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 06-JXXI

LP3906SQ-VPFP/NOPB ACTIVE WQFN NHZ 24 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 06-VPFP

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3906SQ-DJXI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

LP3906SQ-FXPI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

LP3906SQ-JXXI/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

LP3906SQ-VPFP/NOPB WQFN NHZ 24 1000 178.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3906SQ-DJXI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0

LP3906SQ-FXPI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0

LP3906SQ-JXXI/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0

LP3906SQ-VPFP/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Sep-2018

Pack Materials-Page 2

MECHANICAL DATA

NHZ0024B

www.ti.com

SQA24B (Rev A)

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