LOW SKEW , 1-T O-2 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER ICS85411
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 1 ICS8541 1AM REV. C JANUARY 20, 2009
GENERAL DESCRIPTION
The ICS85411 is a low skew, high performance
1-to-2 Differential-to-LVDS Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The CLK,
nCLK pair can accept most standard differential in-
put levels.The ICS85411 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS85411 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
FEATURES
•Two differential LVDS outputs
•One differential CLK, nCLK clock input
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•Maximum output frequency: 650MHz
•Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
•Output skew: 20ps (maximum)
•Part-to-part skew: 250ps (maximum)
•Additive phase jitter, RMS: 0.05ps (typical)
•Propagation delay: 2.5 ns (maximum)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead free (RoHS 6)
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85411
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
ICS
VDD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
Pulldown
Pullup
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 2 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 3 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C
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NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±10%, TA = 0°C TO 70°C
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θ
JA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 4 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±10% TA = 0°C TO 70°C
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IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 5 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ADDITIVE PHASE JITTER
Input/Output Additive Phase
Jitter @ 200MHz (12kHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M 500M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 6 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVDS
3.3V±10%
POWER SUPPLY
+–
Float GND
VDD
PART-TO-PART SKEW
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
PROPAGATION DELAY OUTPUT RISE/FALL TIME
20%
80% 80%
20%
t
R
t
F
V
OD
tsk(o)
Qx
Qy
OUTPUT SKEW
t
PD
nQx
nQy
Q0, Q1
nQ0, nQ1
CLK
nCLK
tsk(pp)
PART 1
PART 2
Qx
Qy
nQx
nQy
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Q0, Q1
nQ0, nQ1
DIFFERENTIAL OUTPUT VOLTAGE SETUP
➤
➤
➤
100
out
out
LVD S
DC Input VOD/Δ VOD
VDD
Q0, Q1
nQ0, nQ1
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 7 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER OFF LEAKAGE SETUP
OFFSET VOLTAGE SETUP
OUTPUT SHORT CIRCUIT CURRENT SETUP DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
out
out
LVD S
DC Input
➤
➤
➤
V
OS
/Δ V
OS
V
DD
out
out
LVDS
DC Input
➤
I
OSD
V
DD
out
LVDS
DC Input
➤
IOS
➤
IOSB
VDD
out
LVDS
➤
I
OFF
V
DD
PARAMETER MEASUREMENT INFORMATION, CONTINUED
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 8 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Cl ock I nput CLK
nCLK
VDD
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there
should be no trace attached.
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 9 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in
Figure
2A,
the input termination applies for IDT HiPerClockS LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driver
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 10 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVDS DRIVER T ERMINATION
A general LVDS interface is shown in
Figure 3.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near the
receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate
the unused outputs.
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 11 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85411.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85411 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
•Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 50mA = 181.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.182W * 103.3°C/W = 88.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (multi-layer).
TABLE 5. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-LEAD SOIC, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 12 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85411 is: 636
TABLE 6. θ
JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
PACKAGE OUTLINE & DIMENSIONS
IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 13 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
TABLE 8. ORDERING INFORMATION
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IDT™ / ICS™ DIFFERENTIAL-T O-L VDS FANOUT BUFFER 14 ICS8541 1AM REV. C JANUARY 20, 2009
ICS85411
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Cont act:
www.IDT.com
For Sales
800-345-7015 (inside USA)
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Fax: 408-284-2775
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For Tech Support
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+480-763-2056
Corporate Headquarters
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6024 Silver Creek V alley Road
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United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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