MCP1810
2016-2018 Microchip Technology Inc. DS20005623B-page 1
Features
• Ultra-Low Quiescent Current: 20 nA (typical)
• Ultra-Low Shutdown Supply Current:
1nA(typical)
• 150 mA Output Current Capability for VR≤3.5V
• 100 mA Output Current Capability for VR3.5V
• Input Operating Voltage Range: 2.5V to 5.5V
• Standard Output Voltages (VR): 1.2V, 1.5V, 1.8V,
2.0V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V, 3.5V, 4.2V
• Low Dropout Voltage: 380 mV maximum at
150 mA
• Stable with 1.0 µF Ceramic Output Capacitor
• Overcurrent Protection
• Available in the following packages:
- 2 x 2 mm No Lead VDFN
- 3 Lead SOT-23 (VR<4.0V)
- 5 Lead SOT-23 (VR<4.0V)
Applications
• Energy Harvesting
• Long-Life, Battery-Powered Applications
• Smart Cards
• Ultra-Low Consumption “Green” Products
• Portable Electronics
Description
The MCP1810 is a 150 mA (for VR≤3.5V), 100 mA (for
VR3.5V) low dropout (LDO) linear regulator that
provides high-current and low-output voltages, while
maintaining an ultra-low 20 nA of quiescent current
during device operation. In addition, the MCP1810 can
be shut down for an even lower 1 nA (typical) supply
current draw.
The MCP1810 comes in 11 standard fixed
output-voltage versions: 1.2V, 1.5V, 1.8V, 2.0V, 2.2V,
2.5V, 2.8V, 3.0V, 3.3V, 3.5V and 4.2V.
The 150 mA output current capability, combined with
the low output-voltage capability, make the MCP1810 a
good choice for new ultra-long-life LDO applications
that have high-current demands, but require ultra-low
power consumption during sleep states.
The MCP1810 is stable with ceramic output capacitors
that inherently provide lower output noise and reduce
the size and cost of the entire regulator solution. Only
1 µF (2.2 µF recommended) of output capacitance is
needed to stabilize the LDO.
The MCP1810 ultra-low quiescent and shutdown
current allows it to be paired with other ultra-low current
draw devices, such as Microchip’s nanoWatt eXtreme
Low Power (XLP) technology devices, for a complete
ultra-low-power solution.
Package Types
MCP1810
2x2 VDFN*
NC
VOUT
NC
VIN
FB
1
2
3
4
8
7
6
5NC
SHDNGND
* Includes Exposed Thermal Pad (EP); see Ta bl e 3-1 .
EP
9
12
4
3
5
12
3
VOUT
VOUT
VIN
VIN
GND NCGND
SHDN
3 Lead-SOT23 5 Lead-SOT23
.
Ultra-Low Quiescent Current LDO Regulator
MCP1810
DS20005623B-page 2 2016-2018 Microchip Technology Inc.
Typical Application
Functional Block Diagram
VIN VOUT
FB
GND
MCP1810
LOAD
CIN COUT
SHDN
+
-
ESR
VIN
SHDN
Voltage
Reference
VOUT
FB
+
-
GND
Overcurrent
SHDN
2016-2018 Microchip Technology Inc. DS20005623B-page 3
MCP1810
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Input voltage, VIN .....................................................................................................................................................+6.0V
Maximum Voltage on any pin - ......................................................................................................(GND - 0.3V) to +6.0V
Output Short-Circuit Duration................................................................................................. ............................Unlimited
Storage Temperature ............................................................................................................................ –65°C to +150°C
Maximum Junction Temperature, TJ..................................................................................................................... +150°C
Operating Junction Temperature, TJ........................................................................................................ –40°C to +85°C
ESD protection on all pins (HBM) .......................................................................................................................... ≥4kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN =V
R+800mV (Note 1), IOUT =1mA, C
IN =C
OUT =2.2µF
ceramic (X7R), TA=+25°C. Boldface type applies for junction temperatures TJ of –40°C to +85°C (Note 2).
Parameters Sym. Min. Typ. Max. Units Conditions
Input Operating Voltage VIN
2.7 —5.5 V
2.5 —5.5 VV
R1.8V, IOUT < 50 mA
Output Voltage Range VOUT 1.2 —4.2 V
Input Quiescent Current IQ—2050 nA
VIN =V
R + 800 mV or 2.7V
(whichever is greater)
IOUT =0
Input Quiescent Current
for SHDN Mode ISHDN — 1 — nA SHDN =GND
Ground Current IGND —200290 µA
VIN =V
R + 800 mV or 2.7V
(whichever is greater)
IOUT = 150 mA, VR 3.5V
IOUT = 100 mA, VR > 3.5V
Maximum Continuous
Output Current IOUT
——150 mA VR≤3.5V
——100 mA VR3.5V
Current Limit IOUT
—350— mA
VOUT =0.9xV
R
VR≤3.5V
—250— mA
VOUT =0.9xV
R
VR3.5V
Output Voltage Regulation VOUT
VR-4% —VR+4% VV
R<1.8V (Note 3)
VR-2% —VR+2% VV
R≥1.8V (Note 3)
Line Regulation VOUT/
(VOUT xVIN)–4 —+4 %/V VIN = VIN(min.) to 5.5V
IOUT =50mA (Note 1)
Note 1: The minimum VIN must meet two conditions: VIN VIN(MIN) and VIN  VRVDROPOUT(MAX).
2: The junction temperature is approximated by soaking the device under test at an ambient temperature
equal to the desired junction temperature. The test time is short enough such that the rise in junction
temperature over the ambient temperature is not significant.
3: VR is the nominal regulator output voltage. VR= 1.2V, 1.5V, 1.8V, 2.0V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V, 3.5V
or 4.2V.
4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 3%
below its nominal value that was measured with an input voltage of VIN =V
OUT(MAX) +V
DROPOUT(MAX).
MCP1810
DS20005623B-page 4 2016-2018 Microchip Technology Inc.
Load Regulation VOUT/VOUT –3 1+3 %
VIN =(V
IN(MIN) +V
IN(MAX))/2
IOUT = 0.02 mA to 150 mA
(Note 1)
Dropout Voltage VDROPOUT
——380 mV IOUT = 150 mA
VR≤3.5V (Note 4)
——280 mV IOUT = 100 mA
VR> 3.5V (Note 4)
Shutdown Input
Logic High Input VSHDN-HIGH 70 ——%V
IN
VIN =V
R + 800 mV or 2.7V
(whichever is greater)
IOUT =1 mA (Note 3)
Logic Low Input VSHDN-LOW ——30 %VIN
VIN =V
R + 800 mV or 2.7V
(whichever is greater)
IOUT =1 mA (Note 3)
AC Performance
Output Delay from SHDN TOR —20— ms
SHDN = GND to VIN
VOUT = GND to 95% VR
Output Noise eN
—0.48—µV/Hz
VIN = 3.3V
CIN = COUT = 2.2 µF ceramic
(X7R)
VR = 2.5V, IOUT = 50 mA
f = 1 kHz
— 48 — µVrms
VIN = 3.3V
CIN = COUT = 2.2 µF ceramic
(X7R)
VR = 2.5V, IOUT = 50 mA
f = 100 Hz to 1 MHz
Power Supply Ripple
Rejection Ratio PSRR — 40 — dB
f = 100 Hz, IOUT =10mA
VINAC =200mV pk-pk
CIN =0µF
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN =V
R+800mV (Note 1), IOUT =1mA, C
IN =C
OUT =2.2µF
ceramic (X7R), TA=+25°C. Boldface type applies for junction temperatures TJ of –40°C to +85°C (Note 2).
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: The minimum VIN must meet two conditions: VIN VIN(MIN) and VIN  VRVDROPOUT(MAX).
2: The junction temperature is approximated by soaking the device under test at an ambient temperature
equal to the desired junction temperature. The test time is short enough such that the rise in junction
temperature over the ambient temperature is not significant.
3: VR is the nominal regulator output voltage. VR= 1.2V, 1.5V, 1.8V, 2.0V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V, 3.5V
or 4.2V.
4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 3%
below its nominal value that was measured with an input voltage of VIN =V
OUT(MAX) +V
DROPOUT(MAX).
2016-2018 Microchip Technology Inc. DS20005623B-page 5
MCP1810
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Junction
Temperature Range TJ-40 — +85 °C Steady State
Maximum Junction
Temperature TJ— — +150 °C Transient
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance,
2 x 2 mm VDFN-8LD
JA — 73.1 — °C/W JEDEC® standard FR4 board with
1 oz. copper and thermal vias
JC — 10.7 — °C/W
Thermal Resistance,
SOT23-3LD
JA —256—°C/W
JC —81—°C/W
Thermal Resistance,
SOT23-5LD
JA —256—°C/W
JC —81—°C/W
MCP1810
DS20005623B-page 6 2016-2018 Microchip Technology Inc.
NOTES:
2016-2018 Microchip Technology Inc. DS20005623B-page 7
MCP1810
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-1: Output Voltage vs. Input
Voltage (VR=1.2V).
FIGURE 2-2: Output Voltage vs. Input
Voltage (VR=2.5V).
FIGURE 2-3: Output Voltage vs. Input
Voltage (VR=3.3V).
FIGURE 2-4: Output Voltage vs. Input
Voltage (VR=4.2V).
FIGURE 2-5: Output Voltag e vs. Load
Current (VR=1.2V).
FIGURE 2-6: Output Voltag e vs. Load
Current (VR=2.5V).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
1.190
1.195
1.200
1.205
1.210
1.215
1.220
2.53.54.55.5
Output Voltage (V)
Input Voltage (V)
TJ= +25°C
TJ= -40°C
TJ= +85°C
VR= 1.2V
2.490
2.495
2.500
2.505
2.510
2.515
2.53.54.55.5
Output Voltage (V)
Input Voltage (V)
TJ= -40°C
TJ= +25°C
TJ= +85°C
VR= 2.5V
3.300
3.302
3.304
3.306
3.308
3.310
3.312
3.54.04.55.05.5
Output Voltage (V)
Input Voltage (V)
TJ= +25°C
TJ= +85°C
TJ= -40°C
VR= 3.3V
4.185
4.190
4.195
4.200
4.205
4.210
4.5 4.7 4.9 5.1 5.3 5.5
Output Voltage (V)
Input Voltage (V)
TJ= +25°C
TJ= +85°C
TJ= -40°C
VR= 4.2V
1.170
1.175
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 25 50 75 100 125 150
Output Voltage (V)
Load Current (mA)
TJ= +85°C
TJ= -40°C
TJ= +25°C
VIN = 2.5V VR= 1.2V
2.470
2.480
2.490
2.500
2.510
2.520
2.530
0 25 50 75 100 125 150
Output Voltage (V)
Load Current (mA)
VIN = 3.3V
TJ= +25°C
TJ= +85°C
TJ= -40°C
VR= 2.5V
MCP1810
DS20005623B-page 8 2016-2018 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-7: Output Voltage vs. Load
Current (VR=3.3V).
FIGURE 2-8: Output Voltage vs. Load
Current (VR=4.2V).
FIGURE 2-9: Dropout Voltage vs. Load
Current (VR = 2.5V)
FIGURE 2-10: Dropout Voltage vs. Load
Current (VR=3.3V).
FIGURE 2-11: Dropout Voltage vs. Load
Current (VR=4.2V).
FIGURE 2-12: Noise vs. Frequency
(VR=1.2V).
3.270
3.280
3.290
3.300
3.310
3.320
3.330
3.340
3.350
3.360
3.370
0 25 50 75 100 125 150
Output Voltage (V)
Load Current (mA)
VIN = 4.1V
TJ= +25°C TJ= +85°C
TJ= -40°C
VR= 3.3V
4.166
4.176
4.186
4.196
4.206
4.216
4.226
4.236
0 255075100
Output Voltage (V)
Load Current (mA)
VIN = 5.0V
TJ= -40°C
TJ= +25°C
TJ= +85°C
VR= 4.2V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 255075100125150
Dropout Voltage (V)
Load Current (mA)
VR= 2.5V
TJ= +85°C
TJ= -40°C
TJ= +25°C
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0 255075100125150
Dropout Voltage (V)
Load Current (mA)
VR= 3.3V
TJ= +25°C
TJ= -40°C
TJ= +85°C
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0 20406080100
Dropout Voltage (V)
Load Current (mA)
VR= 4.2V
TJ= +25°C
TJ= +85°C
TJ= -40°C
0.001
0.01
0.1
1
10
100
0.01 0.1 1 10 100 1000
Output Noise μV/¥Hz
Frequency (kHz)
VR = 1.2V
VIN = 2.5V, CIN = COUT = 2.2 μF
IOUT = 50 mA
Noise (100 Hz to 1 MHz) = 53.49 μVrms
2016-2018 Microchip Technology Inc. DS20005623B-page 9
MCP1810
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-13: Noise vs. Frequency
(VR=2.5V).
FIGURE 2-14: Noise vs. Frequency
(VR=3.3V).
FIGURE 2-15: Noise vs. Frequency
(VR=4.2V).
FIGURE 2-16: Power Supply Ripple
Rejection vs. Frequency (VR=1.2V).
FIGURE 2-17: Power Supply Ripple
Rejection vs. Frequency (VR=2.5V).
FIGURE 2-18: Power Supply Ripple
Rejection vs. Frequency (VR=3.3V).
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100 1000
Output Noise μV/¥Hz
Frequency (kHz)
VR= 2.5V
VIN = 3.3V, CIN= COUT = 2.2 μF
IOUT = 50 mA
Noise (100 Hz to 1 MHz) = 47.57 μVrms
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100 1000
Output Noise μV/¥Hz
Frequency (kHz)
VR= 3.3V
VIN = 4.1V, CIN = COUT = 2.2 μF
IOUT = 50 mA
Noise (100 Hz to 1 MHz) = 43.01 μVrms
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100 1000
Output Noise μV/¥Hz
Frequency (kHz)
VR= 4.2V
VIN = 5.0V, CIN = COUT = 2.2 μF
IOUT = 50 mA
Noise (100 Hz to 1 MHz) = 38.70 μVrms
-60
-50
-40
-30
-20
-10
0
10
0.01 0.1 1 10 100 1000
PSRR (dB)
Frequency (kHz)
VR= 1.2V
CIN = 0, COUT = 2.2 µF
VIN = 2.7V + 0.2 Vpk-pk
IOUT = 50 mA
IOUT = 10 mA
-60
-50
-40
-30
-20
-10
0
10
0.01 0.1 1 10 100 1000
PSRR (dB)
Frequency (kHz)
IOUT = 50 mA
IOUT = 10 mA
VR= 2.5V
CIN = 0, COUT = 2.2 µF
VIN = 3.5V + 0.2 Vpk-pk
-60
-50
-40
-30
-20
-10
0
10
0.01 0.1 1 10 100 1000
PSRR (dB)
Frequency (kHz)
IOUT = 10 mA
IOUT = 50 mA
VR= 3.3V
CIN = 0, COUT = 2.2 µF
VIN = 4.3V + 0.2 Vpk-pk
MCP1810
DS20005623B-page 10 2016-2018 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-19: Power Supply Ripple
Rejection vs. Frequency (VR=4.2V).
FIGURE 2-20: Dynamic Load Step
(VR=1.2V).
FIGURE 2-21: Dynamic Load Step
(VR=2.5V).
FIGURE 2-22: Dynamic Load Step
(VR=3.3V).
FIGURE 2-23: Dynamic Load Step
(VR=4.2V).
FIGURE 2-24: Dynamic Line Step
(VR=1.2V).
-60
-50
-40
-30
-20
-10
0
10
0.01 0.1 1 10 100 1000
PSRR (dB)
Frequency (kHz)
IOUT = 50 mA
IOUT = 10 mA
VR= 4.2V
CIN = 0, COUT = 2.2 µF
VIN = 5.2V + 0.2 Vpk-pk
VOUT (AC Coupled, 100 mV/Div)
10 mA
100 µA
Time = 80 µs/Div
VR = 1.2V, VIN = 2.7V, IOUT = 100 µA to 10 mA
IOUT (DC Coupled, 5 mA/Div)
VOUT
IOUT
VOUT (AC Coupled, 100 mV/Div)
10 mA
100 µA
Time = 80 µs/Div
VR = 2.5V, VIN = 3.3V, IOUT = 100 µA to 10 mA
IOUT (DC Coupled, 5 mA/Div )
VOUT
IOUT
VOUT (AC Coupled, 100 mV/Div)
10 mA
100 µA
Time = 80 µs/Div
VR = 3.3V, VIN = 4.1V, IOUT = 100 µA to 10 mA
IOUT (DC Coupled, 5 mA/Div)
VOUT
IOUT
VOUT (AC Coupled, 100 mV /Div)
10 mA
100 µA
Time = 80 µs/Div
VR = 4.2V, VIN = 5.0V, IOUT = 100 µA to 10 mA
IOUT (DC Coupled, 5 mA/Div)
VOUT
IOUT
VOUT (AC Coupled, 200 mV/Div) Time = 80 µs/Div
VR = 1.2V, VIN = 2.5V to 3.5V, IOUT = 10 mA
2.5V
3.5V
VIN (DC Coupled, 1V/Div)
VIN
VOUT
2016-2018 Microchip Technology Inc. DS20005623B-page 11
MCP1810
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-25: Dynamic Line Step
(VR=2.5V).
FIGURE 2-26: Dynamic Line Step
(VR=3.3V).
FIGURE 2-27: Dynamic Line Step
(VR=4.2V).
FIGURE 2-28: Start-up from VIN
(VR = 1.2V).
FIGURE 2-29: Start-up from VIN
(VR = 2.5V).
FIGURE 2-30: Start-up from VIN
(VR = 3.3V).
VOUT (AC Coupled, 200 mV/Div)
Time = 80 µs/Div
VR = 2.5V, VIN = 3.5V to 4.5V, IOUT = 10 mA
3.5V
4.5V
VIN (DC Coupled, 1V/Div)
VIN
VOUT
VOUT (AC Coupled, 200 mV/Div)
Time = 80 µs/Div
VR = 3.3V, VIN = 4.3V to 5.3V, IOUT = 10 mA
4.3V
5.3V
VIN (DC Coupled, 1V/Div)
VIN
VOUT
VOUT (AC Coupled, 200 mV /Div)
Time = 80 µs/Div
VR = 4.2V, VIN = 4.5V to 5.5V, IOUT = 10 mA
4.5V
5.5V
VIN (DC Coupled, 1V/Div)
VIN
VOUT
VOUT (DC Coupled, 2V/Div)
Time = 10 ms/Div
VR = 1.2V, VIN = 0V to 2.7V, IOUT = 100 µA
0V
2.7V
VIN (DC Coupled, 2V/Div)
VIN
VOUT
VOUT (DC Coupled, 2V/D iv ) Time = 10 ms/Div
0V
3.5V
VIN (DC Coupled, 2V/Div)
VR = 2.5V, VIN = 0V to 3.5V, IOUT = 100 µA
VIN
VOUT
VOUT (DC Coupled, 2V/D iv )
Time = 10 ms/Div
0V
4.3V
VIN (DC Coupled, 2V/Div)
VR = 3.3V, VIN = 0V to 4.3V, IOUT = 100 µA
VIN
VOUT
MCP1810
DS20005623B-page 12 2016-2018 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-31: Start-up from VIN
(VR = 4.2V).
FIGURE 2-32: Start-up from SHDN
(VR = 1.2V).
FIGURE 2-33: Start-up from SHDN
(VR = 2.5V).
FIGURE 2-34: Start-up from SHDN
(VR = 3.3V).
FIGURE 2-35: Start-up from SHDN
(VR = 4.2V).
FIGURE 2-36: Load Regulation vs.
Junction Temperature (VR = 1.2V).
VOUT (DC Coupled, 2V/Div) Time = 10 ms/Div
0V
5.2V
VIN (DC Coupled, 2V/Div )
VR = 4.2V, VIN = 0V to 5.2V, IOUT = 100 µA
VIN
VOUT
VOUT (DC Coupled, 2V/Div)
Time = 10 ms/Div
0V
2.7V
SHDN (DC Coupled, 2V/Div)
VR = 1.2V, VIN = 2.7V, IOUT = 10 mA
~SHDN
VOUT
VOUT (DC Coupled, 2V/Div) Time = 10 ms/Div
0V
3.3V
VR = 2.5V, VIN = 3.3V, IOUT = 10 mA
SHDN (DC Coupled, 2V/Div)
~SHDN
VOUT
VOUT (DC Coupled, 2V/Div) Time = 10 ms/Div
0V
4.1V
SHDN (DC Coupled, 2V/Div)
VR = 3.3V, VIN = 4.1V, IOUT = 10 mA
~SHDN
VOUT
VOUT (DC Coupled, 2V/Div) Time = 10 ms/Div
0V
5.0V
SHDN (DC Coupled, 2V/Div)
VR = 4.2V, VIN = 5.0V, IOUT = 10 mA
~SHDN
VOUT
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-40-1510356085
Load Regulation (%)
Junction Temperature (°C)
VIN = 2.5V
VIN = 3.0V
VIN = 4.0V
VIN = 5.5V
VR= 1.2V
IOUT = 0 mA to 100 mA
2016-2018 Microchip Technology Inc. DS20005623B-page 13
MCP1810
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-37: Load Re gu lat i on v s.
Junction Temperature (VR = 2.5V).
FIGURE 2-38: Load Re gu lat i on v s.
Junction Temperature (VR = 3.3V).
FIGURE 2-39: Load Re gu lat i on v s.
Junction Temperature (VR = 4.2V).
FIGURE 2-40: Line Regulation vs. Junction
Temperature (VR = 1.2V).
FIGURE 2-41: Line Regulation vs. Junction
Temperature (VR = 2.5V).
FIGURE 2-42: Line Regulation vs. Junction
Temperature (VR = 3.3V).
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
-40 -15 10 35 60 85
Load Regulation (%)
Junction Temperature (°C)
VIN = 3.0V
VIN = 4.0V
VIN = 5.5V
VIN = 5.0V
VR= 2.5V
IOUT = 0 mA to 100 mA
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
-40 -15 10 35 60 85
Load Regulation (%)
Junction Temperature (°C)
VIN = 3.5V
VIN = 4.1V
VIN = 5.0V
VIN = 4.5V VIN = 5.5V
VR= 3.3V
IOUT = 0 mA to 100 mA
0.000
0.005
0.010
0.015
0.020
0.025
-40 -15 10 35 60 85
Load Regulation (%)
Junction Temperature (°C)
VIN = 5.5V
VIN = 4.6V
VIN = 5.0V
VR= 4.2V
IOUT = 0 mA to 100 mA
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-40-1510356085
Line Regulation (%/V)
Junction Temperature (°C)
IOUT = 150 mA IOUT = 125 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 10 mA
IOUT = 1 mA
VR= 1.2V
VIN = 2.5V to 5.5V
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
-40 -15 10 35 60 85
Line Regulation (%/V)
Junction Temperature (°C)
IOUT = 150 mA
IOUT = 125 mA IOUT = 100 mA
IOUT = 50 mA IOUT = 10 mA
IOUT = 1 mA
VR= 2.5V
VIN = 3.3V to 5.5V
0.150
0.155
0.160
0.165
0.170
0.175
0.180
0.185
0.190
0.195
0.200
-40-1510356085
Line Regulation (%/V)
Junction Temperature (°C)
IOUT = 150 mA
IOUT = 125 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 1 mA
IOUT = 10 mA
VR= 3.3V
VIN = 4.1V to 5.5V
MCP1810
DS20005623B-page 14 2016-2018 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-43: Line Regulation vs. Junction
Temperature (VR = 4.2V).
FIGURE 2-44: Quiescent Current vs. Input
Voltage (VR = 1.2V).
FIGURE 2-45: Quiescent Current vs. Input
Voltage (VR = 2.5V).
FIGURE 2-46: Quiescent Current vs. Input
Voltage (VR = 3.3V).
FIGURE 2-47: Quiescent Current vs. Input
Voltage (VR = 4.2V).
FIGURE 2-48: Ground Current vs. Junction
Temperature (VR = 1.2V).
0.14
0.15
0.16
0.17
0.18
0.19
0.20
-40 -15 10 35 60 85
Line Regulation (%/V)
Junction Temperature (°C)
IOUT = 1 mA
IOUT = 125 mA IOUT = 150 mA IOUT = 100 mA
IOUT = 10 mA IOUT = 50 mA
VR= 4.2V
VIN = 5.0V to 5.5V
4
6
8
10
12
14
16
18
20
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Quiescent Current (nA)
Input Voltage (V)
T
J
= 85°C
TJ= 25°C
TJ=-40°C
VR= 2.5V
4
6
8
10
12
14
16
18
20
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
T
J
= 85°C
TJ= 25°C
TJ=-40°C
VR= 2.5V
4
6
8
10
12
14
16
18
20
3.5 4.0 4.5 5.0 5.5
Quiescent Current (nA)
Input Voltage (V)
TJ= 85°C
TJ= 25°C
TJ= -40°C
VR= 3.3V
4
6
8
10
12
14
16
18
20
4.5 4.7 4.9 5.1 5.3 5.5
Quiescent Current (nA)
Input Voltage (V)
TJ= 25°C
TJ= 85°C
TJ= -40°C
VR= 4.2V
3.70
3.75
3.80
3.85
3.90
3.95
-40-1510356085
Ground Current (µA)
Junction Temperature (°C)
IOUT = 1 mA VR= 1.2V
VIN = 2.7V
2016-2018 Microchip Technology Inc. DS20005623B-page 15
MCP1810
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-49: Ground Current vs. Junctio n
Temperature (VR = 2.5V).
FIGURE 2-50: Ground Current vs. Junctio n
Temperature (VR = 3.3V).
FIGURE 2-51: Ground Current vs. Junctio n
Temperature (VR = 4.2V).
FIGURE 2-52: Ground Current vs. Load
Current (VR = 1.2V).
FIGURE 2-53: Ground Current vs. Load
Current (VR = 2.5V).
FIGURE 2-54: Ground Current vs. Load
Current (VR = 3.3V).
4.55
4.60
4.65
4.70
4.75
4.80
4.85
4.90
-40 -15 10 35 60 85
Ground Current (µA)
Junction Temperature (°C)
IOUT = 1 mA VR= 2.5V
4.64
4.66
4.68
4.7
4.72
4.74
4.76
4.78
4.8
-40 -15 10 35 60 85
Ground Current (µA)
Junction Temperature (°C)
IOUT = 1 mA VR= 3.3V
4.65
4.70
4.75
4.80
4.85
4.90
4.95
-40 -15 10 35 60 85
Ground Current (µA)
Junction Temperature (°C)
IOUT = 1 mA VR= 4.2V
0
20
40
60
80
100
120
140
160
180
200
0 255075100125150
Ground Current (µA)
Load Current (mA)
TJ= 85°C
TJ= -40°C
TJ= 25°C
VR= 1.2V
VIN = 2.7V
0
20
40
60
80
100
120
140
160
180
200
220
240
0 25 50 75 100 125 150
Ground Current (µA)
Load Current (mA)
TJ= 25°C
TJ= 85°C TJ= -40°C
VR= 2.5V
VIN = 3.3V
0
25
50
75
100
125
150
175
200
225
250
0 25 50 75 100 125 150
Ground Current (µA)
Load Current (mA)
TJ= 85°C
TJ= -40°C
TJ= 25°C
VR= 3.3V
VIN = 4.1V
MCP1810
DS20005623B-page 16 2016-2018 Microchip Technology Inc.
Note: Unless otherwise indicated, COUT = 2.2 µF ceramic (X7R), CIN = 2.2 µF ceramic (X7R), IOUT =1mA,
TA= +25°C, VIN =V
R+ 0.8V, SHDN =1M pull-up to VIN.
FIGURE 2-55: Ground Current vs. Load
Current (VR = 4.2V).
FIGURE 2-56: Ground Current vs. Very
Low Load Current (VR = 1.2V).
FIGURE 2-57: Ground Current vs. Very
Low Load Current (VR = 2.5V).
FIGURE 2-58: Ground Current vs. Very
Low Load Current (VR = 3.3V).
FIGURE 2-59: Ground Current vs. Very
Low Load Current (VR = 4.2V).
0
20
40
60
80
100
120
140
160
180
200
0 20406080100
Ground Current (µA)
Load Current (mA)
TJ= 85°C
TJ= 25°C
TJ= -40°C
VR= 4.2V
VIN = 5V
2016-2018 Microchip Technology Inc. DS20005623B-page 17
MCP1810
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
3.1 Ground Pin (GND)
For optimal noise and power supply rejection ratio
(PSRR) performance, the GND pin of the LDO should
be tied to an electrically quiet circuit ground. This will
help the LDO power supply rejection ratio and noise
performance. The GND pin of the LDO conducts only
ground current, so a heavy trace is not required. For
applications that have switching or noisy inputs, tie the
GND pin to the return of the output capacitor. Ground
planes help lower the inductance and voltage spikes
caused by fast transient load currents.
3.2 Regulated Output Voltage Pin
(VOUT)
The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1810 is stable with
ceramic, tantalum and aluminum-electrolytic
capacitors. See Section 4.2 “Output Capacitor” for
output capacitor selection guidance.
3.3 Feedback Pin (FB)
The output voltage is connected to the FB input. This
sets the output voltage regulation value.
3.4 Input Voltage Supply Pin (VIN)
Connect the unregulated or regulated input voltage
source to VIN. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications (2.2 µF,
typical). The type of capacitor used can be ceramic,
tantalum, or aluminum-electrolytic. However, the low
ESR characteristics of the ceramic capacitor will yield
better noise and PSRR performance at high frequency.
3.5 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the LDO enters a low-quiescent current
shutdown state, where the typical quiescent current is
1nA.
3.6 Exposed Thermal Pad (EP)
The 2 x 2 VDFN 8-Lead package has an exposed
thermal pad on the bottom of the package. The
exposed thermal pad gives the device better thermal
characteristics by providing a good thermal path to
either the printed circuit board (PCB) or heat sink, to
remove heat from the device. The exposed pad of the
package is at ground potential.
TABLE 3-1: PIN FUNCTION TABLE
MCP1810
2x2 VDFN MCP1810
3Ld-SOT23 MCP1810
5Ld-SOT23 Symbol Description
1 3 5 GND Ground
213 V
OUT Regulated Output Voltage
3, 4, 5 – 4 NC Not connected pins (should either be left floated or
connected to ground)
6 – – FB Output Voltage Feedback Input
721 V
IN Input Voltage Supply
8 – 2 SHDN Shutdown Control Input (active-low)
9–– EP
Exposed Thermal Pad, connected to GND
MCP1810
DS20005623B-page 18 2016-2018 Microchip Technology Inc.
NOTES:
2016-2018 Microchip Technology Inc. DS20005623B-page 19
MCP1810
4.0 DEVICE OVERVIEW
The MCP1810 is a 150 mA/100 mA output current, low
dropout (LDO) voltage regulator. The low dropout
voltage of 380 mV maximum at 150 mA of current
makes it ideal for battery-powered applications. The
input voltage ranges from 2.5V to 5.5V. The MCP1810
adds a shutdown-control input pin and is available in
eleven standard fixed-output voltage options: 1.2V,
1.5V, 1.8V, 2.0V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V, 3.5V and
4.2V. It uses a proprietary voltage reference and
sensing scheme to maintain the ultra-low 20 nA
quiescent current.
4.1 Output Current and Current
Limiting
The MCP1810 LDO is tested and ensured to supply a
minimum of 150 mA of output current for the
1.2V-to-3.5V output range, and 100 mA of output
current for the 3.5V-to-4.2V output range. The device
has no minimum output load, so the output load current
can go to 0 mA and the LDO will continue regulating
the output voltage within the specified tolerance.
The MCP1810 also incorporates an output current limit.
The current limit is set to 350 mA typical for the
1.2V VR≤3.5V range, and to 250 mA typical for the
3.5V VR5.5V range.
4.2 Output Capacitor
The MCP1810 requires a minimum output capacitance
of 1 µF for output voltage stability. Ceramic capacitors
are recommended because of their size, cost and
robust environmental qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X7R
0805 capacitor has an ESR of 50 m.
For extreme output currents — below 100 µA or close
to 150 mA/100 mA — an output capacitor with higher
ESR (tantalum, aluminum-electrolytic) is recom-
mended. Ceramic output capacitor may be used if a
0.5 to 1 resistor is placed in series with the capaci-
tor.
4.3 Input Capacitor
Low input-source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF of capacitance is recommended for
most applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides a
low-impedance source of current for the LDO to use for
dynamic load changes. This allows the LDO to respond
quickly to the output load step. For good step-response
performance, the input capacitor should be equivalent
or higher value than the output capacitor. The capacitor
should be placed as close to the input of the LDO as is
practical. Larger input capacitors will also help reduce
any high-frequency noise on the input and output of the
LDO, as well as the effects of any inductance that
exists between the input source voltage and the input
capacitance of the LDO.
4.4 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The maximum
input-low logic level is 30% of VIN and the minimum
high logic level is 70% of VIN.
On the rising edge of the SHDN input, the shutdown
circuitry has a 20 ms (typical) delay before allowing the
LDO output to turn on. This delay helps to reject any
false turn-on signal or noise on the SHDN input signal.
After the 20 ms delay, the LDO output enters its
current-limited soft-start period as it rises from 0V to its
final regulation value. If the SHDN input signal is pulled
low during the 20 ms delay period, the timer will be
reset and the delay time will start over again on the next
rising edge of the SHDN input. The total time from the
SHDN input going high (turn-on) to the LDO output
being in regulation is typically 20 ms. Figure 4-1 shows
a timing diagram of the SHDN input.
FIGURE 4-1: Shutdown Input Timing
Diagram.
SHDN
VOUT
20 ms 10 µs
TOR
20 ns (typical)
MCP1810
DS20005623B-page 20 2016-2018 Microchip Technology Inc.
4.5 Dropout Voltage
Dropout voltage is defined as the input-to-output
voltage differential at which the output voltage drops
3% below the nominal value that was measured with a
VR+ 0.8V differential applied. The MCP1810 LDO has
a low-dropout voltage specification of 230 mV (typical)
for VR= 2.5V, 120 mV for VR= 3.3V at 150 mA out, and
70 mV (typical) for VR 4.2V at 100 mA out. See
Section 1.0 “Electrical Characteristics” for
maximum dropout voltage specifications.
2016-2018 Microchip Technology Inc. DS20005623B-page 21
MCP1810
5.0 APPLICATION CIRCUITS AND
ISSUES
5.1 Typical Application
The MCP1810 is used for applications that require
ultra-low quiescent current draw.
FIGURE 5-1: Typical Application Circuit.
5.2 Power Calculations
5.2.1 POWER DISSIPATION
The internal power dissipation within the MCP1810 is a
function of input voltage, output voltage, output current
and quiescent current. Equation 5-1 can be used to
calculate the internal power dissipation for the LDO.
EQUATION 5-1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the MCP1810 as a
result of quiescent or ground current. The power
dissipation as a result of the ground current can be
calculated by applying Equation 5-2:
EQUATION 5-2:
The total power dissipated within the MCP1810 is the
sum of the power dissipated in the LDO pass device
and the P(IGND) term. Because of the CMOS
construction, the typical IGND for the MCP1810 is
maximum 290 µA at full load. Operating at a maximum
VIN of 5.5V results in a power dissipation of 1.6 mW.
For most applications, this is small compared to the
LDO pass device power dissipation, and can be
neglected.
The maximum continuous operating junction
temperature specified for the MCP1810 is +85°C. To
estimate the internal junction temperature of the
MCP1810, the total internal power dissipation is
multiplied by the thermal resistance from
junction-to-ambient (RJA) of the device. The thermal
resistance from junction to ambient for the 2x2 VDFN
8-Lead package is estimated at 73.1°C/W.
EQUATION 5-3:
The maximum power dissipation capability for a
package can be calculated given the
junction-to-ambient thermal resistance and the
maximum ambient temperature for the application.
Equation 5-4 can be used to determine the package
maximum internal power dissipation.
EQUATION 5-4:
VIN VOUT
FB
GND
MCP1810
LOAD
CIN COUT
SHDN
+
-
ESR
PLDO VIN MAX
VOUT MIN
–IOUT MAX
=
Where:
PLDO = Internal power dissipation of the
LDO pass device
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage
IOUT(MAX) = Maximum output current
PIGND
VIN MAX
IGND
=
Where:
PI(GND) = Power dissipation due to the
quiescent current of the LDO
VIN(MAX) = Maximum input voltage
IGND = Current flowing into the GND pin
TJMAX
PTOTAL R
JA
TAMAX
+=
Where:
TJ(MAX) = Maximum continuous junction
temperature
PTOTAL = Total power dissipation of the device
RJA = Thermal resistance from junction to
ambient
TA(MAX) = Maximum ambient temperature
PDMAX
TJMAX
TAMAX
–
R
JA
---------------------------------------------------=
Where:
PD(MAX) = Maximum power dissipation of the
device
TJ(MAX) = Maximum continuous junction
temperature
TA(MAX) = Maximum ambient temperature
RJA = Thermal resistance from
junction to ambient
MCP1810
DS20005623B-page 22 2016-2018 Microchip Technology Inc.
EQUATION 5-5:
EQUATION 5-6:
5.3 Typical Application Examples
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1 POWER DISSIPATION EXAMPLE
EXAMPLE 5-1:
5.3.1.1 Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and of the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (RJA) is
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
JESD51. The standard describes the test method and
board specifications for measuring the thermal
resistance from junction to ambient. The actual thermal
resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to Application Note AN792, “A Method
to Determine How Much Power a SOT23 Can
Dissipate in an Application” (DS00792), for more
information regarding this subject.
EXAMPLE 5-2:
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
EXAMPLE 5-3:
5.3.1.3 Maximum Package Power
Dissipation at +60°C Ambient
Temperature
EXAMPLE 5-4:
Package
Package Type = 2 x 2 VDFN 8-Lead
Input Voltage
VIN = 3.3V ± 5%
LDO Output Voltage and Current
VOUT = 2.5V
IOUT =150mA
Maximum Ambient Temperature
TA(MAX) = +60°C
Internal Power Dissipation
PLDO(MAX) =(V
IN(MAX) – VOUT(MIN))xI
OUT(MAX)
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
x150mA
PLDO =0.154Watts
TJRISE
PDMAX
R
JA
=
Where:
TJ(RISE) = Rise in the device junction
temperature over the ambient
temperature
PD(MAX) = Maximum power dissipation of the
device
RJA = Thermal resistance from junction to
ambient
TJTJRISE
TA
+=
Where:
TJ= Junction temperature
TJ(RISE) = Rise in the device junction
temperature over the ambient
temperature
TA= Ambient temperature
TJ(RISE) =P
TOTAL xRJA
TJ(RISE) = 0.154W x 73.1°C/W
TJ(RISE) = 11.3°C
TJ =T
J(RISE) +T
A(MAX)
TJ = 11.3°C + 60.0°C
TJ = 71.3°C
2x2 VDFN 8-Lead (73.1°C/W RJA):
PD(MAX) = (85°C – 60°C)/73.1°C/W
PD(MAX) = 0.342W
2016-2018 Microchip Technology Inc. DS20005623B-page 23
MCP1810
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead VDFN (2 x 2 mm) Example
Part Number Code
MCP1810T-12I/J8A A12
MCP1810T-18I/J8A A18
MCP1810T-25I/J8A A25
MCP1810T-30I/J8A A30
MCP1810T-33I/J8A A33
MCP1810T-42I/J8A A42
A12
256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3-Lead SOT23 Example
XXXNNN
12T256
5-Lead SOT23
Example
12OT7
42256
MCP1810
DS20005623B-page 24 2016-2018 Microchip Technology Inc.
0.05 C
0.05 C
0.10 C A B
0.05 C
C
SEATING
PLANE
12
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.10 C
Microchip Technology Drawing C04-1207A Sheet 1 of 2
2X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Very Thin Plastic Dual Flat, No Lead Package (J8A) - 2x2 mm Body [VDFN]
(DATUM B)
(DATUM A)
2.00
2.00
B
A
D2
E2
e
2
e
L
(K)
8X b
A
(A3)
A1
0.08 C
8X
With 1.7x0.9 mm Exposed Pad
2016-2018 Microchip Technology Inc. DS20005623B-page 25
MCP1810
Microchip Technology Drawing C04-1207A Sheet 2 of 2
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
8-Lead Very Thin Plastic Dual Flat, No Lead Package (J8A) - 2x2 mm Body [VDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
A3
e
L
E
N
0.50 BSC
0.20 REF
0.85
0.25
0.20
0.80
0.00
0.25
0.30
0.90
0.85
0.02
2.00 BSC
MILLIMETERS
MIN NOM
8
0.95
0.35
0.30
0.90
0.05
MAX
K 0.25 REFTerminal-to-Exposed-Pad
Overall Length
Exposed Pad Length
D
D2 1.65
2.00 BSC
1.70 1.75
With 1.7x0.9 mm Exposed Pad
MCP1810
DS20005623B-page 26 2016-2018 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
1.95
0.95
MILLIMETERS
0.50 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.70
0.30
Microchip Technology Drawing C04-3207A
NOM
12
20
CContact Pad Spacing 2.10
Contact Pad to Center Pad (X8) G2 0.23
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
E
C
EV
Y2
X1
Y1
ØV
X2
CH
G1
G2
SILK SCREEN
Contact Pad to Pad (X6) G1 0.20
8-Lead Very Thin Plastic Dual Flat, No Lead Package (J8A) - 2x2 mm Body [VDFN]
With 1.7x0.9 mm Exposed Pad
2016-2018 Microchip Technology Inc. DS20005623B-page 27
MCP1810
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b
N
E
E1
2
1
e
e1
D
A
A1
A2
c
L
φ
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MCP1810
DS20005623B-page 28 2016-2018 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc. DS20005623B-page 29
MCP1810
0.15 C D
2X
NOTE 1 12
N
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.20 C
C
SEATING PLANE
AA2
A1
e
NX bB
0.20 C A-B D
e1
D
E1
E1/2
E/2
E
D
A
0.20 C2X
(DATUM D)
(DATUM A-B)
A
A
SEE SHEET 2
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
MCP1810
DS20005623B-page 30 2016-2018 Microchip Technology Inc.
Microchip Technology Drawing C04-091D [OT] Sheet 2 of
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
L
L1
T
VIEW A-A
SHEET 1
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Foot Angle
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
Notes:
L1
I
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0°
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
-
0.60 REF
2.90 BSC
-
2.80 BSC
1.60 BSC
-
-
-
MIN
6
NOM
1.45
1.30
0.15
0.60
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M
2016-2018 Microchip Technology Inc. DS20005623B-page 31
MCP1810
RECOMMENDED LAND PATTERN
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2091A [OT]
Dimension Limits
Contact Pad Length (X5)
Overall Width
Distance Between Pads
Contact Pad Width (X5)
Contact Pitch
Contact Pad Spacing
3.90
1.10
G
Z
Y
1.70
0.60
MAXMIN
C
X
E
Units
NOM
0.95 BSC
2.80
MILLIMETERS
Distance Between Pads GX 0.35
1
5
X
Y
ZC
E
GX
G
2
SILK SCREEN
MCP1810
DS20005623B-page 32 2016-2018 Microchip Technology Inc.
NOTES:
2016-2018 Microchip Technology Inc. DS20005623B-page 33
MCP1810
APPENDIX A: REVISION HISTORY
Revision B (January 2018)
The following is the list of modifications:
1. Added more Standard Output Voltages in the
Features, Description, AC/DC Characteristics,
Device Overview sections.
2. Updated the Package Types section by adding
the 3 Lead-SOT23 and 5 Lead-SOT23
packages.
3. Added two new parameters in the Temperature
Specifications section, under Thermal Package
Resistances.
4. Included the 3Ld-SOT23 and 5Ld-SOT23 pack-
ages in the Ta b le 3 -1 .
5. Updated the Packaging Information section with
two new packages: 3-Lead SOT23 and 5-Lead
SOT23.
6. Updated the Product Identification System.
7. Minor typographical edits.
Revision A (September 2016)
• Original Release of this Document.
MCP1810
DS20005623B-page 34 2016-2018 Microchip Technology Inc.
NOTES:
2016-2018 Microchip Technology Inc. DS20005623B-page 35
MCP1810
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -XX
Output
Device Voltage
X/
Temp.
XXX
Package
Device: MCP1810T: Ultra-Low Quiescent Current LDO Regulator,
Tape and Reel
Standard Output
Voltages*: 12 = 1.2V
15 = 1.5V
18 = 1.8V
20 = 2.0V
22 = 2.2V
25 = 2.5V
28 = 2.8V
30 = 3.0V
33 = 3.3V
35 = 3.5V
42 = 4.2V
*Contact factory for other output voltage options
Temperature: I= -40C to +85C (Industrial)
Package Type: J8A = 8-Lead Very Thin Plastic Dual Flat, No Lead Pack-
age, VDFN, 8-Lead, with 1.7 x 0.9 mm Exposed
Pad
TT = 3-Lead Plastic Small Outline Transistor, SOT-23
OT = 5-Lead Plastic Small Outline Transistor, SOT-23
Examples:
a) MCP1810T-12I/J8A: Tape and reel,
1.2V output voltage,
Industrial temperature
8-LD VDFN package
b) MCP1810T-18I/J8A: Tape and reel,
1.8V output voltage,
Industrial temperature,
8-LD VDFN package
c) MCP1810T-42I/J8A: Tape and reel,
4.2V output voltage,
Industrial temperature,
8-LD VDFN package
d) MCP1810T-15I/TT: Tape and reel,
1.5V output voltage,
Industrial temperature,
3-LD SOT-23 pack-
age
e) MCP1810T-20I/TT: Tape and reel,
2.0V output voltage,
Industrial temperature,
3-LD SOT-23 pack-
age
f) MCP1810T-25I/TT: Tape and reel,
2.5V output voltage,
Industrial temperature,
3-LD SOT-23 pack-
age
g) MCP1810T-33I/TT: Tape and reel,
3.3V output voltage,
Industrial temperature,
3-LD SOT-23 pack-
age
h) MCP1810T-22I/OT: Tape and reel,
2.2V output voltage,
Industrial temperature,
5-LD SOT-23 pack-
age
i) MCP1810T-28I/OT: Tape and reel,
2.8V output voltage,
Industrial temperature,
5-LD SOT-23 pack-
age
j) MCP1810T-30I/OT: Tape and reel,
3.0V output voltage,
Industrial temperature,
5-LD SOT-23 pack-
age
k) MCP1810T-35I/OT: Tape and reel,
3.5V output voltage,
Industrial temperature,
5-LD SOT-23 pack-
age
MCP1810
DS20005623B-page 36 2016-2018 Microchip Technology Inc.
NOTES:
2016-2018 Microchip Technology Inc. DS20005623B-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2016-2018, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-2535-9
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chan dler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’ s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro perip hera ls, n onvolat ile memory and
analog products . In add ition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005623B-page 38 2016-2018 Microchip Technology Inc.
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10/25/17