STPC CONSUMER - STMicroelectronics

STPC® CONSUMER

PC Compatible Embeded Microprocessor

1/718/11/01 Issue 2.4

Figure 1. Logic Diagram

■POWERFUL X86 PROCESSOR

■64-BIT BUS ARCHITECTURE

■64-BIT DRAM CONTROLLER

■SVGA GRAPHICS CONTROLLER

■UMA ARCHIT E CTURE

■VIDEO SCALER

■DIG I TAL PAL/NTSC ENCODER

■VIDEO INPUT PORT

■CRT CONTROLLER

■135 MHz RAM DA C

■3 LINE FLICKER FILTER

■SCAN CONVERTER

■PCI MASTER / SLAVE / ARBITER CTRL

■ISA MASTER/SLAVE INTERFACE

■IDE CONTROLLE R

■DMA CONTROLLE R

■INTERRUPT CONTROLLER

■TIMER / COUNTERS

■PO W E R MAN AGEME N T

STPC C ONSUMER OVERVI EW

The STPC Consumer integrates a standard 5th

generation x 86 core, a DRA M cont roller, a graph-

ics subsystem, a vi deo pipeline an d support logic

including PCI, ISA and IDE controllers to provide a

single Consumer orientated PC compatible sub-

system on a single device.

The device is based on a tightly coupled Unified

Memory Architecture (UMA), sharing the same

memory array between the CPU main memory

and the graphics and video frame buffers.

Extra facilities are implemented to handle video

streams. Features include smooth scaling and

color space conversion of the video input stream

and mixing with graphics data. The chip also in-

cludes a built-in digital TV encoder and anti-flicker

filters that allow stable, high-quality display on

standard PAL or NTSC television sets withou t ad-

ditional components.

The STPC Consumer is packaged in a 388 Plastic

Ball Gr id A r ra y (P BG A).

PBGA388

x86

Core

Host I/F

DRAM

CTRL

VIP

PCI

m/s

PCI BUS

ISA

m/s

EIDE

PCI

m/s

ISA BUS

CRTC HW Cursor

Monitor

TV Output

SY NC Out pu t

Color Sp ace

Converter

Color

Key

Chroma

Key

Video

pipeline

CCIR Input

EIDE

SVGA

AntiFlicker

IPC

Digital

PAL/

NTSC

STPC Consumer

STPC CONSUMER

2/71 Issue 2.4 - November 8, 2001

■X86 Processo r core

■Fully static 32-bit 5-stage pipeline, x86

processo r fu lly PC compat ible.

■Can access up to 4GBytes of external

memory.

■8KByte unified instruction and data cache

with write back and write through c apability.

■P arallel processing integral floating point unit,

with automatic power down.

■Clock core speeds up to of 100 MHz.

■Fully static design for dynamic clock control.

■Low power and sys tem m anage men t modes.

■Optimi zed design for 3. 3V operation.

■DRAM Controller

■Integrated system memory and graphic fr ame

memory.

■Supp ort s up to 128 MBytes system memory

in 4 banks and down to as li ttle as 2Mbytes.

■Supports 4MB, 8MB, 16MB, 32MB single-

sided and double-sided DRAM SIMMs.

■F our quad-word write buffers for CPU to

DRAM and PCI to DRAM cycles.

■F our 4-word read buffers for PCI masters.

■Supp ort s Fas t Page M ode & EDO DRA M.

■Programmable timing for DRAM param eters

including CAS pulse width, CAS pre-charge

time and RAS to CAS delay.

■60, 70, 80 & 100ns DRAM speeds.

■Memory hole between 1 MByte & 8 MByte

supported f or PCI/ISA busses.

■Hidden refresh.

To check if your memory device is supported by

the STPC, please refer to Table 6-24 in the

Programming Manual.

■Graphics Engine

■64-bit windows accelerator.

■Backward compatibility to SVGA standards.

■Hardware acceleration for text, bitb l ts ,

transparent blts and fills.

■Up to 64 x 64 bit graphics hardware cursor.

■Up to 4MB long linear frame buffer.

■8-, 16-, and 24-bit pixels.

■Drivers f o r Windows and other operating

systems.

■VGA Co ntroller

■Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

■Requires external frequency synthesizer and

reference source s.

■8-, 16-, 24-bit pixels.

■Interla ced or non-interlaced out put.

■Video Input port

■Accepts video inputs in CCIR 601/656 or

ITU-R 601/656, and stream decoding.

■Optional 2: 1 decim ator

■Stores captured video in off setting area of

the onboa rd frame buffer.

■Vide o pass through to the onboard PAL /

NTSC encoder for full screen video images.

■HSYNC and B/T gen eration or lock onto

external video timing so urce.

■Vide o Pipe line

■Two-tap interpol ative horizontal filter.

■Two-tap interpol ative vertical filter.

■Color space conversion (RGB to YUV and

YUV to RGB).

■Programmable window size.

■Chroma and color keying for integrat ed video

overlay.

■Programmable two tap filter with gamma

correction or three tap flicker filter.

■Progressive to interlace d scan converter.

■Digital NTSC/PAL encoder

■NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy

programmable video outputs.

■CCIR601 encoding with programmable color

subcarrier frequenc ies.

■Li ne skip/insert capab ilit y

■Interla ce d or non-interlaced operation mode.

■625 lines/ 50Hz or 525 lines/60Hz 8 bit

multiple xed CB-Y-CR digital input.

■CVBS and R,G,B simultaneous analog

outputs throug h 10-bit DACs.

■Cross color reduction by specific tr ap filtering

on luma within CVBS flow.

■Power down mode availab l e on each D AC.

STPC CONSUMER

Issue 2.4 - November 8, 2001 3/71

■PCI Controlle r

■Fully compliant with PCI 2.1 specification.

■Integrated PCI arbitration interface. Up to 3

mast ers can connect directly. Externa l PAL

allows for greater than 3 masters.

■Translation of PCI cycles to ISA bus.

■Tra n slation of ISA master ini tiated cycle to

PCI.

■Support for burst read/write from PCI master.

■

0.33X and 0.5 X CPU clock PCI clock.

■ISA master/slave Interface

■Generates the ISA clock from either

14 .3 18MHz o s c illa t or cl o ck or P C I clo ck

■Supp ort s programmable extra wait state for

ISA cycles

■Supports I/O reco very time for back to bac k

I/O cycle s.

■Fast Gate A20 and Fast reset.

■

Supp ort s the single ROM that C, D, or E.

blocks s hares wit h F block BIOS ROM.

■Supp ort s flash ROM.

■Supp ort s ISA hidden re fresh.

■Buff ered DMA & I SA master cycl es to reduce

bandwidth utilization of t he PCI and Host bus.

NSP comp li a n t.

■IDE Inte rface

■Supports PIO

■

Supports up to Mode 5 Timings

■Transfer Rates to 22 MBytes/sec

■Supports up to 4 IDE devices

■Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

■Support fo r PIO m ode 3 & 4.

■Supp ort for 11.1/16. 6 MB/s, I/O Channel

Ready PIO data transfers.

■Individual drive timing f or all four IDE devices

■Supp ort s both lega cy & native IDE modes

■Supports hard drives larger than 528MB

■Support for CD-ROM and tape peripherals

■Back wa r d com p at ib il ity wit h IDE (ATA-1 ).

■Drivers f o r Windows and other Operating

Systems

■Integrated peripheral contr oller

■2X8237/AT compatible 7-channel DMA

controller.

■2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

■Three 8254 com patible Timer/Counters.

■Co-proce ssor error suppor t logic.

■Powe r Management

■F our power saving modes: On, Doze,

Standby, Suspend.

■Programmable system activity detector

■Supp ort s SM M and APM.

■Supports STOPCLK.

■Supp ort s IO trap & restart.

■Independent peripheral time-out timer to

moni tor hard disk, serial & parallel por t s.

■Supports RTC, interrupts and DMAs wake-up

STPC CONSUMER

4/71 Issue 2.4 - November 8, 2001

GENERAL DESCRIPTION

Issue 2.4 - November 8, 2001 5/71

1. GENERAL DESCRIPTIO N

At the heart of the STPC Consumer is an ad-

vanced processor block, dubbed the 5ST86. The

5ST86 includes a powerful x86 processor core

along with a 64-bit DRAM controller, advanced

64bit accelerated graph ics and video cont roller, a

high speed PCI local-bus controller and Industry

standard PC chip set functions (Interrupt control-

ler, DMA Controller, Interval timer and ISA bus)

and EIDE controller.

The STPC Consumer has in addition to the

5ST86, a Video subsystem and high quality digital

Television output.

The STMicroelectronics x86 processor core is em-

bedded wit h stan dard and appli catio n specif ic pe-

ripheral modules on the same silicon die. The core

has a ll the func tionality of the S TMicroelectronics

standard x86 processor products, including the

low power System Manage ment Mode (SMM).

System Management Mode (SMM) provides an

additional interrupt and address space that can be

used for system power management or software

transparent emulation of peripherals. While run-

ning in isolated SMM address space, the SMM in-

terrupt r outine can execute without interfering with

th e oper ating system or applica ti o n progr a ms.

Further power management facilities include a

suspend mode that can be initiated from either

hardware or software. Because of the static nature

of the core, no internal data is lost.

The STPC Con sumer makes use of a tightly cou-

pled Unified Memory Architecture (UMA), where

the same memory array is used for CPU main

memory and graphics frame-buffer. This signifi-

cantly reduces total system memory with system

performances equa l to that of a compa rable solu-

tion with separate frame buffer and system mem-

ory. In addition, memory bandwidth is improved by

attaching the graphics engine directly to the 64-bit

processor host interface running at the speed of

the processor bus rather than the traditional PCI

bus.

The 64-bit wide memory array provides the sys-

tem w ith 320M B /s peak bandwidth, double that of

an equi vale nt system us ing 32 bits. This all ows for

higher screen resolutions and greater color depth.

The proces sor bus runs at the spe ed of the proc-

essor (DX dev ices) or half the spee d (DX2 devic-

es).

The ‘standard’ PC chipset functions (DMA, inter-

rupt controller, timers, power management logic)

are integrated with the x86 processor core.

The PCI bus is the ma in data comm unication link

to the STPC Consumer chip. The STPC Consum-

er translates appropriate host bus I/O and Memory

cycles onto the PCI bus. It also supports the gen-

eration of Configuration cycles on the PCI bus.

The STPC Consumer, as a PCI bus agent (host

bridge class), fully complies with PCI specification

2.1. The chip-set also implements the PCI manda-

tory header registers in Type 0 PCI configuration

space for easy porting of PCI aware system BI-

OS. The device contains a PCI arbitrati on function

for three external PCI devices.

The STPC Consum er integrates an ISA bus con-

troller. Peripheral modules such as parallel and

serial communications ports, keyboard c ontrollers

and additional ISA devices can be accessed by

the STPC Consumer chip set through this bus.

An industry standard EIDE (ATA 2) controller is

built in to the STPC Cons umer and connect ed in-

ternally via the PCI bus.

Graphics functions are controlled by the on-chip

SVGA controller and the monitor display is man-

aged by the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provid e a balanced graphics system

with a low silicon area cost. It performs limited

graphics drawing ope ra tio ns, which include hard-

ware acceleration of text, bitblts, transparent blts

and fills. These operations can act on off-screen

or on-screen areas. The frame buffer siz e ranges

up to 4 Mbytes anywhere in the physical main

memory.

The graphics resolution supported is a maximum

of 1280x1024 in 65536 colours at 75Hz refresh

rate and is VGA and SVGA compatible. Horizontal

timing fiel ds are VGA compatible while t he vertical

fields are extended by one bit to accommodate the

above display resolution.

STPC Consumer provides several additional func-

tions to handle MPEG or similar video streams.

The Video Input Port accepts an encoded digital

video stream in one of a number of industry stand-

ard formats, d ecodes it, o ptionally de cima tes it by

a factor of 2:1, and deposits it into an off screen

area of the f rame buffer. An interrupt reques t can

be generated when an entire field or frame has

been captured.

GENERAL DESCRIPTION

6/71 Issue 2.4 - November 8, 2001

The video output pipeline incorporates a video-

scaler and color space converter function and pro-

visions in the CRT controller to display a video

window. While repainting the screen the CRT con-

troller fetches both the video as well as the normal

non-video frame buffer in two separate internal

FIFOs (256-Bytes each). The video stream can be

color-space converted (optionally) and smooth

scaled. Smooth interpolative scaling in both hori-

zontal and vertical directions are implemented.

Color and Chroma key functions are also imple-

mented to allow mixing video stream with non-vid-

eo frame buffer.

The video output passes directly to the RAMDAC

for monitor output or through another optional

color space converter (RGB to 4:2:2 YCrCb) to the

programma ble anti-flicker filter. The flicker filter is

configured as either a two line filter with gamma

correction (primarily designed for DOS type text)

or a 3 line flicker filter (prima rily designed for Win-

dows type displays). The flicker filter is optional

and can be software disabled for use with video on

l arg e screen ar eas.

The Video outpu t pipeline of the STPC Cons um er

interfaces directly to t he internal digital T V enc od-

er. It takes a 24 bit RGB non-interlaced pixel

stream and converts to a multiplexed 4:2:2 YCrCb

8 bit output stream, the logic includes a progres-

sive to interlaced scan converter and logic to in-

sert appropriate CCIR656 timing referenc e codes

into the output stream. It facilitates the high quality

display of VGA or full screen video streams re-

ceived via the Video input port to standa rd NTSC

or PAL televisions.

The STPC Consumer core is compliant with the

Advanced Power Management (APM) specifica-

tion to provide a standard method by which the

BIOS can control the power used by personal

computers. The Power Managem ent Unit modu le

(PMU) controls the power consum ption by prov id-

ing a comprehensive set of features that control

the power usage and supports compliance with

the United States Environmental Protection Agen-

cy's Energy Star Computer Program. The PMU

provides following hardware structures to assist

the software in m anaging the power cons umption

by the system.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity

- SUSP# modul atio n to adj ust the syst em pe rform-

ance in various power down states of the system

including full power on state.

- Power control outputs t o disabl e power f rom di f-

ferent planes of the board.

Lack of system activity for progressively longer

period of times is detected by the three power

down timers. These timers can generate SMI in-

terrupts to CPU so that the SMM software can put

the system in decreasing states of power con-

sump ti o n. Alte rn atively, system activit y in a power

down state can generate SMI interrupt to allow the

software to bring the system back up to full power

on state. The chip-set supports up to three power

down states: Doze state, Stand-by state and Sus-

pend mode. These correspon d to decre asing lev-

els of power savings.

Power down puts the STPC Consumer into sus-

pend mode. The processor completes execution

of the current instruction, any pending decoded in-

structions and associated bus cycles. During the

suspend mode, internal clocks are stopped. Re-

moving power down, the processor resumes in-

struction fetching and begins execution in the in-

struction stream at the point it had stoppe d.

A reference design for the STPC Consumer is

available including the schematics and layout

files, the design is a PC ATX motherboard design.

The design is availabl e as a demonst ration board

for application and system development.

The STPC Consumer is supported by several

BIOS vendors, including the super I/O device

used in the reference design. Drivers for 2D accel-

erator, video features and EIDE are availaible on

various operating systems.

The STPC Consumer has been designed using

modern reusable m odular design tec hniques, it is

possible to add or remove the standard features of

the STPC Consumer or other variants of the

5ST86 fam ily. Contact your local STMicroelecton-

ics sales office for furth er information.

GENERAL DESCRIPTION

Issue 2.4 - November 8, 2001 7/71

Fi gure 1- 1 Function nal de sc ript ion

x86

Core

Host I/F

DRAM

I/F

SVGA

VIP

PCI m/s PCI BUS

ISA

m/s

EIDE

PCI m/s

ISA BUS

CRTC HW Cursor

Monitor

TV Output

SYNC Output

IPC

82C206

Anti-Flicker

C ol o r S p ace

Converter

Color

Key

Chroma

Key

Video

pipeline

CCIR Input

EIDE

Digital

PAL/

NTSC

GENERAL DESCRIPTION

8/71 Issue 2.4 - November 8, 2001

Figure 1-2 Typical Application

STPC C onsumer

ISA

PCI

4x 16-bit EDO DRAMs

Super I/O

2x EIDE

Flash

Keyboard / Mouse

Seri a l Port s

Parall el Port

Floppy

Monitor

Video

SVGA

CCIR601

CCIR656

S-VHS

RGB

PAL

NTSC

IRQ

DMA.REQ

DMA.ACK

DMUX

MUX

RTC

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 9/71

2. PIN DESCRIPTION

2.1 INTRODUCTION

The STPC Consum er int egrates most of the func-

tionalities of the PC architecture. As a result, many

of the traditional interconnections between the

host PC microproces sor and the peripheral devic-

es are totally internal to the STPC Consumer. This

offers improved perform ance due to the tight cou-

pling of the proce ssor core and these peripherals.

As a result many of the external pin connections

are made directly to the on-chip peripheral func-

tions.

ure 2-1 shows the STPC Consumer’s external

interfaces. It defines the main busses and their

function. Table 2-1 describes the physical imple-

mentation listing signal types and their functionali-

ties. Tabl e 2-2 provides a full pin listing and de-

scription. Table 2-3 provides a full listing of the

STPC Consumer pin locations of package by

physical connection. Please refer to the pin alloca-

tion drawing for reference. Note: Several interface pins are multiplexed with

other functions, refer to the Pin Description sec-

tion for further details

Table 2-1. Signal Description

Group name Qty

Basic Clocks reset & Xtal(SYS) 12

DRAM Controller 89

PCI interface (PCI) 58

ISA / IDE / IPC combined interface 88

Video Input (VIP) 9

TV Output 10

VGA Monitor interface 10

Grounds 69

VDD 26

Analog speci fic VCC/VDD 12

Reserved 5

Total Pin Count 388

Figure 2-1. STP C Cons um er E xtern al Interfaces

SOUTHNORTH PCI

x86

DRAM VGA VIP TV SYS ISA/IDE IPC

89 10 9 10 58 13 77 11

STPC Consumer

PIN DESCRIPTION

10/71 Issue 2.4 - November 8, 2001

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

BASIC CLOCKS AND RESETS

SYSRSTI# I System Reset / Power good 1

XTALI I 14.3MHz Crystal Input 1

XTALO I/O 14.3MHz Crystal Output - External Oscillator Input 1

HCLK O Host Clock (Test) 1

DEV_CLK O 24MHz Peripheral Clock (floppy drive) 1

GCLK2X I/O 80MHz Graphics Clock 1

DCLK I/O 135MHz Dot Clock 1

PCI_CLKI I 33MHz PCI Input Clock 1

PCI_CLKO O 33MHz PCI Output Clock (from internal PLL) 1

SYSRSTO# O Reset Output to System 1

ISA_CLK O ISA Clock Output - Multiplexer Select Line For IPC 1

ISA_CLK2X O ISA Clock x 2 Output - Multiplexer Select Line For IPC 1

MEMORY INTERFACE

MA[11:0] O Memory Address 12

RAS#[3:0] O Row Address Strobe 4

CAS#[7:0] O Column Address Strobe 8

MWE# O Write Enable 1

MD[63:0] I/O Memory Data 64

PCI INTERFACE

AD[31:0] I/O PCI Address / Data 32

CBE[3:0] I/O Bus Commands / Byte Enables 4

FRAME# I/O Cycle Frame 1

TRDY# I/O Target Read y 1

IRDY# I/O Initiator Ready 1

STOP# I/O Stop Transaction 1

DEVSE L# I/O Device Selec t 1

PAR I/O Parity Signal Transactions 1

SERR# O System Error 1

LOCK# I PCI Lock 1

PCIREQ#[2:0] I PCI Request 3

PCIGNT#[2:0] O PCI Grant 3

PCI_INT[3:0] I PCI Interrupt Request 4

VDD5 I 5V Power Supply for PCI ESD protection 4

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22] / SCS3#,SCS1# I/O Unlatched Address (ISA) / Secondary Chip Select (IDE) 2

LA[21:20] / PCS3#,PCS1# I/O Unlatched Address (ISA) / Primary Chip Select (IDE) 2

LA[19:17] / DA[2:0] O Unlatched Address (ISA) / Address (IDE) 3

RMRTCCS# / DD[15] I/O ROM/RTC Chip Select / Data Bus bit 15 (IDE) 1

KBCS# / DD[14] I/O Keyboard Chip Select / Data Bus bit 14 (IDE) 1

RTCRW# / DD[13] I/O RTC Read/Write / Data Bus bit 13 (IDE) 1

RTCDS# / DD[12] I/O RTC Data Strobe / Data Bus bit 12 (IDE) 1

SA[19:8] / DD[11:0] I/O Latched Address (ISA) / Data Bus (IDE) 16

SA[7:0] I/O Latched Address (IDE) 4

SD[15:0] I/O Data Bus (ISA) 16

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 11/71

ISA/IDE COMBINED CONTROL

IOCHRDY / DIORDY I/O I/O Channel Ready (ISA) - Busy/Ready (IDE) 1

ISA CONTROL

OSC14M O ISA bus synchronisation clock 1

ALE O Address Latch Enable 1

BHE# I/O System Bus High Enable 1

MEMR#, MEMW# I/O Memory Read and Memory Write 2

SMEMR#, SMEMW# O System Memory Read and Memory Write 2

IOR#, IOW# I/O I/O Read and Write 2

MASTER# I Add On Card Owns Bus 1

MCS16#, IOCS16# I Memory/IO Chip Select16 2

REF# O Refresh Cycle. 1

AEN O Address Enable 1

ZWS# I Zero Wait State 1

IOCHCK# I I/O Channel Check. 1

ISAOE# O B idirect ional OE Contro l 1

RTCAS O Real Time Clock Address Strobe 1

GPIOCS# I/O General Purpose Chip Select 1

IDE CONTROL

PIRQ I Primary Interrupt Request 1

SIRQ I Secondary Interrupt Request 1

PDRQ I Primary DMA Request 1

SDRQ I Secondary DMA Request 1

PDACK# O Primary DMA Acknowledge 1

SDACK# O Secondary DMA Acknowledge 1

PIOR# I/O Primary I/O Read 1

PIOW# O Primary I/O Write 1

SIOR# I/O Secondary I/O Read 1

SIOW# O Secondary I/O Write 1

IPC

IRQ_MUX[3:0] I Multiplexed Interrupt Request 4

DREQ_MUX[1:0] I Multiplexed DMA Request 2

DACK_ENC[2:0] O DMA Acknowledge 3

TC O ISA Terminal Count 1

MONITOR INTERFACE

RED, GREEN, BLUE O Red, Green, Blue 3

VSYNC O Vertical Sync 1

HSYNC O Horizontal Sync 1

VREF_DAC I DAC Voltage reference 1

RSET I Resistor Set 1

COMP I Compensation 1

COL_SE L O Colour Selec t 1

SCL / DDC[1] I/O I²C Interface - Clock / Can be used for VGA DDC[1] signal 1

SDA / DDC[0] I/O I²C Interface - Data / Can be used for VGA DDC[0] signal 1

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

PIN DESCRIPTION

12/71 Issue 2.4 - November 8, 2001

VIDEO INPUT

VCLK I Pixel Clock 1

VIN I YUV Video Data Input CCIR 601 or 656 8

TV OUTPUT

RED_TV, GREEN_TV, BLUE_TV O Analog video outputs synchronized with CVBS 3

VCS O Composite Synch or Horizontal line SYNC output 1

ODD_E VEN O Fr ame Synch ronis ation 1

CVBS O Analog video composite output (luminance / chrominance) 1

IREF1_TV I Reference current of 9bit DAC for CVBS 1

VREF1_TV I Reference voltage of 9bit DAC for CVBS 1

IREF2_TV I Reference current of 8bit DAC for R,G,B 1

VREF2_TV I Reference voltage of 8bit DAC for R,G,B 1

VSSA_TV I Analog Vss for DAC 1

VDDA_TV I Analog Vdd for DAC 1

MISCELLANEOUS

SPKRD O Speaker Device Output 1

SCAN_ENABLE I Reserved (Test pin) 1

Table 2-2. Definition of Signal Pins

Signal Name Dir Description Qty

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 13/71

2.2 SIGNAL DESCRIPTIONS

2.2 .1 BASIC CLOCKS AND RESETS

SYSRSTI

System Reset/Power good.

This input is

low when the reset switch is depressed. Other-

wise, it reflects the power supply’s power good

signal. SYSRSTI is asynchronous to all clocks,

and acts as a n egat ive ac tive res et. T he reset cir-

cuit initiates a hard reset on the rising edge of

SYSRSTI.

SYSRSTO#

Reset Output to System.

This is the

system reset signal and is used to r eset the r est of

the components (not on Host bus) in the system.

The ISA bus reset is an externally inverted buff-

ered version of this output and the PCI bus reset is

an externally buffered version of this output.

XTALI

14.3MHz Crystal Input

XTALO

14.3MHz Crystal Output.

These pins are

the 14.318 MHz crystal input; This clock is used as

the reference clock for the internal frequency syn-

thesizer to generate the HCLK, CLK24M,

GCLK2X and DCLK clocks.

A 14.318 MHz Series Cut Quartz Crystal should

be connected between these two pins. Balance

capacitors of 15 pF should also be added. In the

event of an external oscillator providing the master

clock signal to the STPC Consumer device, the

TTL signal should be provided on XTALO.

HCLK

Host Clock.

This is the host 1X clock. Its

frequency can vary from 25 to 75 MHz. All host

transactions and PCI transactions are synchro-

nized to this clock. The DRAM controller to exe-

cute the host transactions is also driven by this

clock. In normal mode, this output clo ck is gener-

ated by the internal pll.

GCLK2X

80MHz Graphics Clock.

This is the

Graphics 2X clo ck, which drives the graphics en-

gine and the DRAM controller to execute the

graphics and display cycles .

Normally GCLK2X is generated by the internal fre-

quency synthesizer, and this pin is an output. By

setting a bit in Strap Register 2, this pin can be

made an input so that an external clock can re-

place the internal frequency synthesizer.

PCI_CLKI

33MHz PCI Input Clock

This signal is the PCI bus clock input and should

be driven from the PCI_CLKO pin.

PCI_CLKO

33MHz PCI Output Clock.

Th is i s th e

maste r PCI bus clo ck outpu t.

DCLK

135MHz Dot Clock.

This is the dot clock,

which drives graphics di splay cycles. I ts frequency

can go from 8M Hz (using internal PLL) up to 135

MHz, and it is re quired to have a wors t case d uty

cycle of 60-40.

This signal is either driven by the internal pll (VGA)

or an external 27MHz oscillator (when the com-

posite video output is enabled). The direct ion can

be controlled by a strap option or an internal regis-

ter b i t .

ISA_CLK

ISA Clo ck O utput (a lso Multiplexer Se-

lect Line For IPC).

This pin produces the Clock

signal for the ISA bus. It is also used with

ISA_CLK2X as the multiplexor control lines for the

Interrupt Controller Interrupt input lines. This is a

divided down version of either the PCICLK or

OSC14M.

ISA_CLKX2

ISA Clock Output (also Multiplexer

Select Line For IPC).

This pin produces a signal

that is twice the frequency of the ISA bus Clock

signal. It is also used with ISA_CLK as the multi-

plexor control lines for the Interrupt Controller in-

put lines.

DEV_CLK

24MHz Peripheral Clock Output.

This

24MHZ signal is provided as a convenience for

the system integration of a Floppy Disk driver

function in an external chip.

OSC14M

ISA bus synchronisation clock Output.

This is the buffered 14.318 Mhz clock to the ISA

bus.

2.2.2 MEMORY INTERFACE

MA[11:0]

Memory Address Output.

These 12 mul-

tiplexed memory address pins support external

DRAM with up to 4K refresh. These include all

16M x N and some 4M x N DRAM modules. The

address signals must be externally buffered to

support mo re tha n 16 DR AM chips. T he timing of

these signals can be adjusted by software to

match the timings of most DRAM modules.

PIN DESCRIPTION

14/71 Issue 2.4 - November 8, 2001

MD[63:0]

Memory Data I/O.

This is the 64-bit

memory data bus. If only half of a bank is populat-

ed, MD63-32 is pulled high, data is on MD31-0.

MD[40-0] are read by the dev ice st rap option reg-

isters during rising edge of SYSRSTI.

RAS#[3:0]

Row Address Strobe Output.

There

are 4 active low row address strobe outputs, one

for each bank of the memory. Each bank contains

4 or 8-Bytes of data. The memory controller allows

half of a bank (4-by tes) to be populat ed to enab le

memory upgrade at finer granularity.

The RAS# signals drive the SIMMs directly with-

out any external buffering. These pins are always

outputs, but they can also simultaneously be in-

puts, to all ow the memory controller to monitor the

value of the RAS# signals at the pins.

CAS#[7:0]

Column Address Strobe Output.

There

are 8 active low column address strobe outputs,

one each for each byte of the memory.

The CAS# s ignals drive the S IMMs either di rectly

or through external buffers.

These pins are always outputs, but they can also

simultaneously be inputs, to allow the memory

controller to monitor the value of the CAS# signals

at the pins.

MWE#

Write Enable Output.

Write enable speci-

fies whether the memory access is a read (MWE#

= H) or a write (MWE# = L). This single write ena-

ble controls all the DRAM. It can be externally

buffered to boost the maximum number of loads

(DRAM chips) supporte d.

The MWE# signals drive the SIMMs directly with-

out any external buffering.

2.2.3 VIDEO INTERFACE

VCLK

Pixel Clock Input.

VIN[7:0]

YUV Video Data Input CCIR 601 or 656.

Time multiplexed 4:2:2 luminance and chromi-

nance data as defined in ITU-R Rec601-2 and

Rec656 (except for T TL input le ve ls). This bu s in-

terfaces with an M PE G vid eo decoder out put po rt

and typically carries a stream of Cb,Y,Cr,Y digital

video at VCLK frequency, clocked on the rising

edge (by default) of VCLK. A 54-Mbit/s ‘double’

Cb, Y, Cr, Y input multiplex is supported for double

encoding application (rising and falling edge of

CKRE F are op erating).

2.2.4 TV OUTPUT

RED_TV / C_TV

Analog video outputs synchro-

nized with CVBS.

This output is current-driven and

must be connected to an alog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is the Chrominance Output.

GREEN_TV / Y_TV

Analog video outputs syn-

chronized with CVBS.

This output is current-driv-

en and must be connected to analog ground over

a load resistor (RLOAD). Following the load resis-

tor, a simple analog low pass filter is recommend-

ed. In S-VHS mode, this is the Luminance Output.

BLUE_TV / CVBS

Analog video outputs synchro-

nized with CVBS.

This output is current-driven and

must be connected to an alog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is a second composite output.

VCS

Line synchronisation Output.

This pin is an

input in O DDEV+HSYNC or VS YNC + HSYN C or

VSYNC slave modes and an output in all other

modes (master/slave)

The signal is synchronous to rising edge of CK-

REF. The default polarity uses a negative pulse

ODD_EVEN

Frame Sy nchronisation Ourput .

This

pin supports the Frame synchronisation signal. It

is an input in slave modes, except when sync is

extracted from YCrCb data, and an output in mas-

ter mode and when sync is extracted from YCrCb

data

The signal is synchronous to rising edge of DCLK.

The default polarity for this pin is:

- odd (not-top) field : LOW level

- even (bottom) field : HIGH level

IREF1_TV

Ref. current

for CVBS 10-bit DAC.

VREF1_TV

Ref. voltage

for CVBS 10-bit DAC.

IREF2_TV

Reference current

for RGB 9-bit DAC.

VREF2_TV

Reference voltage

for RGB 9-bit DA C.

VSSA_TV

Analog V

for DAC

VDDA_TV

Analog V

for DAC

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 15/71

CVBS

Analog video composite output (luminance/

chrominance).

CVBS is current-driven and must

be connected to analog grou nd over a load resis-

tor (RLOAD). Following the load resistor, a simple

analog low pass filter is recommend ed.

2.2.5 PCI INT E RFACE

AD[31:0]

PCI Address/Data.

This is the 32-bit

multiplexed address and data bus of the PCI. This

bus is driven by the master during the address

phase and data phase of write transactions. It is

driven by the target during data phase of read

transactions.

CBE#[3:0]

Bus Commands/Byte Enables.

These

are the multiplexed command and byte enable

signals of the PCI bus. During the addres s phase

they define the command and during the data

phase they carry the byte enable information.

These pins are inputs when a PCI master other

than the STPC Consumer owns the bus and out-

puts when the STPC Consumer owns the bus.

FRAME#

Cycle Frame.

This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Consumer

owns the PCI bus.

TRDY#

Target Ready.

This is t he t arget ready sig-

nal of the PCI bus. It is driven a s an output when

the STPC Consumer is the target of the current

bus transaction. It is used as an input when STPC

Consumer initiates a cycle on the PCI bus.

IRDY#

Initiator Ready.

This is the initiator ready

signal of the PCI bus. It i s used as an output when

the STPC Consumer initiates a bus cycle on the

PCI bu s. It is used as an input during the P CI cy-

cles targeted to the STPC Consumer to determine

when the current PCI master is ready to complete

the current transaction.

STOP#

Stop Transaction.

Stop is used to imple-

ment the disconnect, retry and abort protocol of

the PCI bus. It is used as an input for the b us cy-

cles initiated by the ST PC Consum er a nd is used

as an output when a PCI master cycle is targeted

to the STPC Consum er.

DEVSEL#

I/O Device Select.

This signal is used

as a n input w hen the S TPC Con sumer initiates a

bus cycle on the PCI bus to determine if a PCI

slave device has dec oded itself to be the target of

the current transaction. It is asserted as an output

either when the STPC Consumer is the target of

the current PCI transaction or when no o ther de-

vice asserts DEVSEL# prior to the subtractive de-

code phase of the current PCI transaction.

PAR

Parity Signal Transactions.

This i s the parity

signal of the PCI bus. This signal is used to guar-

antee even parity across AD[31:0], CBE#[3:0],

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

phase of read transactions. (Its assertion is identi-

cal to t hat of the AD bus delayed by one PCI clock

cycle)

SERR#

System Error.

This is the system error si g-

nal of the PCI bus. It may, if enabled , be a sserted

for one PCI clock cycle if target aborts a STPC

Consumer initiated PCI transaction. Its assertion

by either the ST PC Consumer or by ano ther PCI

bus agent will trigger the assertion of NMI to the

host CPU. This is an open drain output.

LOCK#

PCI Lock.

This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

PCIREQ#[2:0]

PCI Request.

This pin are the

three external PCI master request pins. They indi-

cates to the PCI arbiter that the external agents

desire use of the bus.

PCIGNT#[2:0]

PCI Grant.

These pins indicate that

the PCI bus has been granted to the master re-

questing it on its PCI REQ #.

2.2.6 ISA/IDE COMBINED ADDRESS/DATA

LA[23]/SCS3#

Unlatche d Address (ISA )/Second-

ary Ch ip S elec t (IDE ).

This pin has t wo functions,

depending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 23 for 16-bit devices. W hen

ISA bus is accessed by any cycle initiated from

PCI bus, t his pin is in output m ode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally NANDed with

the IS A OE # signal be fore driving the ID E devices

to guarantee it is active only when ISA bus is idle.

PIN DESCRIPTION

16/71 Issue 2.4 - November 8, 2001

LA[22]/SCS1#

Unlatche d Address (ISA )/Second-

ar y Chip Se l ect (IDE)

This pin has two function s, depend ing on whether

the ISA bus is active or the IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 22 for 16-bit devices. W hen

ISA bus is accessed by any cycle initiated from

PCI bus, th is pin is in output m ode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally ANDed with

the IS A OE # signal be fore driving the ID E devices

to guarantee it is active only when ISA bus is idle.

LA[21]/PCS3#

Unlatched Address (ISA)/Primary

Chip Selec t (ID E).

This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 21 for 16-bit devices. W hen

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA-

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip sele ct sig-

nal. This signal is to be externally NANDed with

the IS A OE # signal be fore driving the ID E devices

to guarantee it is active only when ISA bus is idle.

LA[20]/PCS1#

Unlatched Address (ISA)/Primary

Chip Selec t (ID E).

This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 20 for 16-bit devices. W hen

ISA bus is accessed by any cycle initiated from

PCI bus, th is pin is in output m ode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip sele ct sig-

nal. This signal is to be externally NANDed with

the IS A OE # signal be fore driving the ID E devices

to guarantee it is active only when ISA bus is idle.

LA[19:17]/DA[2:0]

Unlatched Address (ISA)/Ad-

dress (IDE).

These pins are multi-function pins.

They are us ed as t he ISA bus unla tched address

bits [19:17] for ISA bus or the three address bits

for the IDE bus devices.

When used by the ISA bus, these pins are ISA

Bus unlatched address bits 19-17 on 16-bit devic-

es. When ISA bus is accessed by any cycle initiat-

ed from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristat ed.

For IDE devices, these signals are used as the

DA[2:0] and are connected to DA[2:0] of IDE de-

vices directly or through a buffer. If the toggling of

signals are to be masked during ISA bus cycles,

they can be externally ORed before being con-

nected to the IDE devices.

SA[19:8]/DD[11:0]

Unlatched Address (ISA)/Data

Bus (IDE).

These are multifunction pins. When the

ISA bus is active, they are used as the ISA bus

system address bits 19-8. When the IDE bus is ac-

tive, they serve as IDE signals DD[11:0].

These pins are used as an input when an ISA bus

master owns the bus and are outputs at all other

times.

IDE devices are connected to SA[19:8] directlyand

ISA bus is connected to these pins through two

LS245 transceivers. The OE of the transceivers

are connected to I SAOE# and DIR is connected to

MASTER#. A bus signals of the transceivers are

connected to CPC and IDE DD bus and B bus sig-

nals are connected to ISA SA bus.

DD[15:12]

Databus (IDE).

The high 4 bits of the

IDE databus are combined with several of the X-

bus lines. Re fer to the follo wing section for X-bus

pins for further information.

SA[7:0]

ISA Bus address bits [7:0].

These are the

8 low bits of the system address bus of ISA on 8-

bit slot. These pins are used as an input when an

ISA bus master owns the bus and are outputs at

all other times.

SD[15:0]

I/O Data Bus (ISA).

These pins are the

external databus to the ISA bus.

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 17/71

2.2.7 ISA/IDE COMBINED CONTROL

IOCHRDY/DIORDY

Channel Ready (ISA)/Busy/

Ready (IDE).

This is a multi-function pin. When

the ISA bus is active, this pin is IOCHRDY. When

the IDE bus is active, this serves as IDE si gnal DI-

ORDY.

IOCHRDY is the IO channel ready signal of the

ISA bus and i s driven as an out put in respons e to

an ISA master cycle targeted to the host bus or an

internal register of the STPC Consumer. The

STPC Consum er monitors this signal as an input

when performing an ISA cycle on behalf of the

host CPU, DMA master or re fresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Consum er

since the access to the system memory can be

considerably delayed due to CRT refresh or a

writ e back cycl e.

2.2.8 ISA CONTROL

ALE

Address Latch Enable.

This is the address

latch enable output of the ISA bus and is asserted

by the S TPC Cons umer to i ndicate that LA 23-17,

SA19-0, AEN and SBHE# signals are valid. The

ALE is driven high during refresh, DMA m aster or

an ISA master cycles by the STPC Consumer .

ALE is driven low after reset.

BHE#

System Bus High Enable.

This signal, when

asserted, indicates that a data byte is being trans-

ferred on SD15-8 lines. It is used as an input when

an ISA master owns the bus and is an output at all

other times.

MEMR#

Memory Read.

This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write.

This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

SMEMR#

System Memory Read.

The STPC Con-

sumer generates SMEMR# signal of the ISA bus

only when th e address is below o ne megabyte or

th e cycle is a refr es h cycle.

SMEMW#

System Memory Write.

The STPC Con-

sumer generat es SMEM W# signal of th e ISA bus

only when the address is below one megabyte.

IOR#

I/O Read.

This is t he IO read c om m and sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

IOW#

I/O Write.

This is the IO write command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

MASTER#

Add On Card Owns Bus.

This signal is

active when an ISA device has been granted bus

ownership.

MCS16#

Memory Chip Select16.

This is the de-

code of LA23-17 address pins of the ISA address

bus withou t any qualification of the c ommand sig-

nal lines. MCS16# is always an input. The STPC

Consumer ignores this signal during IO and re-

fresh cycles.

IOCS16#

IO Chip S elect16.

This signal is the de-

code of SA15-0 address pins of the ISA address

bus withou t any qualification of the c ommand sig-

nals. The STPC Consumer does not drive

IOCS16# (similar to PC-A T design). An ISA mas-

ter access to an internal register of the STPC Con-

sumer is executed as an extended 8-bit IO cycle.

REF#

Refresh Cycle.

This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Consume r performs a refresh cy-

cle on the ISA bus. It is used as an in put when an

ISA master owns the bus and is used to trigger a

refresh cycle.

The STPC Consumer performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

I SA bus.

AEN

Address Enable.

Address E nable is enabled

when the DM A c ontroller is the bus owner to i ndi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

PIN DESCRIPTION

18/71 Issue 2.4 - November 8, 2001

ZWS#

Zero W ait Stat e.

This signal, when assert-

ed by addressed device, indicates that cu rrent cy-

cle can be shortened.

IOCHCK#

IO C hannel Che ck.

IO Cha nnel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

ISAOE#

Bidirectional OE Control.

This signal con-

trols the OE sig nal of the ex ternal t ransceiv er that

connects the IDE DD bus and ISA SA bus.

GPIOCS#

I/O General Purpose Chip Select 1.

This output signa l is used by the ex ternal latc h on

ISA b us t o l atch t he d ata on t he SD [7: 0] bus. T he

latch can be use by P MU un it to control the exter-

nal peripheral devices to power down or any other

desired function.

2.2.9 IDE CONTROL

PIRQ

Primary Interrupt Request.

Interrupt request

from primary IDE channel.

SIRQ

Secondary Interrupt Request.

Interrupt re-

quest from secondary IDE channel.

PDRQ

Primary DMA Request .

DMA reques t from

primary IDE channel.

SDRQ

Secondary DMA Request.

DMA request

from secondary IDE channel.

PDACK#

Primary DMA Acknowledge.

DMA ack-

noledge to primary IDE channel.

SDACK#

Secondary DMA Acknowledge.

DMA

acknoledge to secondary IDE channel.

PIOR#

Primary I/O Read.

Primary channel read.

Active low output.

PIOW#

Primary I/O Write

. Primary channel write.

Active low output.

SIOR#

Secondary I/O Read

Secondary channel

read. Active low output.

SIOW#

Secondary I/O Write

Secondary channel

write. Active low output.

2.2.10 IPC

IRQ_MUX[3:0]

Multiplexed Interrupt Request.

These are the ISA bus interrupt signals. They are

to be encoded before connection to the STPC

Consumer using ISACLK and ISACLKX2 as the

input selection strobes.

Note that IRQ8B, which by convention is connect-

ed to the RTC, is inverted before being sent to the

interrupt controller, so that it may be connected di-

rectly to the IRQ pin of the RTC.

PCI_INT[3:0]

PCI Interrupt Request.

These are

the PCI bus interrupt signals. They are to be en-

coded before connection to the STPC Consumer

using ISACLK and ISACLKX2 as the input selec-

tion strobes.

DREQ_MUX[1:0]

ISA Bus Multiplexed DMA Re-

quest.

These are the ISA bus DMA request sig-

nals. They are to be encoded before connection to

the STPC Consumer using ISACLK and

ISACLKX2 as the input selection strobes.

DACK_ENC[2:0]

DMA Acknowledge.

These are

the ISA b us DMA ac knowledge sig nals. They are

encoded by the STPC Consumer before output

and should be decoded externally using ISACLK

and ISACLKX 2 as the control strobes.

ISA Terminal Count.

This is t he termina l count

output of the DMA controller and is connected to

the TC line of the ISA bus. It is asserted during the

last DMA transfer, when the byte count expires.

SPKRD

Speaker Drive.

This the output to the

speaker and is AND of the counter 2 output with

bit 1 of Port 61, and drives an external speaker

driver. This output should be connected to 7407

type high voltage driver.

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 19/71

2.2.11 X-Bus Interface pins / IDE Data

RMRTCCS# / DD[15 ]

ROM/Real Time clock chip

se lec t.

This pin is a multi-function pin. When

ISAOE# is active, this signal is used as RM-

RTCCS#. This signal is asserted if a ROM access

is decoded during a memory cycle. It should be

combined with MEMR# or MEMW# signals to

properly access the ROM. During a IO cycle, this

signal is asserted if access to the Real Time Clock

(RTC) is decoded. It should be combined with IOR

or IOW# signals to properly access the real time

clock.

When ISAOE# is inactive, this signal is used as

IDE DD[15] signal.

This signal must be ORed externally with ISAOE#

and is then connected to ROM and RTC. An

LS244 or equivalent function can be used if OE# is

connected to ISAOE# and the output is provided

with a weak pull-up resistor.

KBCS# / DD[14]

Keyboard Chip Select.

This pin

is a multi-function pin. When ISAOE# is active,

this signal is used as KBCS#. This signal is assert-

ed if a keyboard access is decoded during a I/O

cycle.

When ISAOE# is inactive, this signal is used as

IDE DD[14] signal.

This signal must be ORed externally with ISAOE#

and is then connected to keyboard. An LS244 or

equivalent function can be used if OE# is connect-

ed to ISAOE# and the output is provided with a

weak pull-up resistor.

RTCRW# / DD[13]

Real Time Clock RW.

This pin

is a multi-function pin. When ISAOE# is active,

this signal is used as RT CRW#. T his s ig nal is as-

serted for any I/O write to port 71H.

When ISAOE# is inactive, this signal is used as

IDE DD[13] signa l. This sig nal must be O Red ex-

ternally with ISAOE# and then connected to the

RTC. An LS244 or equivalent function can be

used if OE is connected to ISAOE# and the output

is provided with a weak pull-up resistor.

RTCDS# / DD[12]

Real Time Clock DS

. This pin is

a multi-function pin. When ISAOE# is active, this

signal is used as RTCDS#. This signal is asserted

for any I/O read to port 71H. Its polarity complies

with the DS pin of t he MT48T86 RTC device when

configured with Intel timings.

When ISAOE# is inactive, this signal is used as

IDE DD[12] signa l. This sig nal must be O Red ex-

ternally with ISAOE# and is then connected to

RTC. An LS244 or equivalent function can be

used if OE# is connected to I SAOE # and the out-

put is provided with a weak pull-up resistor.

RTCAS

Real time clock address strobe.

This sig-

nal is asserted for any I/O write to port 70H.

2.2.12 Monitor Interface

RED, GREEN, BLUE

RGB Video Out put s.

These

are the 3 analog color outputs from the RAM-

DACs. These signals are sensitive to i nterf erence,

therefore they need to be properly shielded.

VSYNC

Vertical Synchronisation Pulse.

This is

the vertical synchronization signal from the VGA

controller.

HSYNC

Horizontal Synchroni sa tion Pulse.

Th is is

the horizontal synchronization signal from the

VGA controller.

VREF_DAC

DAC Voltage reference.

An external

voltage reference is connected to this pin to bias

the DAC.

RSET

R esistor Current Set.

This is reference cur-

rent input to the RAMDAC is used to set the full-

scale output of the RAMDAC.

COMP

Compensation.

T his is the R A M D AC co m-

pensation pin. Normally, an external capacitor

(typically 10nF) is connected between this pin and

VDD to damp oscillations.

DDC[1:0]

Direct Data Channel Serial Link.

These

bidirectional pins are connected to CRTC register

3Fh to implement DDC capabilities. T hey conform

to I2C electrical specifications, they have open-

collector output drivers which are internally con-

nected to VDD through pull -up resistors.

They can instead be used for accessing I²C devic-

es on board. DDC1 and DDC0 correspond to SCL

and SDA respectiv ely.

2.2.13 MISCELLANEOUS

SCAN_ENABLE

Reserved

. The pins are re-

served for Test and Miscellaneous functions)

PIN DESCRIPTION

20/71 Issue 2.4 - November 8, 2001

Table 2-3. Pinout.

Pin # Pin name

AF3 SYSRSTI

A3 XTALI

C4 XTALO

G23 HCLK

F25 DEV_CLK

AF15 GCLK2X

AF9 DCLK

AD15 MA[0]

AF16 MA[1]

AC15 MA[2]

AE17 MA[3]

AD16 MA[4]

AF17 MA[5]

AC17 MA[6]

AE18 MA[7]

AD17 MA[8]

AF18 MA[9]

AE19 MA[10]

AF19 MA[11]

AD18 RAS#[0]

AE20 RAS#[1]

AC19 RAS#[2]

AF20 RAS#[3]

AE21 CAS#[0]

AC20 CAS#[1]

AF21 CAS#[2]

AD20 CAS#[3]

AE22 CAS#[4]

AF22 CAS#[5]

AD21 CAS#[6]

AE23 CAS#[7]

AC22 MWE#

AF23 MD[0]

AE24 MD[1]

AF24 MD[2]

AD25 MD[3]

AC25 MD[4]

AC26 MD[5]

AB24 MD[6]

AA25 MD[7]

AA24 MD[8]

Y25 MD[9]

Y24 MD[10]

V23 MD[11]

W24 MD[12]

V26 MD[13]

V24 MD[14]

U23 MD[15]

U24 MD[16]

R26 MD[17]

P25 MD[18]

P26 MD[19]

N25 MD[20]

N26 MD[21]

M25 MD[22]

M26 MD[23]

M24 MD[24]

M23 MD[25]

L24 MD[26]

J25 MD[27]

J26 MD[28]

H26 MD[29]

G25 MD[30]

G26 MD[31]

AD22 MD[32]

AD23 MD[33]

AE26 MD[34]

AD26 MD[35]

AC24 MD[36]

AB25 MD[37]

AB26 MD[38]

Y23 MD[39]

AA26 MD[40]

Y26 MD[41]

W25 MD[42]

W26 MD[43]

V25 MD[44]

U25 MD[45]

U26 MD[46]

T25 MD[47]

R25 MD[48]

T24 MD[49]

R23 MD[50]

R24 MD[51]

N23 MD[52]

P24 MD[53]

N24 MD[54]

L25 MD[55]

L26 MD[56]

K25 MD[57]

K26 MD[58]

K24 MD[59]

H25 MD[60]

J24 MD[61]

H23 MD[62]

H24 MD[63]

F24 PCI_CLKI

Pin # Pin name D25 PCI_CLKO

A20 AD[0]

C20 AD[1]

B19 AD[2]

A19 AD[3]

C19 AD[4]

B18 AD[5]

A18 AD[6]

B17 AD[7]

C18 AD[8]

A17 AD[9]

D17 AD[10]

B16 AD[11]

C17 AD[12]

B15 AD[13]

A15 AD[14]

C16 AD[15]

D15 AD[16]

A14 AD[17]

C15 AD[18]

B13 AD[19]

D13 AD[20]

A13 AD[21]

C14 AD[22]

C13 AD[23]

A12 AD[24]

B11 AD[25]

C12 AD[26]

A11 AD[27]

D12 AD[28]

B10 AD[29]

C11 AD[30]

A10 AD[31]

D10 CBE[0]

C10 CBE[1]

A9 CBE[2]

B8 CBE[3]

A8 FRAME#

B7 TRDY#

D8 IRDY#

A7 STOP#

C8 DEVSEL#

B6 PAR

D7 SERR#

A6 LOCK#

C21 PCI_REQ#[0]

A21 PCI_REQ#[1]

B20 PCI_REQ#[2]

C22 PCI_GNT#[0]

Pin # Pin name

PIN DESCRIPTION

Issue 2.4 - November 8, 2001 21/71

B21 PCI_GNT#[1]

D20 PCI_GNT#[2]

A5 PCI_INT[0]

C6 PCI_INT[1]

B4 PCI_INT[2]

D5 PCI_INT[3]

F2 LA[17]/DA[0]

G4 LA[18]/DA[1]

F3 LA[19]/DA[2]

F1 LA[20]/PCS1#

G2 LA[21]/PCS3#

G3 LA[22]/SCS1#

H2 LA[23]/SCS3#

J4 SA[0]

H1 SA[1]

H3 SA[2]

J2 SA[3]

J1 SA[4]

K2 SA[5]

J3 SA[6]

K1 SA[7]

K4 SA[8]/DD[0]

L2 SA[9]/DD[1]

K3 SA[10]/DD[2]

L1 SA[11]/DD[3]

M2 SA[12] / DD[4]

M1 SA[13] / DD[5]

L3 SA[14] / DD[6]

N2 SA[15] / DD[7]

M4 SA[16] / DD[8]

N1 SA[17] / DD[9]

M3 SA[18] / DD[10]

P4 SA[19] / DD[11]

P3 RTCDS# / DD[12]

R2 RTCRW# / DD[13]

N3 KBCS# / DD[14]

P1 RMRTCCS# / DD[15]

R1 SD[0]

T2 SD[1]

R3 SD[2]

T1 SD[3]

R4 SD[4]

U2 SD[5]

T3 SD[6]

U1 SD[7]

U4 SD[8]

V2 SD[9]

U3 SD[10]

Pin # Pin name V1 SD[11]

W2 SD[12]

W1 SD[13]

V3 SD[14]

Y2 SD[15]

Y1 IOCHRDY

AE4 SYSRSTO#

AD4 ISA_CLK

AE5 ISA_CLK2X

AF8 OSC14M

W3 ALE

AC9 ZWS#

AA2 BHE#

Y4 MEMR#

AA1 MEMW#

Y3 SMEMR#

AB2 SMEMW#

AA3 IOR#

AC2 IOW#

AB4 MASTER#

AC1 MCS16#

AB3 IOCS16#

AD2 REF#

AC3 AEN

AD1 IOCHCK#

AF2 ISAOE#

A4 RTCAS

AE3 GPIOCS#

B1 PIRQ

C2 SIRQ

C1 PDRQ

D2 SDRQ

D3 PDACK#

D1 SDACK#

E2 PIOR#

E4 PIOW#

E3 SIOR#

E1 SIOW#

E23 IRQ_MUX[0]

D26 IRQ_MUX[1]

E24 IRQ_MUX[2]

C25 IRQ_MUX[3]

A24 DREQ_MUX[0]

B23 DREQ_MUX[1]

C23 DACK_ENC[0]

Pin # Pin name A23 DACK_ENC[1]

B22 DACK_ENC[2]

D22 TC

C5 SPKRD

AE6 RED

AD6 GREEN

AF6 BLUE

AD5 VSYNC

AC5 HSYNC

AD7 VREF_DAC

AE8 RSET

AF5 COMP

C7 SDA / DDC[0]

B5 SCL / DDC[1]

AC12 VCLK

AE13 VIN[0]

AD14 VIN[1]

AD12 VIN[2]

AE14 VIN[3]

AC14 VIN[4]

AF14 VIN[5]

AD13 VIN[6]

AE15 VIN[7]

AF10 RED_TV

AC10 GREEN_TV

AF11 BLUE_TV

AE10 VCS

AD9 ODD_EVEN

AD11 CVBS

AD8 IREF1_TV

AE9 VREF1_TV

AE11 IREF2_TV

AD10 VREF2_TV

B3 SCAN_ENABLE

AF12 VDDA_TV

AC7 VDD_DAC1

AF4 VDD_DAC2

AD19 VDD_GCLK_PLL

AF13 VDD_DCLK_PLL

F26 VDD_HCLK_PLL

G24 VDD_DEVCLK_PLL

A16 VDD5

B12 VDD5

B9 VDD5

Pin # Pin name

PIN DESCRIPTION

22/71 Issue 2.4 - November 8, 2001

D18 VDD5

A22 VDD

B14 VDD

C9 VDD

D6 VDD

D11 VDD

D16 VDD

D21 VDD

F4 VDD

F23 VDD

G1 VDD

K23 VDD

L4 VDD

L23 VDD

P2 VDD

T4 VDD

T23 VDD

T26 VDD

W4 VDD

AA4 VDD

AA23 VDD

AB1 VDD

AB23 VDD

AC6 VDD

AC11 VDD

AC16 VDD

AC21 VDD

AE12 VSSA_TV

AE7 VSS_DAC1

AF7 VSS_DAC2

E25 VSS_DLL

E26 VSS_DLL

A1:2 VSS

A26 VSS

B2 VSS

B25:26 VSS

C3 VSS

C24 VSS

D4 VSS

D9 VSS

D14 VSS

D19 VSS

D23 VSS

H4 VSS

J23 VSS

L11:16 VSS

M11:16 VSS

N4 VSS

Pin # Pin name N11:16 VSS

P11:16 VSS

P23 VSS

R11:16 VSS

T11:16 VSS

V4 VSS

W23 VSS

AC4 VSS

AC8 VSS

AC13 VSS

AC18 VSS

AC23 VSS

AD3 VSS

AD24 VSS

AE1:2 VSS

AE16 VSS

AE25 VSS

AF1 VSS

AF25 VSS

AF26 VSS

C26 RESERVED

D24 RESERVED

B24 RESERVED

A25 RESERVED

Pin # Pin name

STR AP OPT ION

Issue 2.4 - November 8, 2001 23/71

3. STRAP OPTION

This chapter defines the STPC Consumer Strap Options and their location.

Memory

Data

Lines Note Designation Location Actual

Settings Set to ’0’ Set to ’1’

MD0 1 Index 4A, Bit 0 User defined COLOR_SEL SMEMW#

MD16 Reserved Index 4C,bit 0 Pull up - -

MD17 PCI_CLKO Divisor Index 4C,bit 1 User defined HCLK / 2 HCLK / 3

MD18 Reserved Index 4C,bit 2 Pull up - -

MD19 Reserved Index 4C,bit 3 Pull up - -

MD20 Reserved Index 4C, bit4 Pull up - -

MD21 Reserved Index 5F, bit 0 Pull up - -

MD22 Reserved Index 5F, bit 1 Pull up - -

MD23 Reserved Index 5F,bit 2 Pull up - -

MD24 HCLK PLL Speed Index 5F,bit 3 User defined see 3.1.4

MD25 [26:24] Index 5F,bit 4

MD26 Index 5F,bit 5

MD27 Reserved - Pull down - -

MD28 Reserved - Pull down - -

MD29 Reserved - Pull down - -

MD30 Reserved - Pull down - -

MD31 Reserved - Pull down - -

MD32 Reserved - Pull down - -

MD33 Reserved - Pull up - -

MD34 Reserved - Pull down - -

MD35 Reserved - Pull down - -

MD36 Reserved - Pull up - -

MD37 Reserved - Pull up - -

MD38 Reserved - Pull up - -

MD39 Reserved - Pull up - -

MD40 CPU Mode User defined DX1 DX2

MD41 Reserved - Pull down - -

MD42 Reserved - Pull up - -

MD43 Reserved - Pull down - -

Note 1: This Strap Option selects between two different functional blocks, the first is the ISA (SMEMW#) and the other

is the VGA block (Color_Key).

STRAP OPT ION

24/71 Issue 2.4 - November 8, 2001

3.1. ST RAP REGISTER DESCRIPTION

3.1.1 . STRAP REGIS TER 0

This register reflect the status of pins M D[7:0] respectively. They a re expected to be connected on the

system board to the SIMM configuration pins as follows:

Note that the SIMM speed and t ype inform ation read here is mea nt only for the sof tware and is not us ed

by the hardware. The software must program the Host and graphics DRAM controller configuration regis-

ters appropriately based on these bits.

Strap0

Access = 0022h/0023h Regoffset = 04Ah

76543210

MD[7] MD[6] MD[5] MD[4] MD[3] MD[2] Rsv

This register defaults to the values sampled on MD[7:0] pins after reset

Bit Number Sample d Mnem onic Descript ion

Bits 7-2 MD[7:2] Available for user

Bits 1-0 Rsv Reserved.

STR AP OPT ION

Issue 2.4 - November 8, 2001 25/71

3.1.2 . STRAP REGIS TER 1

This register reflect the status of pins M D[15:8] respectively. They are expec ted to be connec ted on t he

system board to the SIMM configuration pins as follows:

Note that the SIMM speed and t ype inform ation read here is mea nt only for the sof tware and is not us ed

by the hardware. The software mu st program the Host and graphi cs dram controller configuration regis-

ters appropriately based on these bits.

Strap1

Access = 0022h/0023h Regoffset = 04Bh

76543210

MD[15] MD[14] MD[13] MD[12] MD[11] MD[10] MD[9] MD[8]

This register defaults to the values sampled on MD[15:8] pins after reset

Bit Number Sample d Mnem onic Descript ion

Bits 7-0 MD[15:8] Available for user

STRAP OPT ION

26/71 Issue 2.4 - November 8, 2001

3.1.3 . STRAP REGIS TER 2

Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta-

tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect.

Strap2

Access = 0022h/0023h Regoffset = 04Ch

76543210

Rsv MD[17] Rsv

This register defaults to the values sampled on MD[23] and MD[20:16] pins after reset

Bit Number Sample d Mnem onic Descript ion

Bits 7-2 Rsv Reserved

Bit 1

This bit reflects the value sampled on MD[17] pin and controls the PCI

clock output as follows:

Setting to ’0’, the PCI clock output = HCLK / 2,

Setting to ’1’, the PCI clock output = HCLK / 3.

Bit 0 Rsv Reserved.

STR AP OPT ION

Issue 2.4 - November 8, 2001 27/71

3.1 .4. HC LK PLL STRAP REGISTER 0

Bits 5-0 of t his regi ster reflect the s tatu s of pins MD[26: 21] respec tively. They are use by the c hip as fol-

lows:

Programming notes:

Strap Options [39:27] are reserved .

HCLK_STRAP0

Access = 0022h/0023h Regoffset = 05Fh

76543210

Rsv MD[26] MD[25] MD[24] Rsv

This register defaults to the values sampled on pins described below after reset

Bit Number Sample d Mnem onic Descript ion

Bits 7-6 Rsv Reserved

Bits 5-3 MD[26:24]

These pins reflect the value sampled on MD[26:24] pins respectively

and control the Host clock frequency synthesizer.

000: 25 MHz

001: 33 MHz

010: 40 MHz

011: 50 MHz

100: 60 MHz

101: 66 MHz

110: 75 MHz

111: 80 MHz

Bits 2-0 Rsv Reserved.

STRAP OPT ION

28/71 Issue 2.4 - November 8, 2001

3.1.5. 486 CLOCK PROGRAMMING (486_CLK)

The bit MD[40] is used to set the clock multiplication factor of the 486 core. With the MD[40] pin pulled low

the 486 will run in DX (x1) mode, while with the MD[40] pin pulled high the 486 will run in DX2 (x2) mode.

The default value of the resistor on this strap input should be a resister to ground (DX mode).

Strap options MD[43:41] are reserved.

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 29/71

4. ELECTRICAL SPECIFICATIONS

4.1 Int roduction

The electrical specifications in this chapter are val-

id for the STPC Consumer.

4.2 Electrical Connections

4.2.1 Power/Ground Connections/Decoupling

Due to the high frequency of operation of the

STPC Consumer, it is necessary to install and test

this device using standard high frequency tech-

niques. The high clock frequencies used in the

STPC Consumer and its output buffer circuits can

cause transient power surges when several output

buffers switch output levels simultaneously. These

effects c an be m inimized by f i lteri ng the DC power

leads with low-inductance decoupling capacitors,

using low impedance wiring, and by utilizing all of

the VSS and VDD pins.

4.2.2 Unused Input Pins

All inputs not used by the designer and no t listed

in the table of pin connections in Chapter 3 should

be connected either to VDD or to VSS. Connect

active-high inputs to VDD through a 20 kΩ (±10%)

pull-down resistor and active-low inputs to VSS

and connect active-low inputs to VCC through a

20 kΩ (±10 %) pull-up resistor to prevent spurious

operation.

4.2.3 Reserved Designated P ins

Pins designated reserved should be left discon-

nected. Connecting a reserved pin to a pull-up re-

sistor, pull-down resistor, or an active signal could

cause unexpected results and possible circuit

malfunctions.

4.3 Absolute Maximum Ratings

The following table lists the absolute maximum

ratings for the STPC Consumer device. Stresses

beyond those listed under Table 4-1 limits may

cause permanent damage to the device. These

are stress ratings only and do not imply that oper-

ation unde r any c onditions ot her than t hose s pec-

ified in section "Operating Conditions".

Exposure to c ondi tions beyond Ta ble 4-1 may (1)

reduce device reliability and (2) result in prema-

ture failure even when there is no immediately ap-

parent sign of failure. P rolonged exposure to con-

ditions at or near the absolute maximum ratings

(Table 4-1) may also result in reduced useful life

and reliab ilit y .

Table 4-1. Absolute M axim um Ratings

Symbol Parameter Value Units

VDDx DC Supply Voltage -0.3, 4.0 V

VI, VODigital Input and Output Voltage -0.3, VDD + 0.3 V

TSTG Storage Temperature -40, +150 °C

TOPER Operating Temperature 0, +70 °C

PTOT Total Power Dissipation of the package 4.8 W

ELECTRICAL SPECIFICA TIONS

30/71 Issue 2.4 - November 8, 2001

4.4 DC Characteri stics

Table 4-2. DC Characteri stics

Recommen ded Operat ing condi tions : VDD = 3.3V ±0.3V, Tcase = 0 to 100°C unless otherwise specified

Symbol Parameter Test conditions Min Typ Max Unit

VDD Operating Voltage 3.0 3.3 3.6 V

PDD Supply Power VDD = 3.3V, HCLK = 66Mhz 3.2 3.9 W

VREF_DAC DAC Voltage Reference 1.215 1.235 1.255 V

VOL Output Low Voltage ILoad =1.5 to 8mA depending of the pin 0.5 V

VOH Output High Voltage ILoad =-0.5 to -8mA depending of the pin 2.4 V

VIL Input Low Voltage Except XTALI -0.3 0.8 V

XTALI -0.3 0.9 V

VIH Input High Voltage Except XTALI 2.1 VDD+0.3 V

XTALI 2.35 VDD+0.3 V

ILK Input Leakage Current Input, I/O -5 5 µA

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 31/71

4.5 AC Characteri stics

Table 4-4 thro ugh Table 4-9 list the AC charac ter-

istics including output delays, input setup require-

ments, input hold requirements and output float

delays. These measurements are based on the

measuremen t points identified in Figure 4-1 . T he

rising clock edge reference level VREF , and other

reference levels are shown in T able 4-3 below for

the STPC Consumer. Input or output signals must

cross these levels during testing.

Figure 4-1 shows output delay (A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums , de-

fining the s m allest a ccep table sam pling window a

synchronous input signal must be stable for cor-

rect operation.

No te: Re fe r to F igure 4-1.

Table 4-3. Drive Level and Measur ement Points for Switc hing Characteristi cs

Symbol Value Units

VREF 1.5 V

VIHD 3.0 V

VILD 0.0 V

Figure 4-1 Drive Level and Me asure ment Po ints for Switch ing Cha racteristi cs

CLK:

VRef

VILD

VIHD

LEGEND: A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

VRef

Valid

OUTPUTS:

INPUTS:

Output n Output n+1

Input

MAX

MIN

Ref

VILD

VIHD

ELECTRICAL SPECIFICA TIONS

32/71 Issue 2.4 - November 8, 2001

Figure 4-2 CLK Timing Measurement Points

Note; The above timin

s are

eneric timin

s and are not specific to the interfaces defined below

CLK

T5 T4T3

VRef

VIL (MAX)

VIH (MIN)

LEGEND: T1 - One Clock Cycle

T2 - Minimum Time at VIH

T3 - Minimum Time at VIL

T4 - Clock Fall Time

T5 - Clock Rise Time

NOTE; All sIgnals are sampled on the rising edge of the CLK.

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 33/71

4.5.1 Powe r on sequen ce

Figure 4-3 describes the power-on sequence of

the STPC, also called cold reset.

There is no constraint on the rising edge of

SYSRSTI#. It just needs to stay low at least 10µs

after power supply is stable to let the STPC PLLs

stabilize.

Strap Options are continuously sampled during

SYSRSTI# low and must remain stable. Once

SYSRSTI# is high, they MUST NOT CHANGE

until SYSRSTO# goes high.

Bus activity starts only few clock cycles after the

release of SYSRSTO#. The toggling signals de-

pend on the STPC configuration.

In ISA m ode, activity is visibl e on PCI prior to the

ISA bus as the controller is part of the south bridge

(CPC).

In Local Bus mode, the PCI bus is not accessed

and the Flash Chip Select is the control signal to

mon itor.

ELECTRICAL SPECIFICA TIONS

34/71 Issue 2.4 - November 8, 2001

Figure 4-3. Power-on timing diagram

S trap O ption s

Power Supplie s

SYSRSTI#

SYSRSTO#

14 M H z

1.6 V

VALID CONFIG URATION

> 1 0 us

HCLK

PCI_CLK

2.3 m s

ISACLK

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 35/71

4.5.2 RESET sequence

Figure 4-4 describes the reset sequence of the

STPC, also call e d warm reset.

The constraints on the strap options and the bus

activities are the same as for the cold reset.

It is mandatory to have a clean reset pulse without

glitches as the STPC could then sample invalid

strap option setting and enter into an umpredi cta-

ble mode.

While SYSRSTI# is active, t h e PCI clock PLL runs

in open loop mode at a speed of few 100’s KHz.

ure 4-4. Reset timin

dia

ram

S trap O ptio ns

SYSRSTI#

SYSRSTO#

14 MHz

VALID CONFIG URATIO N

HCLK

PCI_CLK

2.3 m s

ISACLK

1.6 V

MD[63:0]

ELECTRICAL SPECIFICA TIONS

36/71 Issue 2.4 - November 8, 2001

4.5.3 DRAM CONTROLLER AC TIMING CHARCTERISTICS

Figu re 4- 5 Read Mode ( ref t abl e Table 4-4)

ROW Column

tRCH

tCPN tRCS tCAH

tCOH tCPN

tCRP

tRP

tRC

tRAS

tRAL tRP

tRAS

tRAH

tRAD

tCHR

tRCD

tRC

tCRD

tCCAS

tCRAS

tCMA

CLK

RAS#

CAS#

MWE#

Figure 4-6 Memo ry Ear ly Write Mode (ref table Table 4-4)

ROW Column

Data Valid

tCPNtCPN

tCWL

tRCH

tCHR

tWRH

tCPN

tDS

tWCH

tWCS

tRCS

tCAH

tCPN

tRP

tRC

tCRW

tRWL

tRAS

tRAL

tRP

tDHR

tWCR

tRAD

tRAS

tRAH

tCHR

tRCD

tRC

tCRP

tCCAS

tCRAS

tCMA

CLK

RAS#

CAS#

MWE#

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 37/71

Figure 4-7 EDO Read Mode (ref table T able 4-4)

Figure 4-8 EDO Write Mode (ref table Table 4-4)

Row Column Row

OPEN Valid data OPEN

tCPNtCPN

tCPN tCOH

tRCS tCAH

tCPN

tRCHtRAL

tRAS

tRC

tRAH

tRAD

tAR

tRCD

tCRP

tCSR

tCHR

tRAS

tRPtRP

tRC

tCMD

tCMWE

tCCAS

tCRAS

tCMA

CLK

RAS#

CAS#

MWE#

Row Column Row

OPEN Valid data OPEN

tCPNtCPN

tCPN tCOH

tRCS tCAH

tCPN

tRCHtRAL

tRAS

tRC

tRAH

tRAD

tAR

tRCD

tCRP

tCSR

tCHR

tRAS

tRPtRP

tRC

tCMD

tCMWE

tCCAS

tCRAS

tCMA

CLK

RAS#

CAS#

MWE#

ELECTRICAL SPECIFICA TIONS

38/71 Issue 2.4 - November 8, 2001

Figure 4-9 Fast Page Mode Read (ref table Table 4-4)

Figure 4-10 Fast Page Mode Wr ite (ref table Table 4-4)

Column 1 Column 2 Column N

Dout 1 Dout 2 Dout N

tCPN tCOH

tCAH

tCPN

tCPN tCOH

tCAHtCPNtCPN tCOH

tCAH

tCPN

tCRP

tRPtRAL tRP

tAR

tRAH

tCSH

tRAD

tRCD

tCRP

tCMD tCRAS

tCMD

tCMA tCCAStCMD

tCMA

tCCAStCMA

tCCAS

tCRAS

CLK

RAS#

CAS#

MWE#

ROW Column 1 Column 2 Column N

Dout 1 Dout 2 Dout N

tRAL

tRCH

tCPN

tDS

tCAH

tCPN

tCPN tDS

tRC

tCAHtCPNtCWL

tCPN

tDS

tWCS

tRC

tCAHtCPN

tCRP

tRPtCRW

tRWL

tRAS

tRAL

tRP

tDHR

tWCR

tAR tRAS

tRAH

tCSH

tRAD

tRCD

tCRP

tCMD

tCCAStCMA

tCRAS

CLK

RAS#

CAS#

MWE#

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 39/71

Figure 4-11 Refresh Cycle (ref table Table 4-4)

tCPNtCPNtCPNtCPN

tCSR

tRP

tRPC

tRAS tRP

tCHRtCRS

tCSR tRAS

tRP

tRPC

tRP

tCRAS

tCCAS

CLK

MA[11:0]

RAS#[3:0]

CAS#[7:0]

ELECTRICAL SPECIFICA TIONS

40/71 Issue 2.4 - November 8, 2001

Table 4-4. AC Memory Timing Characteristics

Parameter Min Max Units

tCRAS H CLK (or GCLK2 X) to RAS#[3:0] valid (see Note 3) 17 ns

tCCAS HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3) 17 ns

tCMA HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3) 17 ns

tCMWE HCLK (or GCLK2X) to MWE# valid (see Note 3) 17 ns

tCMD HCLK to MD[63:0] bus valid (see Note 3) 25 ns

tGCMD GCLK2X to MD[63:0] bus valid (see Note 3) 23 ns

tMDG MD[63:0] Generic hold 0 ns

tCAH Column Address Hold Time ≥1TCycles ns

tCHR CAS Hold Time ≥1TCycles ns

tCOH Data Hold TIme from CAS Low Note 1 ns

tCPN CAS Precharge Time 1TCycles ns

tCRP CAS to RAS Precharge Time ≤1TCycles

tCRW CAS Low to RAS HIGH (Write only) ≥1TCycles ns

tCSR CAS Setup Time ≥1TCycles ns

tDS Data In Setup Time ≥1TCycles ns

tRAH Row Address Hold Time ≥1TCycles ns

tRAS RAS Pulse Width ≥3TCycles ns

tRC Random Read or Write Time Cycle ≥6TCycles ns

tRCD RAS to CAS Delay Time ≥1TCycles ns

tRCH Read Command Hold Time ≥1TCycles ns

tRCS Read Command Setup Time ≥1TCycles ns

tRP RAS Precharge Time ≥2TCycles ns

tWCH Write Command Hold Time ≥1TCycles ns

tWCS WE Command Setup Time ≥1TCycles ns

tWRH WE Hold Time Note 2 ns

tWRP WE Setup Time ≥1TCycles ns

tAR Column Address Hold Time from RAS ≥1TCycles ns

tRAD RAS to valid Column Address Delay ≥1TCycles ns

tRAL Column Address to RAS Setup Time ≥2TCycles ns

tWCR Write Command Hold Reference to RAS ≥1TCycles ns

tRWL Write Command to RAS Setup Time (Note 2) ≥1TCycles ns

tCWL Write Command to CAS Setup Time (Note 2) ≥1TCycles ns

tDHR Data Hold Reference to RAS ≥3TCycles ns

tRPC RAS High to CAS Low Precharge ≥1TCycles ns

tCRS CAS Before RAS Setup Time ≥1TCycles ns

tCHR CAS Before RAS Hold Time ≥1TCycles ns

tCSH CAS Hold Time after RAS ≥1TCycles ns

Note 1; TCycle x nCAS + (tData off - tCAS out)

Where TCycle is the the number of clock cycles.

nCAS is the number of CAS Cycles (see section 6.7. )

TDataoff is the Generic Datahold

tCAS Out the CLK (either HCLK or GCLK2X) to CAS Low.

TDataoff and tCAS Out are used to refine the timing programming.

Note 2; Value to be derived from CAS pulse width which is programmable (see section 6.7. ).

Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 41/71

4.5.4 PCI interface

Table 4-5 lists the AC characteristics of the PCI in-

terface.

Table 4-5. PCI Bus AC Timing

Name Parameter Min Max Unit

t1 PCI_CLKI to AD[31:0] valid 2 11 ns

t2 PCI_CLKI to FRAME# valid 2 11 ns

t3 PCI_CLKI to CBE#[3:0] valid 2 11 ns

t4 PCI_CLKI to PAR valid 2 11 ns

t5 PCI_CLKI to TRDY# valid 2 11 ns

T6 PCI_CLKI to IRDY# valid 2 11 ns

T7 PCI_CLKI to STOP# valid 2 11 ns

T8 PCI_CLKI to DEVSEL# valid 2 11 ns

T9 PCI_CLKI to PCI_GNT# valid 2 12 ns

t10 AD[31:0] bus setup to PCI_CLKI 5 ns

t11 AD[31:0] bus hold from PCI_CLKI 0 ns

t12 PCI_REQ#[2:0] setup to PCI_CLKI 4 ns

t13 PCI_REQ#[2:0] hold from PCI_CLKI 4 ns

t14 CBE#[3:0] setup to PCI_CLKI 5 ns

t15 CBE#[3:0] hold to PCI_CLKI 0 ns

t16 IRDY# setup to PCI_CLKI 5 ns

t17 IRDY# hold to PCI_CLKI 0 ns

t18 FRAME# setup to PCI_CLKI 5 ns

t19 FRAME# hold from PCI_CLKI 0 ns

ELECTRICAL SPECIFICA TIONS

42/71 Issue 2.4 - November 8, 2001

4.5.5 Isa interface AC Timing characteristics

Table 4-12 and Table 4-6 list the AC characteris-

tics of the ISA interfac e.

Figure 4-12 ISA Cycle (ref Table 4-6)

Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.

The clock has not been represented as it is dependent on the ISA Slave mode.

Valid AENx

Valid Address

Valid Address, SBHE*

V.Dat

VALID DATA

57 27

56 29

918

ALE

AEN

LA [23:17]

SA [19:0]

CONTROL (Note 1)

IOCS16#

MCS16#

IOCHRDY

READ DATA

WRITE DATA

Table 4-6. ISA Bus AC Timing

Name Parameter Min Max Units

2 LA[23:17] valid before ALE# negated 5T Cycles

3 LA[23:17] valid before MEMR#, MEMW# asserted

3a Memory access to 16-bit ISA Slave 5T Cycles

3b Memory access to 8-bit ISA Slave 5T Cycles

9 SA[19:0] & SBHE valid before ALE# negated 1T Cycles

10 SA[19:0] & SBHE valid before MEMR#, MEMW# asserted

10a Memory access to 16-bit ISA Slave 2T Cycles

10b Memory access to 8-bit ISA Slave 2T Cycles

10 SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted

Note: The si

nal numberin

refers to Table 4-12

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 43/71

10c Memory access to 16-bit ISA Slave 2T Cycle

10d Memory access to 8-bit ISA Slave 2T Cycle

10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 2T Cycles

11 ISACLK2X to IOW# valid

11a Memory access to 16-bit ISA Slave - 2BCLK 2T Cycles

11b Memory access to 16-bit ISA Slave - Standard 3BCLK 2T Cycles

11c Memory access to 16-bit ISA Slave - 4BCLK 2T Cycles

11d Memory access to 8-bit ISA Slave - 2BCLK 2T Cycles

11e Memory access to 8-bit ISA Slave - Standard 3BCLK 2T Cycles

12 ALE# asserted before ALE# negated 1T Cycles

13 ALE# asserted before MEMR#, MEMW# asserted

13a Memory Access to 16-bit ISA Slave 2T Cycles

13b Memory Access to 8-bit ISA Slave 2T Cycles

13 ALE# asserted before SMEMR#, SMEMW# asserted

13c Memory Access to 16-bit ISA Slave 2T Cycles

13d Memory Access to 8-bit ISA Slave 2T Cycles

13e ALE# asserted before IOR#, IOW# asserted 2T Cycles

14 ALE# asserted before AL[23:17]

14a Non compressed 15T Cycles

14b Compressed 15T Cycles

15 ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated

15a Memory Access to 16-bit ISA Slave- 4 BCLK 11T Cycles

15e Memory Access to 8-bit ISA Slave- Standard Cycle 11T Cycles

18a ALE# negated before LA[23:17] invalid (non compressed) 14T Cycles

18a ALE# negated before LA[23:17] invalid (compressed) 14T Cycles

22 MEMR#, MEMW# asserted before LA[23:17]

22a Memory access to 16-bit ISA Slave. 13T Cycles

22b Memory access to 8-bit ISA Slave. 13T Cycles

23 MEMR#, MEMW# asserted before MEMR#, MEMW# negated

23b Memory access to 16-bit ISA Slave Standard cycle 9T Cycles

23e Memory access to 8-bit ISA Slave Standard cycle 9T Cycles

23 SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated

23h Memory access to 16-bit ISA Slave Standard cycle 9T Cycles

23l Memory access to 16-bit ISA Slave Standard cycle 9T Cycles

23 IOR#, IOW# asserted before IOR#, IOW# negated

23o Memory access to 16-bit ISA Slave Standard cycle 9T Cycles

23r Memory access to 8-bit ISA Slave Standard cycle 9T Cycles

24 MEMR#, MEMW# asserted before SA[19:0]

24b Memory access to 16-bit ISA Slave Standard cycle 10T Cycles

24d Memory access to 8-bit ISA Slave - 3BLCK 10T Cycles

24e Memory access to 8-bit ISA Slave Standard cycle 10T Cycles

24f Memory access to 8-bit ISA Slave - 7BCLK 10T Cycles

24 SMEMR#, SMEMW# asserted before SA[19:0]

24h Memory access to 16-bit ISA Slave Standard cycle 10T Cycles

24i Memory access to 16-bit ISA Slave - 4BCLK 10T Cycles

24k Memory access to 8-bit ISA Slave - 3BCLK 10T Cycles

Table 4-6. ISA Bus AC Timing

Name Parameter Min Max Units

Note: The si

nal numberin

refers to Table 4-12

ELECTRICAL SPECIFICA TIONS

44/71 Issue 2.4 - November 8, 2001

24l Memory access to 8-bit ISA Slave Standard cycle 10T Cycles

24 IOR#, IOW# asserted before SA[19:0]

24o I/O access to 16-bit ISA Slave Standard cycle 19T Cycles

24r I/O access to 16-bit ISA Slave Standard cycle 19T Cycles

25 MEMR#, MEMW# asserted before next ALE# asserted

25b Memory access to 16-bit ISA Slave Standard cycle 10T Cycles

25d Memory access to 8-bit ISA Slave Standard cycle 10T Cycles

25 SMEMR#, SMEMW# asserted before next ALE# asserted

25e Memory access to 16-bit ISA Slave - 2BCLK 10T Cycles

25f Memory access to 16-bit ISA Slave Standard cycle 10T Cycles

25h Memory access to 8-bit ISA Slave Standard cycle 10T Cycles

25 IOR#, IOW# asserted before next ALE# asserted

25i I/O access to 16-bit ISA Slave Standard cycle 10T Cycles

25k I/O access to 16-bit ISA Slave Standard cycle 10T Cycles

26 MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted

26b Memory access to 16-bit ISA Slave Standard cycle 12T Cycles

26d Memory access to 8-bit ISA Slave Standard cycle 12T Cycles

26 SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted

26f Memory access to 16-bit ISA Slave Standard cycle 12T Cycles

26h Memory access to 8-bit ISA Slave Standard cycle 12T Cycles

26 IOR#, IOW# asserted before next IOR#, IOW# asserted

26i I/O access to 16-bit ISA Slave Standard cycle 12T Cycles

26k I/O access to 8-bit ISA Slave Standard cycle 12T Cycles

28 Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted

28a Memory access to 16-bit ISA Slave 3T Cycles

28b Memory access to 8-bit ISA Slave 3T Cycles

28 Any command negated to IOR#, IOW# asserted

28c I/O access to ISA Slave 3T Cycles

29a MEMR# , MEMW# nega ted before next ALE# asserted 1T Cycles

29b SMEMR#, SMEMW# negated before next ALE# asserted 1T Cycles

29c IOR#, IOW# negated before next ALE# asserted 1T Cycles

33 LA[23:17] valid to IOCHRDY negated

33a Memory access to 16-bit ISA Slave - 4 BCLK 8T Cycles

33b Memory access to 8-bit ISA Slave - 7 BCLK 14T Cycles

34 LA[23:17] valid to read data valid

34b Memory access to 16-bit ISA Slave Standard cycle 8T Cycles

34e Memory access to 8-bit ISA Slave Standard cycle 14T Cycles

37 ALE# asserted to IOCHRDY# negated

37a Memory access to 16-bit ISA Slave - 4 BCLK 6T Cycles

37b Memory access to 8-bit ISA Slave - 7 BCLK 12T Cycles

37c I/O access to 16-bit ISA Slave - 4 BCLK 6T Cycles

37d I/O access to 8-bit ISA Slave - 7 BCLK 12T Cycles

38 ALE# asserted to read data valid

38b Memory access to 16-bit ISA Slave Standard Cycle 4T Cycles

38e Memory access to 8-bit ISA Slave Standard Cycle 10T Cycles

38h I/O access to 16-bit ISA Slave Standard Cycle 4T Cycles

Table 4-6. ISA Bus AC Timing

Name Parameter Min Max Units

Note: The si

nal numberin

refers to Table 4-12

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 45/71

38l I/O access to 8-bit ISA Slave Standard Cycle 10T Cycles

41 SA[19:0] SBHE valid to IOCHRDY negated

41a Memory access to 16-bit ISA Slave 6T Cycles

41b Memory access to 8-bit ISA Slave 12T Cycles

41c I/O access to 16-bit ISA Slave 6T Cycles

41d I/O access to 8-bit ISA Slave 12T Cycles

42 SA[19:0] SBHE valid to read data valid

42b Memory access to 16-bit ISA Slave Standard cycle 4T Cycles

42e Memory access to 8-bit ISA Slave Standard cycle 10T Cycles

42h I/O access to 16-bit ISA Slave Standard cycle 4T Cycles

42l I/O access to 8-bit ISA Slave Standard cycle 10T Cycles

47 MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated

47a Memory access to 16-bit ISA Slave 2T Cycles

47b Memory access to 8-bit ISA Slave 5T Cycles

47c I/O access to 16-bit ISA Slave 2T Cycles

47d I/O access to 8-bit ISA Slave 5T Cycles

48 MEMR#, SMEMR#, IOR# asserted to read data valid

48b Memory access to 16-bit ISA Slave Standard Cycle 2T Cycles

48e Memory access to 8-bit ISA Slave Standard Cycle 5T Cycles

48h I/O access to 16-bit ISA Slave Standard Cycle 2T Cycles

48l I/O access to 8-bit ISA Slave Standard Cycle 5T Cycles

54 IOCHRDY asserted to read data valid

54a Memory access to 16-bit ISA Slave 1T(R)/2T(W) Cycles

54b Memory access to 8-bit ISA Slave 1T(R)/2T(W) Cycles

54c I/O access to 16-bit ISA Slave 1T(R)/2T(W) Cycles

54d I/O access to 8-bit ISA Slave 1T(R)/2T(W) Cycles

55a IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,

SMEMW#, IOR#, IOW# negated 1T Cycles

55b IOCHRY asserted to MEMR#, SMEMR# negated (refresh) 1T Cycles

56 IOCHRDY asserted to next ALE# asserted 2T Cycles

57 IOCHRDY asserted to SA[19:0], SBHE invalid 2T Cycles

58 MEMR#, IOR#, SMEMR# negated to read data invalid 0T Cycles

59 MEMR#, IOR#, SMEMR# negated to data bus float 0T Cycles

61 Write data before MEMW# asserted

61a Memory access to 16-bit ISA Slave 2T Cycles

61b Memory access to 8-bit ISA Slave (Byte copy at end of

start) 2T Cycles

61 Write data before SMEMW# asserted

61c Memory access to 16-bit ISA Slave 2T Cycles

61d Memory access to 8-bit ISA Slave 2T Cycles

61 Write Data valid before IOW# asserted

61e I/O access to 16-bit ISA Slave 2T Cycles

61f I/O access to 8-bit ISA Slave 2T Cycles

64a MEMW# negated to write data invalid - 16-bit 1T Cycles

64b MEMW# negated to write data invalid - 8-bit 1T Cycles

64c SMEMW# negated to write data invalid - 16-bit 1T Cycles

Table 4-6. ISA Bus AC Timing

Name Parameter Min Max Units

Note: The si

nal numberin

refers to Table 4-12

ELECTRICAL SPECIFICA TIONS

46/71 Issue 2.4 - November 8, 2001

4.5.6 IDE INTERFACE

Table 4-7 lists the AC characteristics of the IDE

interface.

4.5.7 VGA INTERFACE

Table 4-8 lists the AC characteristics of the VGA

interface.

4.5.8 VIDEO INPUT PORT

Table 4-9 lists the AC characteristics of the VIP

interface.

64d SMEMW# negated to write data invalid - 8-bit 1T Cycles

64e IO W# negat ed to write data invalid 1T Cycles

64f MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte

by ISA Master 1T Cycles

64g IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by

ISA Master 1T Cycles

Table 4-6. ISA Bus AC Timing

Name Parameter Min Max Units

Note: The si

nal numberin

refers to Table 4-12

Table 4-7. IDE Bus AC Timing

Name Parameter Min Max Unit

DD[15:0] setup to PIOR#/SIOR# falling 15 ns

DD[15:0} hold to PIOR#/SIOR# falling 0 ns

Table 4-8. Grap hics Adap ter (VGA) AC Timing

Name Parameter Min Max Unit

DCLK to VSYNC valid 30 ns

DCLK to HSYNC valid 30 ns

Table 4-9. Video Input AC Timing

Name Parameter Min Max Unit

VIN[7:0] setup to VCLK 5 ns

VIN[7:0] hold from VCLK 4 ns

VCLK to ODD_EVEN valid 15 ns

VCLK to VCS valid 15 ns

ODD_EVEN setup to VCLK 10 ns

ODD_EVEN hold from VCLK 5 ns

VCS setup to VCLK 10 ns

VCS hold from VCLK 5 ns

ELEC TR ICAL SPECIFIC ATIONS

Issue 2.4 - November 8, 2001 47/71

ELECTRICAL SPECIFICA TIONS

48/71 Issue 2.4 - November 8, 2001

MECHANICAL DATA

Issue 2.4 - November 8, 2001 49/71

5. ME CHANIC AL DA TA

5.1. 388-PIN PACKAGE DIMENS ION

The pin numbering for the STPC 388-pin Plastic

BGA package is shown in Figure 5-1.

Dimensions are shown in Figure 5-2, Table 5-1

and Figure 5-3, Table 5-2.

Figure 5-1. 388-Pin PBGA P ackag e - Top View

135791113151719212325

2 4 6 8 10 12 14 16 18 20 22 24 26

135791113151719212325

2468101214161820222426

MECHANICAL DATA

50/71 Issue 2.4 - November 8, 2001

Figure 5-2. 388-pin PBGA Package - PCB Dimensions

Table 5-1. 388-pin PBGA Package - PCB Dimensions

Symbols mm inches

Min Typ Max Min Typ Max

A 34.95 35.00 35.05 1.375 1.378 1.380

B 1.22 1.27 1.32 0.048 0.050 0.052

C 0.58 0.63 0.68 0.023 0.025 0.027

D 1.57 1.62 1.67 0.062 0.064 0.066

E 0.15 0.20 0.25 0.006 0.008 0.001

F 0.05 0.10 0.15 0.002 0.004 0.006

G 0.75 0.80 0.85 0.030 0.032 0.034

Detail

A1 Ball Pad Corner

MECHANICAL DATA

Issue 2.4 - November 8, 2001 51/71

Figure 5-3. 388-pin PBGA Package - Dimensio ns

Table 5-2. 388-pin PBGA Packag e - Dimensions

Symbols mm inches

Min Typ Max Min Typ Max

A 0.50 0.56 0.62 0.020 0.022 0.024

B 1.12 1.17 1.22 0.044 0.046 0.048

C 0.60 0.76 0.92 0.024 0.030 0.036

D 0.52 0.53 0.54 0.020 0.021 0.022

E 0.63 0.78 0.93 0.025 0.031 0.037

F 0.60 0.63 0.66 0.024 0.025 0.026

G 30.0 11.8

Solderball Solderball after collapse

MECHANICAL DATA

52/71 Issue 2.4 - November 8, 2001

5.2. 388-PIN PACKAGE THERMAL DATA

The 388-pin PBGA package has a Power

Dissipation Capability of 4.5W. This increases to

6W when used with a Heatsink.

The structure in shown in Fi

ure 5-4.

Thermal dissipation options are illustrated in

ure 5-5 and Fi

ure 5-6.

Figure 5-4. 388-Pin PBGA stru cture

Thermal balls

Power & Ground layersSignal layers

Figure 5-5. Thermal Dissipation Without Heatsink

Ambient

Board

Case

Junction

Board

Ambient

Case

Junction

Board

Rca

Rjc

Rjb

Rba

1258.5

Rja = 13 °C/W

Airflow = 0

Board dimensions:

The PBGA is centred on board

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

There are no other devices

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board temperature taken at the centrecentre b

MECHANICAL DATA

Issue 2.4 - November 8, 2001 53/71

Figure 5-6. Thermal Dissip ation With Heatsink

Board

Ambient

Case

Junction

Board

Ambient

Case

Junction

Board

Rca

Rjc

Rjb

Rba

508.5

Rja = 9.5 °C/W

Airflow = 0

Board dimensions:

The PBGA is centred on board

Copper thickness:

- 17µm for internal layers

- 34µm for external layers

- 10.2 cm x 12.7 cm

- 4 layers (2 for signals, 1 GND, 1VCC)

There are no other devices

Heat sink is 11.1°C/W

1 via pad per ground ball (8-mil wire)

40% copper on signal layers

Board temperature taken at the centre balls

MECHANICAL DATA

54/71 Issue 2.4 - November 8, 2001

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 55/71

6. DESIGN GUIDELINES

6.1 Typical Applications

The STPC Consumer is well suited for many appli-

cations. Some of the possible implementations are described below.

6.1.1 Web Box

A web bo x is an an al og set to p box pr oviding int er-

net browsing capability to a TV set. It has a TV

output for connecting to the TV set, a modem for

internet connection, a smartcard interface for the

ISP access control, and an infrared interface for

the remote control or the keyboard.

6.2 Architecture reco mm en dation s

This section describes the recommend implemen-

tations for the STPC inte rfaces. Fo r more detail s, download the "References Schematics" from the

STPC web site.

6.2.1 14MHz oscillator stage

The 1 4.31818 MH z oscilla tor stage c an be im ple-

mented using a quartz, which is the preferred and

cheaper solution, or using an external 3.3V oscil-

lator.

The crystal must be used in its series-cut funda-

mental mode and not in overtone mode. It must

have an Equivalent Series Resistance (ESR,

sometimes referred to as Rm) of less than 50

Ohms (typically 8 Ohms) and a shunt capacitance

(Co) of less than 7 pF. The ba lance capa citors of

16 pF must be added, one connected to each pin,

as described in F igure 6-2.

In the e vent of an ex ter nal osc illato r prov iding the

master clock s ig nal to t he ST PC Atl as dev ice, t he

LVTTL s ignal should be connect ed to XTALO, as

described in Figure 6-2.

As this clock is the reference for all the other on-

chip generated clocks, it is strongly recommend-

ed to sh ield this stage , i ncludin g the 2 wires go-

Figure 6-1. Web Box

STPC

TV OUTPUT

CONSUMER

SDRAM 64

FLASH

MODEM

AUDIO

PCI

IDE / PCI

SmartCard

R,G,B, CSYNC

S-VHS

CVBS

VIP

STV2310

SCART 1

SCART 2

microphone

Infrared

Printer port

Local B us

ISA Bus

glue logic

DESIGN GUIDELINES

56/71 Issue 2.4 - November 8, 2001

ing to the STP C balls, in order to reduc e the jitter

to the minimum and reach the optimum system

stability.

Figure 6-2. 14.31818 MHz stage

15pF15pF

XTALIXTALO XTALIXTALO

3.3V

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 57/71

6.2.2 PCI bus

The PCI bus is always active and the following

control signals must be pulled-up to 3.3V or 5V

through 2K2 resistors even if this b us is not con-

nected to an external device: FRAME#, TRDY#,

IRDY#, STOP#, DEVSEL#, LOCK#, SERR#,

PERR#, PCI_REQ#[2:0].

PCI_CLKO must be connected to PCI_CLKI

through a 10 to 33 Ohms resistor. Figure 6-3

shows a typical implement ation.

For more information on layout constraints, go to

the place and route recommendations section.

Figure 6-3. Typical PCI clock routing

PCICLKI

PCICLKO

PCICLKA

PCICLKB

PCICLKC

10 - 22

0 - 22

Device A

Device B

Device C

DESIGN GUIDELINES

58/71 Issue 2.4 - November 8, 2001

6.2.3 IPC

Most of the IPC signals are multiplexed: Interrupt

inputs, DMA Request inputs, DMA Acknowledge

outputs. Figure 6-4 describes a complete imple-

mentation of the IRQ[15:0] time-multiplexing.

When an interrupt line is used internally, the corre-

sponding input can be grounded. In most of the

embedded designs, only few interrupts lines are

necessary and the glue logic can be simplified.

When the interface is integrated into the STPC,

the correspondi ng interrupt line can be grounded

as it is connected internally.

For example, if the integrated IDE controller is ac-

tivated, the IRQ[14] and IRQ[15] inputs can be

grounded.

Figure 6-4. Typical IRQ multiplexing

74x153

1C0

IRQ[0]

IRQ_MUX[0]

1C1

1C2

1C3

2C0

2C1

2C2

2C3

2Y IRQ_MUX[1]

IRQ[1]

IRQ[2]

IRQ[3]

IRQ[4]

IRQ[5]

IRQ[6]

IRQ[7]

74x153

1C0

IRQ_MUX[2]

1C1

1C2

1C3

2C0

2C1

2C2

2C3

2Y IRQ_MUX[3]

IRQ[8]

IRQ[9]

IRQ[10]

IRQ[11]

IRQ[12]

IRQ[13]

IRQ[14]

IRQ[15]

ISA_CLK2X

ISA_CLK

Ti m er 0

Keyboard

Slave P IC

COM2/COM4

COM1/COM3

LPT2

LPT1

RTC

Mouse

FPU

PCI / ID E

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 59/71

Figure 6-5 describes a complete implementation

of the external glue logic for DMA Request time-

multiplexing and DMA Acknowledge demultiplex-

ing. Like for the interrupt lines, this logic can be

simplified when only few DM A channel s are used

in the application.

This glue logic is not needed in Local bus mode as

it does not support DMA transfers.

Figure 6-5. Typical DMA multiplexing and demultiplexing

74x153

1C0

DRQ[0]

DREQ_MUX[0]

1C1

1C2

1C3

2C0

2C1

2C2

2C3

2Y DREQ_MUX[1]

DRQ[1]

DRQ[2]

DRQ[3]

DRQ[4]

DRQ[5]

DRQ[6]

DRQ[7]

74x138

Y0#

G2B

DACK0#

Y1#

Y2#

Y3#

Y4#

Y5#

Y6#

Y7#

G2A

ISA_CLK2X

ISA_CLK

ISA, Refresh

ISA, PIO

ISA, FDC

ISA, PIO

Slave DMAC

ISA

DMA_ENC[0]

DMA_ENC[1]

DMA_ENC[2]

DACK1#

DACK2#

DACK3#

DACK5#

DACK6#

DACK7#

DESIGN GUIDELINES

60/71 Issue 2.4 - November 8, 2001

6.2.4 VGA interface

The STPC integrates a VGA DACs and video buff-

ers. The amount of external devices is then limited

to the min imum as des cribed in the Figure 6-6.

All the resistors and capacitors have to be as

close as possible to the STPC while the circuit

protector DALC112S1 must be close to the VGA

connector.

The DDC[1:0] lines, not represented here, have

also to be protected when they are used on the

VGA connector.

COL_SEL can be used when implementing the

Picture-In-Picture function outside the STPC, for

example when multiplexing an analog video

source. In that case, the CRTC of the STPC has to

be genlocked to this analog source.

DCLK is usually used by the TFT displays which

have RGB inputs in order to synchronise the pic-

ture at the level of the pixel.

When the VGA interface is not needed, the signals

R, G, B, HSYNC, VSYNC, COMP, RSET can be

left unconnected, VSS_DAC[2:1] and VDD_DAC

must then be connected to GND .

6.3 Place and route recommendations

Figure 6-6. T y pical VGA im ple me n t a t io n

536

VDD_DAC

COMP

VREF_DAC

RSET

VSS_DAC1

3.3V

10nF

100nF 47uF

AGND

COL_SEL

DCLK

HSYNC

VSYNC

75 1% DALC112S1

AGND3.3V

VSS_DAC2

1% 100nF

16VLM385BZ

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 61/71

6.3.1 General recommendations

Some STPC Interfaces run at high speed and

need to be carefully routed or even shielded like:

1) Me mory Int erfa c e

2) PCI bus

3) Graphics and video interfaces

4) 14 MHz oscillator stage

All clock signals have to be routed first and shield-

ed for speeds of 27MHz or higher. The high speed

signals follow the same constraints, as for the

memory and PCI control signals.

The next interfaces to be routed are Memory, PCI,

and Video/graphics.

All the analog noise-sensitive signals have to be

routed i n a s ep arate area and henc e ca n b e rout-

ed indepedent ly.

Fig ur e 6-7. Shield in g si gn a ls

ground ring

ground pad

shielded signal line

ground pad shielded signal lines

DESIGN GUIDELINES

62/71 Issue 2.4 - November 8, 2001

6.3.2 Thermal dissipation

6.3.2.1 Power saving

Thermal dissipation of the STPC depends mainly

on supply voltage. When the system does not

need to work at the upper voltage limit, it may

therefore be beneficial to reduce the voltage to the

lower voltage limit, where possible. This could

save a few 100’s of mW.

The second area to look at is unused interfaces

and functions. Depending on the application,

some input signals can be grounded, and some

blocks not powered or shutdown. Clock speed dy-

namic adjustment is also a solution that can be

used along with the integrated power manage-

ment unit.

6.3.2.2 Thermal balls

The standard way to route thermal balls to ground

layer implements only one via pad for each ball

pad, connected using a 8-mil wire.

With such configuration the P lastic BG A package

does 90% of the thermal dissipation through the

ground balls, and especially the central thermal

balls which are directly connected to the die. The

remaining 10% is dissipated through the case.

Adding a heat sink reduces this value to 85%.

As a result, some basic rules must be followed

when routing the STPC in order to avoid thermal

problems.

As the whole ground layer acts as a heat sink, the

ground balls must be dir ectly connected to it, as il-

lustrated in Figure 6-8. If one ground layer is not

enough, a second ground plane may be added.

Figure 6-8. Ground routing

Pad for ground ball

Thru hole to ground layer

Top Layer : Signals

Power layer

Internal layer: signals

Bottom Layer : ground layer

Note: For better visibility, ground balls are not all routed.

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 63/71

When considering thermal d issipation, one o f the

most important parts of the layout is the connec-

tion between the ground balls and t he ground lay-

er.

A 1-wire connection is shown in Figure 6-9. The

use of a 8-mil wire results in a therm al resistance

of 105°C/W assuming copper is used (418 W/

m.°K). This high value is due to the thickness (34

µm) of the copper on the external side of the PCB.

Considering only the central matrix o f 36 thermal

balls and one via for each ball, the global therm al

resistance is 2.9°C/W. This can be easily im-

proved u sing four 12. 5 m il wires t o co nnect to t he

four vias around the ground pad link as in Figure

6-10. This g ives a t otal of 49 vias and a glo bal re-

sistance for the 36 thermal balls of 0.5°C/W.

The use of a ground plane like in Figure 6-11 is

even better.

Figure 6-9. Recomm end ed 1-wire Po wer /Grou nd Pad Layout

Solder Mask (4 mil)

Pad for ground ball (diamete r = 25 mil)

Hole to ground layer (diameter = 12 mil)

Connection Wire (width = 12.5 mil)

Via (diameter = 24 mil)

34.5 mil

1 mil = 0.0254 m m

Figu re 6- 10. Reco m m ende d 4-wi re Gro und P ad La yout

4 via pad s for each ground ball

DESIGN GUIDELINES

64/71 Issue 2.4 - November 8, 2001

To avoid s older wicking over t o the via pads during

soldering, it is important to have a solder mas k of

4 mil around the pad (NSMD pad). This gives a di-

ameter of 33 mil for a 25 mil ground pad.

To obtain the optimum ground layout, place the

vias directly under the ball pads. In this case no lo-

cal board distortion is tolerated.

6.3.2.3 Heat dissipation

The thickness of the cop per on P CB layers is typ-

ically 34 µm for external layers and 17 µm for inter-

nal layers. This means that thermal dissipation is

not good; high board temperatures are concen-

trated around the devices and these fall quickly

with increased distance.

Where possible, place a metal layer inside the

PCB; this improves dramatically the spread of

heat and hence the thermal dissipation of the

board.

The possibility of using the whole system box for

thermal diss ipation is very us eful in cases o f high

internal temperatures and low outside tempera-

tures. Bottom side of the PBGA should be ther-

mally connected to the metal chassis in order to

propagate the heat flow through the metal. Ther-

mally connecting also the top side will improve fur-

thermore the heat dissipation. Figure 6-12 illus-

trates such an implementation.

Figure 6-11. Optimum Layout for Central Ground Ball - top layer

Via to Ground layer

Pad for ground ball

Clearance = 6mil

diame ter = 25 mil

hole diam eter = 14 mil

Sol der mask

diame ter = 33 mil

External diameter = 37 mil

conne ction s = 10 mil

Figure 6-12. Use of Me tal Plate for Thermal Dissipa tio n

Metal planes Thermal conductor

Board

Die

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 65/71

As the PCB acts as a heat sink, the layout of top

and ground layers must be done wit h care to max-

imize the board surface dissipa ting the heat. The

only limitation is the risk of losing routing chan-

nels. Figure 6-13 and Figure 6-14 show a partial

routing with a good thermal dissipation thanks to

an optimized placement of power and signal vias.

The ground plane should be on bottom layer for

the best heat spreading (thicker layer than internal

ones) and dissipation (direct contact with air). .

Figu re 6- 13. Lay out f or Go od Therm a l Di ssip at io n - to p lay e r

Not co nnecte dball

Via

STPC ball GN D ball

DESIGN GUIDELINES

66/71 Issue 2.4 - November 8, 2001

Figure 6-14. Recommend signal wiring (top & ground layers) with corresponding heat flow

STPC balls

External row

I n t ernal row

GND PowerPower

DESIGN GUIDELINES

Issue 2.4 - November 8, 2001 67/71

DESIGN GUIDELINES

68/71 Issue 2.4 - November 8, 2001

ORDERING DATA

Issue 2.4 - November 8, 2001 69/71

7. ORDERING DATA

7.1 Ordering Codes

ST PC C01 66 BT C 3

STMicroelectronics

Prefix

Product Family

PC: PC Compatible

Product ID

C01: Consumer

Core Speed

66: 66MHz

75: 75MHz

80: 80MHz

10: 100MHz

Package

BT: 388 Overmoulded BGA

Temperature Range

C: Commercial

0 to +70°C

Tcase = 0 to +100°C

I: Industrial

-40 to +85°C

Tcase = -40 to +100°C

Operating Voltage

3 : 3.3V ± 0.3V

ORDERING DATA

70/71 Issue 2.4 - November 8, 2001

7.2 Available Part Numbers

Part Number Core Frequency

(MHz) CPU Mode Tcase Range

(V)

STPCC0166BTC3 66 DX 0°C to +100°C 3.3V ± 0.3V

STPCC0180BTC3 80 DX

STPCC0166BTI3 66 DX -40°C to +100°C

STPCC0180BTI3 80 DX

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