A63G7332 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary with Burst Counter and Pipelined Data Output
PRELIMINARY (December, 1998, Version 2.1) AMIC Technology, Inc.
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No. History Issue Date Remark
1.0 Initial issue November, 1997 Preliminary
1.1 Change pin 14 description from VCC to NC June 17, 1998
Change package type from 100-pin TQFP to 100-pin LQFP
2.0 Change fast access times from 4.5/5/5.5 ns to 4.2/4.5/5.0 ns August 27, 1998
2.1 Modify 100-pin LQFP symbol y dimensions - December 31, 1998
Max. in mm : 0.08 → 0.1
Max. in inches : 0.003 → 0.004
A63G7332 Series
128K X 32 Bit Synchronous High Speed SRAM
Preliminary with Burst Counter and Pipelined Data Output
PRELIMINARY (December, 1998, Version 2.1)1AMIC Technology, Inc.
Features
nFast access times: 4.2/4.5/5.0 ns (143/133/100 MHZ)
nSingle +3.3V+10% or +3.3V-5% power supply
nSeparate +2.5V+0.4V/-0.12V isolated output buffer
n3.3V tolerant inputs
nSynchronous burst function
nIndividual Byte Write control and Global Write
nRegistered output for pipelined applications
nThree separate chip enables allow wide range of
options for CE control, address pipelining
nSelectable BURST mode
nSLEEP mode (ZZ pin) provided
nAvailable in 100-pin LQFP package
General Description
The A63G7332 is a high-speed, low-power SRAM
containing 4,194,304 bits of bit synchronous memory,
organized as 131,072 words by 32 bits.
The A63G7332 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 128K X 32 SRAM core to provide
a wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A16), all data inputs (I/O1 - I/O32), active LOW chip
enable (CE ), two additional chip enables (CE2, CE2 ),
burst control inputs (ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1, BW2 , BW3 , BW4 ) and Global
Write (GW ). Asynchronous inputs include output enable
(OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
(ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63G7332
and controlled by the burst advance (ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1
controls I/O1 - I/O8, BW2 controls I/O9 - I/O16, BW3
controls I/O17 - I/O24, and BW4 controls I/O25 - I/O32, all
on the condition that BWE is LOW. GW LOW causes
all bytes to be written.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 2AMIC Technology, Inc.
Pin Configuration
NC
I/O
17
I/O
18
VCCQ
GNDQ
I/O
19
I/O
20
I/O
21
I/O
22
GNDQ
I/O
23
I/O
24
VCCQ
VCC
NC
I/O
31
GND
I/O
25
I/O
26
VCCQ
GNDQ
I/O
27
I/O
28
I/O
29
I/O
30
GNDQ
VCCQ
I/O
32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
30
27
29
80
79
78
77
76
75
74
72
73
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
16
I/O
15
VCCQ
GNDQ
I/O
14
I/O
13
I/O
12
I/O
11
GNDQ
VCCQ
I/O
10
I/O
9
GND
NC
VCC
ZZ
I/O
8
I/O
7
VCCQ
GNDQ
I/O
6
I/O
5
I/O
4
I/O
3
GNDQ
VCCQ
I/O
2
I/O
1
NC
50
49
48
47
46
45
44
43
42
40
41
39
38
37
36
35
34
33
32
31
A16
A15
A14
A13
A12
A11
A10
NC
NC
VCC
GND
NC
NC
A0
A1
A2
A3
A4
A5
MODE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CE2
A7
A6
CLK
GND
VCC
A9
A8
A63G7332
NC
ADV
ADSP
ADSC
OE
BWE
GW
CE2
BW1
BW2
BW3
BW4
CE
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 3AMIC Technology, Inc.
Block Diagram
MODE
LOGIC
CLK
LOGIC
ADDRESS
REGISTERS
BURST
LOGIC
ADDRESS
COUNTER
CLR
BYTE
WRITE
ENABLE
LOGIC
BYTE1
WRITE
DRIVER
BYTE2
WRITE
DRIVER
BYTE3
WRITE
DRIVER
BYTE4
WRITE
DRIVER
8
8
8
8
128KX8X4
MEMORY
ARRAY
8
8
8
8
32
OUTPUT
REGISTERS
DATA-IN
REGISTERS
4
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC OUTPUT
ENABLE
LOGIC
4
32
17
ZZ
MODE
ADV
CLK
ADSC
ADSP
A0-A16
GW
BWE
BW1
BW2
BW3
BW4
CE
CE2
CE2
OE
I/O
1
- I/O
32
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 4AMIC Technology, Inc.
Pin Description
Pin No. Symbol Description
32 - 37, 44 - 50, 81,
82, 99, 100 A0 - A16 Address Inputs
89 CLK Clock
87, 93 - 96 BWE , BW1 - BW4 Byte Write Enables
88 GW Global Write
86 OE Output Enable
92, 97, 98 CE2 ,CE2, CE Chip Enables
83 ADV Burst Address Advance
84 ADSP Processor Address Status
85 ADSC Controller Address Status
31 MODE Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
64 ZZ Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
2, 3, 6 - 9, 12, 13,
18, 19, 22 - 25, 28,
29, 52, 53, 56 - 59,
62, 63, 68, 69,
72 - 75, 78, 79
I/O1- I/O32 Data Inputs/Outputs
1,14,16, 30, 38, 39,
42, 43, 51, 66, 80 NC No Connection
14, 15, 41, 65, 91 VCC Power Supply
17, 40, 67, 90 GND Ground
4, 11, 20, 27,
54, 61, 70, 77 VCCQ Isolated Output Buffer Supply
5, 10, 21, 26,
55, 60, 71, 76 GNDQ Isolated Output Buffer Ground
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 5AMIC Technology, Inc.
Synchronous Truth Table (See Notes 1 Through 5)
Operation Address
Used
CE
CE2
CE2
ADSP
ADSCADV
WRITE
OE
CLK I/O
Operation
Deselected Cycle,
Power-down NONE HX X X LX X X L-H High-Z
Deselected Cycle,
Power-down NONE LXL L X X X X L-H High-Z
Deselected Cycle,
Power-down NONE LHXLX X X X L-H High-Z
Deselected Cycle,
Power-down NONE LXLHLX X X L-H High-Z
Deselected Cycle,
Power-down NONE LHXHLX X X L-H High-Z
READ Cycle,
Begin Burst External L L HLX X X LL-H Dout
READ Cycle,
Begin Burst External L L HLX X X HL-H High-Z
WRITE Cycle,
Begin Burst External L L H H LXLXL-H Din
READ Cycle,
Begin Burst External L L H H LXHLL-H Dout
READ Cycle,
Begin Burst External L L H H LXH H L-H High-Z
READ Cycle,
Continue Burst Next XXX H H LHLL-H Dout
READ Cycle,
Continue Burst Next XXX H H LH H L-H High-Z
READ Cycle,
Continue Burst Next HX X X HLHLL-H Dout
READ Cycle,
Continue Burst Next HX X X HLH H L-H High-Z
WRITE Cycle,
Continue Burst Next XXX H H L L XL-H Din
WRITE Cycle,
Continue Burst Next HX X X HL L XL-H Din
READ Cycle,
Suspend Burst Current XXX H H H H LL-H Dout
READ Cycle,
Suspend Burst Current XXX H H H H H L-H High-Z
READ Cycle,
Suspend Burst Current HX X X H H H LL-H Dout
READ Cycle,
Suspend Burst Current HX X X H H H H L-H High-Z
WRITE Cycle,
Suspend Burst Current XXX H H H LXL-H Din
WRITE Cycle,
Suspend Burst Current HX X X H H LXL-H Din
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 6AMIC Technology, Inc.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx (BW1,BW2 ,BW3 , or BW4 ) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ H H X X X X
READ HLH H H H
WRITE Byte 1 HL L H H H
WRITE all bytes HLLLLL
WRITE all bytes LXXXXX
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 7AMIC Technology, Inc.
Linear Burst Address Table (MODE = LOW)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VCC (Vin,
Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W
Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C
Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Recommended DC Operating Conditions
(0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%, VCCQ = +2.5V+0.4V/-0.125V, unless otherwise noted)
Symbol Parameter Min. Typ. Max. Unit Note
VCC Supply Voltage (Operating Voltage Range) 3.1 3.3 3.6 V
VCCQ Isolated Input Buffer Supply 2.375 2.5 2.9 V
GND Supply Voltage to GND 0.0 -0.0 V
VIH Input High Voltage 1.7 -VCC+0.3 V1, 2
VIHQ Input High Voltage 1.7 -VCC+0.3 V
VIL Input Low Voltage -0.3 -0.7 V1, 2
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 8AMIC Technology, Inc.
DC Electrical Characteristics
(0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%, VCCQ = +2.5V+0.4V/-0.125V, unless otherwise noted)
Symbol Parameter Min. Max. Unit Test Conditions Note
ILIInput Leakage Current -±2.0 µAAll inputs VIN = GND to VCC
ILOOutput Leakage Current -±2.0 µAOE = VIH, Vout = GND to VCC
ICC1 Supply Current -300 mA Device selected; VCC = max.
Iout = 0mA, all inputs = VIH or VIL
Cycle time = tKC min. 3, 11
ISB1 Standby Current -25 mA
Device deselected; VCC = max.
All inputs are fixed.
All inputs ≥ VCC - 0.2V
or ≤ GND + 0.2V
Cycle time = tKC min.
11
ISB2 -10 mA ZZ ≥ VCC - 0.2V
VOL Output Low Voltage -0.7 VIOL = 2.0 mA
-0.4 VIOL = 1.0 mA
VOH Output High Voltage 1.7 -VIOH = -2.0 mA
2.0 -VIOH = -1.0 mA
Capacitance
Symbol Parameter Typ. Max. Unit Conditions
CIN Input Capacitance 3 4 pF TA = 25 C; f = 1MHz
CI/O Input/Output Capacitance 4 5 pF VCC = 3.3V
* These parameters are sampled and not 100% tested.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 9AMIC Technology, Inc.
AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%)
Symbol Parameter -4.2 -4.5 -5.0 Unit Note
Min. Max. Min. Max. Min. Max.
tKC Clock Cycle Time 7-7.5 -10 -ns
tKH Clock High Time 1.9 -1.9 -3.2 -ns
tKL Clock Low Time 1.9 -1.9 -3.2 -ns
tKQ Clock to Output Valid -4.2 -4.5 -5.0 ns
tKQX Clock to Output Invalid 1.5 -1.5 -1.5 -ns
tKQLZ Clock to Output in Low-Z 1.5 -1.5 -1.5 -ns 5, 6
tKQHZ Clock to Output in High-Z 1.5 4.2 1.5 4.5 1.5 5.0 ns 5, 6
tOEQ OE to Output Valid -4.2 -4.5 -5.0 ns 8
tOELZ OE to Output in Low-Z 0-0-0-ns 5, 6
tOEHZ OE to Output in High-Z -4.2 -4.5 -5.0 ns 5, 6
Setup Times
tAS Address 2.0 -2.0 -2.0 -ns 7, 9
tADSS Address Status
(ADSC , ADSP )2.0 -2.0 -2.0 -ns 7, 9
tADVS Address Advance (ADV )2.0 -2.0 -2.0 -ns 7, 9
tWS Write Signals
(BW1, BW2 , BW3 ,
BW4 , BWE , GW )
2.0 -2.0 -2.0 -ns 7, 9
tDS Data-in 2.0 -2.0 -2.0 -ns 7, 9
tCES Chip Enable
(CE , CE2, CE2 )2.0 -2.0 -2.0 -ns 7, 9
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 10 AMIC Technology, Inc.
AC Characteristics (continued)
Symbol Parameter -4.2 -4.5 -5.0 Unit Note
Min. Max. Min. Max. Min. Max.
Hold Times
tAH Address 0.5 -0.5 -0.5 -ns 7, 9
tADVH Address Status
(ADSC , ADSP )0.5 -0.5 -0.5 -ns 7, 9
tAAH Address Advance (ADV )0.5 -0.5 -0.5 -ns 7, 9
tWH Write Signal
(BW1, BW2 , BW3 ,
BW4 , BWE , GW )
0.5 -0.5 -0.5 -ns 7, 9
tDH Data-in 0.5 -0.5 -0.5 -ns 7, 9
tCEH Chip Enable
(CE , CE2, CE2 )0.5 -0.5 -0.5 -ns 7, 9
Notes:
1. All voltages refer to GND.
2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2.
Undershoot: VIH ≥ -0.7V for t ≤ tKC/2.
Power-up: VIH ≤ +3.6 and VCC ≤ 3.1V
for t ≤ 200ms
3. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and (ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 11 AMIC Technology, Inc.
Timing Waveforms
CLK
ADSP
ADSC
ADDRESS A1 A2 A3
GW,BWE
BW1-BW4
CE
(NOTE *2)
ADV
OE
Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)
High-Z
DOUT t
KQLZ
(NOTE *3)
t
KQ
t
OEHZ
t
OELZ
t
OEQ
t
KQX
t
KQ
Burst wraps around
to its initial state
t
KQHZ
Single READ BURST READ
Delselected
cycle
Burst continued with
new base address
ADV suspends
burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
(NOTE *4)
Q(A3)
(NOTE *1)
Read Timing
Notes: *1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to
be driven until after the rising edge of the following clock.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 12 AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS A1 A2 A3
OE
D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1)High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
t
ADSS
ADSC extends burst
GW
CE
(NOTE *2)
ADV
D(A1) D(A2+1) D(A3+2)
DOUT
BURST READ Single WRITE Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE *3)
(NOTE *4) ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst t
WH
t
WS
BWE,BW1-BW4
(NOTE *5)
(NOTE *1)
Write Timing
Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
*4. ADV must be HIGH to permit a Write to the loaded address.
*5. Byte Write enables are decided by means of a Write truth table.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 13 AMIC Technology, Inc.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS A1 A3
CE
(NOTE *2)
ADV
OE
D(A3) D(A5) D(A6)High-Z
DIN
t
CEH
t
CES
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
A2 A4 A5 A6
GW,BWE,
BW1-BW4
(NOTE *3)
High-Z Q(A1) Q(A2) Q(A3) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)DOUT
Back-to-Back READs Single WRITE Pass-through
READ
(NOTE *4)
BURST READ Back-to-Back
WRITEs
(NOTE *1)
t
KQ
t
OELZ
t
DH
t
DS
t
OEHZ
t
KQ
t
KQLZ
t
WS
t
WH
t
AS
t
AH
Read/Write Timing
Notes: *1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the internal burst address immediately
following A4.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Byte Write enables are decided by means of a Write truth table.
*4. Pass-through occurs when data is first written, then Read in sequence.
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 14 AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels GND to 2.5V
Input Rise and Fall Times 1.5ns
Input Timing Reference Levels 1.25V
Output Reference Levels 1.25V
Output Load See Figures 1 and 2
Z
O
=50
Ω
Q
R
L
=50
Ω
V
T
=1.5V
Figure 1. Output Load Equivalent
1538
Ω
Q
+2.5V
1667
Ω
5pF
Figure 2. Output Load Equivalent
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 15 AMIC Technology, Inc.
Ordering Information
Part No. Access Times (ns) Package
A63G7332E-4.2 4.2 100L LQFP
A63G7332E-4.5 4.5 100L LQFP
A63G7332E-5 5.0 100L LQFP
A63G7332 Series
PRELIMINARY (December, 1998, Version 2.1) 16 AMIC Technology, Inc.
Package Information
LQFP 100L Outline Dimensions unit: inches/mm
Symbol Dimensions in inches Dimensions in mm
Min. Nom. Max. Min. Nom. Max.
A10.002 - - 0.05 - -
A20.053 0.055 0.057 1.35 1.40 1.45
b0.011 0.013 0.015 0.27 0.32 0.37
c0.005 -0.008 0.12 -0.20
HE0.860 0.866 0.872 21.85 22.00 22.15
E0.783 0.787 0.791 19.90 20.00 20.10
HD0.624 0.630 0.636 15.85 16.00 16.15
D0.547 0.551 0.555 13.90 14.00 14.10
e0.026 BSC 0.65 BSC
L0.018 0.024 0.030 0.45 0.60 0.75
L10.039 REF 1.00 REF
y- - 0.004 - - 0.1
θ0°3.5°7°0°3.5°7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
31
50
51
80
81
100
HD
D
E
H
E
1 30
b
D
y
A
1
A
2
L1
c
e
θ
L
