SN74LS193 Presettable 4-Bit Binary Up/Down Counter The SN74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and the circuits can operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. * * * * * * * http://onsemi.com LOW POWER SCHOTTKY Low Power . . . 95 mW Typical Dissipation High Speed . . . 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 C TA Operating Ambient Temperature Range IOH Output Current - High - 0.4 mA 1 IOL Output Current - Low 8.0 mA SOIC D SUFFIX CASE 751B 16 ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 - Rev. 0 1 Device Package Shipping SN74LS193N 16 Pin DIP 2000 Units/Box SN74LS193D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS193/D SN74LS193 CONNECTION DIAGRAM DIP (TOP VIEW) VCC P0 MR TCD TCU PL P2 P3 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 P1 2 Q1 3 Q0 4 CPD 5 CPU 6 Q2 7 Q3 8 GND LOADING (Note a) PIN NAMES CPU CPD MR PL Pn Qn TCD TCU Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output Terminal Count Up (Carry) Output HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 11 PL 5 CPU 4 CPD 15 1 10 P0 P1 P2 9 P3 MR Q0 Q1 Q2 Q3 14 3 2 6 TCU 12 TCD 13 7 VCC = PIN 16 GND = PIN 8 http://onsemi.com 2 SN74LS193 STATE DIAGRAM 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 LOGIC EQUATIONS FOR TERMINAL COUNT TCU = Q0 Q1 Q2 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD COUNT UP COUNT DOWN 8 LOGIC DIAGRAM P0 PL (LOAD) CPU (UP COUNT) 11 P1 15 P2 P3 10 1 9 5 12 SD SD Q T SD Q T CD Q SD Q T CD Q Q T CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 6 2 Q0 Q1 7 Q2 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS http://onsemi.com 3 TCU (CARRY OUTPUT) Q3 TCD (BORROW OUTPUT) SN74LS193 FUNCTIONAL DESCRIPTION The LS193 is a 4-Bit Binary Synchronous UP / DOWN (Reversable) Counter. Each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave, and thus the Q output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When a circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (P0, P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. MODE SELECT TABLE MR PL CPU CPD H L L L L X L H H H X X H X X H H H MODE Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care = LOW-to-HIGH Clock Transition http://onsemi.com 4 SN74LS193 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Min Typ Max 2.0 0.8 - 0.65 2.7 - 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = - 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 A VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V - 0.4 mA VCC = MAX, VIN = 0.4 V - 100 mA VCC = MAX 34 mA VCC = MAX - 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol Parameter Min Typ 25 32 Max Unit fMAX Maximum Clock Frequency tPLH tPHL CPU Input to TCU Output 17 18 26 24 ns tPLH tPHL CPD Input to TCD Output 16 15 24 24 ns tPLH tPHL Clock to Q 27 30 38 47 ns tPLH tPHL PL to Q 24 25 40 40 ns tPHL MR Input to Any Output 23 35 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol Parameter Min Typ tW Any Pulse Width 20 ns ts Data Setup Time 20 ns th Data Hold Time 5.0 ns trec Recovery Time 40 ns Test Conditions VCC = 5 5.0 0V DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the PL transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the PL transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the PL transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. http://onsemi.com 5 SN74LS193 AC WAVEFORMS tW 1.3 V CPU or CPD tPLH tPHL Q 1.3 V 1.3 V 1.3 V Figure 1. CPU or CPD Pn 1.3 V tPHL tPLH tPHL TCU or TCD 1.3 V Qn 1.3 V tPLH 1.3 V NOTE: PL = LOW Figure 2. Figure 3. 1.3 V Pn PL 1.3 V tw 1.3 V CPU or CPD tPHL tPLH tPHL 1.3 V Qn 1.3 V Q Figure 4. Pn Figure 5. 1.3 V 1.3 V th(H) ts(H) th(L) ts(L) 1.3 V MR 1.3 V PL trec tW PL 1.3 V tW trec 1.3 V CPU or CPD Qn Q=P Q=P tPHL * The shaded areas indicate when the input is permitted * to change for predictable output performance Q Figure 6. 1.3 V Figure 7. http://onsemi.com 6 SN74LS193 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE -T- K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS193 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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