Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 0 1Publication Order Number:
SN74LS193/D
SN74LS193
Presettable 4-Bit Binary
Up/Down Counter
The SN74LS193 is an UP/DOWN MODULO-16 Binary Counter.
Separate Count Up and Count Down Clocks are used and the circuits
can operate synchronously. The outputs change state synchronous
with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without
extra logic, thus simplifying multistage counter designs. Individual
preset inputs allow the circuits to be used as programmable counters.
Both the Parallel Load (PL) and the Master Reset (MR) inputs
asynchronously override the clocks.
•Low Power . . . 95 mW Typical Dissipation
•High Speed...40 MHz Typical Count Frequency
•Synchronous Counting
•Asynchronous Master Reset and Parallel Load
•Individual Preset Inputs
•Cascading Circuitry Internally Provided
•Input Clamp Diodes Limit High Speed Termination Ef fects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS193N 16 Pin DIP 2000 Units/Box
SN74LS193D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS193
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Flip–Flop Outputs
Terminal Count Down (Borrow) Output
Terminal Count Up (Carry) Output
CPU
CPD
MR
PL
Pn
Qn
TCD
TCU
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
14 13 12 11 10 9
1234567
16 15
8
VCC
P1
P0MR TCDTCUP2
PL P3
Q1Q0CPDCPUQ2Q3GND
5
4
3267
12
91011511
CPDQ0Q1Q2Q3TCD
P3
P2
P1
P0
PL
CPUTCU
13
MR
14
SN74LS193
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3
STATE DIAGRAM
COUNT UP
COUNT DOWN
01234
5
6
7
891011
12
13
14
15
LOGIC EQUATIONS
FOR TERMINAL COUNT
TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU
TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD
LOGIC DIAGRAM
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
P0P1P2P3
Q0Q1Q2Q3
MR
(CLEAR)
(DOWN
COUNT)
CPD
(UP COUNT)
CPU
(LOAD)
PL1
267
3
4
5
911
12
10
13
15
14
SDQ
Q
CD
T
SDQ
Q
CD
T
SDQ
Q
CD
T
SDQ
Q
CD
T
TCU
(CARRY
OUTPUT)
TCD
(BORROW
OUTPUT)
SN74LS193
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4
FUNCTIONAL DESCRIPTION
The LS193 is a 4-Bit Binary Synchronous UP /DOWN
(Reversable) Counter. Each circuit contains four
master/slave flip-flops, with internal gating and steering
logic to provide master reset, individual preset, count up and
count down operations.
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes
the slave, and thus the Q output to change state. Synchronous
switching, as opposed to ripple counting, is achieved by
driving the steering gates of all stages from a common Count
Up line and a common Count Down line, thereby causing all
state changes to be initiated simultaneously. A
LOW-to-HIGH transition on the Count Up input will
advance the count by one; a similar transition on the Count
Down input will decrease the count by one. While counting
with one clock input, the other should be held HIGH.
Otherwise, the circuit will either count by twos or not at all,
depending on the state of the first flip-flop, which cannot
toggle as long as either Clock input is LOW.
The Terminal Count Up (TCU) and T erminal Count Down
(TCD) outputs are normally HIGH. When a circuit has
reached the maximum count state of 15, the next
HIGH-to-LOW transition of the Count Up Clock will cause
TCU to go LOW. TCU will stay LOW until CPU goes HIGH
again, thus effectively repeating the Count Up Clock, but
delayed by two gate delays. Similarly, the TCD output will
go LOW when the circuit is in the zero state and the Count
Down Clock goes LOW. Since the TC outputs repeat the
clock waveforms, they can be used as the clock input signals
to the next higher order circuit in a multistage counter.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW,
information present on the Parallel Data inputs (P0, P3) is
loaded into the counter and appears on the outputs regardless
of the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both Clock inputs, and latch each Q output in the LOW state.
If one of the Clock inputs is LOW during and after a reset or
load operation, the next LOW-to-HIGH transition of that
Clock will be interpreted as a legitimate signal and will be
counted.
MODE SELECT TABLE
MR PL CPUCPDMODE
H X X X Reset (Asyn.)
L L X X Preset (Asyn.)
L H H H No Change
L H H Count Up
L H H Count Down
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
= LOW-to-HIGH Clock Transition
SN74LS193
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5
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per T ruth Table
VO
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
tp
u
t
LOW
Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL
or
V
IH
per T ruth Table
I
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
Inp
u
t
HIGH
C
u
rrent
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 34 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 25 32 MHz
tPLH
tPHL CPU Input to
TCU Output 17
18 26
24 ns
tPLH
tPHL CPD Input to
TCD Output 16
15 24
24 ns VCC = 5.0 V
tPLH
tPHL Clock to Q 27
30 38
47 ns
CC
CL = 15 pF
tPLH
tPHL PL to Q 24
25 40
40 ns
tPHL MR Input to Any Output 23 35 ns
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tWAny Pulse Width 20 ns
tsData Setup T ime 20 ns
VCC =50V
thData Hold T ime 5.0 ns
V
CC =
5
.
0
V
trec Recovery Time 40 ns
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the PL transition from LOW-to-HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following
the PL transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the PL transition
from LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
SN74LS193
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6
AC WAVEFORMS
Figure 1.
Figure 2. Figure 3.
Figure 4. Figure 5.
Figure 6. Figure 7.
1.3 V
CPU or CPD
CPU or CPD
CPU or CPD
Q
Q
Q
tw
CPU or CPD
TCU or TCD
PL
PL
Pn
Qn
MR
tPHL tPLH
tPLH
Pn
Qn
NOTE: PL = LOW
tW
tPHL
Pn
PL
Qn
ts(H) ts(L)
th(H) th(L)
* The shaded areas indicate when the input is permitted
* to change for predictable output performance
Q = P Q = P
tPLH
trec
tPLH tPHL
tPHL
tW
tPHL
tPHL
tW
1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
trec
SN74LS193
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7
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
SN74LS193
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8
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