74AHCT08BQ,115 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74AHC08; 74AHCT08 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74AHC08; 74AHCT08 provides the quad 2-input AND function.

2. Features

■Balanced propagation delays

■All inputs have a Schmitt-trigger action

■Inputs accepts voltages higher than VCC

■For 74AHC08 only: operates with CMOS input levels

■For 74AHCT08 only: operates with TTL input levels

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A115-A exceeds 200 V

◆CDM JESD22-C101C exceeds 1000 V

■Multiple package options

■Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74AHC08; 74AHCT08

Quad 2-input AND gate

Rev. 03 — 14 November 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC08D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

74AHCT08D

74AHC08PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74AHCT08PW

74AHC08BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

74AHCT08BQ

Product data sheet Rev. 03 — 14 November 2007 2 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)

mna222

1B 1Y

2B 2Y

3B 3Y

4B 4Y

12 11

mna223

mna221

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 4. Pin conﬁguration SO14 and TSSOP14 Fig 5. Pin conﬁguration DHVQFN14

1A VCC

1B 4B

1Y 4A

2A 4Y

2B 3B

2Y 3A

GND 3Y

001aac945

7 8

001aac946

GND(1)

Transparent top view

2Y 3A

2B 3B

2A 4Y

1Y 4A

1B 4B

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Product data sheet Rev. 03 — 14 November 2007 3 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

7. Limiting values

Table 2. Pin description

Symbol Pin Description

1A 1 data input

1B 2 data input

1Y 3 data output

2A 4 data input

2B 5 data input

2Y 6 data output

GND 7 ground (0 V)

3Y 8 data output

3A 9 data input

3B 10 data input

4Y 11 data output

4A 12 data input

4B 13 data input

VCC 14 supply voltage

Table 3. Function selection[1]

Input Output

nA nB nY

LXL

XLL

HHH

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7.0 V

VIinput voltage −0.5 +7.0 V

IIK input clamping current VI < −0.5 V [1] −20 - mA

IOK output clamping current VO<−0.5 V or VO>V

CC + 0.5 V [1] -±20 mA

IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA

ICC supply current - 75 mA

IGND ground current −75 - mA

Tstg storage temperature −65 +150 °C

Product data sheet Rev. 03 — 14 November 2007 4 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly with 8 mW/K above 70 °C.

[3] Ptot derates linearly with 5.5 mW/K above 60 °C.

[4] Ptot derates linearly with 4.5 mW/K above 60 °C.

8. Recommended operating conditions

9. Static characteristics

Ptot total power dissipation Tamb = −40 °C to +125 °C

SO14 package [2] - 500 mW

TSSOP14 package [3] - 500 mW

DHVQFN14 package [4] - 500 mW

Table 4. Limiting values

…continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 74AHC08 74AHCT08 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V

VIinput voltage 0 - 5.5 0 - 5.5 V

VOoutput voltage 0 - VCC 0- V

CC V

Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C

∆t/∆V input transition rise

and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V

VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V

Table 6. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

For type 74AHC08

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V

VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V

VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V

VIL LOW-level

input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V

VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V

VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V

VOH HIGH-level

output voltage VI= VIH or VIL

IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V

IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V

Product data sheet Rev. 03 — 14 November 2007 5 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

VOL LOW-level

output voltage VI= VIH or VIL

IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current VI= 5.5 Vor GND; VCC =0V

to 5.5 V - - 0.1 - 1.0 - 2.0 µA

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC = 5.5 V - - 2.0 - 20 - 40 µA

CIinput

capacitance - 3.0 10 - 10 - 10 pF

For type 74AHCT08

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO=−50 µA 4.4 4.5 - 4.4 - 4.4 - V

IO=−8.0 mA 3.94 - - 3.8 - 3.7 - V

VOL LOW-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO= 50 µA - 0 0.1 - 0.1 - 0.1 V

IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current VI= 5.5 V or GND; VCC =0V

to 5.5 V - - 0.1 - 1.0 - 2.0 µA

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC = 5.5 V - - 2.0 - 20 - 40 µA

∆ICC additional

supply current per input pin;

VI=V

CC −2.1 V; IO= 0 A;

other pins at VCC or GND;

VCC = 4.5 V to 5.5 V

- - 1.35 - 1.5 - 1.5 mA

CIinput

capacitance - 3.0 10 - 10 - 10 pF

Table 6. Static characteristics

…continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 14 November 2007 6 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

10. Dynamic characteristics

[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[2] tpd is the same as tPLH and tPHL.

[3] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz, fo= output frequency in MHz

CL= output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL×VCC2×fo) = sum of the outputs.

Table 7. Dynamic characteristics

GND = 0 V; For test circuit see Figure 7.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max Min Max

For type 74AHC08

tpd propagation

delay nA, nB to nY; see Figure 6 [2]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 4.0 8.8 1.0 10.5 1.0 11.0 ns

CL= 50 pF - 5.6 12.3 1.0 14 1.0 15.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 3.0 5.9 1.0 7.0 1.0 7.5 ns

CL= 50 pF 4.2 7.9 1.0 9.0 1.0 10.0 ns

CPD power

dissipation

capacitance

CL= 50 pF; fi = 1 MHz;

VI= GND to VCC

[3] - 10.0 - - - - - pF

For type 74AHCT08

tpd propagation

delay nA, nB to nY; see Figure 6 [2]

VCC = 4.5 V to 5.5 V

CL= 15 pF - 3.2 6.9 1.0 8.0 1.0 9.0 ns

CL= 50 pF - 4.2 7.9 1.0 9.0 1.0 10.0 ns

CPD power

dissipation

capacitance

CL= 50 pF; fi = 1 MHz;

VI= GND to VCC

[3] - 12.0 - - - - - pF

Product data sheet Rev. 03 — 14 November 2007 7 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays

mna224

nA, nB input

nY output

tPLH

tPHL

GND

VOH

VOL

Table 8. Measurement points

Type Input Output

VMVM

74AHC08 0.5VCC 0.5VCC

74AHCT08 1.5 V 0.5VCC

Product data sheet Rev. 03 — 14 November 2007 8 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig 7. Load circuit for switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

PULSE

GENERATOR

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

74AHC08 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC

74AHCT08 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC

Product data sheet Rev. 03 — 14 November 2007 9 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

12. Package outline

Fig 8. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 03 — 14 November 2007 10 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

Fig 9. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 14 November 2007 11 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

Fig 10. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 03 — 14 November 2007 12 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

LSTTL Low-power Schottky Transistor-Transistor Logic

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

CDM Charged Device Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC_AHCT08_3 20071114 Product data sheet - 74AHC_AHCT08_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN14 package added.

•Section 7: derating values added for DHVQFN14 package.

•Section 12: outline drawing added for DHVQFN14 package.

74AHC_AHCT08_2 19990924 Product speciﬁcation - 74AHC_AHCT08_1

74AHC_AHCT08_1 19981218 Product speciﬁcation - -

Product data sheet Rev. 03 — 14 November 2007 13 of 14

NXP Semiconductors 74AHC08; 74AHCT08

Quad 2-input AND gate

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AHC08; 74AHCT08
Quad 2-input AND gate
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 November 2007
Document identifier: 74AHC_AHCT08_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
Contents
General description . . . . . . . . . . . . . . . . . . . . . .  1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
Ordering information. . . . . . . . . . . . . . . . . . . . .  1
Functional diagram . . . . . . . . . . . . . . . . . . . . . .  2
Pinning information. . . . . . . . . . . . . . . . . . . . . .  2
1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  3
Functional description  . . . . . . . . . . . . . . . . . . .  3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .  3
Recommended operating conditions. . . . . . . .  4
Static characteristics. . . . . . . . . . . . . . . . . . . . .  4
Dynamic characteristics . . . . . . . . . . . . . . . . . .  6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .  9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  12
Revision history. . . . . . . . . . . . . . . . . . . . . . . .  12
Legal information. . . . . . . . . . . . . . . . . . . . . . .  13
1 Data sheet status . . . . . . . . . . . . . . . . . . . . . .  13
2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .  13
4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .  13
Contact information. . . . . . . . . . . . . . . . . . . . .  13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14