All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
D
DI
I2
2C
CM
M
I2C Bus Interface - Master
ver 3.02
OVERVIEW
I2C is a two-wire, bi-directional serial bus that
provides a simple and efficient method of data
transmission over a short distance between
many devices. The DI2CM core provides an
interface between a microprocessor / micro-
controller and an I2C bus. It can work as a
master transmitter or master receiver depend-
ing on working mode determined by micro-
processor/microcontroller. The DI2CM core
incorporates all features required by the latest
I2C specification including clock synchroniza-
tion, arbitration, multi-master systems and
High-speed transmission mode. Built-in timer
allows operation from a wide range of the clk
frequencies.
KEY FEATURES
● Conforms to v.2.1 of the I2C specification
● Master operation
○ Master transmitter
○ Master recei ver
● Support for all transmission speeds
○ Standard (up to 100 kb/s)
○ Fast (up to 400 kb/s)
○ High Speed (up to 3,4 Mb/s)
● Arbitration and clock synchronization
● Support for multi-master systems
● Support for both 7-bit and 10-bit address-
ing formats on the I2C bus
● Interrupt generation
● Build-in 8-bit timer for data transfers speed
adjusting
● Host side interface dedicated for micro-
processors/microcontrollers
● User-defined timing (data setup, start
setup, start hold, etc.)
● Fully synthesizable
● Static synchronous design with positive
edge clocking and synchronous reset
● No internal tri-states
● Scan test ready
APPLICATIONS
● Embedded microprocessor boards
● Consumer and professional audio/video
● Home and automotive radio
● Low-power applications
● Communication systems
● Cost-effective reliable automotive systems
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, mi-
nor and major versions changes
● Delivery the documentation up-
dates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source cod e called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Ne tlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Desi gns
SYMBOL
datai(7:0) datao(7:0)
irq
rd
we
address(1:0)
scli
sdai
cs
rst
clk
sclhs
sclo
sdao
PINS DESCRIPTION
PIN TYPE DESCRIPTION
clk input Global clock
rst input Global reset
address(1:0) input Processor address lines
cs input Chip select
we input Processor write strobe
rd input Processor read strobe
scli input I2C bus clock line (input)
sdai input I2C bus data line (input)
datai(7:0) input Processor data bus (input)
datao(7:0) output Processor data bus (output)
sclo output I2C bus clock line (output)
sclhs output High-speed clock line (output)
sdao output I2C bus data line (output)
irq output Processor interrupt line
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
BLOCK DIAGRAM
Figure below shows the DI2CM IP Core block
diagram.
address
(
1:0
)
datai
(
7:0
)
datao
(
7:0
)
rd
cs
we
rst
clk
ir
q
CPU
Interface
sdai
sdao
scli
sclo
Input
Filter
Output
Register
Shift
Register
Clock
Generator
Output
Register
Input
Filter
Timer
Control
Logic
Clock
Synchronization
Send
Data
Receive
Data
Slave
Address
Control
Register
Status
Register
Arbitration
Logic
Output
Register sclhs
CPU Interface – Performs the interface func-
tions between DI2CM internal blocks and mi-
croprocessor. Allows easy connection of the
core to a microprocessor/microcontroller sys-
tem.
Control Logic – Manages execution of all
commands sent via interface. Synchronizes
internal data flow.
Shift Register – Controls SDA line, performs
data and address shifts during the data
transmission and reception.
Control Register – Contains five control bits
used for performing all types of I2C Bus
transmissions.
Status Register – Contains seven status bits
that indicates state of the I2C Bus and the
DI2CM core.
Clock Generator – Performs generation of
the serial clock.
Input Filter – Performs spike filtering.
Clock Synchronization – Performs clock
synchronization.
Arbitration Logic – Performs arbitration dur-
ing operations in multi-master systems.
Timer – Allows operation from a wide range of
the input frequencies. It is programmed by an
user before transmission and can be repro-
grammed to change the SCL frequency.
IMPLEMENTATION
Figures below show the typical DI2CM imple-
mentations in system with Standard/Fast and
High-speed devices.
open drain
open drain
RPRP
VDD
sdai
SCL
SD
A
sdao
RSRS
sclo
scli
DI2CM
Slave
device
scl
RS
RS
sda
sclhs
DI2CM implementation in I2C-bus system with
Standard/Fast devices only
open drain
open drain
RPRP
VDD
sdai
SCL
SD
A
sdao
RSRS
sclo
scli
DI2CM
Slave
device
scl
RS
RS
sda
sclhs
VDD
current-source
pull-up
DI2CM implementation in I2C-bus system with
High-speed devices
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
Device Speed
grade Logic Cells Fmax
MERCURY -5 290 210 MHz
STRATIX -5 290 270 MHz
CYCLONE -6 290 250 MHz
APEX II -7 290 210 MHz
APEX20KC -7 290 185 MHz
APEX20KE -1 290 160 MHz
APEX20K -1 290 120 MHz
ACEX1K -1 290 130 MHz
FLEX10KE -1 290 140 MHz
MAX 7000AE -5 149 64 MHz
MAX 3000A -7 149 47 MHz
Core performance in ALTERA® devices
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
The main features of each Digital Core Design I2C compliant cores have been summarized in table
below. It gives a briefly member characterization helping user to select the most suitable IP Core
for its application.
Design
I2C specification
version
Master operation
Slave operation
CPU interface
Passive device
interface
Interrupt
generation
Clock
synchronization
Arbitration
7-bit addressing
10-bit addressing
Standard mode
Fast mode
High-speed mode
User defined
timing
Spike filtering
DI2CM 3.0 - -
DI2CS 2.1 - - - -
DI2CSB 2.1 - - - - - - -
I2C cores summary table
All trademarks mentioned in this document http://www.DigitalCoreDesign.com
are trademarks of their respective owners. http://www.dcd.pl
Copyright 1999-2004 DCD – Digital Core Design. All Rights Reserved.
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
e-mail: i
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.p
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tel. : +48 32 282 82 66
fax : +48 32 282 74 37
Distributors:
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