11.3 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2526
Rev. A
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FEATURES
3.3 V operation
Up to 11.3 Gbps operation
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p diff
Automatic laser shutdown (ALS)
Cross point adjustment (CPA)
XFP-compliant bias current monitor
SFP+ MSA compliant
Optical evaluation board available
Compact 3 mm × 3 mm LFCSP
APPLICATIONS
SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules
GENERAL DESCRIPTION
The ADN2526 laser diode driver is designed for direct modula-
tion of packaged laser diodes that have a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination in the
ADN2526 absorbs signal reflections from the TOSA end of the
output transmission lines, enabling excellent optical eye quality to
be achieved even when the TOSA end of the output transmission
lines is significantly misterminated. ADN2526 is an SFP+ MSA-
compliant device, and its small package and enhanced ESD
protection provide the optimum solution for compact modules
where laser diodes are packaged in low pin-count optical
subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various
average optical power and extinction ratio control schemes,
including closed-loop or look-up table control. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with a
LVTTL logic source.
The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
50Ω
200Ω
800Ω
200Ω2Ω
VCC
DATAP
DATAN
MSET VEE BSET
IBMON
IBIAS
IMODP
IMODN
ADN2526
V
CC
A
LS
VCC
CPA
GND
VCC
50Ω
50Ω
200Ω
800Ω
IMOD
CROSS
POINT
ADJUST
07511-001
Figure 1.
ADN2526
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Input Stage ................................................................................... 10
Bias Current ................................................................................ 10
Automatic Laser Shutdown (ALS) ........................................... 11
Modulation Current ................................................................... 11
Load Mistermination ................................................................. 12
Crosspoint Adjustment .............................................................. 13
Power Sequence .......................................................................... 13
Power Consumption .................................................................. 13
Applications Information .............................................................. 14
Typical Application Circuit ....................................................... 14
Layout Guidelines....................................................................... 14
Design Example .......................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Changes to θJ-PAD Maximum Value (Table 2) ................................. 4
Changes to Figure 5 and Figure 6 ................................................... 8
1/09—Revision 0: Initial Version
ADN2526
Rev. A | Page 3 of 16
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted. Typical values are specified at
TA = 25°C, IMODD
1 = 40 mA, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range 10 100 mA
Bias Current While ALS Asserted 300 μA ALS = high
Compliance Voltage2 0.6 VCC V IBIAS = 100 mA
0.6 VCC V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range 10 80 mA diff RLOAD = 5 Ω to 50 Ω differential
Modulation Current While ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)3, 4 24 32.5 ps
Fall Time (20% to 80%)3, 4 24 32.5 ps
Random Jitter3, 4 0.4 0.9 ps rms
Deterministic Jitter3, 5 7.2 12 ps p-p Includes pulse width distortion
Pulse Width Distortion3, 4 2 5 ps PWD = (|THIGH – TLOW|)/2
Differential |S22| −10 dB 5 GHz < f < 10 GHz, Z0 = 50 Ω differential
−14 dB f < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage2 VCC − 1.1 VCC + 1.1 V
DATA INPUTS (DATAP, DATAN)
Input Data Rate 11.3 Gbps NRZ
Differential Input Swing 0.15 1.6 V p-p diff Differential, ac-coupled
Differential |S11| −16.8 dB f < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 100 Ω Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain 90 mA/V
BSET Input Resistance 1000 Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain 50 78 100 mA/V See Figure 29
MSET Input Resistance 1000 Ω
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio 10 μA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 % 10 mA ≤ IBIAS < 20 mA, RIBMON = 1 kΩ
−4.0 +4.0 % 20 mA ≤ IBIAS < 40 mA, RIBMON = 1 kΩ
−2.5 +2.5 % 40 mA ≤ IBIAS < 70 mA, RIBMON = 1 kΩ
−2 +2 % 70 mA ≤ IBIAS < 100 mA, RIBMON = 1 kΩ
AUTOMATIC LASER SHUTDOWN (ALS)
VIH 2.0 V
VIL 0.8 V
IIL −30 +30 μA
IIH 0 200 μA
ALS Assert Time 2 μs Rising edge of ALS to falling edge of IBIAS and
IMOD below 10% of nominal, see Figure 2
ALS Negate Time 10 μs Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal, see Figure 2
ADN2526
Rev. A | Page 4 of 16
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
VCC 3.0 3.3 3.6 V
ICC6 46 55 mA VBSET = VMSET = 0 V
ISUPPLY7 74 95 mA VBSET = VMSET = 0 V; ISUPPLY = ICC + IMODP + IMODN
CPA 1.88 V In NC mode (refer to Table 4)
Cross Point 50 % From an optical eye in NC mode
1 IMOD is the total modulation current sink capability for a differential driver. IMOD = IMODP + IMODN, the dynamic current sank by the IMODP and IMODN pins.
2 Refers to the voltage between the pin for which the compliance voltage is specified and VEE.
3 The pattern used is a repetitive sequence of eight 1s followed by eight 0s at 11.3 Gbps.
4 Measured using the high speed characterization circuit shown in Figure 3.
5 The pattern used is K28.5 (00111110101100000101) at a 11.3 Gbps rate.
6 Only includes current in the VCC pins.
7 Without laser diode loaded.
THERMAL SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Conditions/Comments
θJ-PAD 2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad
θJ-TOP 65 72.2 79.4 °C/W Thermal resistance from junction to top of package
IC Junction Temperature 125 °C
90%
10%
ALS
IBIAS
AND IMOD
ALS
ASSERT TIME
A
LS
NEGATE TIME
t
t
0
7511-002
Figure 2. ALS Timing Diagram
ADN2526
Rev. A | Page 5 of 16
MSET CPA ALS
BSET IBMON IBIAS VEE
VEE
VCC
IMODP
IMODN
VCC
10nF
10nF
J8 J5
V
EE
V
EE
TP1 10nF
ADN2526
22µF
VEE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
50Ω
50Ω
OSCILLOSCOPE
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 20dB ATTENUATOR
ADAPTER
VBSET
Z0 = 50ΩZ0 = 25ΩZ0 = 50Ω
Z0 = 25ΩZ0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
1kΩ
V
EE
GND GND GND
VEE
VMSET
VEE
VCPA
TP2
10Ω
70Ω
35Ω
35Ω
10nF GND
VEE
J2
GND GND GND
GND
VCC
VCC
DATAN
DATAP
GND
GNDGND
J3
GND GND
BIAS
TEE
BIAS
TEE
ADAPTER
ATTENUATOR
ATTENUATOR
0
7511-003
Figure 3. High Speed Characterization Circuit
ADN2526
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VEE connected to supply ground.
Table 3.
Parameter Rating
Supply Voltage, VCC to VEE −0.3 V to +4.2 V
IMODP, IMODN to VEE 1.1 V to 4.75 V
DATAP, DATAN to VEE VCC − 1.8 V to VCC − 0.4 V
All Other Pins −0.3 V to VCC + 0.3 V
HBM ESD on IMODP, IMODN 200 V
HBM ESD on All Other Pins 1 kV
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Soldering Temperature
(Less Than 10 sec)
300°C
ESD CAUTION
ADN2526
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1MSET
2CPA
3ALS
4VEE
11 IBMON
12 BSET
10 IBIAS
9VEE
5
VCC
6
IMODN
7
IMODP
8
VCC
15 DATAN
16 VCC
14 DATAP
13 VCC
TOP VIEW
(Not to Scale)
ADN2526
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VCC OR THE GND PLANE.
07511-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic I/O1 Description
1 MSET AI Modulation Current Control Input.
2 CPA AI Adjustable Cross Point. Defaults to not connected (NC) mode (floating).
3 ALS DI Automatic Laser Shutdown.
4 VEE P Negative Power Supply. Normally connected to system ground.
5 VCC P Positive Power Supply.
6 IMODN AI Modulation Current Sink, Negative.
7 IMODP AI Modulation Current Sink, Positive.
8 VCC P Positive Power Supply.
9 VEE P Negative Power Supply. Normally connected to system ground.
10 IBIAS AI Bias Current Sink.
11 IBMON AO Bias Current Monitoring Output.
12 BSET AI Bias Current Control Input.
13 VCC P Positive Power Supply.
14 DATAP AI Data Signal Positive Input.
15 DATAN AI Data Signal Negative Input.
16 VCC P Positive Power Supply.
17 (EPAD) Exposed Pad (EPAD) P The exposed pad on the bottom of the package must be connected to VCC or the GND plane.
1 AI = analog input, DI = digital input, P = power, AO = analog output.
ADN2526
Rev. A | Page 8 of 16
0
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
0 2040608010
RISE TIME (ps)
IMOD (mA)
07511-005
Figure 5. Rise Time vs. IMOD
27.0
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
0 2040608010
FALL TIME (ps)
IMOD (mA)
0
07511-006
Figure 6. Fall Time vs. IMOD
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 2040608010
JITTER (ps)
IMOD (mA)
0
07511-007
Figure 7. Random Jitter vs. IMOD
9
8
7
6
5
4
3
2
1
0
0 2040608010
JITTER (ps)
IMOD (mA)
0
07511-008
Figure 8. Deterministic Jitter vs. IMOD
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0 102030405060708090100
TOTAL I
V
CC (A)
IMOD (mA)
IBIAS = 10
IBIAS = 50
IBIAS = 100
07511-009
Figure 9. Total Supply Current vs. IMOD
FREQUENCY (GHz)
1501234567891011121314
DIFFERENTIAL |S11| (dB)
0
–40
–35
–30
–25
–20
–15
–10
–5
07511-036
Figure 10. Differential |S11|
ADN2526
Rev. A | Page 9 of 16
FREQUENCY (GHz)
1501234567891011121314
DIFFERENTIAL |S22| (dB)
0
–40
–35
–30
–25
–20
–15
–10
–5
07511-035
Figure 11. Differential |S22|
RISE TIME (ps)
3023 24 25 26 27 28 29
OCCURRENCE (%)
16
10
12
14
6
8
4
2
0
07511-012
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
FALL TIME (ps)
3023 24 25 26 27 28 29
OCCURRENCE (%)
16
10
12
14
8
6
4
2
0
07511-013
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, TA = 85°C)
07511-014
Figure 14. Electrical Eye Diagram
(11.3 Gbps, PRBS31, IMOD = 80 mA)
07511-015
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for Reference)
07511-016
Figure 16. Filtered 10 Gb Ethernet Optical Eye
ADN2526
Rev. A | Page 10 of 16
THEORY OF OPERATION
As shown in Figure 1, the ADN2526 consists of an input stage
and two voltage-controlled current sources for bias and modula-
tion. The bias current, which is available at the IBIAS pin, is
controlled by the voltage applied at the BSET pin and can be
monitored at the IBMON pin. The differential modulation
current, which is available at the IMODP and IMODN pins, is
controlled by the voltage applied to the MSET pin. The output
stage implements the active back-match circuitry for proper
transmission line matching and power consumption reduction.
The ADN2526 can drive a load having differential resistance
ranging from 5 Ω to 50 Ω. The excellent back-termination in
the ADN2526 absorbs the signal reflections from the TOSA
end, enabling excellent optical eye quality, even though the
TOSA is significantly misterminated.
INPUT STAGE
The input stage of the ADN2526 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
VCC
50Ω
50Ω
V
CC
DATAP
DATAN
07511-017
Figure 17. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which can otherwise lead to degradation in
the output eye diagram. It is not recommended to drive the
ADN2526 with single-ended data signal sources.
The ADN2526 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance much less than 50 Ω over the required
frequency range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
In SFP+ MSA applications, the DATAP and DATAN pins need
to be connected to the SFP+ connector directly. This connection
requires enhanced ESD protection to support the SFP+ module
hot plug-in application.
ADN2526
DATAP
DATAN
C
C
50Ω50Ω
DATA SIGNAL SOURCE
07511-018
Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 19.
GND
200Ω
800Ω
2Ω
RR
VCC
IBMONBSET
I
BMON
ADN2526
I
BIAS
200Ω
IBIAS
07511-019
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and VEE, the bias current can be moni-
tored as a voltage across the resistor. A low temperature coefficient
precision resistor must be used for the IBMON resistor (RIBMON).
Any error in the value of RIBMON that is due to tolerances or to drift
in its value over temperature contributes to the overall error
budget for the IBIAS monitor voltage. If the IBMON voltage is
connected to an ADC for analog-to-digital conversion, RIBMON
should be placed close to the ADC to minimize errors due to
voltage drops on the ground plane.
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
V
C
C
BSET
VCC
800Ω
200Ω
07511-020
Figure 20. Equivalent Circuit of the BSET Pin
ADN2526
Rev. A | Page 11 of 16
2Ω
2kΩ
100Ω
IBIAS
VCC
V
CC
07511-021
Figure 21. Equivalent Circuit of the IBIAS Pin
VCC
IBMON
V
CC
100Ω
500Ω
V
CC
07511-022
Figure 22. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
ADN2526
BSET
VBSET GND
IBMON IBMON
IBIAS
TO LASER CATHODE
L
R
1kΩ
IBIAS
07511-023
Figure 23. Recommended Configuration for the BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (10 mA and 100 mA), but it can be calculated for
any bias current by
VCOMPLIANCE_MAX (V) = VCC (V) − 0.75 − 4.4 × IBIAS (1)
See the Applications Information section for examples of
headroom calculations.
The function of the inductor, L, is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Table 7.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Tabl e 5.
Table 5. ALS Functions
ALS Logic State IBIAS and IMOD
High Disabled
Low Enabled
Floating Enabled
The ALS pin is compatible with 3.3 V CMOS and LVTTL logic
levels. Its equivalent circuit is shown in Figure 24.
V
CC
A
LS
V
CC
100Ω
40kΩ
2kΩ
07511-024
Figure 24. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor, as shown in
Figure 25.
50Ω
200Ω
800Ω
MSET
GND
IMODP
IMODN
ADN2526
VCC
V
O
g
m
× V
O
FROM INPUT STAGE
IMOD
07511-025
Figure 25. Generation of Modulation Current on the ADN2526
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and amplified by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination.
A small portion of the modulation current flows in the virtual
50 Ω active back-termination resistor. All of the preset IMOD
modulation current, the range specified in Table 1, flows into
the external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 26 and Figure 27. The two 25 Ω
resistors in Figure 27 are not actual resistors. They represent the
active back-termination resistance.
ADN2526
Rev. A | Page 12 of 16
V
CC
MSET
800Ω
200Ω
V
CC
07511-026
Figure 26. Equivalent Circuit of the MSET Pin
V
CC
V
C
C
3.3Ω3.3Ω
25Ω
IMODPIMODN
25Ω
07511-027
Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Table 7 for the
recommended components.
ADN2526
MSET
V
MSET
VEE
IMODP
IBIAS
VCC
L
C
TOSA
L
IMODN
Z
0
= 25ΩZ
0
= 25Ω
VCC
VCC
L
C
L
Z
0
= 25ΩZ
0
= 25Ω
0
7511-028
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
DIFFERENTIAL LOAD RESISTANCE (Ω)
I
MOD
/
MSET
(mA/V)
07511-029
MINIMUM
MAXIMUM
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
220
210
0 102030405060
TYPICAL
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2526 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for these pins over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
IMODP, IMODN
VCC
V
CC – 1.1V
V
CC + 1.1V
NORMAL OPERATION REGION
07511-030
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2526 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case, with
50 Ω differential transmission lines connecting the ADN2526 to
the load, the load end of the transmission lines are misterminated.
This mistermination leads to signal reflections back to the driver.
The excellent back-termination in the ADN2526 absorbs these
reflections, preventing their reflection back to the load. This
enables excellent optical eye quality to be achieved, even when
the load end of the transmission lines is significantly mistermi-
nated. The connection between the load and the ADN2526 must
be made with 50 Ω differential (25 Ω single-ended) transmission
lines so that the driver end of the transmission lines is properly
terminated.
ADN2526
Rev. A | Page 13 of 16
CROSSPOINT ADJUSTMENT
The optical eye cross point is adjustable between 35% and 65%
using the cross point adjust (CPA) control input. The equivalent
circuit for the CPA pin is shown in Figure 31. In a default CPA
setting, leave CPA unconnected (maintain pin-to-pin compatibil-
ity with the ADN2525). The internal bias circuit presents about
1.9 V at the CPA pin and the eye cross point is set to 50%. To set
the cross point at various points, apply an external voltage to the
CPA pin.
7kΩ
7kΩ7kΩ
VCC
CPA
07511-031
Figure 31. Equivalent Circuit for CPA Pin
POWER SEQUENCE
To ensure reliable operation, the recommended power-up
sequence is: the supply rail to ADN2526 first, then the BSET
pin, followed by the MSET pin, and, finally, the CPA pin.
To turn off the ADN2526, the operation is reversed: shut down
CPA first, then MSET, followed by BSET, and, last, the supply rail.
POWER CONSUMPTION
The power dissipated by the ADN2526 is given by
IBIASVI
V
VCCP IBIASSUPPLY
MSET ×+
⎟
⎠
⎞
⎜
⎝
⎛+×= 13.5
where:
VCC is the power supply voltage.
VMSET is the voltage applied to the MSET pin.
ISUPPLY is the sum of the currents that flow into VCC, IMODP,
and IMODN, which are sank by the ADN2526 when VBSET =
VMSET = 0 V, expressed in amps (see Table 1).
VIBIAS is the average voltage presented on the IBIAS pin.
IBIAS is the bias current sank by the ADN2526.
Considering VBSET/IBIAS = 10 mV/mA as the conversion factor
from VBSET to IBIAS, the dissipated power becomes
IBIAS
BSET
SUPPLY
MSET V
V
I
V
VCCP ×+
⎟
⎠
⎞
⎜
⎝
⎛+×= 105.13
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2526 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the SFP+ module case
can work as a heat sink, as shown in Figure 32. A compact
optical module is a complex thermal environment, and
calculations of device junction temperature using the package
junction-to-ambient thermal resistance (θJA) do not yield
accurate results.
T
TOP
T
J
TPAD
DIE
PACKAGE
THERMAL COMPOUND MODULE CASE
PCB
VIAS
COPPER PLANE
THERMOCOUPLE
07511-032
Figure 32. Typical Optical Module Structure
The parameters in Table 6 can be used to estimate the IC
junction temperature.
Table 6. Definitions
Parameter Description Unit
TTOP Temperature at the top of the package °C
TPAD Temperature at the package exposed paddle °C
TJ IC junction temperature °C
P Power dissipation W
θJ-TOP Thermal resistance from the IC junction to
the package top
°C/W
θJ-PAD Thermal resistance from the IC junction to
the package exposed paddle
°C/W
TTOP and TPA D can be determined by measuring the temperature
at points inside the module, as shown in Figure 32. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 33, the junction temperature can be calculated by
TJ =
(
)
TOPJ
PADJ
TOPJ
PADPADJ
TOPTOPJ
PADJ TTP
−
−
−
−
−
−
+
×+×+××
θθ
θθθθ
where:
θJ-TOP and θJ-PAD are given in Table 2.
P is the power dissipated by the ADN2526.
P
θ
J-TOP
T
PAD
T
TOP
T
TOP
θ
J-PAD
07511-033
Figure 33. Electrical Model for Thermal Calculations
ADN2526
Rev. A | Page 14 of 16
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 34 shows the typical application circuit for the ADN2526.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on or turn off the bias and modulation currents, depending on
the logic level applied to the pin. The data signal source must be
connected to the DATAP and DATAN pins of the ADN2526
using 50 Ω transmission lines. The modulation current outputs,
IMODP and IMODN, must be connected to the load (TOSA)
using 50 Ω differential (25 Ω single-ended) transmission lines.
It is recommended that the components shown in Table 7 be
used between the ADN2526 and the TOSA for an example ac
coupling circuit. For up-to-date component recommendations,
contact your local Analog Devices, Inc., sales representative.
Working with a TOSA laser sample, the circuit in Figure 34
delivers optical performance shown in Figure 15 and Figure 16.
For additional applications information and optical eye perfor-
mance of other laser samples, contact your local Analog Devices
sales representative.
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2526 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Well controlled transmission line
impedance must be used for the high speed signal paths. The
length of the transmission lines must be kept to a minimum to
reduce losses and pattern-dependent jitter. The PCB layout
must be symmetrical, on both the DATAP and DATAN inputs
and the IMODP and IMODN outputs, to ensure a balance
between the differential signals. All VCC and VEE pins must be
connected to solid copper planes by using low inductance
connections. When the connections are made through vias,
multiple vias should be used in parallel to reduce the parasitic
inductance. Each VEE pin must be locally decoupled with high
quality capacitors. If proper decoupling cannot be achieved
using a single capacitor, the user can use multiple capacitors in
parallel for each VEE pin. A 20 μF tantalum capacitor must be
used as a general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2526, see
the Amkor Technology® Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages.
Table 7. Recommended Components for AC-Coupling
Component Value Description
R1, R2 36 Ω 0603 size resistor
R3, R4 200 Ω 0603 size resistor
C3, C4 100 nF 0603 size capacitor, Phycomp 223878615649
L2, L3 20 nH 0402 size inductor, Murata LQW15AN20NJ0
L6, L7 0402 size ferrite Murata BLM15HG102SN1
L1, L4, L5, L8 10 μH 0603 size inductor, Murata LQM21FN100M70L
CPA
MSET CPA ALS VEE
BSET IBMON IBIAS VEE
VCC
DATAP
DATAN
VCC
VCC
IMODP
IMODN
VCC
DATAP
DATAN
C1
C2
MSET
BSET
R5
1kΩ
ADN2526
Z
0
= 50ΩZ
0
= 25ΩZ
0
= 25Ω
Z
0
= 50Ω
GND
VCC
GND
VCC
TOSA
C4
C7
200µF
L2
L1 R1
3.3V
VCC VCC
VCC
VCC
VCC
TP1 C5
10nF
GND
GND
VCC
C6
10nF
GND
ALS
L7
L8 R4
L6
L5 R3
VCC
L3
L4 R2
VCC
Z
0
= 25ΩZ
0
= 25Ω
C3
GND
0
7511-034
Figure 34. Typical Application Circuit
ADN2526
Rev. A | Page 15 of 16
DESIGN EXAMPLE
This design example covers:
• Headroom calculations for the IBIAS, IMODP, and
IMODN pins.
• Calculation of the typical voltage required at the BSET and
MSET pins to produce the desired bias and modulation
currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is VF = 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 34,
the voltage at the IBIAS pin can be written as
VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA
where:
VCC is the supply voltage.
VF is the forward voltage across the laser at low current.
RTOSA is the resistance of the TOSA.
VLA is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that VLA = 0 V, VF = 1 V, and IBIAS =
40 mA
VIBIAS = 3.3 − 1 − (0.04 × 25) = 1.3 V
VIBIAS = 1.3 V > 0.6 V, which satisfies the requirement.
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
VCOMPLIANCE_MAX = VCC − 0.75 − 4.4 × IBIAS (2)
For this example,
VCOMPLIANCE_MAX = VCC – 0.75 − 4.4 × 0.04 = 2.53 V
VIBIAS = 1.3 V < 2.53 V, which satisfies the requirement.
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC, due to the ac-coupled configuration, and a swing equal
to IMOD × 25 Ω. For proper operation of the ADN2526, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
VLB is the dc voltage drop across L1, L2, L3, and L4. Assuming
that VLB = 0 V and IMOD = 60 mA, the minimum voltage at the
modulation output pins is equal to
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2526 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA
and the typical IBIAS/VBSET ratio of 100 mA/V, the BSET voltage
is given by
V4.0
100
40
mA/V100
(mA) === IBIAS
VBSET
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
K
IMOD
VMSET =
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K is equal to 120 mA/V.
Assuming that IMOD = 60 mA and using the preceding
equation, the MSET voltage is given by
V5.0
120
60
mA/V120
(mA) === IMOD
VMSET
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
ADN2526
Rev. A | Page 16 of 16
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
071708-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADN2526ACPZ1 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 F0C
ADN2526ACPZ-R21 −40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape & Reel, 250-Piece Reel CP-16-3 F0C
ADN2526ACPZ-R71 −40°C to +85°C 16-Lead LFCSP_VQ, 7” Tape & Reel, 1,500-Piece Reel CP-16-3 F0C
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07511-0-8/09(A)