Handbook - Lattice Semiconductor

SERDES Handbook

April 2003

Dear Valued Customer,

Lattice Semiconductor is pleased to provide you this second edition of our SERDES Handbook. Since offering the initial

version last year, we have introduced several new products based on our superior sysHSI™ technology:

ORT42G5 4 channel version of our leading-edge ORT82G5 FPSC for XAUI and Fibre Channel backplanes

ORSO82G5 8 channels of SERDES running at 2.7 Gbps with embedded SONET capabilities

ORSO42G5 4 channel version of the ORSO82G5

ispGDX2 4 to 20 channels of SERDES running at 850 Mbps with embedded digital switch

ispXPGA™ 4 to 16 channels of SERDES running at 850 Mbps with up to 1M gates of non-volatile, reconfigurable

FPGA Logic

The content of this Handbook demonstrates Lattice’s philosophy of “Bringing the Best Together” through the exceptional

capabilities of the world’s fastest and most cost-effective programmable backplane devices. Illustrating this concept, the

ORT82G5 Field-Programmable System-on-a-Chip (FPSC) includes backplane transceivers supporting eight channels at up to

3.7 Gbits/s coupled with over 10,000 lookup tables (LUTs) based on our ORCA

FPGA architecture.

The ORT82G5 offers the world’s finest programmable SERDES with unsurpassed performance:

Programmable Data Rates • 8 channels at 1.0 to 3.125 Gbps

• Demonstrated performance at up to 3.7 Gbps

Standards Compliance • Exceeds XAUI signal integrity specification by at least 50%

• Fibre Channel (1G, 2G) and FC-XAUI (10G)

Rx Jitter Tolerance • 0.75UI superior to XAUI and Fibre Channel specifications

Tx Total Jitter • 0.17UI superior to XAUI and Fibre Channel specifications

Low Power per SERDES Channel • <225 mW worst case, including I/O buffers

Fast Locking Times • Bit Realignment 300 nanoseconds (938 bit times @ 3.125 Gbps)

Transmitter Output (CML) • Full-amplitude mode: 0.8V p-p Minimum

• Half-amplitude mode: 0.4V p-p Minimum

Demonstrated Data Bandwidth • 3.7 Gbps1

Demonstrated Drive Length • At least 40 inches of FR-4 backplane at 3.125 Gbps2

This Handbook contains a variety of updated resources that illustrate the capabilities of all our SERDES-based products, an

essential building block for your next system design. We have included:

• Product briefs discussing all of our SERDES-based products

• A product brief describing our 10GbE XGXS intellectual property core which provides a complete bridging solution

between XGMII and XAUI for fast design of 10GbE applications.

• Technical notes that provide detailed technical back-up supporting the superiority of Lattice’s SEDES-based products:

–ORT82G5 High-Speed Backplane Measurements

–High-Speed PCB Design Considerations

–FPSC SERDES CML Buffer Interface

–SERDES Test Chip Jitter

–Lock Times for the ORT82G5 SERDES

– SERDES Reference Clock

– Introduction to the sysHSI Block / ispXPGA and ispGDX2

Please contact us should you require additional information on any of our SERDES-based products. We would be pleased to

work with you to create world-class communications solutions.

Regards,

Stan Kopec,

Vice President of Corporate Marketing

Lattice Semiconductor

SERDES tested at 3.7 Gbps across 26 inches of FR-4

Running at 3.125 Gbits/sec. SERDES was not tested to failure

SERDES Handbook

Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), LSC, Beyond

Performance, E2CMOS, FIRST-TIME-FIT, GAL, Generic Array Logic, in-system programmable, in-system programmability, ISP, ispATE,

ispDesignEXPERT, ispDOWNLOAD, ispEXPLORER, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2, ispGDXVA, ispJTAG, ispLEVER,

ispLEVERCORE, ispLSI, ispMACH, ispPAC, ispSOC, ispSVF, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA,

ispXPLD, LINE2AR, LOGIBUILDER, MACH, ORCA, PAC, PAC-Designer, PAL, PALCE, Performance Analyst, SCUBA, Silicon Forest,

Speedlocked, Speed Locking, SPEEDSEARCH, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysHSI, sysI/O,

sysMEM, The Simple Machine for Complex Design, Twin GLB, UltraMOS, V Vantis (design), Vantis, Vantis (design), Variable-Grain-Block,

Variable-Length-Interconnect, and specific device designations are either registered trademarks or trademarks of Lattice Semiconductor

Corporation or its subsidiaries in the United States and/or other countries. ISP and Bringing the Best Together are service marks of Lattice

Semiconductor Corporation.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective

companies.

Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. patents: 4,554,640; 4,562,484; 4,608,678;

4,609,998; 4,625,162; 4,625,311; 4,635,230; 4,638,189; 4,638,243; 4,645,953; 4,646,269; 4,654,824; 4,654,825; 4,661,922; 4,668,880;

4,670,708; 4,670,714; 4,679,310; 4,684,826; 4,684,830; 4,697,105; 4,717,912; 4,725,979; 4,740,485; 4,742,247; 4,742,252; 4,742,491;

4,758,746; 4,758,747; 4,761,768; 4,766,569; 4,771,285; 4,779,010; 4,779,229; 4,789,797; 4,789,951; 4,796,075; 4,814,646; 4,833,646;

4,849,933; 4,852,044; 4,855,954; 4,857,770; 4,864,165; 4,876,640; 4,879,688; 4,887,239; 4,891,683; 4,896,296; 4,914,322; 4,924,278;

4,931,671; 4,933,577; 4,933,897; 4,935,648; 4,939,391; 4,947,060; 4,963,768; 4,984,151; 4,994,691; 5,005,155; 5,015,884; 5,017,809;

5,019,996; 5,027,315; 5,042,004; 5,079,450; 5,081,380; 5,101,378; 5,124,568; 5,128,871; 5,130,574; 5,138,198; 5,151,623; 5,153,462;

5,162,679; 5,168,177; 5,179,716; 5,185,706; 5,189,322; 5,191,242; 5,191,243; 5,204,556; 5,212,652; 5,225,719; 5,231,315; 5,231,316;

5,231,588; 5,231,602; 5,233,539; 5,237,218; 5,239,213; 5,239,510; 5,245,226; 5,247,195; 5,247,213; 5,251,169; 5,255,203; 5,255,221;

5,260,881; 5,261,116; 5,264,740; 5,272,666; 5,281,906; 5,295,095; 5,307,352; 5,311,080; 5,315,174; 5,329,179; 5,329,460; 5,331,590;

5,336,951; 5,349,544; 5,349,670; 5,353,246; 5,357,156; 5,359,536; 5,359,573; 5,381,058; 5,384,497; 5,386,156; 5,394,031; 5,394,033;

5,394,037; 5,396,126; 5,402,081; 5,404,055; 5,406,139; 5,408,145; 5,410,268; 5,412,260; 5,418,390; 5,418,472; 5,418,482; 5,422,823;

5,426,335; 5,432,463; 5,436,514; 5,436,579; 5,438,277; 5,438,278; 5,442,304; 5,442,306; 5,452,229; 5,457,404; 5,457,409; 5,469,088;

5,469,368; 5,485,104; 5,489,857; 5,490,074; 5,491,433; 5,493,205; 5,495,195; 5,506,517; 5,510,738; 5,521,529; 5,526,278; 5,528,170;

5,559,450; 5,565,794; 5,568,066; 5,570,039; 5,570,046; 5,574,678; 5,581,126; 5,583,451; 5,586,044; 5,587,921; 5,587,945; 5,589,782;

5,594,365; 5,594,657; 5,594,687; 5,596,524; 5,598,346; 5,612,631; 5,615,150; 5,617,042; 5,617,064; 5,621,650; 5,623,217; 5,635,855;

5,638,018; 5,644,496; 5,646,901; 5,666,087; 5,666,309; 5,668,488; 5,670,907; 5,672,521; 5,700,698; 5,717,342; 5,719,516; 5,723,984;

5,734,275; 5,736,888; 5,739,713; 5,740,069; 5,742,542; 5,748,525; 5,751,163; 5,751,164; 5,754,471; 5,756,367; 5,760,605; 5,760,609;

5,761,116; 5,764,078; 5,781,030; 5,789,939; 5,796,295; 5,796,750; 5,801,551; 5,805,607; 5,808,942; 5,809,522; 5,811,986; 5,811,987;

5,818,254; 5,818,294; 5,830,795; 5,835,405; 5,841,701; 5,844,912; 5,854,114; 5,862,365; 5,864,486; 5,869,981; 5,885,904; 5,886,378;

5,892,962; 5,904,575; 5,905,385; 5,912,550; 5,942,780; 5,949,279; 5,959,336; 5,960,274; 5,969,992; 5,978,272; 5,982,193; 5,982,683;

5,986,471; 5,986,480; 5,989,957; 5,990,702; 5,991,907; 5,999,449; 6,002,610; 6,003,150; 6,009,033; 6,020,755; 6,023,570; 6,025,637;

6,028,446; 6,028,447; 6,028,463; 6,028,758; 6,028,789; 6,028,993; 6,031,365; 6,034,538; 6,034,541; 6,034,544; 6,034,893; 6,043,677;

6,043,969; 6,049,224; 6,060,902; 6,064,105; 6,064,225; 6,064,595; 6,066,977; 6,067,252; 6,072,351; 6,075,293; 6,075,724; 6,081,473;

6,087,275; 6,087,696; 6,087,854; 6,091,595; 6,093,946; 6,097,212; 6,097,664; 6,100,715; 6,102,963; 6,104,207; 6,107,823; 6,108,806;

6,118,693; 6,124,730; 6,124,732; 6,127,843; 6,128,770; 6,130,551; 6,133,164; 6,133,750; 6,133,769; 6,134,703; 6,137,738; 6,150,841;

6,150,842; 6,154,050; 6,154,051; 6,157,568; 6,163,168; 6,163,175; 6,169,432; 6,172,392; 6,175,266; 6,181,163; 6,184,713; 6,190,966;

6,191,609; 6,191,612; 6,197,638; 6,202,182; 6,204,686; 6,207,989; 6,208,559; 6,211,695; 6,214,666; 6,215,700; 6,216,191; 6,216,257;

6,218,857; 6,221,733; 6,225,821; 6,228,696; 6,229,336; 6,232,631; 6,249,144; 6,255,169; 6,255,847; 6,256,758; 6,261,944; 6,265,900;

6,274,898; 6,275,064; 6,278,311; 6,282,123; 6,284,626; 6,287,916; 6,288,937; 6,291,327; 6,292,930; 6,294,809; 6,294,810; 6,294,811;

6,294,925; 6,297,128; 6,304,099; 6,326,663; 6,326,808; 6,347,387; 6,348,813; 6,351,157; 6,353,352; 6,356,107; 6,359,466; 6,362,684;

6,370,071; 6,380,759; 6,389,321; 6,404,006; 6,404,226; 6,413,826; 6,414,521; 6,424,000; 6,424,003; 6,424,209; 6,429,692; 6,433,602;

6,455,375; 6,455,912; 6,462,602; 6,470,485; 6,472,904; 6,480,026; 6,483,342; 6,486,705; 6,489,806; 6,489,835; 6,492,877; 6,496,969;

6,498,538; 6,507,212 Additional patents are pending. LSC does not represent that products described herein are free from patent infringement

or from any third-party right. This legal notice is updated from time to time and users are advised to check the most current notice, which is

available at www.latticesemi.com.

LSC may make changes to these materials, specifications, or information, or to the products described herein, at any time without notice. LSC

makes no commitment to update this documentation. LSC reserves the right to discontinue any product or service without notice and assumes

no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends

its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current.

LATTICE SEMICONDUCTOR CORPORATION

5555 Northeast Moore Court

Hillsboro, Oregon 97124 U.S.A.

Tel.: (503) 268-8000

FAX: (503) 268-8347

http://www.latticesemi.com

Table of Contents

Product Briefs

sysHSI™ SERDES Technology........................................................................................................................... 1

ORCA

ORT82G5 and ORT42G5 – World’s Fastest Programmable Backplane Transceivers............................5

ORCA ORSO82G5 and ORSO42G5 – Programmable Serial SONET Backplane Transceivers......................... 7

ORT8850 – High-Speed Programmable SERDES with SONET Framing ........................................................... 9

ispXPGA™ – FPGAs with Cost-Effective SERDES........................................................................................... 11

ispGDX2™ – High Performance Digital Crosspoint Switch with Cost-Effective SERDES................................. 15

ORCA ORT82G5 Evaluation Board................................................................................................................... 19

ORCA ORT8850 Evaluation Board.................................................................................................................... 21

Application Examples

ORCA ORT82G5 Applications........................................................................................................................... 23

Intellectual Property Cores

10 Gigabit Ethernet XGXS Intellectual Property Cores..................................................................................... 25

Technical Notes

ORT82G5 High-Speed Backplane Measurements............................................................................................29

High-Speed PCB Design Considerations .......................................................................................................... 43

FPSC SERDES CML Buffer Interface................................................................................................................ 53

SERDES Test Chip Jitter ................................................................................................................................... 65

Lock Times for the ORT82G5 SERDES............................................................................................................. 71

SERDES Reference Clock................................................................................................................................. 75

Introduction to the sysHSI Block / ispXPGA and ispGDX2................................................................................81

sysHSI

sysHSI SERDES Technology

HIGH PERFORMANCE PROGRAMMABLE SERDES SOLUTIONS

Over the last several years designers have been challenged

to obtain higher data rates, reduce PCB traces, reduce

connectors, and reduce EMI emissions and susceptibility.

SERDES technologies

have become

increasingly popular

as a method to meet

these challenges for

chip-to-chip, board-

to-board, and

backplane

applications.

Lattice has implemented sysHSI™ SERDES technologies in

a variety of programmable products. High performance

SERDES are integrated into Lattice’s Field Programmable

System Chip (FPSC) devices. A cost effective SERDES is

implemented in Lattice’s ispXPGA™ family of FPGAs and

its ispGDX2 programmable interconnect family.

Lattice sysHSI SERDES technology leads the programmable

logic industry in terms of maximum bit rate, low TX jitter,

RX jitter tolerance and power consumption per channel.

With sysHSI SERDES technology, Lattice products

demonstrate the fastest bit rates and the longest error-free

connections.

Proven SERDES Leadership

sysHSI SERDES Key Capabilities

■Wide Range of Bandwidth Supported

• 126 Mbps to 3.7 Gbps

• Roadmap to 10 Gbps

■Low TX Jitter

• 0.17UI @ 3.125 Gbps

■Excellent RX Jitter Tolerance

• 0.75UI @ 3.125 Gbps

■Programmable Pre-emphasis (FPSCs)

• 0%, 12.5%, 25%

■Robust High Speed

• Reliable transmission over:

– 26 inches of FR4 at 3.7 Gbps

– 40 inches of FR4 at 3.125 Gbps

– 75 feet of co-axial cable at 622 Mbps

■Low Power CMOS Operation

• <225 mW per channel at 3.125 Gbps

• <50 mW per channel at 622 Mbps

■Choice of Programmable Fabric

• ispGDX® – Programmable digital interconnect

• ispXPGA – FPGA

• FPSC – FPGA + embedded interface core

■Support For Multiple Standards

• XAUI, Fibre channel, Gigabit Ethernet, SONET

Lattice Programmable SERDES

“Lattice’s ORSO82G5 FPSC technology allows our Zeus™ groom-

ing switch to seamlessly interface with existing and emerging

SONET line cards, thus preser ving the carrier’s enormous invest-

ment made in SONET-based systems.”

Bill Woodruff, VP of Marketing

Velio Communication

“FPSC technology allowed NEC to

place our custom backplane interface

design in the programmable portion of

the device, while utilizing the built-in

SERDES channels provided in the em-

bedded core of the ORT8850. Lattice

FPSCs provide a distinct advantage

over a discrete SERDES and FPGA so-

lution.”

Shigeki Suyama, General Manager

NEC Corporation

Aggregate Bandwidth

per Device

Programmable

Digital Interconnect

+ SERDES

FPGA + SERDES FPGA +

Embedded Interface

Cores + SERDES

The world's largest selection of

programmable SERDES!

15G

30G

ispGDX2

256

ispGDX2

128

ispGDX2

ispXPGA

500

ispXPGA

1200

ispXPGA

200

ispXPGA

125

ORCA

ORT8850

ORCA

ORT82G5

ORCA

ORSO

82G5

ORCA

ORT42G5

ORCA

ORSO

42G5

16 Channels

@ 850Mbps

8 Channels

@ 850Mbps

8 Channels

@ 850Mbps

4 Channels

@ 2.7Gbps

8 Channels

@ 2.7Gbps

4 Channels

@ 3.7Gbps

8 Channels

@ 3.7Gbps

12 Channels

@ 850Mbps

20 Channels

@ 850Mbps

4 Channels

@ 850Mbps

4 Channels

@ 850Mbps

8 Channels

@ 850Mbps

SERDES Solutions

ORT82G5 RX Eye Diagram over 26 inches

(65 centimeters) of FR4 at 3.7 Gbps ORT82G5 RX Eye Diagram over 40 inches

(100 centimeters) of FR4 at 3.125 Gbps

ORSO82G5 RX Eye Diagram over 30 inches

(75 centimeters) of FR4 at 2.7 Gbps

Superior SERDES Perfor mance

Lattice sysHSI SERDES technology leads the programmable logic industry in terms

of maximum bit rate and low jitter. The following actual eye diagrams illustrate

the outstanding characteristics of Lattice’s sysHSI SERDES technology.

Typical SERDES evaluation test setup

for Lattice devices.

Interoperability

Designers may successfully use Lattice’s

sysHSI SERDES in conjunction with a

variety of other SERDES implemented in

a standard chip or ASIC. To date,

interoperability has been demonstrated

between Lattice SERDES and devices

from Velio, AMCC and Agere.

High Perfor mance SERDES Solutions

Lattice has integrated high performance SERDES into five of its ORCA®

FPSC (Field Programmable System Chip) devices for use in a variety of

communications applications. Key features of these SERDES include:

■High bit rates up to 3.7 Gbps

■TX jitter as low as 0.17UI at 3.125 Gbps

■RX jitter tolerance up to 0.75UI at 3.125 Gbps

■Power per channel ≤ 225 mW at 3.125 Gbps

Lattice’s high performance SERDES is available on the

ORT82G5, ORT42G5, ORSO82G5, ORSO42G5, and

ORT8850 FPSC devices.

ispXPGA Block Diagram

Cost Effective SERDES Soutions

Lattice has developed it’s most cost effective SERDES for use in a variety of chip-to-

chip, board-to-board, and backplane applications where a moderate speed SERDES is

required. This SERDES is available on the ispXPGA and ispGDX2 devices.

ispXPGA FPGA

Up to 20 x 850 Mbps SERDES + FPGA

The ispXPGA family couples an ispXP™ (ISP™

eXpanded Programmability) based FPGA with up to

20 SERDES channels. With ispXP technology, the

ispXPGA family provides infinite reconfigurability

through SRAM technology and the benefits of

instant-on, security, and a single chip solution

through E2CMOS® non-volatility.

sysCLOCK PLLs

sysIO Blocks for

advanced I/O

support

Programmable I/O Cells

sysMEM™ Blocks

Each sysHSI Block provides

2 duplex 850Mbps SERDES

Programmable

Function Units

sysHSI

Block

ERDE

FIF

DX Bloc

PLL

Global Routin

Poo

sysHSI

Block

SERDES SERDES

FIFO FIFO

GDX Block GDX Block

sysIO Block sysIO Block

sysIO™ Block sysIO Block

sIO Blocks f

advanced I

O su

sHSI Block

rovides 2 du

lex

850Mb

s SERDE

sCLOC

™

PLL

FIFOs for bufferin

data

streams

(

15x10 bits

)

DX Bl

kincludes

control lo

ic and data

multi

lexer

Flexible routin

timized for bus

switchin

sysIO Block

IO Bl k

sysIO Block

O B

ispGDX2 Block Diagram

ispGDX2 – Programmable Interconnect

Up to 16 x 850 Mbps SERDES + Interconnect

The ispGDX2 family provides cost effective SERDES

solutions at less than $2.00 per channel for high volume

applications. These SERDES are coupled with a

multiplexer-based programmable interconnect and

switching fabric and flexible I/Os. Many designers use the

ispGDX2 device as a universal parallel-to-serial converter.

ORSO82G5/42G5 FPGA with

Embedded Core

2.7Gbps SERDES + SONET Framing + FPGA

ORSO82G5 and ORSO42G5 devices include eight or

four high performance SERDES, respectively. Coupled

with on-chip SONET framing, these device provide an

excellent SONET-based solution for implementing chip-

to-chip or backplane applications.

ORT82G5/42G5 FPGAs with Embedded Core

3.7 Gbps SERDES + XAUI / Fibre Channel + FPGA

ORT82G5 and ORT42G5 devices provide eight or four high

performance SERDES, respectively. Standard compliance and on-

chip link state machines make these devices ideal for

implementing XAUI, 10 Gbps Ethernet and Fibre Channel links in

chip-to-chip and backplane applications.

ORT8850 FPGA with Embedded Core

850Mbps SERDES + SONET Framing + FPGA

The ORT8850 includes eight 850Mbps SERDES

channels plus on-chip SONET framing. The ORT8850

provides an alternative to Ethernet technology for

implementing chip-to-chip or backplane applications.

ASIC Gates

Provide

cost effective,

high-speed,

pre-designed

support logic

SERDES/

CDR

ORCA

eries

ates

I/O

h Performance s

ERDE

ORT82G5/42G5: 0.6 to 3.7Gb

ORSO82G5/42G5: 0.6 to 2.7Gb

ORT8850: 126 to 850Mb

Flexible s

™

abilit

Single-ended

(

GTL+,

Differential

(

LVDS,

LVPECL

)

, DD

ASIC Gate

ORT82G5

42G5:

10b

encodin

/decodin

multi-channel ali

nment

ic, XAUI & Fibre

hannel state machine

ORSO82G5

42G5:

SONET framin

, SONET

scrambling, pa

load

8850

NET

ramin

, SONET

scramblin

ates

Provide

h-s

eed

pre-desi

support lo

FPSC Block Diagram

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

sysHSI SERDES Enabled Devices

Serial Standards Quick Reference

Fibre Lattice

Specification Channel Infiniband SFI-5 XAUI ORT82G5

Baud Rate 1.0625 Gbps 2.5 Gbps 2.5 Gbps 3.125 Gbps 3.125 Gbps

TX Total Jitter 0.65UI 0.35UI 0.35UI 0.35UI 0.17UI

RX Jitter Tolerance 0.70UI 0.65UI 0.65UI 0.65UI 0.75UI

ORT82G5 / 42G5 ORSO82G5 / 42G5 ORT8850H ORT8850L ispXPGA ispGDX2

Data Rate 3.7 – 0.6 Gbps 2.7 – 0.6 Gbps 850 – 126 Mbps 850 – 126 Mbps 850 – 400 Mbps 850 – 400 Mbps

per Channel

# of Channels 8 / 4 8 / 4 8 8 4 – 20 4 – 16

SERDES I/O CML CML LVDS LVDS LVDS LVDS

TX Jitter 0.17UI 0.16UI 0.25UI 0.25UI 0.25UI 0.25UI

RX Jitter 0.75UI 0.79UI 0.6UI 0.6UI 0.4UI 0.4UI

On-Chip Yes Yes Yes Yes No No

Termination

Pre-emphasis 25, 12.5, 0% 25, 12.5, 0% — — — —

Settings

Power / Channel 225 mW 225 mW 50 mW 50 mW 65 mW 65 mW

Encoding 8b/10b SONET SONET SONET 10b/12b 10b/12b

Support 8b/10b* 8b/10b*

Standards XAUI, Fibre Channel SONET-based SONET-based SONET-based Proprietary Proprietary

Support Gigabit Ethernet SERDES links SERDES links SERDES links SERDES links SERDES links

FPSC 8b/10b encoding Pseudo-SONET Pseudo-SONET Pseudo-SONET — —

Functionality XAUI & Fibre Framing, TOH Framing, TOH Framing, TOH

channel link state insertion/extraction insertion/extraction insertion/extraction

machines, multi-channel multi-channel multi-channel

multi-channel alignment, payload alignment, alignment,

alignment cell processor pointer mover pointer mover

Programmable 10,368 LUTS 10,368 LUTS 16,192 LUTS 4,992 LUTS 1.9K – 15.3K LUTS ispGDX2 multiplexer

Section 643K Gates 643K Gates 899K Gates 397K Gates 125K – 1.2M Gates and interconnect

372 / 204 I/O 372 / 204 I/O 297 I/O 278 I/O 176 – 496 I/O fabric

Typical Bridging, Bridging, Bridging, Bridging, PCI, SDRAM interface, Multiplexer

Programmable proprietary packet proprietary packet proprietary packet proprietary packet Utopia interface

Functions processing processing processing processing

High Performance SERDES Cost Effective SERDES

* Bit alignment. 8b/10b encoding/decoding must be implemented outside of the sysHSI block.

ORT82G5/42G5

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

Key Features and Benefits

■High Performance ORCA Series 4 FPGA Gates:

• Internal performance of > 250 MHz.

• Over 10,000 Lookup Tables.

• 1.5V operation (30% less power than 1.8V operation)

• Comprehensive I/O selections including LVTTL,

LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bus-LVDS, and LVPECL.

■Ease of Design

• Supported by ispLEVER™ ver. 3.0 design software.

• Complete ORT82G5 and ORT42G5 design kits

supplies simulation models for embedded core,

configuration tool, and integrates with ispLEVER

ver. 3.0 design software.

■Easy System Integration

• SERDES performance exceeds XAUI specifications.

• XGMII IP core for FPGA side supports interfacing to

10 Gbps Ethernet MACs.

• XAUI to XGMII translator (XGXS IP Core)

• Easy integration of 10 Gbps Ethernet and Fibre-

Channel for data over fibre applications.

Building Better Backplanes...

Lattice Semiconductor has developed a new generation of

Field Programmable System Chips (FPSC) targeted at high-

speed serial backplane data transmission. Built on the

ORCA® Series 4 reconfigurable embedded system-on-a-chip

(SoC) architecture, the ORT82G5 contains eight backplane

transceiver channels, each operating in the range from 600

Mbits/sec to 3.7 Gbps, together with a full-duplex

synchronous interface with built-in clock and data recovery

(CDR), and more than 10,000 lookup tables. The

ORT42G5 provides the same functionality with four

SERDES channels.

Designers can also use the devices to drive high-speed data

transfers across buses within systems because of the

embedded 8b/10b capability. For example, with the

ORT82G5, designers can build a 20 Gbps bridge (10 Gbps

work and 10 Gbps protect) for 10 Gbps Ethernet; the high-

speed SERDES interfaces implement two XAUI interfaces

with configurable back-end interfaces such as XGMII

implemented on the FPGA side. The ORT82G5 can also be

used to provide two full 10 Gbps backplane data

connections for work and protection between a line card

and switch fabric. The ORT42G5 can be used for one full-

duplex 10 Gbps backplane data connection between a line

card and switch fabric.

Both the ORT82G5 and ORT42G5 offer a clockless high-

speed interface for inter-device communication on a board

The World’s Fastest Programmable Backplane Transceivers!

ORCA ORT82G5 Block Diagram

or across a backplane. The built-in clock recovery of the

ORT82G5 and ORT42G5 allows higher system

performance, easier-to-design clock domains in a

multiboard system, and fewer signals on the backplane.

Network designers will also benefit from the backplane

transceivers as network termination devices. The devices

support embedded 8b/10b encoding/decoding and link

state machines for 10G Ethernet, as well as Fibre Channel.

CML I/Os

Quad Channel

MUX/deMUX Micro-

processor

Interface

and

Registers

CML I/Os

Quad Channel

MUX/deMUX

User-Configurable I/Os

4k x 36

Dual-Port

RAM

System Bus Parallel Data

Parallel Data

2:1 Data

Selector

Multi-Chan.

Alignment

+ FIFO

2:1 Data

Selector

Multi-Chan.

Alignment

+ FIFO

ORCA Series 4 FPGA Gates

Selectable High-Speed Data Rates – 1.25 / 2.5 / 3.125 Gbits/sec

Clock Clock

4k x 36

Dual-Port

RAM

Quad Serializer-DeSerializer

with 8B/10B Encoder/Decoder Quad Serializer-DeSerializer

with 8B/10B Encoder/Decoder

3.7 Gbps

DEMONSTRATED!

Note: The ORT42G5 provides one quad SERDES channel.

ORCA ORT82G5 and ORT42G5 Attributes

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

Embedded Core Features

■Robust High Speed - Reliable transmission over:

– 26 inches of FR4 at 3.7 Gbps

– 40 inches of FR4 at 3.125 Gbps

– 75 feet of co-axial cable at 622 Mbps

■Lowest power consumption of any programmable

SERDES – less than 225mW (worst case) per

channel at 3.125 Gbps over full temperature/voltage

range.

■Low Tx Jitter: 0.17UI @ 3.125 Gbps

■Excellent Receive Jitter Tolerance: 0.75 UI @ 3.125

Gbps

■Transmit pre-emphasis (programmable) for improved

receive data eye opening: 0%, 12.5%, 25%

■32-bit (8b/10b) or 40-bit (raw data) parallel internal

bus for data processing in FPGA logic.

■Exceeds XAUI serial data specification for 10 GbE

applications with protection. Includes integrated

XAUI state machine.

■Compliant to Fibre Channel physical layer

specification, including integrated Fibre Channel

state machine.

■SERDES has low-power CML buffers to allow use

with optical transceiver, coaxial copper media,

shielded twisted pair wiring or high-speed

backplanes such as FR-4.

FPGA PFU EBR FPGA Max

Usable RAM RAM User FPGA I/O SERDES Data Rate

Device Gates PFUs LUTs Registers Bits Bits I/O Package Compatibility Channels per Channel

ORT82G5

333 - 643K 1,296 10,368 12,780 277K 111K 372 680PBGAM 1.5/1.8/2.5/3.3V 8 3.7 Gbps

ORT42G5

333 - 643K 1,296 10,368 12,780 277K 111K 204 484PBGAM 1.5/1.8/2.5/3.3V 4 3.7 Gbps

The ORT82G5 and ORT42G5 are ideal for 10 Gigabit

Ethernet systems. The ORT82G5 provides 8 channels of

3.125 Gbps data to drive across two XAUI backplanes for

work and protection. The ORT42G5 provides one channel

of 3.125 Gbps data to drive across one XAUI backplane

connection. Both devices connects directly to a XENPAK

optical transponder on the line card side, and to a 10 GbE

MAC via an XGMII interface implemented in FPGA gates.

This elegant solution allows network system designers to

immediately deploy 10 GbE in the LAN, in the MAN, and

in the WAN.

The ORT42G5 can be used as a cost-effective backplane

driver for systems requiring up to 10Gbps across a XAUI-

based backplane. The programmable gates on the

ORT42G5 are ideal for implementing interfaces to switch

fabrics or network processors.

Actual data eye at 3.7 Gbps across 26 inches of FR-4 backplane

with 25% pre-emphasis.

ORT82G5 and ORT42G5 CDR Eye

Diagram Measurements

ORCA ORT82G5 and ORT42G5 Applications

Protect Optical

Line Card

ORCA

ORT82G5

Backplane

Transceiver

10 Gigabit

Ethernet

MAC

XGMII

Backplane

XAUI

70-Pin MSA

XENPAK

Transponder

Work Optical

Line Card

XAUI

ORCA

ORT42G5

Backplane

Transceiver

ORCA

ORT42G5

Backplane

Transceiver

Network

Processor

OC-48

Framer

Optics

Backplane

XAUI

Switch Fabric

ORSO82G5/42G5

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

Key Features and Benefits

■High Performance ORCA Series 4 FPGA Gates:

• Internal performance of > 250 MHz.

• Over 10,000 lookup tables.

• 1.5V operation (30% less power than 1.8V operation)

• Comprehensive I/O selections including LVTTL,

LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bus-LVDS, and LVPECL.

■Ease of Design

• Supported by ispLEVER™ ver. 3.0 design software.

• Complete ORSO82G5 and ORSO42G5 design kits

supplies simulation models for embedded core,

configuration tool, and ispLEVER ver. 3.0 design

software integration.

■Easy System Integration

• Programmable platform for bridging network

processor/routing devices to switch fabrics over

SONET SERDES. On the line side, the ORSO82G5 can

be utilized to provide a flexible interface to various

optical modules (such as VSR-3).

Building Better Backplanes...

Lattice Semiconductor has developed a next-generation

Field Programmable System-on-a-Chip (FPSC) solution for

high-speed serial SONET backplane data transmission. Built

on the ORCA® Series 4 reconfigurable embedded system

on-a-chip (SoC) architecture, the ORSO82G5 includes eight

backplane transceiver channels, each operating at up to 2.7

Gbps data rate, providing a full-duplex synchronous

interface with built-in Clock/Data Recovery (CDR) and over

10,000 lookup tables. The ORSO42G5 provides the same

functionality with four SERDES channels.

The ORSO82G5 provides a full 10 Gbps backplane data

connection with protection between a line card/redundant

line card and switch fabric/redundant switch fabric. The

FPGA portion can be used to implement 2.5 Gbps and 10

Gbps SONET-based switch fabric interfaces. The

ORSO42G5 can also implement a 10 Gbps backplane

without the protection scheme.

The ORSO82G5 and ORSO42G5 provide a SERDES-based

high-speed interface for inter-device communication on a

board or across a backplane. The built-in clock recovery of

the ORSO82G5 and ORSO42G5 supports higher system

performance, easier-to-design clock domains in a

multiboard system, and fewer signals on the backplane.

The ORSO82G5 and ORSO42G5 support SONET data

scrambling and descrambling, streamlined SONET framing,

transport overhead handling, cell insertion and extraction,

idle cell insertion/deletion plus the programmable logic to

High Speed — Low Overhead — Serial SONET Backplane Transceiver

ORCA ORSO82G5 Block Diagram

terminate the network into proprietary systems. All SONET

functionality is hidden from the user and no prior

networking knowledge is required. The user can optionally

bypass all SONET functionality (SERDES-only mode) to

enable the implementation of proprietar y processing

schemes. Optional Cell Mode processing blocks provide a

glueless interface to switch fabrics, 2.5 Gbps and 10 Gbps

network processors, or can be used when both ends of a

link are either ORSO82G5 or ORSO42G5 devices for

generic cell-based backplanes.

CML I/Os

SONET

Alignment

FIFO Micro-

processor

Interface

and

Registers

CML I/Os

User-Configurable I/Os

4k x 36

Dual-Port

RAM

System Bus 40-bits

@ 156MHz

Tx FIFO

OPC

Cell

Insert

IPC

Cell

Extraction

ORCA Series 4 FPGA Gates

8 Full Duplex Channels Each at 2.7 Gbits/sec

32-bits

@ 78MHz

4k x 36

Dual-Port

RAM

Pseudo-SONET Rx Block

Framer, TOH Extraction,

Descrambler

Pseudo-SONET Tx Block

TOH Insertion, Scrambler

40-bits

@ 156MHz 32-bits

@ 78MHz

Note: The ORSO42G5 provides four SERDES channels.

ORCA ORSO82G5 and ORSO42G5 Attributes

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

Embedded Core Features

■FIFOs optionally align incoming data across groups

of two or four channels. The ORSO82G5 can also

align across 8 channels.

■In-band management through transport overhead

insertion and extraction. Options to insert SONET

TOH bytes or have them automatically inserted with

default values.

■Programmable enable of SONET scrambler/

descrambler.

■Two 4K x 36 dual-port RAMs with access to the

programmable logic.

■Optional bypass of SONET frames for raw data

interface to the FPGA logic.

■Optional Cell Mode available that uses SONET for

physical layer and cells inserted as payload.

■Multiple fixed-length cell payload sizes available (64,

68, 72 or 80 bytes).

■Cell generation and insertion into payload on Tx.

■Cell extraction and error checking on Rx.

■Automatic idle cell generation and deletion for rate

matching

■No knowledge of SONET/SDH needed in generic

applications. Simply supply data (125 MHz – 168.75

MHz clock) and an optional frame pulse.

■The ORSO82G5 provides an embedded eight-channel

HSI core running at 2.7 Gbps serial bandwidth per

channel for a total chip bandwidth of >20 Gbps (full

duplex).

■The ORSO42G5 provides an embedded four-channel

HSI core running at 2.7 Gbps serial bandwidth per

channel >10 Gbps bandwidth (full duplex).

■Error-free operation demonstrated at 2.7 Gbps across

40” of FR-4 backplane and two connectors.

■Transmit pre-emphasis (programmable) for improved

receive data eye opening.

■High-speed SERDES programmable serial data rates

from 600 Mbits/s to 2.7 Gbps.

FPGA PFU EBR FPGA Max

Usable RAM RAM User FPGA I/O SERDES Data Rate

Device Gates PFUs LUTs Registers Bits Bits I/O Package Compatibility Channels per Channel

ORSO82G5 333 - 643K 1,296 10,368 12,780 277K 111K 372 680PBGAM 1.5/1.8/2.5/3.3V 8 2.7 Gbps

ORSO42G5 333 - 643K 1,296 10,368 12,780 277K 111K 204 484PBGAM 1.5/1.8/2.5/3.3V 4 2.7 Gbps

The ORSO82G5 FPSC is ideal for driving backplanes in

SONET-based systems. The device provides 8 channels

of 2.7 Gbits/s serial bandwidth to drive across the

backplane. The programmable gates on the ORSO82G5

allow for flexible interfaces to the framer and cross-

connect devices. The ORSO42G5 provides the same

capability, however without redundancy.

ORCA ORSO82G5 Application –

Backplane Driver for Grooming Switch

Redundant

Main

Redundant

SONET

Framer

Backplane

Main

Cross

Connect

ORCA

ORSO82G5

Backplane

Transceiver

ORCA

ORSO82G5

Backplane

Transceiver

Optional

ORCA ORT8850

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

Key Features and Benefits

■High Performance ORCA Series 4 FPGA Gates:

• Internal performance of > 250 MHz.

• Up to 600K usable system gates (with ORT8850H).

• 1.5 V operation (30% less power than 1.8 V operation)

• Comprehensive I/O selections including LVTTL,

LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bused-LVDS, and LVPECL.

■Ease of Design

• Supported by ORCA Foundry 2001 design software

• Complete ORT8850 design kit supplies simulation

models for embedded core, configuration tool, and

integrates with ORCA Foundry 2001

Lattice has developed a solution for designers who need the

many advantages of FPGA-based design implementation,

coupled with high-speed serial backplane data transfer.

Built on the ORCA® Series 4 reconfigurable embedded

system-on-a-chip (SoC) architecture, the ORT8850 family is

made up of backplane transceivers containing eight

channels, each operating at up to 850 Mbits/s (6.8 Gbits/s

when all eight channels are used) full-duplex synchronous

interface, with built-in clock and data recovery (CDR) in

standard-cell logic, along with up to 600K usable FPGA

system gates.

The ORT8850 family offers a clockless high-speed interface

for inter-device communication, on a board or across a

backplane. The built-in clock recovery of the ORT8850

allows higher system performance, easier- to-design clock

domains in a multiboard system, and fewer signals on the

backplane. Network designers will also benefit from the

backplane transceiver as a network termination device. The

backplane transceiver offers SONET scrambling/

descrambling of data and streamlined SONET framing,

pointer moving, and transport overhead handling, plus the

programmable logic to terminate the network into

proprietary systems. For non-SONET applications, all

SONET functionality is hidden from the user and no prior

networking knowledge is required.

8-Channel High-Speed Serial Backplane Driver

ORCA ORT8850 Block Diagram

Also included on the device are three full-duplex, high-

speed parallel interfaces, consisting of 8-bit data, control

(such as start-of-cell), and clock. The interface delivers

double data rate (DDR) data at rates up to 311 MHz (622

Mbits/s per pin), and converts this data internal to the

device into 32-bit wide data running at half rate on one

clock edge. Functions such as centering the transmit clock

in the transmit data eye are done automatically by the

interface. Applications delivered by this interface include a

parallel backplane interface similar to the RapidIO packet-

based interface.

Low-Power LVDS I/Os

Clock & Data

Recovery

User-Configurable I/Os

Byte-

Wide

Byte-

Wide

Data

ORCA Series 4 FPGA

Up to 600K Gates

Selectable High-Speed Data Rates – 8X 155/212/622/850 Mbits/sec

Pseudo-SONET

Framer

311 MHz

DDR

Interface

311 MHz

DDR

Interface

311 MHz

DDR

Interface

ORCA ORT8850 Attributes

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

ORT8850 Application – 4 Gbits/sec

Serial Backplane for Switching

• SERDES operates at up to 850 Mbits/sec. With

one ORT8850 on port-card and one on switch-

card, 4 Gbits/sec throughput achieved

• 850 Mbits/sec with SONET scrambling (3.3%

overhead) allows > 800 Mbits/sec raw data

transfer

• Packet-Over-SONET (POS) or RapidIO-like

interface to Network Processor on port card

Usable PFU EBR Available User I/O I/O SERDES Maximum

Device Gates PFUs LUTs Registers RAM Bits RAM Bits 352PBGA 680PBGAM Compatibility PLLs Channels Data Rate

ORT8850L

360-470K 624 4,992 6,504 154K 74K 161 278 1.8 / 2.5 / 3.3V 4 8 850 Mbits/sec

ORT8850H

530-600K 2,024 16,192 19,824 406K 147K N/A 297 1.8 / 2.5 / 3.3V 4 8 850 Mbits/sec

Protect Switch Fabric

Work Switch Fabric

Protect Port Card

Framer

Network

Processor

Backplane

850Mb

LVDS Links

POS

Work Port Card

Switch

Device

ORCA

ORT8850

850 MBits/sec

Backplane

Transceiver

ORCA

ORT8850

850 MBits/sec

Backplane

Transceiver

Key Features and Benefits (cont.)

■Easy System Integration

• Supports wide range of SONET-based backplane

applications as well as generic data moving for high-

speed backplane data transfer. No knowledge of

SONET/SDH needed in generic applications: simply

supply data, 63 MHz-106 MHz clock, and a frame

pulse.

• High-speed interface (HSI) function for clock/data

recovery serial backplane data transfer without

external clocks.

• Eight-channel HSI function provides 850 Mbits/s serial

interface per channel for a total chip bandwidth of

6.8 Gbits/s (full duplex). Rates from 126 Mbits/s to

850 Mbits/s are supported directly (lower rates directly

supported through decimation and interpolation).

• Powerdown option of HSI receiver on a per-channel

basis.

• SONET scrambler/descrambler.

• Three full-duplex, double data rate (DDR) I/O groups

include 8-bit data, one control, and one clock. Each

interface is implemented with LVDS I/Os that include

on-board termination to allow long-haul driving of

backplanes, such as those similar to the industry

standard RapidIO interface.

• Redundant outputs and multiplexed redundant inputs

for CDR I/Os allow implementation of eight channels

with redundancy on a single device.

• On-chip, phase-lock loop (PLL) clock meets B jitter

tolerance specification of ITU-T recommendation

G.958.

• FIFOs align incoming data across all eight channels

(two groups of four channels or four groups of two

channels). Optional ability to bypass alignment FIFOs.

• 1 + 1 protection supports STS-12/STS-48 redundancy

by either software or hardware control for protection

switching applications. STS-192 and above rates are

supported through multiple devices.

Instant-on

Non-Volatile &

Reprogrammable

ispXPGA

IN-SYSTEM PROGRAMMABLE GATE ARRAY

Key Features and Benefits

■Non-Volatile, Infinitely Reconfigurable

•Power-up in Microseconds via On-Chip E2 Cells for

Instant-on Usage

•Reconfigure SRAM-based Logic In-System

•In-System Programmable

•No External Configuration Memory

■System-Level Integration

•139K to 1.25M System Gates

•Up to 496 I/Os

•Up to 414Kb Embedded Memory

■High Performance Logic Blocks (PFUs)

■Block and Distributed Memory

■Variable-Length-Interconnect™ Routing

■sysCLOCK™ PLLs for Clock Management

■sysIO™ for High Performance Interfacing

■sysHSI™ for 850Mbps Serial Communications

■1.8V, 2.5V, and 3.3V Operation

The World’s First FPGA to Offer

Non-Volatility and Reconfigurability

The ispXPGA™ family of devices allows the creation of

high-performance

logic designs that

are both non-volatile

and infinitely re-

configurable. Other

FPGA solutions force

a compromise, being

either re-

programmable, or

reconfigurable, or

non-volatile. This

family offers all of these

capabilities with a mainstream architecture containing the

features required for today’s system-level design. We call

this concept ispXP™, for eXpanded Programmability.

ispXPGA Programming / Configuration

•Auto-configure at Power-up in Microseconds

•Reconfigure In-System

•Reprogram During System Operation

•Configure from On-Chip E2 or CPU

•Set Security Bits to Prevent Readback

•No External Configuration Memory

•Totally Secure from Bit-Stream Snooping

Non-Volatile Infinitely-Reconfigurable Instant-On FPGAs

System Logic Block Distributed sysHSI™ User

Family Member Gates PFUs LUT-4 FFs RAM RAM Channels I/O Vcc Packaging Body Size

ispXPGA 125 139K 484 1936 3.8K 92K 30K 4 160 1.8, 2.5, 3.3V 256 fpBGA 17x17mm

176 516 fpBGA* 31x31mm

ispXPGA 200 210K 676 2704 5.4K 111K 43K 8 160 1.8, 2.5, 3.3V 256 fpBGA 17x17mm

208 516 fpBGA* 31x31mm

ispXPGA 500 476K 1764 7056 14.1K 184K 112K 12 336 1.8, 2.5, 3.3V 516 fpBGA* 31x31mm

336 900 fpBGA 31x31mm

ispXPGA 1200 1.25M 3844 15376 30.8K 414K 246K 20 496 1.8, 2.5, 3.3V 680 fpSBGA* 40x40mm

496 900 fpBGA 31x31mm

* Thermally enhanced

ispXPGA Family

Non-Volatile

Instant-On

Infinitely

Reconfigurable

sysHSI BlocksysHSI Block

sysIOsysIO

SERDESSERDES

LVDS

PLL

LVDS

PLL

Clock RecoveryClock Recovery

TXD_A

SOUT_A

SOUT_B

SIN_A

SIN_B

SS_CLKOUT

SS_CLKIN

TXD_B

RXD_A

RXD_B

RECCLK_A

RECCLK_B

REFCLK

PIC

Routing

Pool

SERDESSERDES

Clock RecoveryClock Recovery

PIC

Direct PFU

DECA (40)

Double (32)

Long (8)

Global Lines (5)

Direct + Feedback (14 + 4)

PFU PFU PFU

Input

Mux

put

Inp

Input

Mux

Input

Mux

PFU

Input

Mux

Input

Mux

Input

Mux

Input

Mux

PFU

Input

Mux

Input

Mux

Input

Mux

Input

Mux

PFU

Input

Mux

Input

Mux

Input

Mux

Input

Mux

CLE 0CLE 0 CSE 0CSE 0

LUT-4LUT-4 FFFF

Carry

Logic

Carry

Logic FFFF

5522To

Routing

From

Routing

From

Routing COUT(r,c)

CLE 1CLE 1 CSE 1CSE 1

LUT-4LUT-4 FFFF

Carry

Logic

Carry

Logic FFFF

5522To

Routing

From

Routing

CLE 2CLE 2 CSE 2CSE 2

LUT-4LUT-4 FFFF

Carry

Logic

Carry

Logic FFFF

5522To

Routing

From

Routing

CLE 3CLE 3 CSE 3CSE 3

LUT-4LUT-4 FFFF

Carry

Logic

Carry

Logic FFFF

5522To

Routing

From

Routing

Wide Logic GeneratorWide Logic Generator

Control

Logic

Control

Logic

Programmable Function Unit (PFU)

• Dedicated Arithmetic Logic

• Up to 20-Input Logic Functions

• Dual Flip Flop per LUT-4 for Pipelining

• 64 Bits of Distributed Memory

- Single-Port, Dual-Port or Shift Register

sysHSI Blocks

• Dedicated High-Speed Interface (HSI) Circuits

• Built-in Clock Data Recovery (CDR) and

Serialization and De-serialization (SERDES)

• 850 Megabit LVDS, Up to 20 Channels per Device

• Can be utilized separately to allow multiple

reference clocks and data rates

• 8B/10B and 10B/12B Coding

• Up to 34 Gbps

Optimized Routing Resources

• Segmented Routing for Superior Fitability and Performance

• Intra-PFU Feedback

• Direct, Double, Deca and Long Connects

ispXPGA Block Diagram

ispXPGA Ar chitectur e

sysMEM Block

4Kb RAM, FIFO or ROM

sysMEM Block

4Kb RAM, FIFO or ROM

ADDR_AADDR_A

CLK_ACLK_A

Clock Enable AClock Enable A

Write Enable AWrite Enable A

Output Enable AOutput Enable A

DATA_ADATA_A

ADDR_BADDR_B

CLK_BCLK_B

Clock Enable BClock Enable B

Write Enable BWrite Enable B

Output Enable BOutput Enable B

DATA_BDATA_B

Chip to Memory

SSTL2 I and II

SSTL3 I and II

HSTL I

HSTL III

HSTL IV

CTT

↓

SDRAM

DDR SRAM

QDR SRAM

ZBT SRAM

Chip to Memory

SSTL2 I and II

SSTL3 I and II

HSTL I

HSTL III

HSTL IV

CTT

↓

SDRAM

DDR SRAM

QDR SRAM

ZBT SRAM

Chip to Chip

LVTTL

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

Prog. Impedance

Chip to Chip

LVTTL

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

Prog. Impedance

Chip to Backplane

PCI33_3

PCI66_3

PCI-X

GTL+

AGP

Bus-LVDS

LVDS

LVPECL

Chip to Backplane

PCI33_3

PCI66_3

PCI-X

GTL+

AGP

Bus-LVDS

LVDS

LVPECL

Clock_Net

SEC_OUT

CLK_OUT

PLL_LOCK

PLL

Input Clock

(M) Divider

÷1-32

Feedback

Divider (N)

÷1-32

Secondary

Clock (K)

Divider

÷2, 4, 8, 16, 32

CLK_IN

10-320MHz 10-320MHz

10-320

MHz

0 to ±2.8ns

in 325ps Steps

100-400

MHz

10-320

MHz

PLL_RST

PLL_FBK

Post-scalar

(V) Divider

÷1, 2, 4, 8,

16, 32, 64

Programmable

+Delay

Programmable

–Delay

sysIOsysIO

Input

Routing

Pool

Input

Routing

Pool

Output

Routing

Pool

Output

Routing

Pool

OE0OE0

OE1OE1

Programmable

I/O (PIO) 0

Programmable

I/O (PIO) 0

Programmable

I/O Cell (PIC)

Programmable

I/O Cell (PIC)

Programmable

I/O (PIO) 1

Programmable

I/O (PIO) 1

sysIOsysIO

Flexible I/O Cells

• Separate Input, Output and OE Registers

• Flexible Set, Reset, Clock Enable and Polarity

• Input Register Offers Delay Option for Zero t

HOLD

• Programmable Output Slew Rate sysIO High Speed Interface

• Supports Multiple Interface Standards

• Programmable Drive Strength for Series Termination

• Programmable Bus Maintenance

• Multiple Banks for Easy Control

sysCLOCK Phase Locked Loops (PLL)

• 8 PLLs per Device

- Plus 8 Global Clocks

- Plus 8 Low-Skew Clock Nets

• Clock Frequency Synthesis

• Multiple Clock Signal Generation

• Device or Board Clock Alignment

• 10 - 320MHz, t

LOCK

25 µs

• Jitter: Cycle-to-Cycle ±100ps; Period ±150ps; Input ±300ps

sysMEM™ Embedded RAM Blocks

• Up to 414Kb of Dedicated Memory per ispXPGA

• Configurable as Single- or Dual-Port RAM, FIFO or ROM

• 512x9 Bits or 256x18 Bits

• Cascadable Width and Depth

• Sub-3ns Access Times

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

ispLEVER™ Design Software

Lattice’s ispLEVER is a new generation of PLD design tool

equipped to provide a complete system for FPSC, FPGA,

ispXPLD™, CPLD, ispGDX® and SPLD design. ispLEVER

includes a fully integrated, push-button design environment

and advanced features for interactive design optimization

and debug.

Features

■Fully Integrated Synthesis and RTL and Timing

Simulation Tools

■Complete Design Flow for All In-System

Programmable (ISP™) Lattice Device Families

■Advanced Timing-Driven Placement and Routing

■IP Manager and Module Generator

■Fast, Efficient Run Times and Competitive Device

Perfor mance and Utilization

■Supported by Libraries from Leading CAE Vendors

•Aldec

•Cadence

• Innoveda

•Mentor Graphics

•Synopsys

•Synplicity

■Windows® and UNIX® Solutions

ispLEVER Design Software Flow Chart

Logic Simulation

and

Timing Analysis

Design

Synthesis

HDL Capture

and Simulation

LatticeLattice

Timing-Driven

Place and

Route

Function

Compilers

and IP

Packing

Timing Analyzer

Delay File

Lattice OEM EDA Partners:

• Mentor Graphics

Leonardo Spectrum

• Mentor Graphics ModelSim

• Synplicity

Synplify

Library

Design

Database

ispVM™

System

Floor Planner

EDA Partner

ispXPGA Select Perfor mance

TA = 25º C; VCC = 1.8V

Function Speed

4-Input LUT Delay 440ps

Synchronous Counter 8-bit 334MHz

Loadable Up/Dn Carry-Ripple Counter 64-bit 156MHz

Carry-Ripple Adder 64-bit 232MHz

Multiplexer 64:1 237MHz

De-Multiplexer 1:64 371MHz

Shift Reg Up/Dn, Circular Shift 64-bit 315MHz

Barrel Shifter 64-bit 184MHz

PLL Frequency Min 10 MHz

Max 320 MHz

LVDS with Clock Recovery Max 850Mbit

Fast I/O

ispGDX2

IN-SYSTEM PROGRAMMABLE INTERFACING & SWITCHING

Key Features and Benefits

■High Perfor mance Bus Switching

• 13.6 Gbps (SERDES), 38 Gbps (without SERDES)*

• Up to 16 (15X10) FIFOs for data buffering

• High-speed Performance: fMAX = 330 MHz, tPD = 3.0ns

• I/O intensive: 64 to 256 I/Os

• Expanded MUX capability up to 188:1 MUX

■sysCLOCK PLL

• Frequency synthesis and skew management

• Clock shifting, multiply and divide capability

• Jitter as low as 150ps

• Up to four PLLs

■sysIO Interfacing

• LVCMOS 1.8, 2.5, 3.3 and LVTTL support

• SSTL 2/3 Class I and II support

• HSTL Class I, III and IV support

• GTL+, PCI-X support

• LVPECL, LVDS and Bus LVDS support

• Hot socketing

■Up to 16 Channels of 850Mbps sysHSI SERDES

• Serializer/de-serializer (SERDES) included

•Built-in Clock Data Recovery (CDR)

•10B/12B support

- Encoding / decoding

- Sync pattern support

- Symbol alignment

•8B/10B support

- Sync pattern support

- Symbol alignment

•Source synchronous capability

■Flexible Programming & Testing

• IEEE 1532 compliant ISP

• Boundary Scan test through IEEE 1149.1 Interface

Fast Serial I/O and High Bandwidth

Bus Interface

The ispGDX2™ family is Lattice’s next generation in-system

programmable (ISPTM) high performance digital crosspoint

switch for high-speed bus switching and interfacing with

bandwidth of up to 38Gbps. This family combines a

flexible switching architecture with advanced high speed

serial I/O (sysHSITM blocks), sysCLOCKTM PLLs, and

sysIOTM interfaces to meet the needs of today’s high-speed

systems. A multiplexer based architecture and on-chip

control logic facilitate the high performance implementation

of common switching functions.

ispGDX2 devices are provided in 3.3V, 2.5V or 1.8V core

voltage versions and can be programmed in-system via an

IEEE 1149.1 interface that is compliant with the IEEE 1532

standard. Voltages required for the I/O buffers are

independent of the core voltage supply. This further

enhances the design flexibility of the family. Typical

applications for the ispGDX2 include multi-port multi-

processor interfaces, serial backplanes, wide data and

address bus multiplexing, programmable control signal

routing and programmable bus interfaces.

High Perfor mance Digital Crosspoint Switch

ispGDX2-64 Block Diagram

* Bandwidth assumes 50% of I/Os are inputs and 50% are outputs.

sHSI

lock

ERDE

SERDES

FIFO FIFO

DX Bloc

GDX Block

PLL

Global Routing Pool

sysHSI

Bloc

ERDE

SERDES

FIFO FIFO

DX Bloc

GDX Block

sysIO Bloc

int

ace

standard su

sHSI Bloc

–

two du

lex

850 Mb

s SERDE

sCLOCK PL

FIF

for bufferin

data

streams

(

15x10 bits

)

DX Bl

ock

includes control

ic and data multiplexer

Flexible Routin

timized

for bus switchin

sysIO Block sysIO Block

ispGDX2 Architecture

GDX Block

•4 to 16 GDX Blocks per device

•16 4:1 MUX and Register Blocks (MRBs) optimized for

bus switching

•Separate registers for input, output, and output enable

•32 input programmable control array provides block-

level MUX select, clock, set/reset and output enable

sysHSI – High Speed Interface

•2 to 8 sysHSI Blocks per device

•Each sysHSI includes two 850 Mbps duplex SERDES

(with CDR)

•Multiple sysHSI Blocks can be combined for source

synchronous operation

sysCLOCK PLL for Timing Control

•2 to 4 sysCLOCK PLLs per device

•10 to 320 MHz PLL operation

•PLL with period jitter of ±150ps

Clock Net

PLL

(n)

Input

Clock (M)

Divider

÷ 1 to 32

Feedback

Divider (N)

X 1 to 32

Clock (K)

Divider

2,4,8,16,32

GCLK_IN

PLL_RST

PLL_FBK

PLL_Lock

CLK_Out

Adjacent

PLL

From

Adjacent

PLL

Post-scalar

(V) Divider

2,4,8,16,32

Programmable

+Delay

Programmable

–Delay

sysHSI Block Core Logic

CSPLL

SS_CLKOUT

SS_CLKIN

INITIALIZATION

Shared Source

Synchronous pins

drive multiple

sysHSI blocks

LOCK

TXD

RXD

RECCLK

Serializer

SERDES

SOUT

SIN

FIFO

De-serializer

with CDR

FIFO

Reference clocks

from CLK (0:3)

GDX

Block

GDX

Block

GRP

Serializer

De-serializer

with CDR

TXD

RXD

RECCLK

SOUT

SIN

SERDES

OUT

GDX Block sysIO

Bank

32 bits Control MUX

Select

16 bits

4 bits

Control Array

Nibble 3

MRBs 12-15

Nibble 2

MRBs 8-11

Nibble 1

MRBs 4-7

Nibble 0

Global

Routing

Pool

MUX and Register

Block (MRB)

MUX and Register

Block (MRB)

MUX and Register

Block (MRB)

MUX and Register

Block (MRB)

sysIO Interfaces

•On-board sysIO Banks allow ispGDX2 devices to

support a wide range of I/O standards

•8 sysIO Banks per ispGDX2 device

•Each sysIO Bank has its own separate I/O supply

voltage and reference voltage

High-Speed

Backplane

Logic

(Logic, ASICs,

CPU, DSP)

Clock

Chip

High-Speed

SRAM

Synchronous DRAM

SSTL

LVTTL

LVCMOS

CTT

LVTTL

LVCMOS

LVDS

BLVDS

GTL+

PCI

PCI-X

AGP

HSTL

LVTTL

LVCMOS

ispGDX2

with sysIO

4X4 Serial High-Speed Switch

The high performance architecture of the ispGDX2 is

perfect for implementing crosspoint switches with multiple

devices. In this application, the ispGDX2 device performs:

• Bi-directional 4X4 serial high-speed switches

• Bus-LVDS enables bigger crosspoint switches with

multiple devices

ispGDX2 Applications

CDR 10

Bits

CDR 10

Bits

CDR 10

Bits

CDR 10

Bits

CDR 10

Bits

32 4X1 MUXes

CDR

Bits

CDR

Bits

CDR

Bits

CDR

Bits

CDR

Channel 0 Out B

Channel 1 Out B

Channel 2 Out B

Channel 3 Out B

Bits

CDR 10

Bits CDR

Bits

CDR 10

Bits CDR

Bits

CDR 10

Bits CDR

Bits

Channel 0 In A

Channel 1 In A

Channel 2 In A

Channel 3 In A

Channel 0 In B

Channel 1 In B

Channel 2 In B

Channel 3 In B

Channel 0 Out A

Channel 1 Out A

Channel 2 Out A

Channel 3 Out A

Graphic Card

ispGDX2

Memory Card

ispGDX2

LVCMOS, SSTL, HSTL, LVDS, GTL+, PCI, Bus-LVDS

CPU Card

ispGDX2

Flexible High-Speed Backplane Driver

The sysIO capability of the ispGDX2 provides flexility in

implementing backplane drivers. In the application below,

the ispGDX2 devices provide the following features:

• Up to 38 Gbps bandwidth per ispGDX2 device

• In-system programmability and JTAG at board edge

Multi-Gigabit Serial Switched Backplane

The ispGDX2 offers a superior solution for signal routing

and switching across backplanes. In the application below,

the ispGDX2 devices provide the following features:

• One part type for implementing high-speed circuits on

both line card and switch board

• Up to 13.6 Gbps bandwidth per ispGDX2

• Easy board side interface using sysIO and sysCLOCK

features

Line Card

ispGDX2

Line Card

ispGDX2

Line Card

ispGDX2

Switch

Control

Card

ispGDX2

Flexible I/O Buffer

The ispGDX2 provides a flexible method to integrate

multiple buffers into a single device. ispGDX2 devices

provide:

• Support for multiple standards

• In-system programmability and JTAG testability

ispGDX2

Bus-LVDS

LVDS

LVCMOS

HSTL

SSTL

PCI

GTL+

Bus-LVDS

LVDS

LVCMOS

HSTL

SSTL

PCI

GTL+

ispGDX2 Family Attributes

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

ispGDX2 Advanced Packaging

Feature ispGDX2-64* ispGDX2-128* ispGDX2-256*

I/Os

64 128 256

GDX Blocks

4 8 16

3.0 ns 3.0 ns 3.5 ns

2.0 ns 2.0 ns 2.0 ns

3.1 ns 3.1 ns 3.2 ns

MAX

330 MHz 330 MHz 300 MHz

Max. Bandwidth (SERDES)

3.5 Gbps 7.0 Gbps 13.6 Gbps

Max. Bandwidth (without SERDES)

11 Gbps 21 Gbps 38 Gbps

sysHSI Channels

4 8 16

Bus LVDS (Pairs)

32 64 128

PLLs

2 2 4

Package

100-Ball fpBGA 208-Ball fpBGA 484-Ball fpBGA

Dimensions refer to package body size.

*Preliminary Information

ORCA ORT82G5

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

Evaluate 3.7Gbps SERDES + FPGA Quickly and Easily

Evaluation

Board

ORCA

ORT82G5

SERDES A

SERDES B

CHAR I/O MPI INT

GP I/O

HSI

Mode

Cont

Serial

Prog

HSI JTAG

MPI

Connectors

VSS

Connectors

Making the Right Choice…

Choosing the right device to drive 3.7Gbits/s

data over your backplane can be a critical

decision, but evaluating your options

shouldn’t be complicated. Lattice has created

the ORCA® ORT82G5 Evaluation Board so

you can efficiently test the characteristics of a

3.7Gbits/s data stream generated by Lattice’s

ORT82G5 FPSC.

Examine Features Such as:

■ Field Programmable System Chip

(FPSC) flexibility and features

■ORT82G5 SERDES functionality and

performance

■Programmable I/O capabilities

■Output strength and clarity

■Compliance to data transmission

standards, from fiber channel to

10Gbit Ethernet (XAUI)

Working on an ORT82G5

Application?

Use the ORT82G5 Evaluation Board to help

develop your application in an established

and flexible environment. Download your

design to the ORT82G5 for instant feedback.

Full Feature Set

■Push-button switches assert/de-assert the logic levels

on the FPGA PRGMN, PRESET, and the SERDES

reset.

■Interconnect test points for SERDES characterization.

■SMA connectors for differential inputs to the

ORT82G5’s four on-chip PLLs.

■Independent power supplies for the board and

SERDES I/O.

■Downloadable programming bit streams are available

from www.latticesemi.com for testing specific

functions of the ORT82G5.

ORT82G5 Evaluation Board Block Diagram

Programming and JTAG

Download your design to the ORT82G5. Or, use

board-specific evaluation bit streams.

SERDES I/O SMA Connectors

Dual high-speed 8-bit SERDES

channels accessible through

quiet SMA connectors.

Microprocessor Interface

Send or receive data through MC860

connectors.

FPSC I/O Access

Connect to the ORT82G5’s programmable

I/O through standard PCB headers.

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

About the ORCA ORT82G5…

Lattice’s ORT82G5 is a Field Programmable System Chip is

based on the ORCA Series 4 architecture. The ORT82G5

integrates eight 3.7Gbits/s backplane transceiver channels

and a full-duplex synchronous interface with built-in Clock

and Data Recovery with a flexible FPGA logic core.

■Eight channels at 1.25 to 3.7 Gbits/s, exceeds XAUI

specifications for 10Gbits/s Ethernet applications

■Optional 8b/10b encoding/decoding support on all

channels

■Multi-channel alignment FIFOs available in 8b/10b

mode

■More than 400K of usable FPGA gates, internal

perfor mance of >250MHz

■Four programmable PLLs

■Two extra embedded 4Kx36 dual-port RAM blocks

■Programmable I/O with programmable drive and

slew rate control supports LVTTL, LVCMOS, GTL,

GTL+, PECL, SSTL/3, HSTL, ZBT, DDR, LVDS,

BLVDS and LVPECL

■372 programmable user I/O

See www.latticesemi.com for complete specifications of the

ORT82G5

CML I/Os

Quad Channel

MUX/deMUX Micro-

processor

Interface

and

Registers

CML I/Os

Quad Channel

MUX/deMUX

User-Configurable I/Os

4K x 36

Dual-Port

RAM

System Bus Parallel Data

Parallel Data

2:1 Data

Selector

Multi-Chan.

Alignment

+ FIFO

2:1 Data

Selector

Multi-Chan.

Alignment

+ FIFO

ORCA Series 4 FPGA Gates

Selectable High-Speed Data Rates – 1.25 / 2.5 / 3.125 Gbits/sec

Clock Clock

4K x 36

Dual-Port

RAM

Quad Serializer-DeSerializer

with 8B/10B Encoder/Decoder Quad Serializer-DeSerializer

with 8B/10B Encoder/Decoder

ORCA ORT82G5 Block Diagram

■Included with the ORT82G5 Evaluation Board:

•ORT82G5-2BM680 device

•ORCA download cable

•Board schematic and bill of materials

■Available on www.latticesemi.com:

•ORT82G5 Eval Board User Manual and Tutorial

•IBIS and HSPICE models, and BSDL files

•Schematic and Gerber files

•Evaluation bit streams

ispLEVER™ Development Tools

ispLEVER is an integrated software

sysem for the development of all

Lattice programmable logic devices,

including the ORT82G5. The

ispLEVER software incorporates

ASIC design techniques and FPGA

development methodologies that

meet today’s high-speed design

demands.

Clear Your Eyes With the ORT82G5!

With data wavelengths now shorter than your backplane,

clean and reliable signals are crucial. The ORT82G5

provides I/O capabilities that exceed today’s tight standards.

The ORT82G5 also features programmable pre-emphasis

for transmission of reliable low-jitter SERDES signals, giving

you more flexibility in applications utilizing Clock and Data

Recovery (CDR).

With the ORT82G5 Evaluation board, you can measure the

I/O performance of the ORT82G5 in an environment you

control. The signal to the left is the actual data-eye of a

3.7Gbps SERDES transmission across 26 inches of FR-4

backplane, generated by the ORT82G5 using 25% pre-

emphasis.

ORCA ORT8850

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

8 x 850Mbits/s SERDES Plus up to 899K FPGA Gates on One Chip!

Evaluation

Board

Making the Right Choice

Choosing the right backplane transceiver

solution is an important investment

decision, but evaluating your options

shouldn’t be complicated. Lattice has

created the ORCA® ORT8850 Evaluation

Board so you can efficiently test the

performance of a completed PCB design

based on the ORT8850 Field

Programmable System Chip (FPSC)

architecture.

Examine Features Such as:

■FPSC flexibility

■ORT8850 perfor mance and features

■Programmable I/O capabilities

■Output strength and clarity

Working on an ORT8850

Application?

Use the ORT8850 Evaluation Board to

help develop your customized ORT8850

solution in an established and flexible

environment. Download your design to

the ORT8850 for instant feedback.

ORCA

ORT8850

50Ω SMA

PLL

Available Device I/O: 180

MPC860

Bus

VCXO

77.76 MHz

66 MHz

15 MHz

Switch

FPGA Control & Test

Extra I/Os LVDS I/Os

HSI

ORT8850 Evaluation Board Block Diagram Full Feature Set

■180 of the ORT8850H’s I/Os are accessible on the

board. These include 32 HSI (LVDS) I/Os and other

I/Os directly from up to 899K FPGA system gates.

■Includes a regulated power supply for easy set-up.

■Downloadable programming bit streams are available

from www.latticesemi.com for testing specific

functions of the ORT8850.

Micro

rocessor Interfaces

onnect to Power-P

third-part

development daughte

cards via M

860 connectors

VDD I

O Contro

Controls six I/O banks at 3.3V

2.5

or 1.8V. The ORT8850 su

orts 1

O standards

FPSC I

O Access

onnect to the

RT8850

’

s pro

rammable

I/O throu

h standard PCB headers. Chec

Tx/Rx data throu

h microstri

connectors.

Programming and JTA

Download

our design to the ORT8850

Or, use board-s

ecific evaluation bi

streams available from Lattice

PLL Clock In

uts

Send differential clock si

nals strai

to the

RT8850

’

s four PLLs. Or

use the

on-board 77.76MHz V

and 66MH

and 15MHz oscillators

www.latticesemi.com

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

ORCA ORT8850 Block Diagram

ispLEVER™ Development Tools

ispLEVER is an integrated software

sysem for the development of all

Lattice programmable logic devices,

including the ORT8850. The

ispLEVER software incorporates

ASIC design techniques and FPGA

development methodologies that

meet today’s high-speed design

demands.

■Included with the ORT8850 Evaluation Board:

•ORT8850H-BM680 device

•ORCA Download Cable

•Power supply

•Board schematic and bill of materials

■Available on www.latticesemi.com:

•ORT8850 Eval Board User Manual and Tutorial

•IBIS and HSPICE Models, and BSDL files

•Schematic and Gerber files

•Evaluation bit streams

About the ORCA ORT8850...

Lattice’s ORT8850 is a Field Programmable System Chip

based on the ORCA Series 4 Architecture. The ORT8850

integrates eight 850Mbits/s backplane transceiver channels

with a flexible FPGA logic core. Features of the ORT8850

include:

■Up to 899K of usable FPGA system gates and 147Kb

Embedded RAM (ORT8850H)

■Internal per formance of >250MHz

■LVDS I/Os compliant with EIA-644

■Multi-channel alignment FIFOs available

■SONET scrambler/descrambler

■Four programmable PLLs

■297 programmable user I/O (ORT8850H)

See www.latticesemi.com for complete specifications of the

ORT8850

Low-Power LVDS I/Os

Clock & Data

Recovery

User-Configurable I/Os

Byte-Wide

Data

Byte-Wide

Data

ORCA Series 4 FPGA

Up to 899K FPGA System Gates

Selectable High-Speed Data Rates – 8X 155/212/622/850 Mbits/sec

Pseudo-SONET

Framer

Sharpen Your Focus With the Eye of the

ORT8850

Clean data transmission has always been important, but

with data wavelengths getting shorter than your backplane,

it’s crucial! We’ve focused our engineering efforts on the

ORT8850 I/O structure to provide high-quality data

transmission exceeding today’s tight standards.

With the ORT8850 Evaluation board, you can measure the

I/O performance of the ORT8850 in an environment you

control. The signal to the left is an actual data-eye of a PRBS

pattern generated by the ORT8850’s LVDS I/Os at

880Mbits/sec.

23 www.latticesemi.com

September 2002

Applications Support

1-800-LATTICE (528-8423)

(408) 826-6002

techsupport@latticesemi.com

OC-48 Multiservice CardOC-48 Multiservice Card

OC-48c Port Card (ATM only)OC-48c Port Card (ATM only)

SONET/SDH

Add/Drop

Chip Set

ATM

Layer

Processor

ORCA

ORT82G5

16 x 3.125Gbps

Backplane

Parallel Interface

SONET/SDH

Add/Drop

Chip Set

Network

Processor ORCA

ORT82G5

PL-3

Switch

Fabric

Chip set

Terabit Switch FabricTerabit Switch Fabric

ORT82G5 in Multi-Service Switching and Routing

2.5Gb CSIX Switch Fabric2.5Gb CSIX Switch Fabric

Gigabit Ethernet TerminationGigabit Ethernet Termination

ORCA

FPGA

CSIX

Interposer

Network

Processor

10/100/Gb

MAC

10/100/Gb

PHY

Terabit Switch FabricTerabit Switch Fabric

Network

Processor

+ Traffic

Manager

SONET/SDH

Add/Drop

Chip Set

OC-48 Port Card (Protocol Independent) OC-48 Port Card (Protocol Independent)

Protocol-

Independent

Switch

Fabric

16 x 3.125Gbps

Backplane

PL-3FIFO

I/F

PL-3 ORCA

ORT82G5

High-Speed

Backplane

10 Gigabit Serial LAN10 Gigabit Serial LAN

10 Gb

MAC

XAUI

Backplane

XENPAK

70-Pin 10Gb

Transponder XGMII

Protection

ORCA

ORT82G5

Network

Processor ORCA

ORT82G5

10 Gbits/sec

Backplane

Work

OC-48c Port Card (ATM only)OC-48c Port Card (ATM only)

SONET/SDH

Add/Drop

Chip Set

ATM

Layer

Processor

ORCA

ORT82G5

Parallel Interface

CSIX

Fabric

ORCA

ORT82G5

ORT82G5 in Metro Access Applications

ORCA ORT82G5

The World’s Fastest Programmable SERDES Solution!

Applications

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

www.latticesemi.com

pbxgxsip_02

10 Gigabit Ethernet XGXS

Intellectual Property Core

April 2003 Product Brief

Overview

The 10 Gigabit ethernet eXtender Subla yer (XGXS) Intellectual Property (IP) Core enables creation of system solu-

tions for 10 Gigabit Ethernet applications as deﬁned by IEEE 802.3ae. This IP Core targets the programmable

arra y section of the ORCA

ORT82G5 FPSC and provides a bridging function between 10 GbE Media Independent

Interf ace (XGMII) and 10 GbE Attachment Unit Interface (XAUI) de vices . It is implemented as a soft IP core for ﬂex-

ibility.

The XGMII interface block provides an interface to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data

rate, parallel short-reach (typically less than 2 inches) interconnect interface.

XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB

trace on standard FR-4 material. Each XAUI interface is comprised of 4 self-timed 8b10b encoded serial lanes,

each operating at 3.125 Gbits/s.

The IP core from Lattice Semiconductor is provided with all implementation scripts, test benches, and documenta-

tion to allow customers to integrate the functions for 10GbE LAN/WAN applications and also for modiﬁcation of the

core to meet differing application needs.

10 Gigabit Ethernet ORT82G5 and IP Core Features

The embedded portion of the ORT82G5 includes:

• Eight channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding

• Fibre-channel and XAUI compliant lane-by-lane synchronization

• Lane deskew function

• PRBS generator/checker for selftest

•Microprocessor interface programmable via the ORCA Series 4 system bus

The soft XGXS IP core implements the interface functions needed to take data from XAUI lanes to an XGMII inter-

face device (e.g. MAC) and vice-versa. The programmable logic implementation allows for changes to the core to

reﬂect changes in the standards deﬁnition in the future.

The XGMII consists of 4 lanes, labeled [0:3], and 1 clock in both the transmit and receive directions. Each lane is

an 8-bit data path plus a control signal. Double Data Rate (DDR) signaling is used to transfer 312.5 MBytes/s per

lane with a 156.25 MHz clock. The data and control lines are sampled on both the rising and falling edges of the

clock. XGXS’s location in the 10GbE protocol stack is shown in Figure 1 on the following page

Lattice Semiconductor 10 Gigabit Ethernet XGXS Intellectual Property Core

Figure 1. XGXS Location in Protocol Stack

The receiv e path, sho wn in Figure 2, is the data path from the XAUI to the XGMII interf ace. It maps 8b10b decoded

XAUI data to XGMII data and optionally transmits the data off-chip via the 36-bit 156Mhz DDR XGMII interface.

Figure 2. XGXS Receive Path Dataﬂow

The transmit path, shown in Figure 3, is the data path from XGMII to XAUI. The XGXS transmit path maps the 36-

bit DDR XGMII data and control to the 8b10b transmission code. The XGMII data and control are clocked by DDR

registers in the I/O blocks. A slip buffer performs clock compensation between the external clock and the internal

synthesized 156.25 Mhz clock. Data and control read from the buffer are then passed into the idle generation logic.

Upper Layers

MAC Control (Optional)

Media Access Control

Reconciliation

Physical Coding Sublayer

WAN Interface Sublayer

Physical Medium Attachment

Physical Medium Dependent

Medium

XGXS*

XGMII

XAUI

XGMII

XSBI

MDI

XGMII / XAUI

64b / 66b Coding

WAN-Compatible Framing

16-bit Parallel (OIF)

Retime, SerDes, CDR

E / O

XGMII 10G Medium Independent Interface

XGXS XAUI Extended Sublayer

XAUI 10G Attachment Unit Interface

XSBI 10G Sixteen Bit Interface

MDI Medium Dependent Interface

Notes:

1. Adding the WIS makes the WAN PHY

2. * Denotes Optional Sublayer

abcde fghji

00111 1XXX1

KABCD FGHE

C0123 56 74

Properly Aligned Columns

10B8B Decoding

XGXS Mapping

XGXS Receive Function

Lane 1 Lane 2 Lane 3

01234567012345670123456701234567

Octet N Octet N+1 Octet N+2 Octet N+3

MAC Serial Bit Stream

(output)

XAUI Lane 0

RS / XGMII Decoding

Lattice Semiconductor 10 Gigabit Ethernet XGXS Intellectual Property Core

Figure 3. XGXS Transmit Path Dataﬂow

Figure 4. Generator/Checker Interface

Figure 5. Interface with External MAC

abcde fghji

KABCD FGHE

C0123 56 74

8B10B Encoding

XGXS Mapping

XGXS Transmit Function

Lane 1 Lane 2 Lane 3

01234567012345670123456701234567

Octet N Octet N+1 Octet N+2 Octet N+3 MAC Serial Bit Stream

(input)

XAUI Lane 0

RS / XGMII Encoding

HDINN_BA

HDINP_BA

HDINN_BB

HDINP_BB

HDINN_BC

HDINN_BD

HDOUTN_BA

HDOUTP_BA

HDOUTN_BB

HDOUTP_BB

HDOUTN_BC

HDOUTP_BC

HDOUTN_BD

HDOUTP_BD

Rx Lane

Tx Lane

Frame

Capture

Check

Receive

XGXS

ORT82G5

Transmit

XGXS

Frame

Generator

tx_clk

rx_clk

Software Register Interface

(MDIO)

xgmii_ref_clk

REFCLK[N,P]_B Backplane

rx_dat

rx_control

8 bits

tx_dat

tx_control

8 bits

DDR IO

XGMII IO

OUT

xgmii_tx_clk

xgmii_rx_clk

PLL

90o

DDR IO

XAUI Connector

10Gb

Ethernet

MAC

XGXS

XGMII

Transmit

and

Receive

Interface

XGXS

PHY

8B10B

Encode/

Decode,

Byte-

Alignment,

Deskew

36-bit

156.25 MHz

DDR

36-bit

156.25 MHz

DDR

3.125Gbps

ORT82G5 FPSC

XAUI XGMII

Lattice Semiconductor 10 Gigabit Ethernet XGXS Intellectual Property Core

For Ethernet, the idle generation state machine generates the random /A/, /K/ and /R/ characters. The Idle signal /I/

at the XGMII end is mapped to a random sequence of /A/, /R/ and /K/ code groups to reduce radiated emissions

and help designers meet EMI requirements. The /A/ code-groups are included for the purpose of lane alignment

and, to that end, have a guaranteed minimum spacing of 16 code-groups. The /K/ code-groups contain a comma

sequence and are used by the XAUI receive section to establish code-group alignment. The /R/ code-groups are

used for clock-compensation and may be inserted or deleted by the XGXS to accommodate for differences

between transmit and receive clocks.

The ORT82G5 XGXS interfaces to XGMII in one of two ways:

•A built-in 64-bit 156Mhz XGMII CRPAT/CJPAT packet generator/checker (Figure 4).

•A standard 36-bit IO DDR interface (e.g. to a MAC) (Figure 5).

Figure 6. ORCAstra GUI Interface

Using the ORCAstra

control center, a graphical user interface similar to the one shown in Figure 6 performs real

time modiﬁcations and monitoring. In addition to the FPSC speciﬁc functions shown in Figure 6, the GUI has

entries for XGXS speciﬁc registers , such as FIFO threshold, loopback modes control, and push buttons to run spe-

ciﬁc synchronization algorithms. Control over the internal packet generator functions, and monitoring of the internal

packet generator error outputs are also available.

Other Information

Product briefs, data sheets, application notes and other inf ormation on many of the products used in the abov e sys-

tem solutions are available from Lattice Semiconductor. FPSC solutions are also highlighted on the Lattice Semi-

conductor website at: http://www.latticesemi.com.

Ordering Information

Implementing a design in an OR T82G5 requires the ispLEVER™ softw are and an ORT82G5 FPSC Design Kit. For

ordering information, please contact your local Lattice Semiconductor sales representativ e or visit the Lattice Semi-

conductor website.

www.latticesemi.com

tn1027_02

ORT42G5 and ORT82G5 High-Speed

Backplane Measurements

April 2003 Technical Note TN1027

Introduction

The Lattice ORT82G5 FPSC device contains two Quad-SERDES blocks. The Lattice ORT42G5 FPSC device con-

tains one Quad-SERDES block. Each SERDES (SERializer/DESerializer) provides a ser ial high-speed backplane

transceiver interface, operational at data rates up to 3.7 Gbit/s.

This document illustrates SERDES high-speed backplane capabilities, through a series of laboratory tests. The

Tyco HM-Zd Backplane Evaluation system

was used extensively in these tests. Three different conﬁguration

experiments are described:

•Eye-Diagram Experiment I – Shows performance over a standard reference backplane.

•Eye-Diagram Experiment II — Shows performance variations with signal pre-emphasis, board layers and

trace length.

• Data-Rate Experiment — Shows data rate limits measured for 26 and 40 inch FR4 path lengths.

Bit-error rate and eye-diagram measurements are used to evaluate link performance and margins. Error-free per-

formance is observed through various backplane connections and over different operating conditions, for test inter-

vals of several minutes. The effects and beneﬁts of transmitter pre-emphasis and amplitude adjustment are

illustrated. Finally, some general application recommendations are made for high-speed backplane interconnection

design.

Eye-Diagram Experiment I

Eye-diagram signal waveforms observed at the receive end of PCB interconnection paths were recorded. This

measurement displays the effect of various system error contributions on received signal integrity. A series of such

measurements made while driving through the Tyco test backplane

are described in this section.

Test Equipment

– ORT82G5 evaluation board

– Tyco Electronics XAUI backplane with two port cards

– HPE3648A power supplies

– HP8133A clock source

– Temptronic E3648A thermal soaker

– PicoSecond 5575A Bias-T

– Agilent 86100A DCA oscilloscope

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 1. Eye-Diagram Test Setup

Test Setup

Figure 1 shows the test setup used to measure the data eye-openings discussed in this document. The TX signal

comes directly from an ORT82G5 high-speed serial output. A pseudo-random signal pattern generated in the

ORT82G5 was processed through an internal 8B/10B encoder.

Test Setup Parameters

– ORT82G5 680 PBGAM plastic ball grid array (wire-bond), -3 speed grade

– Power Supply = 1.5 V

– Ambient Temperature = 25° C

– Data Pattern = PRBS 2^32 - 1 with 8B/10B encoding

PCB Speciﬁcation

– The 2-inch PWB section (port card) is composed of 6 mil wide (1/2 oz. copper thickness) 100 Ohm differen-

tial impedance traces

– Backplane - 200 mils thick, 14 layers, Nelco 4000-6 FR4

– All signal layers are 10 mil wide (1/2 oz. copper thickness) traces designed for 100 Ohm differential imped-

ance

– All signal layers buried and surrounded by GND planes

– Port Card - 93 mils thick, 14 layers, Nelco 4000-4 FR4

– Total trace length: 3 + 2 + 2 + 16 = 23 inches

Typical Eye-diagram Measurements

A typical application might have a total PWB trace path length of 12 to 24 inches, between two interconnected

devices. This section shows a series of eye-diagram measurements for a 23 inch path length. Receiver eye-dia-

gram measurements can provide an e xcellent indication of expected link perf ormance. Data rate and pre-emphasis

levels were varied. Eye-opening time and amplitude are indicated below each waveform. All tests in this section

were performed at room temperature and nominal supply voltage.

The ORT42G5 and ORT82G5 high-speed outputs provide software programmed pre-emphasis parameters of 0%,

12.5% or 25%. Pre-emphasis compensates for the high frequency losses that a typical physical interconnection

system e xhibits . Enabling pre-emphasis pro vides increased interconnection path length capability and/or increased

eye-opening f or a giv en path length. In general, pre-emphasis should only be enab led where needed, since there is

a slight increase in power dissipation and EMC radiation associated with this feature.

Bias T

Backplane (FR4)

16 inch path length

HM-Zd Conn.

Port

Card

2 in.

trace

length

Scope

Port

Card

2 in.

trace

length

ORT82G5

3 in. trace

length

2 ft. coax

connection 2 ft. coax

connection

1.5 V

Supply

50 ohm

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 2. Receiver Eye Patterns at 3.125 and 3.3 Gb/s Over a 23 inch Path Length

In Figure 2, note that the vertical scale is 100mV/div, except in the top-right eye pattern where it is 50mV/div.

The eye-opening amplitudes in the above Figure can be compared to the 80 mV eye requirement speciﬁed in the

ORT42G5 and ORT82G5 data sheet. At all data rates, the eye amplitude without pre-emphasis is above the

required level.

3.125Gb/s 3.300Gb/s

00.0%

Pre-emphasis

186 ps 155 mV 177 ps 145 mV (50mV/div)

12.5%

Pre-emphasis

221 ps 217 mV 212 ps 211 mV

25.0%

Pre-emphasis

241 ps 277 mV 240 ps 267 mV

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 3. Receiver Eye Patterns at 3.5 Gb/s and 3.7 Gb/s Over a 23 inch Path Length

The eye-openings are smaller in the above Figure because of the higher data rates, where the path losses are

greater. At these data rates 25% pre-emphasis must be used to achieve a comfortable margin above the 80 mV

required eye-opening level.

In Figure 3, note that the vertical scale is 50mV/div in each eye pattern.

3.500Gb/s 3.700Gb/s

00.0%

Pre-emphasis

153 ps 122 mV 139 ps 96 mV

12.5%

Pre-emphasis

197 ps 238 mV 186 ps 160 mV

25.0%

Pre-emphasis

223 ps 251 mV 212 ps 224 mV

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Eye-Diagram Experiment II

This section describes some additional, detailed measurements made with a preliminar y version of the Tyco XAUI

backplane reference system. Note that it has some differences in the PCB description, as compared to section 2.

This particular backplane had multiple traces of equal length, run on different PCB layers.

Test Equipment

– ORT82G5 evaluation board.

– Tyco XAUI Backplane with ﬁxed lengths of 4, 16 & 24in.

– HPE3630A, HPE3610A, HP6213A power supplies

– HP8656B clock source

– Temptronic Thermostream TP04100A-1

– PicoSecond 5575A Bias-T

– Agilent 86100A DCA oscilloscope

Test Setups

Figure 4 shows the test setup used to measure the data eye-openings discussed in this section.

Figure 4. Eye-Diagram Test Setup

Figure 5 shows the test setup used for bit-error rate measurements discussed in this section.

Figure 5. Bit Error Rate Test Setup

Bias T

Backplane (FR4)

4, 16 & 24 inch

path length

Port

Card

3 in.

trace

length

Scope

Port

Card

3 in.

trace

length

ORT82G5

3 in. trace

length

2 ft. coax

connection 2 ft. coax

connection

1.5 V

Supply

50 ohm

TYCO

HM-Zd Conn.

Bias T

Backplane (FR4)

4, 16 & 24 inch path

lengths

TYCO

HM-Zd Conn.

Port

Card

3 in.

trace

length

Port

Card

3 in.

trace

length

Agilent 70843B

Bit-Error Rate Tester

ORT82G5

Ch AA

In parallel

loopback

mode

3 in. trace

len

1.5 V

Supply

ORT82G5

Ch AB

In parallel

loopback

mode

3 in. trace

len

coax

connections

coax

connections 50

ohm

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Test Setup Parameters

– ORT82G5 680 PBGAM plastic ball grid array (wire-bond), -3 speed grade

– Power Supply = 1.5 V

– Ambient Temperature = 25 degree C

– Data Pattern = PRBS 2^7 - 1

Backplane Speciﬁcation

– The 3 inch PWB section (port card) is composed of 10 mil wide 100 Ohm differential impedance traces

– Backplane - 205 mils thick, 14 layers, Nelco 4000-6 FR4

– All signal layers designed for 100 Ohm differential impedance

– All signal layers buried and surrounded by GND planes

– Line Card - 115 mils thick, 10 layers, Nelco 4000-4 FR4

– The backplane and line card details can be obtained from Tyco Electronics

The HM-Zd Evaluation System consists of 16 unique testable differential pairs for each interconnection length, as

listed in Table 1. The basic information for each signal pair is given below. From our measurements, layer 4 and

la y er 1 w ere determined to be the best and worst from a signal integrity standpoint. Since the signal la y er geometry

is the same f or both la y ers , the diff erence in signal integ rity between the two la y ers is probab ly due to the difference

in the via stub seen at layer 1 versus layer 4.

Table 1. PWB Trace Signal Pair Descriptions

Signal Pair Number Line Card Trace Width Backplane T race Width Signal Layer Connection

18 mils 12 mils 1

2,5,7 8 mils 12 mils 4

3,6,8 8 mils 12 mils 2

4 8 mils 12 mils 3

9 5 mils 12 mils 1

10 5 mils 12 mils 4

11 5 mils 12 mils 2

12 5 mils 12 mils 3

13 5 mils 8 mils 1

14 5 mils 8 mils 4

15 5 mils 8 mils 2

16 5 mils 8 mils 3

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 6 is a plot showing the variation in data eye-opening between the various 33" signal pairs (24" backplane +

6" line card + 3" ORT82G5 board). For the 0% pre-emphasis case the variation between the best signal pair (#4)

and the worst signal pair (#13) is 214mV - 157mV = 57mV (26%). The speciﬁed minimum data eye-opening at the

receiver for the ORT42G5 and ORT82G5 SERDES macro is 80mVp-p differential. Therefore, all signal pairs have

adequate system performance without pre-emphasis.

Figure 6. 33 Inch Path Length Eye-Openings

Lattice ORT82G5 FPSC SERDES

Full Amplitude Data Eye

33" FR4 Trace Pair Receive End

Data Eye Opening

(mV p-p Differential)

100

150

200

250

300

350

1 2 3 4 9 10 13 14

Signal Pair Number

Tyco Z-Pack HM-Zd Evaluation Test System

(P/N 1469012-01)

12.50

Pre-emphasis

Setting

Conditions

3.125 Gbs

2^7-1 PRBS

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 7 and Figure 8 are plots showing the v ariation in data ey e-opening for signal trace pair #2 between the three

trace lengths (24", 16" and 4" backplane + 6" line card + 3" ORT82G5 board). Notice that for the 4" and 16" back-

plane traces 25% pre-emphasis actually degrades the data eye. Figure 7 shows data eye-openings for full ampli-

tude transmit buffer signal outputs. Figure 8 shows data eye-openings for one half amplitude transmit buffer signal

outputs. The one half amplitude mode is used as a power saving f eature and is set through a microprocessor regis-

ter bit. Also shown in Figures 7 and 8 are the power consumption values for the Transmit Output buffer power sup-

ply (VDDOB).

Figure 7. Pair 2 Full-Amplitude Eye-Opening vs. Pre-Emphasis and Trace Length

Lattice ORT82G5 FPSC SERDES

Full Amplitude Data Eye Opening vs.

Total Trace Length and Pre-emphasis Setting

Data Eye Opening

(mV p-p Differential)

Pre-emphasis Setting

Conditions

3.125 Gbs

2^7-1 PRBS

150

200

250

300

350

400

450

500

0% 12.50% 25%

33 Inches

25 Inches

13 Inches

26.1mW 28.9mW 29.7mW

P (Output Buffer)

*Tyco HM-Zd Evaluation Backplane Pair #2

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 8. Pair 2 Half-Amplitude Eye-Opening vs. Pre-Emphasis and Trace Length

The nominal TX output buffer power consumption vs. pre-emphasis and output amplitude settings is shown in the

following table (data taken from Figures 5 and 6).

Table 2. Nominal TX Output Power vs. Parameter Settings

The power penalty/beneﬁt of these settings can be determined by comparing values in the table.

Figure 9 and Figure 10 are plots showing the variation in vertical data eye-opening for signal trace pair #13. Notice

the difference in data eye-opening between the measurements for signal trace pair #2 and signal trace pair #13.

The primary difference between these two trace pairs is trace width and layout geometry (see Table 1).

Pre-Emphasis 0% 12.5% 25%

Half-Amplitude 21.7 mW 23.2 mW 26.3 mW

Full-Amplitude 26.1 mW 28.9 mW 29.7 mW

Lattice ORT82G5 FPSC SERDES

Half Amplitude Data Eye Opening vs.

Backplane Length and Pre-emphasis Setting

Data Eye Opening

(mV p-p Differential)

Pre-emphasis Setting

Conditions

3.125 Gbs

2^7-1 PRBS

33 Inches

25 Inches

13 Inches

100

150

200

250

300

350

0% 12.50% 25%

(Output Buffer)

21.7mW 23.2mW 26.3mW

*Tyco HM-Zd Evaluation Backplane Pair #2

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 9. Pair 13 Full-Amplitude Eye-Opening vs. Pre-Emphasis and Trace Length

Figure 10. Pair 13 Half-Amplitude Eye-Opening vs. Pre-Emphasis and Trace Length

Lattice ORT82G5 FPSC SERDES

Full Amplitude Data Eye Opening vs.

Backplane Length and Pre-emphasis Setting

Data Eye Opening

(mV p-p Differential)

Pre-emphasis Setting

Conditions

3.125 Gbs

2^7-1 PRBS

33 Inches

25 Inches

13 Inches

*Tyco HM-Zd Evaluation Backplane Pair #13

150

200

250

300

350

400

450

500

0% 12.50% 25%

Lattice ORT82G5 FPSC SERDES

Half Amplitude Data Eye Opening vs.

Backplane Length and Pre-emphasis Setting

Data Eye Opening

(mV p-p Differential)

Pre-emphasis Setting

100

150

200

250

300

0% 12.50% 25%

Conditions

3.125 Gbs

2^7-1 PRBS

33 Inches

25 Inches

13 Inches

*Tyco HM-Zd Evaluation Backplane Pair #13

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Figure 11 shows the horizontal eye-opening as a function of trace length and pre-emphasis for signal trace pair #2

at full transmit amplitude. With no pre-emphasis, the eye-opening varies from 268ps for the 4" backplane trace pair

to 226 ps for the 24" backplane trace pair. At full (25%) pre-emphasis, the waveform for the 4" trace pair is signiﬁ-

cantly degraded while the 24" trace pair continues to beneﬁt from the additional pre-emphasis.

Figure 12 is similar to Figure 11 except for backplane trace pair #13. Notice that unlike the data taken from back-

plane trace pair #2, the data eye-opening for the 16" and 24" backplane trace lengths continue to beneﬁt from full

pre-emphasis (25%).

Figure 11. Pair 2 Eye-Opening vs. Pre-Emphasis and Trace Length

Figure 12. Pair 13 Eye-Opening vs. Pre-Emphasis and Trace Length

Lattice ORT82G5 FPSC SERDES

Full Amplitude Horizontal Data Eye Opening vs.

Backplane Length and Pre-emphasis Setting

Data Eye Opening

(ps)

Pre-emphasis Setting

*Tyco HM-Zd Evaluation Backplane Pair #2

Conditions

3.125 Gbs

2^7-1 PRBS

33 Inches

25 Inches

13 Inches

200

210

220

230

240

250

260

270

280

290

300

0% 12.50% 25%

Waveform

distortion due to

Pre-emphasis

Lattice ORT82G5 FPSC SERDES

Full Amplitude Horizontal Data Eye Opening vs.

Backplane Length and Pre-emphasis Setting

Data Eye Opening

(ps)

Pre-emphasis Setting

*Tyco HM-Zd Evaluation Backplane Pair #13

Conditions

3.125 Gbs

2^7-1 PRBS

33 Inches

25 Inches

13 Inches

200

210

220

230

240

250

260

270

280

290

300

0% 12.50% 25%

Waveform

distortion due to

Pre-emphasis

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Data-Rate Experiment

Bit-error rate testing was performed across 16 and 30 inch backplane traces, at 25 and 125 degree C tempera-

tures. The total PCB trace path length for this testing is 26 and 40 inches, when port card and ORT82G5 evaluation

board traces are included. Supply voltage and operating speed were varied as indicated. The test criterion used

was the observation of 1E12 data bits received with no bit-errors occurr ing. Detailed bit-error rate and jitter perfor-

mance is bey ond the scope of this application note . A detailed discussion of the OR T42G5 and ORT82G5 jitter and

error-rate performance, can be found in another application note

Test Equipment

– ORT82G5 evaluation board

– Tyco Electronics XAUI backplane with two port cards

– Agilent 70843B Error Performance Analyzer

– HPE3630A, HPE3610A, HP6213A power supplies

– HP8656B clock source

– Temptronic Thermostream TP04100A-1

– PicoSecond 5575A Bias-T

Test Setup

The test conﬁguration used to ver ify error-free operation is shown in Figure 13. High-speed ORT82G5 ser ial inter-

face buff ers are connected at both the Tx and Rx signal ends of the PCB signal path under test. Two separate SER-

DES channel in the ORT82G5 device were each placed in a parallel loopback mode of operation (with 8B/10B

encoding/decoding disabled). The Agilent BERT was used to generate the data test pattern. Matched length 50

ohm coax cables used in the signal path were found to have minimal loss, as compared to PCB traces.

Figure 13. Bit-Error Rate Test Setup

Test Setup Parameters

– ORT82G5 680 PBGAM plastic ball grid array (wire-bond), -3 speed grade

– Ambient temperature = 25 to 125° C

– Data pattern = PRBS 2^7 - 1

– Power supply = 1.4V to 1.6V

Bias T

Backplane (FR4)

16 and 30 inch

path length

TYCO

HM-Zd Conn.

Port

Card

2 in.

trace

length

Port

Card

2 in.

trace

length

Agilent 70843B

Bit-Error Rate Tester

ORT82G5

Ch AA

In parallel

loopback

mode

3 in. trace

length

1.5 V

Supply

ORT82G5

Ch AB

In parallel

loopback

mode

3 in. trace

len

coax

connections

coax

connections 50

ohm

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

PCB Speciﬁcation

– The 2 inch PWB section (port card) is composed of 6 mil wide (1/2 oz. copper thickness) 100 Ohm differen-

tial impedance traces

– Backplane - 200 mils thick, 14 layers, Nelco 4000-6 FR4

– All signal layers are 10 mil wide (1/2 oz. copper thickness) traces designed for 100 Ohm differential imped-

ance

– All signal layers buried and surrounded by GND planes

– Port Card - 93 mils thick, 14 layers, Nelco 4000-4 FR4

Data Summary

A small sampling of devices was tested over temperature and supply voltage variations. The maximum speed of

operation was determined at each test condition. Results of the testing for the worst-case device are shown in

Table 3 and Table 4.

Table 3. Bit-Error Rate Test Results with 26 Inch PCB Connection

Table 4. Bit-Error Rate Test Results with 40 Inch PCB Connection

Test criterion used for all tests was 1E-12 maximum bit-error rate.

VDSerdes Temp PE Speed

1.60 25C 25% 4.1G

1.40 25C 25% 3.9G

1.60 125C 25% 3.8G

1.40 125C 25% 3.7G

VDSerdes Temp PE Speed

1.60 25C 25% 3.5G

1.40 25C 25% 3.4G

1.60 125C 25% 3.3G

1.40 125C 25% 3.2G

ORT42G5 and ORT82G5

Lattice Semiconductor High-SpeedBackplane Measurements

Conclusion and Backplane Design Guidelines

The ORT42G5 and ORT82G5 FPSCs can support high-speed serial backplane interconnections over a broad

range of data rates and connection path lengths. Measurement data presented in this document illustrates device

performance over a typical backplane system, designed for high-speed serial interconnections. ORT42G5 and

OR T82G5 (per channel) progr ammable po w er output le v els and pre-emphasis le v els , allo w applications to optimize

each signal interface.

The effectiveness of using pre-emphasis to compensate for the high-frequency losses of longer path lengths was

shown in Sections 2 and 3. Eye-diagram measurements were found to be a very good indication of backplane

interconnection perf ormance. The speciﬁed 80mV minimum e ye-opening criterion for the ORT42G5 and ORT82G5

was found to consistently predict error-free performance (less than 1E-12 error-rate) in all the measurements

made.

Perf ormance variations due to PCB la y out/board-construction were measured in Section 3. It was sho wn that these

variations can be signiﬁcant, e ven between different layers within the same board. This illustr ates the critical nature

of hardware designs extending to multi-Gb/s interconnection rates.

High-speed interconnection perf ormance in a system is dependent on many de vice , system and environment char-

acteristics. For this reason it is not possible to specify performance limits that apply to all applications. Table 5

shows the ORT42G5 and ORT82G5 operating data rate limit for the fastest device speed grade.

Table 5. ORT42G5 and ORT82G5 FPSC Frequency Limit

This table takes into account variations in device speed, temperature, and supply voltage. The data of Section 4 is

consistent with this table, for a speed g r ade -3 device, while oper ating over a 26 inch connection path, in the TYCO

backplane test system. The maximum connection path length that an application can reliab ly use , is a comple x sys-

tem level question that the application designer must address.

The following suggestions are made, for ORT42G5 and ORT82G5 applications, to help achieve best interconnec-

tion performance results:

• Careful selection of backplane connectors and other components touching the high-speed path, is critical.

Each component should be electrically characterized through the frequency range of operation. Pay close

attention to the parasitic reactance parameters of these components.

• Great care should be taken in the port card and backplane PCB design to follow good high-speed design

practices.

• Use analog simulation tools extensively. Analog interconnection circuit simulation is a valuable tool at the

system design le v el. SPICE models of interf ace and connection de vices , which are a v ailab le from most ven-

dors, can be used to assess signal integrity issues, prior to building models.

• Early laboratory measurements of the longer and/or more critical interconnection paths should be made to

reduce technical risk, prior to full system model design. Eye-diagram and bit-error rate measurements are

recommended. ORT42G5 and ORT82G5 SERDES I/O buffer HSPICE models are available.

References

1. Tyco Electronics XAUI Z-Pack HM-Zd Bac kplane Evaluation Test System (this system was selected b y 10GEC

as the XAUI interoperability standard)

2. SERDES Test-Chip Jitter Performance, Lattice Technical Note TN1032

3. ORCA

ORT42G5 and ORT82G5 Data Sheet

Device Speed Grade Max Data Rate

-3 3.7 Gb/s

www.latticesemi.com

tn1033_02

High-Speed PCB Design

Considerations

April 2003 Technical Note TN1033

Introduction

The backplane is the physical interconnection where typically all electrical modules of a system conv erge . Comple x

systems rely on the wires, tr aces, and connectors of the bac kplane to handle large amounts of data at high speeds .

The communications between the various backplane modules depends on the inherent electrical characteristics

such as impedance, capacitance, and inductance der ived from connectors, trace lengths, vias, and termination, to

name a few. An extremely important factor for a distributed-load, high performance backplane is a basic under-

standing of the design practices used to ensure good signal integrity.

This technical note examines some basic differences in interconnection topologies. It describes the various issues

that should be considered while designing a backplane and focuses on the critical aspects of point-to-point trans-

mission lines that are run through a backplane. These aspects include PCB line structure, vias, device packaging

and backplane connectors. A PCB design checklist is provided to aid the designer. Some frequency speciﬁc dis-

cussion and guidelines are given. This document also discusses Lattice Semiconductor's FPSC product line and

it's high-speed backplane interfaces. These provide serial streams up to 3.7 Gbps through CML differential buffers.

Backplane Topology and Overview

Three different system interconnection topologies are normally used in backplanes today. These are multi-point,

multi-drop and point-to-point. Traditionally systems have used multi-point/ multi-drop connection topologies, which

provided efﬁcient interconnection and comm unication between m ultiple devices, with a single net (node), as sho wn

in Figure 1.

Figure 1. Multi-Point Backplane Illustration

Unfortunately, this net str ucture provides serious data-rate limitations. Each net contains tees or branches at each

point where the card connects to the backplane. These tees provide transmission line discontinuities and mis-

matches along the backplane signal path. The result is large signal reﬂections occur at every card to backplane

interface. These reﬂections can propagate back and forth for substantial time periods and severely degrade signal

integrity at higher speeds. Acceptable signal communication is normally achieved by waiting for the reﬂected sig-

nals to settle out, for each bit of transmitted data. This imposes signiﬁcant speed limitations. For this reason multi-

point and multi-drop backplane topologies generally have speed limits below 100 Mbps. This limit can easily drop

below 10 Mbps as physical line lengths and the number of card slots increase.

The point-to-point interconnection topology eliminates the signal path branches described abov e . The resulting sig-

nal reﬂections are eliminated and maximum data rates are increased dramatically. This type of backplane intercon-

nection can be used with data-rates to 3 Gbps and above, with careful design methods.

The disadvantage of this approach is an increase in the number of backplane nets and card port interfaces that

may be needed. The single net connection between n cards, in a multi-point backplane, must be replaced with n(n-

Tx Rx Tx Rx Tx Rx

Lattice Semiconductor High-Speed PCB Design Considerations

1) unidirectional point-to-point links. Each card must provide n-1 tr ansmit and n-1 receive ports for full system inter-

connectivity. As an example, a four PCB module system with full interconnectivity is shown in Figure 2.

Figure 2. Four Card Point-to-Point Interconnection System

Each card must pro vide 3 transmitter and 3 receiver ports. Each arrowed line represents a point-to-point bac kplane

net.

Recent communications equipment designs have shown a rapidly growing need for higher bandwidth interconnec-

tion between PCB modules. The fast evolving IC technology, with its multi-gigabit processing and dr iving capabili-

ties, has made point-to-point backplane the topology of choice for many of today's new hardware systems. Both

serial and parallel data structures can be supported with this topology. Lattice Semiconductor has introduced sev-

eral IC products with multiple ports, each designed with Gbps backplane drive capability. These devices will be

described later in this document. The remainder of this document will focus on PCB design aspects of the point-to-

point backplane interconnection links.

Point-to-Point Backplane Signal Path Structure

The typical point-to-point topology utilizes a simple , single-path interconnection structure that e xtends from a trans-

mitting device on one card, across a backplane and second card, to a receiving device on another card. The phys-

ical path for such an interconnection is illustrated in Figure 3.

Figure 3. Interconnection Link Physical Structure

The point-to-point interconnection elements are all serially connected and provide a single signal path. Each ele-

ment may be thought of as a transmission line segment. Ideally, by controlling and matching the characteristic

impedance of each line segment, a uniform electr ical signal path is created. Signals can then propagate the entire

path length with no reﬂections occurring. Adding a resistive termination at the receive de vice input, with v alue equal

to the characteristic impedance of the line elements, would provide a distor tionless data link with maximum band-

width, between the transmit and receive devices.

Each of the elements in Figure 3 can be broken down into of a number of sub-elements. The PCB elements for

example, which provide the more signiﬁcant transmission line segments in the data path, consists of the sub-ele-

ments: metal traces, dielectr ic layers, ground plane layers, and (inter-layer) vias. Each of these sub-elements is a

critical part of the signal path and can cause electrical line discontinuities and signal reﬂections, if not properly

designed. The design aspects of the elements and sub-elements contained in Figure 3 will be discussed in the fol-

lowing sections.

Card 3

Card 1 Card 2

Card 4

Device

Package Card

PCB Connector Backplane

PCB Connector Card

PCB Device

Package

Lattice Semiconductor High-Speed PCB Design Considerations

Advantages of Differential Signaling

The inherent system advantages of differential signal interconnection schemes are well known in all ﬁelds of elec-

tronic design. These advantages are especially important in high bandwidth, high-density hardware systems where

very low error-rate data links are required. Differential signaling provides critically needed immunity to common-

mode electrical noise that is present at signiﬁcant levels in most application systems. For example, using differen-

tial signaling avoids the classic "ground bounce" noise prob lem that is experienced with many high density ICs that

use single-ended interfaces. It also provides higher noise margins, which lead to lower bit-error rates in digital data

links. F or these reasons , Lattice Semiconductors pro vides fully differential I/O interf aces, as will be described in the

Device Introduction section. Differential signal interconnection methods should be used for all critical, high-speed

interconnections.

Board Design Practices

Differential T race Design

Differential signal trace-pairs with controlled impedance can be arranged in a number of different conﬁgurations.

Most common are the following four ﬁgures.

Figure 4. Edge Coupled Microstrip (surface routing)

Figure 5. Edge Coupled Stripline (sandwiched between two reference planes)

Figure 6. Offset Edge Coupled Stripline (same as Figure 5, but not centered between reference planes)

Figure 7. Broadside Coupled Stripline (also referred to as Dual Stripline)

100 ohm characteristic impedance has become an industr y standard value for differential lines used for intercon-

nection. This impedance level lends itself well to PCB structures and other components designs where controlled

transmission line impedance must be provided.

TH2

Lattice Semiconductor High-Speed PCB Design Considerations

A 100 ohm differential line can be constructed with two 50 ohm single-ended lines of equal length.

As the two line traces are brought near each other (as shown in Figure 4 through Figure 7), the ﬁeld coupling

between the traces reduces the differential mode impedance of the line. To maintain 100 ohm differential imped-

ance, the trace width must be reduced slightly. As a result the common mode impedance of each trace in a 100

ohm couple-trace differential pair will be slightly less than 50 ohms.

Achie ving a 100 ohm _diff erential impedance with a coupled pair of tr aces implies that the single ended impedance

of Z0 ranges from 53 _to 60 ohm, with a coupling coefﬁcient typically ranging from 1-15%. The relationship

between the common mode impedance Z0 and the differential impedance Zdiff is given by the expression Zdiff = 2

Z0 (1 - kb)/(1 + kb), where k is the trace coupling coefﬁcient.

50 ohm resistors, tied to ground, are nor mally used to terminate the 100 ohm differential lines. This provides the

ideal differential line termination, which is most important since the data links use differential signals. The slight

impedance mismatch that occurs in the common mode is usually of little consequence. Normally only noise and

crosstalk signals occur in common mode.

Common Mode Noise Tolerance

In order to prevent common mode noise from conver ting to differential mode noise, it is impor tant to maintain the

symmetr y of the differential pair. Reﬂections and impedance mismatch in the common mode will not affect the dif-

ferential mode performance as long as the two modes can be kept relatively orthogonal.

The loop area is deﬁned as the area between the signal path and its return path. On diff erential traces, the signal is

on one trace and the return is on the other trace. So the loop area is a function of how close the traces are routed

together. If we are concer ned about EMI emission and susceptibility, which is generally understood as a loop area

concern, we must route the traces close together. The more closely we route them to each other, the smaller the

loop area will be and the less EMI will be generated.

One of the primary advantages of differential signals is the signal-to-noise ratio improvement that is obtained.

Since the signal is one polarity on one trace and the other polarity on the other trace, the resulting signal at the

receiving device is twice what the single-ended signal would be. Ideally common mode rejection at the receiving

device is such that the receiving device only responds to the difference in signal level between the two traces.

Since noise is typically in the common mode, it is rejected at the receiv er and maintains a high differential signal-to-

noise ratio.

In order to hav e good common mode noise rejection, it is important that any noise that is present aff ects the signals

on both traces equally. That is, if noise is coupled into one tr ace, an equal amount of noise m ust be coupled into the

other trace. Then the common mode rejection capability of the receiving circuit will reject the noise. But if noise is

coupled into one trace more strongly than into the other trace, the noise will appear as a differential mode signal to

the receiver and be ampliﬁed. The way to ensure that any noise is coupled equally into both traces is to route the

two traces very close together. Then they will both be in the same noise environment.

PCB Trace Impedance Calculation

In the past, calculation of the characteristic impedance for a printed circuit board trace was a complex, error prone

process involving complicated calculations and approximation. Nomographs and simpliﬁed formulas have been

generated to simplify the design process, but are often inaccurate. The most accurate method available is a ﬁeld

solver program (usually 2D, sometimes 3D), which solves Maxwell's equations directly over the volume of PCB

under consideration using ﬁnite elements. These simulations can be veriﬁed in hardware with a Time Domain

Reﬂectometer (TDR) measurement device.

One example of a 2D ﬁeld solver program is the Si6000b program from Polar Instruments[1]. This is available as a

shareware evaluation version, and can be downloaded for evaluation and testing on a workstation.

Even using a ﬁeld solver, there are still uncertainties in the impedance calculation arising from variations in the

effective dielectric constant in the glass ﬁber, prepreg, and epoxy used in typical FR4 manufacturing. The average

Lattice Semiconductor High-Speed PCB Design Considerations

dielectric constant of FR4 varies from 4.2 to 4.5, depending on the material, exact location, and construction meth-

ods used.

Veriﬁcation of the impedance on a PCB depends on actual measurements of typical copper traces . Some manuf ac-

turers use an auxiliar y test section of a PCB called a coupon, which is a long rectangular test section of PCB with

pads designed to accept probes from a TDR measuring instrument. It is not unknown for manufacturing errors to

result in ov er-etching of the copper tr aces , with a resultant impedance error. Monitoring production quality with cou-

pons can prevent this type of problem.

Examples of PCB Trace Impedance Calculation

As a calculation example, we will ﬁnd the differential impedance for a pair of 6 mil traces in 1/2 ounce copper with

10 mil spacing that is on an FR4 substrate with a spacing of 5 mils abo v e the ground plane (microstrip). The copper

thickness (T) is 0.7 mils. Figure 8 shows the parameters. Note that this example uses a predecessor to the Polar

Si6000b transmission line calculator product mentioned previously.

Figure 8. Differential Microstrip example with Polar CITS25 Impedance Calculator Tool

In a typical FR4 PCB, there will be three types of differential pair routing encountered. For connections to surface

mounted components, edge coupled microstrips may be needed, while connections between through-hole compo-

nents or via pairs can use stripline and offset stripline. Dual stripline with broadside coupling should be avoided,

since this conﬁguration is subject to differential noise coupling from the reference planes. Another problem with

broadside coupling is that any asymmetry in the PCB manuf acturing can result in an asymmetric trace impedance,

causing mismatch in the effective electrical length, even if the physical lengths match exactly. Using edge coupled

differential pairs; it is easier to maintain symmetry.

Vias, connectors , and component pads all introduce impedance discontin uities into the signal path, and this can be

measured with TDR techniques.

In order to avoid crosstalk, when laying out differential pair trace with spacing of value S, it is recommended to

place pairs no closer than a distance of 3 S, and preferably a distance of 4 S if possible. This rule can be relaxed if

a differential pair is only brieﬂy in proximity with another pair, such as at a connector or via layer switch.

PCB Design Checklist

1. Use 100 ohm_ differential impedance pairs on PCB. Controlled impedance lines should be speciﬁed in PCB

manufacture.

2. Match trace lengths in a pair with tolerance of 20% of the signal rise/fall time.

3. Use connectors that are designed and characterized at the highest data frequency. (Vendors should provide

characterization and model data.)

Lattice Semiconductor High-Speed PCB Design Considerations

4. Use stripline construction with ground/VDD planes above and below the differential pairs.

5. Use edge-coupled pairs in PCBs; try to avoid broadside coupled pairs.

6. Use 3 S separation rules between pairs to avoid crosstalk and excess coupling. Use offset stripline routing to

get higher density of differential pairs with each routing layer running orthogonal to each other.

PCB Layer Design (Board Stack-up)

Multi-la y er boards are a must in both daughter board and bac kplane design. The m ultiple metal la y ers f acilitate high

connection density, minimum crosstalk, and good ElectroMagnetic Compatibility (EMC). These factors are key to

achieving good signal integrity for all the signal interconnections. Ideally, all signal layers should be separated from

each other by ground or power planes (metal layers). This minimizes crosstalk and provides homogeneous trans-

mission lines, with properly controlled characteristic impedance, between devices and other board components.

Best perf ormance is obtained when using dedicated ground and pow er plane layers that are continuous across the

entire board area. When it is not feasible to provide ground or pow er planes between signal layers, great care must

be taken to ensure signal line coupling is minimized. Or thogonal routing on adjacent signal layers minimizes cou-

pling and should be used. CAD tools, which predict line coupling and signal crosstalk, can be very helpful in this

type of design.

Vias

Vias generally provide two pur poses. One is used for mounting a through-hole component to a board. The second

is to interconnect traces on different metal layers. Electrically, vias are often modeled as having an inductive and

capacitive parasitic value. Smaller vias have lower capacitance. Short length, larger diameter vias have lower

inductance. Both parasitic elements can have detrimental affects, but it is often the inductance parasitic element

that provides an unexpected series impedance that creates problems.

Lattice High-Speed I/O Offerings

Lattice Semiconductor has introduced a series of silicon devices utilizing high-speed CML and LVDS serial inter-

faces that feature cloc k synthesis to embed data and cloc k in a serial stream in the transmitter monolithic cloc k and

data recovery in the device receiver. These devices are listed in the following table.

Table 1. Lattice Semiconductor ORCA FPGA, FPSC, ispXPGA and ispGDX2 High-Speed I/O Devices

The ORT8850H/L, ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5 have integrated serializer and deserializer

with CDR (Clock & Data Recovery) blocks, and also feature de-skew FIFO's that remove skew between multiple

serial channels. This facilitates bonding of multiple ser ial channels for synchronized gigabit data transfers between

chips, boards, racks, and systems. The data format is either SONET, with a subset of the full GR253 standard sup-

ported, or 8b/10b coding. The ORT82G5 and ORT42G5 support eight or four channels of serial data at rates up to

3.7 Gbps (2.96 Gbps per channel after 8b/10b decoding). The ORSO82G5 and ORSO42G5 suppor t eight or four

channels of serial data at rates up to 2.7 Gbps. At these high speeds Current Mode Logic (CML) I/O buffers are

used.

Device Description

OR4E02/04/06 FPGA Family with high-speed differential I/Os

ORLI10G 10 Gbps Line interface FPSC

ORT8850H/L 6.8 Gbps Backplane FPSC (850 Mbps/ch)

ORT82G5 29.6 Gbps Backplane FPSC (3.7 Gbps/ch)

ORT42G5 14.8 Gbps Backplane FPSC (3.7 Gbps/ch)

ORSO82G5 21.6 Gbps SONET Backplane FPSC (2.7 Gbps/ch)

ORSO42G5 10.8 Gbps SONET Backplane FPSC (2.7 Gbps/ch)

ispXPGA 17 Gbps with SERDES FPGA (850 Mbps/ch)

ispGDX2 13.6 Gbps with SERDES (850 Mbps/ch), 38 Gbps without SERDES

Lattice Semiconductor High-Speed PCB Design Considerations

The ORLI10G provides a simpler high speed interface of 16 LVDS channels, without CDR or skew compensation.

A synchronous, forward clocked interface can be used, with rates up to 850 Mbps. Great care must be taken by

system designers to insure interconnection skews are properly controlled. This may impose speed and/or intercon-

nection distance limits in some applications.

The ispXPGA and ispGDX2 also have embedded SERDES blocks with CDR circuits. Both families support 8b/10b,

10b/12b and Source Synchronous mode. The encoding and decoding of 8b/10b blocks are not implemented in

these devices.

Integrated Input Terminations

Lattice devices with high-speed ser ial CML and LVDS inputs provide built in, programmable, 100 ohm differential

line termination resistors. Integrating these resistors on-chip is very important in high-density packaging such as

ball-grid arrays where an on-board resistor cannot be placed close to the device inputs, off-chip resistors signiﬁ-

cantly reduce performance and increase the effects of reﬂections. Lattice differential input terminations include

center-tap access. The ORT8850 input, for example, is shown in Figure 9.

Figure 9. LVDS Receiver Termination

The center-tap is a virtual ground which may be ac-coupled to ground to increase receiver common mode noise

immunity, as shown in the ﬁgure. Embedded LVDS output buffers also have on-chip 100 ohm_ differential termina-

tions, b ut do not ha v e a center tap . These terminations hav e been shown to reduce near-end crosstalk signiﬁcantly.

ORCA Series 4 FPGAs and the programmable I/O buffers on the FPSCs, including the ORT8850H/L, ORT82G5,

OR T42G5, ORSO82G5 and ORSO42G5 also include special prog rammable LVDS drivers and receiv ers. This type

of termination scheme is also available on the Series 4 general purpose FPGAs. These LVDS I/Os also include

driver and receiv er on-board 100 ohm _termination, but without the center tap . This termination resistor can also be

disabled at the LVDS pair level. This scheme works well for receiver termination on a pin-by-pin basis, however it is

programmable and can be implemented on the transmitters (drivers) also, thereb y extending the reach of the LVDS

signaling.

ispXPGA and ispGDX2 Family devices do not provide internal input ter mination resistors and require external ter-

mination at receiver inputs.

Special Design Considerations at 622/850 Mbps

Line Loss and Impedance Discontinuities

At data rates of 622 Mbits and higher, it should be realized that the skin eff ect is extremely important for signal con-

duction. Small traces on a PCB (like 4 or 5 mil widths) will exhibit signiﬁcant signal attenuation over long distances.

Over-etching of a PCB can produce narrow traces that can reduce the signal amplitude available at the receiver.

Off-Chip On-Chip

CTAP Pad

0.01 F

Lattice Semiconductor High-Speed PCB Design Considerations

The end result is that, to the designer, the interconnection between devices resembles a badly designed low pass

ﬁlter, with attenuation, which increases with frequency. For this reason, the longer the backplane, the wider the sig-

nal traces should be made. Long backplane traces (more than 20 in.) should have trace widths of 10 or 12 mils.

Connectors and vias in the signal path introduce discontinuities that resemble lumped elements in an electrical

model. One wa y to take this into account is to perform SPICE simulation of the backplane system using lossy trans-

mission line models, and manufacturer supplied models of the connectors, signal drivers, and signal receivers.

High-Speed Connectors

Many connectors have been tried and discarded in high-speed applications. Sur pr isingly, some out-dated connec-

tor designs have been f ound to be usab le at gigabit data r ates . An example of this is the venerab le DB-9 connector,

which is sometimes found in Fibre Channel products. A more modern approach is to use controlled impedance

connectors speciﬁcally designed for high-speed data, where abundant ground connections and shielding features

reduce the noise and impedance discontinuities seen in older connectors.

Examples of these are the AMP Mictor connectors, and the 2mm standard backplane connector families that are

available from various suppliers for the 2 mm hard metric backplane standard (such as the AMP HS3 connector).

These are available in both vertical and horizontal conﬁgurations. Several evaluation cards use an unshielded 2

mm connector (AMP 636120-1), and this provides good perfor mance for driving twinax cables up to a distance of

65 ft (at 622 Mbps), error free.

Device Packaging

Transmitter and receiver device packaging parasitic reactances are important to signal integrity. Wire-bond and

package substr ate inductance and capacitance should be included in de vice SPICE models . Simulation of pac kage

parasitics has shown that impedance transformation and signal reﬂections can result at higher frequencies. Pin

location in larger packages can have a signiﬁcant impact on the parasitic values of the model. Internal receiving

device ter minations, such as provided in Lattice LVDS and CML buffers, were found to have superior performance

when compared to receivers which require external resistor termination components.

High-Speed Copper Cables

High-performance cables generally far outperf orm PCB interconnections in terms of bandwidth and signal attenua-

tion. This is because a high-performance cable uses expanded Teﬂon dielectric (PTFE); silver-plated conductors,

and low-loss shielding material. These cables are also engineered with a conductor geometry that is usually

extremely close to the optimal position for the desired bandwidth and characteristic impedance.

One cable that performs extremely well is the W. L. Gore DXSN2112 Eye-opener Plus cable. This high perfor-

mance cable is engineered speciﬁcally for data transmission at 622 Mbps. Unfortunately, this cable is not easily

assembled with connectors using simple hand tools. Complete cables with connectors may be ordered directly

from Gore. The cable assembly that matches the 2 mm backplane connector (AMP 636120- 1) on many Lattice

evaluation cards is Gore part number 2MMA3106.

Another cabling example is included with the Lattice OR T8850 evaluation boards . In this case, connections through

a path including dips witches , bac kplane connector and 65 ft of Gore DXSN2112 cab le were error free at 622 Mbps .

When routing the signal through Motorola LVPECL buffers and receivers with Gore DXN2151 cable, this was seen

to be error free at a distance of up to 90 ft. Minimal reductions in the distances are expected at the maximum 850

Mbps for the ORT8850.

Caution: Do not attempt to use Cat-5 or Cat-6 Ethernet cable. This cable is not designed for high-speed applica-

tions.

Special Design Considerations at 2.5/3.125/3.7 Gbps

At 2.5/3.125/3.7 Gbps, the design problem becomes substantially more difﬁcult. The higher copper and dielectric

losses occurring at these frequencies, generally limit PCB interconnection lengths to about 40 inches . The greatest

care in all aspects of PCB layer and layout design is required at these frequencies.

Lattice Semiconductor High-Speed PCB Design Considerations

Board Thickness and Vias

Backplane thickness and via design can have signiﬁcant affects on signal integr ity. A backplane thickness of less

than 0.200 inches generally gives the best results. Vias used to interconnect between layers create transmission

line discontinuities. PCB designs with high-speed signal traces should be routed on as few layers as possible, thus

limiting the number of vias. Thicker boards nor mally have longer length vias that can cause larger discontinuities,

and degrade the signals. Longer vias connecting signal layers that are close together will appear as transmission

line stubs, attached to the signal path. Stubs have been shown to have a very detrimental affect on signal integr ity.

Buried vias can be used to reduce this problem in thicker boards, but manufactur ing costs for this technology can

be prohibitive. Ideally, each signal path through the backplane should be kept on the same layer.

Board Material

FR4 dielectric loss becomes a signiﬁcant design factor above 2 Gbps. Another design option is to use low-loss

dielectric PCB material, such as Rogers 4350, GETEK, or ARLON. This is approximately double the cost of FR4

PCB material, but can provide increased eye-opening performance when longer trace interconnections are

required; as shown from data collected by AMP Inc. Figure 10 gauges the improvement in signal eye opening at

2.4 Gbps, as lower loss materials are used. It can be seen from the ﬁgure that FR-4 material may deliver a satis-

factory eye opening. It might then be the preferred low cost solution for a particular application.

Figure 10. System Eye Patterns (2.4Gbs) vs. PCB Dielectric Material

High-Speed Connectors and IC Packaging

Above 1 Gbps, connectors speciﬁcally designed for higher frequencies are recommended. Several new controlled

impedance backplane connectors have become available, with data-rate capabilities in excess of 3 Gbps. A popu-

lar example is the Tyco Z-Pack HD-Zd 2-mm pitch family, which has been carefully characterized and modeled at

frequencies up to 5 GHz. This class of connector provides some additional shielding beneﬁts, which can aid the

designer in controlling system noise and crosstalk.

Lattice Semiconductor High-Speed PCB Design Considerations

The IC packaging comments of the previous section apply here as well. SPICE modeling of the package parasitics

is the best way to evaluate effects on system performance, since measurement probes typically have parasitics

equal to or greater than the pac kages used toda y. Care should be taken to insure that the v endor provided pac kage

models are valid through the intended frequency of operation.

Pre-Emphasis

Signal pre-emphasis is a means of compensating for the increased PCB loss that occurs at higher frequencies. A

simple algorithm can be employed in the line driver to increase transmitted signal amplitude, whenever the data

patterns have tr ansitions (and theref ore higher frequency content). This function is provided by the ORT82G5 SER-

DES CML drivers [4].

For longer PCB interconnection trace lengths, a signiﬁcant increase in e y e opening often results [3]. Use of the pre-

emphasis can extend the maximum useable interconnection length, or allow the use of lower cost (greater loss)

material and components, in system design. A more detailed description of the pre-emphasis feature may be found

in Reference [4].

Conclusion

PCB backplane interconnections with serial data rates up to 3.7 Gbps are possible with today's technology. Lattice

FPSC de vices allo w easy system design at r ates to 850 Mbps through the ORT8850H/L serial or ORLI10G parallel

interface. Increased performance with rates up to 3.7 Gbps is achievable with the ORT82G5, but greater care is

needed in the PCB design. Systems running at these higher data rates ma y beneﬁt from the use of transmitter pre-

emphasis, controlled impedance connectors, and low loss PCB dielectric materials.

References

1. Si6000b ﬁeld solving impedance calculator (downloadable demo version): http://www.polarinstruments.com/

2. W.L. Gore high-performance interconnect products: http://goreelectronics.com/

3. ORT82G5 High Speed Backplane Measurements, Lattice Tech Note TN1027

4. ORCA ORT82G5 and ORT42G5 Data Sheet

5. ORCA ORSO82G5 and ORSO42G5 Data Sheet

53 tn1029_02

FPSC SERDES CML

Buffer Interface

April 2003 Technical Note TN1029

Introduction

This document discusses the high-speed serial buffers provided in Lattice’s ORT82G5, ORT42G5, ORSO82G5

and ORSO42G5 FPSC devices. These current mode logic (CML) buffers are part of a second generation Quad

SERDES macrocell design and provide the high-speed (1.0 to 3.7Gbps) serial data input and output ports. The

data sheet description of this device can be found in Reference 1. Por tions of this data sheet are included in this

document. Off-chip signal interface design and characteristics are the focus of this document. Interfacing to exter-

nal high-speed devices with LVDS and LVPECL ports is also discussed. Transmission line interconnections

between devices are required because of the high data rates. Practical considerations related to printed circuit

boards, cables and connectors that carry these signals are also touched on in this document.

CML Buffer Description

The SERDES macro uses 0.16 µm technology (0.16 µm drawn, 0.135 µm physical). Inter nal input and output ter-

minations are provided to simplify board level interfacing for the user. A simpliﬁed schematic of the serial input and

output buffers are shown below in Figure 1. The termination resistors and coupling capacitors are internal to the

macro.

The SERDES macrocell provides separate Rx and Tx power input nodes VDDIB and VDDOB for each channel,

allowing the receiver input termination and transmitter output termination to be biased at different level, indepen-

dent of the core VDD voltage (1.5V).

Figure 1. SERDES CML Buffer Schematic Diagram.

R = 86

R = 86 R = 50

R = 50

OUTPUT BUFFER INPUT BUFFER

CML TRANSMITTER CML RECEIVER

VTERM= VDDOB

15 mA Vterm= VDDIB

Vterm= VDDIB

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Interface Parameter Speciﬁcation

The high operational speed of the SERDES serial I/O makes understanding the interface parameters especially

important to the user. Proper inter pretation of the parameters is needed for successful integration within a system.

Signal interconnection performance, reliability and integrity are closely tied to these characteristics and their varia-

tional limits. This section attempts to summarize and discuss critical serial buffer interface parameters.

Correctly specifying the buffer I/O is a complex process. Methods used include extensive SPICE simulation and

laboratory measurements. The ofﬁcial speciﬁcation listing for the SERDES should be obtained from the Device

data sheet (Reference 1). Re vised issues of these documents will reﬂect updates and reﬁnements in buffer speciﬁ-

cations, as they are determined.

Input Buffer

Table 1 describes input buffer parameters and characteristics that are needed for application interface to other

printed wiring board devices.

Table 1. Rx Input Characteristics

Figure 2. Receive Data Eye-Diagram Template (Differential)

Symbol Parameter Conditions Min Typ Max Unit

TjOperating Junction Temperature -40 - 125 oC

RiInternal Buffer Termination Resis-

tance Each input, to VDDIB 40 50 60 Ω

Differential return loss Package dependent - - - db

Common-mode return loss Package dependent - - - db

VDDIB Input Termination Supply Voltage Externally supplied 0 1.5 /1.8 1.9 V

ViPeak Input Voltage Limits -0.3 - VDD +0.3 V

Common-mode Noise Tolerance VDDIB bias dependent TBD - - V

Internal Input ac-Coupling Time

Constant - 1.4 - µS

Clock and data recovery (CDR)

closed loop bandwidth -3-MHz

1.2 V

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Figure 2 provides an eye mask characterization of the SERDES receiver input. The eye-mask is speciﬁed in

Table 2 for two different eye-mask heights. It provides guidance on a number of input parameters, including signal

amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental char-

acteristics of trnasmit signal and the interconnection link design result in eye-closure. This, combined with the eye-

opening limitations of the line receiver, can provide a good indication of a link’s ability to transfer data error-free.

Table 2. Receiver Eye-Mask Speciﬁcations1

Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital

links and of systems with high noise le v el en vironments. An interesting characteristic of the clock and data reco v ery

(CDR) portion of the SERDES receiver is its ability to ﬁlter incoming signal jitter that is below the clock recovery

PLL bandwidth (estimated to be about 3 MHz). For signals with high levels of low frequency jitter the receiver can

correctly detect an incoming data stream, even with eye-openings signiﬁcant less than that of Figure 2. This phe-

nomenon has been observed in the laboratory.

Eye-diagram measurement and simulation are excellent tools of design. They are both highly recommended when

designing serial link interconnections and evaluating system signal integrity.

Parameter Conditions Value Unit

Input Data

Eye Opening Width (H)@ 3.125Gbps V=175 mV diff10.55 UIP-P

Eye Opening Width (T)@ 3.125Gbps V=175 mV diff10.15 UIP-P

Eye Opening Width (H)@ 3.125Gbps V=600 mV diff10.35 UIP-P

Eye Opening Width (T)@ 3.125Gbps V=600 mV diff10.10 UIP-P

Eye Opening Width (H)@ 2.5Gbps V=175 mV diff10.42 UIP-P

Eye Opening Width (T)@ 2.5Gbps V=175 mV diff10.15 UIP-P

Eye Opening Width (H)@ 2.5Gbps V=600 mV diff10.33 UIP-P

Eye Opening Width (T)@ 2.5Gbps V=600 mV diff10.10 UIP-P

1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter , all channels operating, FPGA logic activ e, REFCLK jitter

of 30 ps., TA = 0oC to 85oC, 1.425 V to 1.575 V supply, socketed device.

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Output Buffer

Table 3 describes output buffer parameters and characteristics that are needed for application interface to other

printed wiring board devices.

Table 3. Tx Output Characteristics

The CML outputs are designed to avoid damage with inadvertent short-circuit connections to ground and VDD.

Symbol Parameter Conditions Min Typ Max Unit

TjOperating Junction Tempera-

ture -40 - 125

VDDOB Output Termination Supply

Voltage Externally supplied 1.3 1.5 /1.8 1.9 V

RoInternal Buffer Termination

Resistance Internally tied to VDDOB 69 86 103 Ω

RlPreferred external

load Terminated to 1.5V/1.8V -50-W

Differential peak-to-peak out-

put Full-amplitude mode

Half-amplitude mode 0.8

0.4 1.0

0.5 1.2

0.6 V

VOH Output voltage - High VDDOB = 1.5V, 50Ω ext.

load to 1.5V

VDDOB = 1.8V, 50Ω ext.

load to 1.8V - 1.5

1.8 -V

VOL Output voltage - Low VDDOB = 1.5V, 50Ω ext.

load to 1.5V

VDDOB = 1.8V, 50Ω ext.

load to 1.8V - 1.0

1.3 -V

tr/tf Rise and fall time

(20% - 80%) Preferred ext. load (Rl)50 - 110 pS

Differential output skew Preferred ext. load (Rl)-5-+5 pS

Pre-Emphasis amplitude Low mode

High mode -+12.5

+25 -%

Lattice Semiconductor FPSC SERDES CML Buffer Interface

External Interface

The SERDES high-speed serial buffers were optimized to interface exter nally to other similar buffers. Direct inter-

connection of Lattice SERDES buffers requires no exter nal devices or components at the PCB level. Interconnec-

tion to other vendor's CML buffers is possible, but may require the addition of some passive components.

All interconnection circuits described in this section should use match length pairs of 50 ohm transmission line.

Each will provide characteristic impedance termination of the line to provide maximum signal bandwidth. 50 ohms,

an industr y standard, provides maximum compatibility and suits present printed wiring board technology intercon-

nections well, for circuit pack and backplane applications. It is also consistent with 100 ohm balanced transmission

line interfaces which are becoming popular for high bandwidth shielded pair cable connections.

LVDS Device Interface

LVDS, like CML is intended for low-voltage differential signal point-to-point transmission (Reference 3). Many com-

mercial LVDS devices provide internal 100 ohm input terminations. They are thus intended for use with 100 ohm

characteristic impedance transmission line connections. Standard LVDS is speciﬁed with about 3 mA signal current

which translates to a nominal signal voltage of 600 mVp-p (differential). Low power LVDS provides about 2 mA sig-

nal current. LVDS input and output parameters are shown in Table 4, as speciﬁed in the LVDS Standard.

Table 4. LVDS Parameters

Table 4 shows that LVDS devices have some degree of signal voltage range overlap with SERDES. Both use inter-

nal 100 ohm differential terminations at the receiver port. A direct interconnection of the two technologies, as

shown in Figure 3, is therefore possible.

Symbol Parameter Conditions Min Max Units

Driver Speciﬁcations

Voh Output voltage high Rload (dif)=100 ohm - 1475 mV

Vol Output voltage low Rload (dif)=100 ohm 925 - mV

|Vod| Output differential voltage Rload (dif)=100 ohm 250 400 mV

Ro Output impedance, single ended Vcm=1.0V to 1.4V 40 140 ohm

Receiver Speciﬁcations

Vi Input voltage range 0 2400 mV

Vidth Input differential threshold -100 +100 mV

Vhyst Input differential hysteresis 25 - mV

Rin Receiver differential input imped-

ance 90 110 ohm

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Figure 3. DC-Coupled SERDES CML to LVDS Interface

Within LVDS receivers , an internal input differential termination, of value 100 ohms , is typically provided. This termi-

nation resistor is usually ﬂoating with respect to ground. In the SERDES receiver the differential input ter mination

resistor is center-tapped and biased to a voltage equal to 1.5V or 1.8V. This is required for proper operation of the

output buffer. To properly drive the LVDS input from the SERDES output an e xternal 100 ohm resistor to VDDOB is

required on each output, as shown in Figure 3. Some LVDS devices provide a center-tapped input termination

resistor, internally. If this center-tap is accessible, a capacitor to ground can be added to provide an additional level

of immunity to system level common-mode noise.

In the LVDS to SERDES direction (lower por tion of Figure 3), a ﬂoating input termination resistor may be provided

by leaving the SERDES VDDIB pin ﬂoating. This provides a signal at the receiver input with a nominal common

mode voltage of 1.2V. The maximum voltage swing at each input is +/- 200 mV. This is within the acceptable input

voltage range of the receiver. A simple direct interface like this can be used in many applications. Higher common

mode noise tolerance may be achieved with alternate ac-coupled LVDS driver to SERDES receiver connection, as

shown in Figure 4.

Figure 4. AC Coupled LVDS to SERDES Scheme

86 86

AAN

VBIAS

ORCA

LVDS

VDDOB= 1.5V

50 50

100

VDDIB (leave floating)

100

SERDES

SERDES LVDS

50 50

VDDIB

1.5V

470

0.01uF

0.1uF

Lattice Semiconductor FPSC SERDES CML Buffer Interface

The signal coupling capacitors and resistive voltage divider circuit is added to translate the LVDS output signal to

the center of the SERDES input voltage range. This will increase the receiver tolerance to common-mode input

noise voltage, and provide a higher tolerance range to common-mode and system and ground noise. Note that

nominal resistor and capacitor values are shown in Figure 3 and Figure 4. Optimum values will var y in each appli-

cation.

Analog simulation of interface circuits can be a very useful par t of the design process. As a simple example, the

SERDES to LVDS interface portion of Figure 5 is simulated, using the HSPICE models for the SERDES output

buffer that is available from Lattice. Two 50 ohm ideal transmission lines of matched length were provided between

the SERDES output and the LVDS input, representing PCB traces. Figure 5 shows the resulting signal voltage

waveforms at the LVDS device input terminals, as predicted b y simulation. De vice pac kage parasitic-elements w ere

included. The P and N input common-mode (single-ended) and differential mode w aveforms are shown. A random-

digital signal pattern was used in the simulation to drive the SERDES buffer. Other parameters and conditions

assumed were nominal IC processing parameters, nominal supply voltage and room temperature. Figure 5 shows

a well behaved differential signal that should be an adequate LVDS input signal.

Figure 5. SERDES to LVDS Signal Simulation - Nominal Case

Add Bob results with. 100 ohm.

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Figure 6 repeats the simulation of Figure 5, but under some worst case conditions. Extreme IC process parame-

ters, low supply voltage, and 0 degree C temperature were assumed. The resulting waveforms in Figure 5 and

Figure 6 are well within the acceptable operating range of a typical LVDS device. One of the important functions of

circuit simulation is to v erify correct operation while varying parameters and operating conditions o v er the expected

range of variation.

Figure 6. SERDES to LVDS Signal Simulation - Worst Case

Lattice Semiconductor FPSC SERDES CML Buffer Interface

Low Voltage PECL Interface

Parameters for a typical LVPECL I/O device are listed in Table 5.

Table 5. Typical LVPECL I/O Speciﬁcations

A comparison of Table 5 with Table 1 and Table 3 will show that signiﬁcant signal I/O voltage and termination differ-

ences exist between LVPECL and SERDES. In both signal directions there is almost zero overlap in signal voltage

range. To interface these technologies, signal voltage offset must be provided by the interconnection circuit.

The proposed circuit for SERDES to LVPECL interconnection is shown in Figure 7.

Figure 7. DC-Coupled LVPECL Interface

Symbol Parameter Conditions Min Max Units

Driver Speciﬁcations

Voh Output voltage high Outputs terminated with 50 ohms

to Vcc-2.0V 2215 2420 mV

Vol Output voltage low Outputs terminated with 50 ohms

to Vcc-2.0V 1470 1680 mV

|Vod| Output differential voltage Outputs terminated with 50 ohms

to Vcc-2.0V 535 950 mV

Ro Output impedance, single ended Vcm=1.0V to 1.4V 3 10 ohm

Receiver Speciﬁcations

Vi Input voltage range, common-mode < 500mVp-p

> 500mVp-p 1.1

1.3 3.1

3.1 V

|Vin-diff.| Input voltage range, differential-

mode 200 > 2000 mVp-p

Iih Input HIGH current - 150 uA

Iil Input LOW current -600 - uA

Rin Receiver differential input imped-

ance No internal termination resistor

provided >> 50 - ohm

86 86

AAN

VBIAS

SERDES

LVPECL

VDDOB= 1.8 V VDD= 3.3 V

V=VDDOB

VDDIB

Lattice Semiconductor FPSC SERDES CML Buffer Interface

The circuit of Figure 7 minimizes external components and provides dc-signal coupling. The SERDES VDDOB

supply is used at the LVPECL input to bias the two 50 ohm termination resistors, which characteristically terminate

the transmission lines used for interconnection. The higher VDDOB value of 1.8V is preferred here to better align

signal v oltages . The LVPECL driver output bias current ﬂows through the series 62 ohm resistors and the SERDES

input internal 50 ohm ter mination resistors. This conﬁguration provides the voltage offset and attenuation required

for proper interface to the SERDES receiver. It also provides the matched transmission line termination for the

interconnection.

Figure 8 shows an AC-coupled SERDES/ECL interface.

Figure 8. AC-Coupled LVPECL Interface.

This interf ace circuit requires a higher number of e xternal components than the dc-coupled method, but will pro vide

tolerance to higher levels of common-mode system and ground noise. This is achieved by biasing the signal com-

mon-mode v oltage le v el near the center of the input range , at each receiv er. This method off ers ﬂe xib le signal offset

capability and can be adapted f or use with 5V PECL and -5V ECL interf ace applications . F or these cases , bias v olt-

age and resistor value modiﬁcations are required.

Note that nominal resistor and capacitor values are shown in Figure 7 and Figure 8. Optimum values may var y in

each application.

86 86

AAN

VBIAS

SERDES

LVPECL

VDDOB= 1.5 V or 1.8 V VDD= 3.3 V

3.3 V

VDDIB

0.01uF

100

0.01uF

130

100 100

50 0.01uF

100

130

0.01uF

1.5V or 1.8V

470

0.1uF

Lattice Semiconductor FPSC SERDES CML Buffer Interface

PCB, Connector and Cable Considerations

The sub-nanosecond rise time of the SERDES signals require very careful interconnection design techniques be

used at the PCB level. The key to successful interconnection is using consistent transmission line paths with mini-

mal discontinuities and true characteristic-impedance termination at the receive end of the line. Multi-layer lami-

nated PCB backplanes and daughter cards are recommended, for best results. Use of controlled impedance

connectors, PCB lines and cables provide the best result. Extensive test results for the ORT82G5 driving through a

real backplane system, can be found in Reference 3. A good discussion of high-frequency PCB design consider-

ations can be found in Reference 4.

Conclusion

Lattice SERDES serial I/O can be interfaced to LVDS, LVPECL, PECL and ECL technologies, as was described in

this document. As with any high-speed electrical interface, success depends on very careful design at all levels,

including the device package and printed wir ing board design. Designers should follow good high-frequency PCB

design practices, as described in Reference 4.

HSPICE models of the SERDES input and output buffers can be obtained through applications personnel. It is

highly recommended that they be used to verify the performance of SERDES interface circuits, in all applications.

High- frequency HSPICE models are available for many passive and active commercial components. Including

these will increase the accuracy of the simulation results and provide higher conﬁdence in the design integrity.

References

1. ORCA ORT82G5 and ORT42G5 Data Sheet

2. IEEE Standard for Lo w-Voltage Diff erential Signals (LVDS) f or Scalab le Coherent Interf ace (SCI), IEEE Std

1596.3-1996

3. ORT82G5 FPSC High-speed Backplane Measurements, Lattice Technical Note 1027

4. ORCA ORSO82G5 and ORSO42G5 Data Sheet

www.latticesemi.com 65 tn1032_01

SERDES Test Chip Jitter

July 2002 Technical Note TN1032

Introduction

The OR T82G5 Field Progr ammab le System Chip (FPSC) 1 contains two quad SERDES backplane interface bloc ks .

The two quad SERDES provide eight high-speed ser ial channel interfaces that are capable of data rates up to 3.7

Gbits/s. Each channel can transmit and receive simultaneously and provides full clock and data recovery. At high

data rates, jitter becomes a critical characteristic for error-free data transfer. This document discusses the device

jitter performance and presents laboratory test results showing SERDES transmit and receive jitter characteristics.

The test data was taken using a test chip that contained one quad macrocell, identical to the two quad macrocells

on the ORT82G5.

Transmit Jitter

Total Jitter Measurement

The laboratory test setup used to measure total SERDES transmit jitter is shown in Figure 1.

Figure 1. Transmit (Total) Jitter Measurement Setup

The serial data rate f or this test is 3.125 Gbits/s . A pseudo random bit stream test data pattern is applied to a SER-

DES channel, conﬁgured in parallel loop-back mode. The transmitter output wavefor m is obser ved in eye-diagram

form with a HP83480A sampling digital communications analyzer. Peak-to-peak and RMS time-jitter at the 50 per-

cent crossing level are calculated by the analyzer. The automated measurement process followed by the DCA

includes digitizing waveform segments of the incoming data signal into 1350 data point sets, and acquiring 3000 of

these waveform segments to calculate the jitter statistical parameters.

Test results are shown in Table 1. Three different devices with intentionally varied manufacturing process parame-

ters, were used in this experiment. The designations Fast, Nominal and Slow are used in Table 1 to indicate the

direction of each device bias. The pur pose was to broaden device population that was represented in the exper i-

ment. Temperature and supply voltage variations were also included in the experiment.

2^7-1 PRBS

Pattern Generator

ORT82G5 HP 83480A

HP 8656B

SERDES in

Parallel Loopback

Mode

Digital

Communications

Analyzer

Signal Generator

Ref CLK

Lattice Semiconductor SERDES Test Chip Jitter

Table 1. Transmit Jitter Measurement Result

The worst-case measurement seen in Table 1 shows a RMS jitter value of 8.3 pS and peak-to-peak value of 0.174

UI. All values in Table 1 are within the acceptable total jitter range for XAUI3, Fibre Channel4, and Inﬁniband5 stan-

dards, although the test pattern used may not be the speciﬁc type speciﬁed in each standard.

Jitter Component Measurement

Emerging high-speed interf ace standards are requiring that the different jitter components be identiﬁed in measure-

ments, and that each conform to speciﬁed limits. Appropriate measurement methods are still being devised and

debated. One common measurement method for decomposing the total jitter (TJ) into a random component (RJ)

and a deterministic component (DJ) is descr ibed in Reference 2. It uses a Bit-Error Rate Tester (BERT) combined

with a Time Interv al Analyzer (TIA) to generate transmit jitter bathtub-curve characterization. This is also discussed

in Reference 2. Preliminar y bathtub-cur ve testing of the ORT82G5 SERDES has been perfor med. Resulting bath-

tub-curves and the corresponding jitter component lev els are sho wn in Figure 2. Curves measured at sever al differ-

ent transmit data rates are shown, along with resulting jitter component breakdown for each curve.

Device Ambient

Temperature Voltage (V) Tx Jitter pS RMS Tx Jitter pS p-p Tx Jitter (UI)

Nominal 0°C 1.5 6.0 40.0 0.125

Nominal 25°C 1.5 6.1 46.7 0.146

Nominal 85°C 1.5 6.2 44.4 0.139

Slow 0°C 1.5 6.5 46.7 0.146

Slow 25°C 1.5 6.6 44.4 0.139

Slow 85°C 1.5 7.2 48.9 0.153

Slow 85°C 1.575 7.2 51.1 0.160

Fast 0°C 1.5 5.7 42.2 0.132

Fast 25°C 1.5 6.8 46.7 0.146

Fast 85°C 1.5 7.9 55.6 0.174

Fast 0°C 1.575 5.5 42.2 0.132

Fast 0°C 1.425 8.3 53.3 0.167

Lattice Semiconductor SERDES Test Chip Jitter

Figure 2. Preliminary Bathtub-Curve Measurement Results

Receive Jitter Tolerance

Receive jitter tolerance is a critical system interface parameter. It indicates the ability of the SERDES receiver to

recover incoming serial data in the presence of transit signal jitter and path generated jitter that is generally addi-

tive. Such jitter will be present in all applications, in varying degrees, but must be kept within the limits of the

receiver.

A receiv er's ability to tolerate incoming signal jitter is v ery dependent on jitter type. High-speed serial interface stan-

dards have recognized this fact and have recently modiﬁed speciﬁcations to indicate tolerance levels for the differ-

ent jitter types (such as those described in Section 2).

Jitter T olerance Measurement

As with transmit jitter measurement methods, receive jitter tolerance measurement methods have not been ﬁrmly

established. Preliminar y test effor ts have deﬁned one test method which provides jitter components and levels as

deﬁned for the 10G Ethernet XAUI standard3. The test setup for this method is shown in Figure 3.

RJrms = 0.0140UI

DJ = 0.0038UI

TJ = 0.2035UI

RJrms = 0.0179UI

DJ = 0.0062UI

TJ = 0.2611UI

RJrms = 0.0150UI

DJ = 0.1090UI

TJ = 0.3234UI

RJrms = 0.0000UI

DJ = 0.0553UI

TJ = 0.0553UI

RJ = Random Jitter

DJ = Deterministic Jitter

TJ = Total Jitter

2.5Gb/s

(a)

3.125Gb/s

(b)

2.5Gb/s

(d)

4.5Gb/s

(c)

Lattice Semiconductor SERDES Test Chip Jitter

Figure 3. XAUI Receiver Jitter Tolerance Test Setup

PJ = sinusoidal periodic jitter

RJ = random jitter

DDJ = data dependent jitter

A detailed discussion of the test setup and procedure may be found in Reference 2. The measured eye-diagram of

the incoming signal to the DUT in Figure 3, is shown in Figure 4.

Figure 4. Eye-Diagram for Receive Jitter Tolerance Test of Figure 3

Note that Figure 4 also shows a density function of the wav eform level transition crossings through the center (hor-

izontal) axis, between the second and third eye openings.

FM Source

10Hz - 10MHz Noise/Com

DDJ Injection

Pattern

100Hz - 1.5GHz

Random Noise

Filter / Backplane

Trace

Generator

BERT

Clock Source

Hybrid

Error

Detector

DUT

ORT82G5 SERDES

placed in parallel

loop-back mode

PJ Source

RJ Source

DDJ Source

Clock Source

Tx Rx

Lattice Semiconductor SERDES Test Chip Jitter

Jitter T olerance Results

A pass/fail test was perfor med. Each jitter source component in the setup was adjusted to XAUI speciﬁed levels3.

The same SERDES devices tested in Section 2 (and listed in Table 1) were used in this experiment. All tempera-

ture and supply v oltage parameter levels, as speciﬁed in Table 1, were included in this testing. A CJT test data pat-

tern was used. All testing performed passed the test criteria with measured bit error-rates of less than 1E-12.

Conclusion

Lattice FPSC SERDES transmit jitter generation and receive jitter tolerance have been measured and the results

described. The results to date indicate excellent device performance in both of these areas. A summary of jitter

requirements is shown in Table 2.

Table 2. Summary of Standards Jitter Requirements

*This standard is presently only speciﬁed at 1.065 Gbits/s rate

For the limited device test group used, all the transmit total-jitter measurement results were well within the limits of

all three standards listed in Table 2. The XAUI receive jitter-tolerance tests showed standard limit compliance for

the entire test group.

As system designers realize the importance of device jitter perf ormance, standards and measurement methods are

evolving and becoming more sophisticated. Additional device characterization is anticipated as the high-speed

serial data interface standards mature.

References

1. Lattice ORT82G5 Field Programmable System Chip, Data Sheet

2. Jitter Testing for Multi-Gigabit Backplane SERDES, IEEE 2002 International Test Conference, Proceedings draft

3. IEEE Draft P802.3ae/D3.3, XGMII/XGMS/XAUI section, October 2001

4. FIBRE CHANNEL 10 Gigabit (10GFC), T11/Project 1413-D/Rev 1.1, May 11, 2001

5. InﬁniBand Architecture Speciﬁcation Volume 2, Release 1.0-a, June 19, 2001

Standard Tx-Total Jitter Rx-Jitter Tolerance

XAUI 0.35 UI 0.65 UI

Fibre Channel 0.65 UI* 0.70 UI*

Inﬁniband 0.35 UI 0.65 UI

www.latticesemi.com 71 tn1025_02

Lock Times for the ORT82G5

and ORT42G5 SERDES

April 2003 Technical Note TN1025

Users of the ORT82G5 and ORT42G5 often are interested in the SERDES receiver’s performance during acquisi-

tion and re-acquisition (locking) on to the incoming high-speed serial data stream. However, this term can have

many meanings. For this reason, this note seeks to describe the various components of the acquisition process

and report the results of measurements of each component.

The ORT82G5 and ORT42G5 SERDES RX logic performs four levels of synchronization on the incoming serial

data stream. Each level builds upon the previous, providing ﬁrst bit, then byte (character), then channel (32-bit

word), and ﬁnally multichannel alignment. Each is described below.

Bit Alignment

Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-

tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL

is unable to lock to the serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator

(VCO), and periodically switches back to the serial data stream to again attempt synchronization. This process

continues until a valid input data stream is detected and lock is achieved.

The CDR can maintain lock on data as long as the input data stream contains an adequate data “eye” (i.e., jitter is

within speciﬁcation), maximum data stream run length is not e xceeded, and the average DC component of the sig-

nal is zero.

Bit alignment times fall into two categories: alignment from a no-signal condition, and re-alignment when the input

serial data stream experiences an abrupt phase change (as may occur when protection switching is performed

between two paths having different delays).

Alignment from a no-signal condition has two components. First, there is the re-acquisition to the data’s frequency

and phase. The time required for re-acquisition to the data’s frequency is minimized by logic that periodically

switches the PLL to lock to the REFCLK when it fails to lock on the serial data stream, thus limiting the VCO’s fre-

quency wander. Second, there is the time spent while the PLL is locking to REFCLK, which can be from zero to a

nominal maximum value of approximately 30 microseconds, depending on when the ser ial data stream becomes

valid in relation to the PLL’s switching to/from REFCLK.

Re-alignment is v ery quick, since the PLL’s VCO is already lock ed on frequency and only needs to adapt to the ne w

phase. In the lab, this re-alignment has been observed to nominally require approximately 300 nanoseconds at

3.125 GHz, which is 938 bit times.

It is possible to avoid the 30-microsecond delay while the CDR re-aligns to the REFCLK by using Control Register

bits ENBYSYNC‡ (to force synchronization to REFCLK) and/or TESTMODE‡ = E (to force synchronization to data).

Using these signals, the CDR can be made to attempt to lock on data precisely when the data stream becomes

valid. When these signals are used, care should be taken to ensure that the CDR’s PLL frequency does not wander

from its nominal value by limiting the time that the CDR is attempting to lock to an invalid data stream to 30 micro-

seconds. If this time is exceeded, lock time will become excessive.

Lattice Semiconductor Lock Times for the ORT82G5 and ORT42G5 SERDES

Byte Alignment

Byte alignment, as observed on signal BYTSYNC‡, occurs once valid bit alignment is achieved. The byte aligner

looks for a particular 7-bit sequence (either 0011111 or its complement, 1100000) that, in data that has been

8B/10B encoded per IEEE 802.3, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte align-

ment only occurs when the ENBYSYNC‡ signal for that channel is active HI, and re-alignment occurs on each 7-bit

sequence encountered. However, if ENBYSYNC‡ is asser ted active HI and no comma character is encountered,

and then is brought inactive LO, the channel will still perform one byte alignment operation on the next comma

character.

Byte alignment occurs immediately when an alignment sequence is detected, so lock time is only one clock period.

Word (32-bit) Alignment

Word (32-bit) alignment requires that the Fibre-Channel (XAUI_MODE‡ = 0) or XAUI (XAUI_MODE‡ = 1) state

machine has achieved the synchronized state.

Fibre-Channel Mode

In Fibre-Channel Mode, synchronization (WDSYNC‡ = 1) will occur after three ordered sets of data have been

received, in the absence of any code violations. After this, the next comma character will cause the output data to

be aligned such that the comma character is in the most signiﬁcant byte. Thus, three ordered sets plus a comma

character must be detected after byte sync is achieved before 32-bit word alignment occurs. The time required is

directly dependent on comma-character density. This has been veriﬁed in the lab. Note: once word alignment is

accomplished, no further alignment occurs unless and until WDSYNC goes to z ero and back to one again. Comma

characters that are not located in the most signiﬁcant byte position will not trigger further re-alignment while

WDSYNC is active. This behavior is as deﬁned by the Fibre-Channel speciﬁcation. But it means that, if the channel

exper iences an abrupt delay change (as could occur if an external MUX performs a protection switch between two

links), and the delay change is close enough to a full character or characters that not enough code violations are

generated to cause loss of WDSYNC, the channel could become misaligned and remain that way indeﬁnitely. This

behavior has been observed in the lab. As mentioned above, this is as deﬁned by the Fibre-Channel speciﬁcation.

This behavior can be a voided by pro viding a set of three consecutiv e “idle ordered sets” so that correct alignment is

guaranteed.

XAUI Mode

In XAUI mode, the state diagram in the data sheet indicates that three error-free code-groups containing commas

must be detected before synchronization is declared.

Multi (2, 4 or 8) Channel Alignment

Multi (2, 4 or 8) channel alignment does not occur until after 32-bit word alignment is complete. Alignment will not

occur until the last (most delayed) channel has been received. The maximum skew between the earliest and latest

channels cannot be greater than 18 cycles of the parallel receive data clock RWCK. At 78.125 MHz, this is 12.8 ns

X 18 = 230.4 ns maximum.

Lattice Semiconductor Lock Times for the ORT82G5 and ORT42G5 SERDES

Figure 1. Re-Lock After Positive Loop Delay Change

Re-Lock After Abrupt Loop Delay Change

Figure 1 displays the performance of the ORT82G5 and ORT42G5 when the high-speed serial bit stream experi-

ences an abrupt loop delay change in the serial link. Here, the delay change is caused by a switch into or out of

internal loopback, where the non-loopback path is looped back externally. The transmitter is sending an idle

ordered set every 32nd word. Code violations mark the beginning of the abrupt delay change. When the receiver

re-establishes phase lock and a comma character is recognized, code violations cease. Three comma characters

later, word sync is re-established. Word alignment is performed on the next comma character, at which time the

PRBS data checker implemented in the FPGA ceases to report errors.

Conclusion

In conclusion, the “lock time” can mean many things, but breaks down into the components outlined above: bit,

byte, word and multi-channel alignment. Once the chip has recovered from reset and REFCLK is stable, the time

required to lock onto a high-speed serial data stream is sub-microsecond. Further time required for byte synchroni-

zation, word synchronization, word alignment and multi-channel alignment depends on density of comma charac-

ters: one for byte sync, three for word sync, and one for word alignment. Multi-channel alignment occurs shortly

after the latest channel arrives. Table 1 below summarizes these values.

‡ Note: The various reference points mentioned in this article can be accessed as listed in Table 2 below.

Table 1. Summary of Lock Times

Synchronization Type Lock Time

Initial Bit Alignment 1-31 µsec

Bit Realignment 300 nsec (938 bit times @ 3.125 GHz) nominal

Byte Alignment Immediately upon encountering ﬁrst comma character

Word Alignment After encountering 3 additional comma characters (see text for further Fibre-Channel

and XAUI mode details)

Multi-Channel Alignment After alignment characters received from all channels being aligned

Code Viloation

Byte Sync

Word Sync

PRBS Error

Lattice Semiconductor Lock Times for the ORT82G5 and ORT42G5 SERDES

Table 2. List of Access Points

AA AB AC AD BA BB BC BD

XAUI_MODE 30820

(7) 30920

(7)

Testmode (4:0) 30006

(4:0) 30016

(4:0) 30026

(4:0) 30036

(4:0) 30106

(4:0) 30116

(4:0) 30126

(4:0) 30136

(4:0)

ENBYSYNC 30800

(0) 30800

(1) 30800

(2) 30800

(3) 30900

(0) 30900

(1) 30900

(2) 30900

(3)

BYTSYNC Not observable Observable, one channel at a time, on charac-

terization port pin AH31

WDSYNC Not observable Observable, one channel at a time, on charac-

terization port pin AJ34

www.latticesemi.com 75 tn1040_02

SERDES Reference Clock

April 2003 Technical Note TN1040

Introduction

This document discusses the ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5 FPSC devices [1] reference

clock input character istics and the selection/interconnection of the exter nal reference clock source. The reference

clock signal quality is critical to SERDES high speed signal interfaces, as is demonstrated in Appendix A. Clock

signal jitter can cause jitter generation at the transmit data output port and affect jitter tolerance of receiver data

input port. Care m ust be tak en in the selection and connection of the ref erence cloc k source to obtain optimum jitter

perfor mance. Several possible commercial oscillator manufacturers are identiﬁed and alter native interconnections

circuits are presented.

Reference Clock Input Characteristics

The OR T82G5, OR T42G5, ORSO82G5 and ORSO42G5 pro vide tw o separate REFCLK differential inputs, to allow

device operation under two different clock domains. Each REFCLK input port services four of the eight available

SERDES channels. Each differential input port has an internal differential ampliﬁer with signiﬁcant common-mode

signal rejection characteristics. The minimum required differential input level requirement is 500 mVp-p. The maxi-

mum input is 2 Vp-p. The input common-mode voltage may be set to any level which maintains each input peak

voltage between VDD and ground potential.

Clock Source Selection

A crystal oscillator or crystal oscillator-based clock source with differential output is recommended. The experiment

described in Appendix A shows that ref erence cloc k signal jitter does contribute directly to SERDES tr ansmit signal

jitter. It is therefore important to select a clock source with low jitter characteristics.The source should contain

power supply decoupling (inter nal and/or external) and ideally be located on the same circuit board as the SER-

DES device.

A number of crystal oscillator products on the mar ket are compatible with the ORT82G5, ORT42G5, ORSO82G5

and ORSO42G5. Several are listed in the table below.

Table 1. Crystal Oscillator Products Compatible with the ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5

Devices

Interconnection Circuit Alternatives

A diff erential output interconnection to the OR T82G5, ORT42G5, ORSO82G5 and ORSO42G5 is recommended to

minimize the conversion of system common mode noise into clock signal jitter. This is achieved by taking advan-

tage of the common-mode rejection of the internal differential receiver. If the source signal is shared with other

devices or inputs on the circuit board, it is recommended that high speed differential buffering be provided to dis-

tribute a dedicated differential output signal to each device reference clock input.

The recommended interconnection of a 3.3V LVPECL Reference Clock source to the Quad SERDES input port is

shown in Figure 1.

Vendor Model Output Comments

Connor Winﬁeld [6] P123 LVPECL small size SMD package

Epson [3] EG-2101CA PECL SMD package, 50ppm

MF Electronics [5] M2980 LVPECL thru-hole/ gull-wing pkg, low jitter speciﬁed

Saronix [2] SDS3811 LVDS SMD package, to 20ppm

Vectron [4] XO-480 LVPECL or LVDS SMD package, to 10ppm

Lattice Semiconductor SERDES Reference Clock

Figure 1. DC Coupled LVPECL Interface

The dc coupling scheme from the 3.3V LVPECL clock signal buffer output allows a minimal number of discrete

components in the interconnection circuit.

Figure 2. DC-Coupled LVDS Interface

The standard LVDS output dc voltage is compatible with the ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5

RefClk input, allowing a very simple interface circuit. The single termination resistor should minimize the possibility

of system generated EM noise coupling into the reference clock signal.

3.3V R4=50

R3=50

R1=62

R2=62

ORT82G5,

T1=50

T2=50

Buffer

LVPECL

REFCLKP_x

REFCLKN_x

Ω

ΩΩ

Ω

ΩΩ

ORT42G5,

ORSO82G5

or ORSO42G5

3.3V

R3=100

T1=50

T2=50

Buffer

LVDS

REFCLKP_x

REFCLKN_x

Ω

ORT82G5,

ORT42G5,

ORSO82G5

or ORSO42G5

Lattice Semiconductor SERDES Reference Clock

Figure 3. AC-Coupled PECL Interface

A conventional ECL source ter minated conﬁguration is used with ac coupling. Resistive voltage divider biasing of

the Reference Clock input pins must be provided.

Applications where SERDES jitter performance is not critical may consider using single-ended reference clock

interconnections. Such interconnections have been successfully used in laboratory testing. For these cases, exter-

nal biasing and capacitiv e bypassing of the unused input must be pro vided. These applications may also choose to

drive both reference clock ports of the ORT82G5, ORT42G5, ORSO82G5 or ORSO42G5 with a single clock

source output. Care must be taken to minimize trace lengths between the transmission line, line termination resis-

tors, and Reference Clock input pins.

PCB Layout Recommendations

To minimize differential clock signal noise and jitter at the ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5

device input, the T1/T2 transmission line connection path should have the following characteristics:

• adjacent stripline point-to-point 50 ohm transmission lines or coupled adjacent lines with 100 ohm differential

characteristic impedance

•matched length, to within 0.05 inch (1.27mm)

• cross-talk coupling to other signal traces on the PCB minimized

• stripline implementation

• The discrete components in Figures 1 and 3 should be placed according to the following recommendations:

• PCB connection trace lengths should be kept as short as possible.

• Corresponding components on the P and N signal sides should be placed close to each other, to minimize sys-

tem coupled differential noise.

Conclusion

The ORT82G5, ORT42G5, ORSO82G5 and ORSO42G5 SERDES jitter performance is sensitive to the external

reference clock signal jitter. For best performance, a differential transmission line clock signal should be used.

Interconnection circuits f or sever al oscillator output formats were recommended and described. Careful PCB lay out

with some speciﬁc recommendations was presented. Several possible oscillator vendors were identiﬁed.

R4=

R2=

R6=50

T1 50

Buffer

PECL

R3=

R1=

T2 50

R5=50

R8=

R7=

270

VDD=1.5V

C1=100pF

C2=100pF

REFCLKP_x

REFCLKN_x

Ω

ΩΩ

Ω

ORT82G5,

ORT42G5,

ORSO82G5

or ORSO42G5

Lattice Semiconductor SERDES Reference Clock

References

1. ORCA ORT82G5 and ORT42G5 Data Sheet

2. Saronix, http://www.saronix.com/

3. Epson Electronics America, http://www.eea.epson.com/go/products/displayCategory?catego-

ryId=EEA.QD.Crystal_Oscillators

4. Vectron International, http://www.vectron.com/

5. MF Electronics, http://www.mfelectronics.com/products/xo/

6. Connor Winﬁeld, http://www .conwin.com

7. ORCA ORSO82G5 and ORSO42G5 Data Sheet

Lattice Semiconductor SERDES Reference Clock

Appendix A - SERDES Jitter Sensitivity

A simple experiment was performed in the laboratory to determine the effect of reference clock input jitter on

OR T82G5, OR T42G5, ORSO82G5 and ORSO42G5 SERDES tr ansmit jitter. Sinusoidial jitter w as injected onto the

ref erence clock signal, while observing SERDES output signal jitter. DCA measured eye-diag ram wavef orms of the

data output signal and reference clock input signal are shown in the following 4 ﬁgures. Figure 4 is with no jitter

added. Figures 5, 6, and 7 are with sinusoidial jitter added to the reference clock signal. The frequency of the jitter

signal is indicated in each of these ﬁgures. Note that in all four Figures, a density function of the reference clock

transitions (horizontal axis crossing, at the center level) is shown.

Figure 4. Transmit Data Output & Ref Clk Eye-Diagrams with No Jitter Added

Figure 5. Transmit Data Output & Ref Clk Eye-Diagrams with 10 KHz Jitter Added

Lattice Semiconductor SERDES Reference Clock

Figure 6. Transmit Data Output & Ref Clk Eye-Diagrams with 100 KHz Jitter Added

Figure 7. Transmit Data Output & Ref Clk Eye-Diagrams with 500 KHz Jitter Added

Discussion

Comparing Figure 4 to Figure 5, it can been seen that adding jitter to the reference cloc k signal causes an increase

in transmitter output signal jitter. Observing the amount of jitter on the two wa v eforms in Figures 5 through Figure 7,

it can be seen they are approximately the same. The conclusion drawn from this experiment is that there is a 1 to 1

jitter transf er from the reference clock signal to the tr ansmit output signal. This is an expected result which will apply

to jitter frequencies below about 5 MHz (the closed loop bandwidth of the SERDES transmit clock PLL).

www.latticesemi.com 81

Introduction to the sysHSI

Block

ispXPGA and ispGDX2

April 2003 Technical Note

™

™™

Introduction

Embedding clocks into serial data streams is a popular technique in high-speed data communications systems

applications. The embedded clock is reco vered at the receiver by a Clock and Data Reco very (CDR) circuit. Source

Synchronous mode provides another way of achieving high speed data rate without embedding the clock.

Lattice provides sysHSI blocks on ispXPGA and ispGDX2 device families to support both embedded clock and

source synchronous clocking applications. This document provides an introduction to the sysHSI Blocks. Refer to

Technical Note TN1020 for detailed description.

Modes of Operation

The sysHSI block suppor ts number of different modes. In Clock Data Recover y (CDR) mode, clock is encoded in

the transmit data stream and CDR reco vers this clock from the incoming data. In Source Synchronous Mode, clock

is transmitted along with data via a separate channel.

Three fuse programmable modes and their related system speciﬁcations are summarized in Table 1.

Table 1. Fuse Programmable Modes

CDR Mode

In CDR mode clock is encoded in serial data streams to achieve higher data transfer rates. This is achieved by

encoding the transmitted data in such a way as to ensure a minimum number of clock transitions. From this mini-

mum number of transitions a complete clock can be recovered at the receiver.

The sysHSI block suppor ts two encoding options. In both options the sysHSI block recovers data using 16 times

over-sampling. This leads to better performance than many other solutions that use lower over-sampling rates.

SERDES without Encoding/Decoding (8B/10B: Encoding and Decoding is not included)

This mode supports serial links that use the common 8B/10B encoding scheme. With this scheme eight bits of data

are encoded into 10 bit symbols to ensure a minimum of 40% transition in every 10-bit code.

In 8B/10B mode the sysHSI block does not encode or decode the data. The block receives encoded 8B/10B data

as 10-bit wide parallel data and transmits it serially. It receives serial data and converts it to 10-bit wide 8B/10B

encoded data. This data can be re-transmitted or decoded elsewhere dependent on the application needs.

SERDES with Encoding (10B/12B: Encoding and Decoding is done by sysHSI Block)

This mode supports serial links that use 10B/12B encoding. This high speed serial data f ormat consists of 10 data

bits plus 2 ﬁxed insertion bits (01) to ensure a minimum of two transitions for every 12 bits in the serial data

stream.

Mode Data

Code Serial Data

Rate (Mbps)

Pay Load

Data Rate

(Mbps)

Parallel

Data/Clk

(MHz) Parallel Data

Width

Serial/

Parallel

Ratio

Symbol

Alignment

Pattern CDR

Support

SERDES without

Encoding/Decoding 8B/10B 400 to 850 320 to 680 40 to 85 10b

Encoded 10 K28.5 +/- CDR

SERDES with

Encoding/Decoding 10B/12B 400 to 850 333 to 708 33.3 to 70.8 10b

Raw Data 12 SymPat CDR

Source-Synchronous

(n channels) N/A 400 to 800 n x (400

to 800) 50 to 100

67 to 133

100 to 200

n x 8b

n x 6b

n x 4b

4SymPat1

(De-skew) De-skew

(optional)

1. In Source-Synchronous mode, only De-skew mode requires symbol alignment.

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

Source-Synchronous(SS) Modes

Some users are implementing source synchronous clocking to achieve high speed data transfer. Here the clock is

transmitted along with the data. This remo v es the propagation dela y betw een the transmitter and receiv er as a limit

on clock speed and performance. Skew control and other factors limit the maximum performance that can be

achieved using this method of data transfer. Multiple sysHSI blocks can be combined to create source synchro-

nous interf aces of diff erent widths . The maximum width supported is de vice dependent. These interfaces can oper-

ate in two modes.

Normal Mode SS Mode (with Optional Phase Adjustment)

Normal Mode without Phase Adjustment:

In normal source synchronous mode data for each channel is captured using a common phase shifted version of

the incoming clock. This mode is useful in smaller devices where clock-tree skew is minimum.

Normal Mode with Phase Adjustment:

Optional Phase Adjustment is provided in this mode . The kno wn sk e w adjustment phase v alue can be prog rammed

by user.

De-Skew SS Mode

In this mode, a calibration cycle allows the CDR circuitr y to be used to select per channel different phases of the

incoming clock with which to capture the incoming data. This allows the device to compensate for ﬁxed system

level skews. Thus allowing designers to achieve higher perfor mance by conducting a calibration cycle at system

start up.

sysHSI Block

Each sysHSI Block includes two SERDES units and one CSPLL. Each SERDES unit consists of one receiver and

one transmitter circuit block. Each pair of receiver and transmitter can be used as a full duplex channel. For receiv-

ing, the SERDES receives high speed serial input data stream from the sysIO differential input buffer and provides

low speed parallel data associated with recovered clock to synchronizer or core logic. For transmitting, the SER-

DES converts the parallel low speed data to high speed serial data stream and sends the data to the sysIO LVDS

differential output buffers. Figure 1 shows high level representation of a sysHSI Block.

Figure 1. sysHSI Block Diagram

There is always a 10-bit wide data transmitted or received at the low speed side of the SERDES for both 10B/12B

and 8B/10B modes. In 10B/12B encoding mode, the start bit(1) and stop bit(0) are added or removed within the

sysHSI Block. In SERDES mode without encoding/decoding, (currently 8B/10B mode is suppor ted), the encoding

SS MODE ONLY

sysIO

CORE

LOGIC

CORE

LOGIC

HSTCLK

HSRCLK

sysHSI Block

TXD_A

TXD_B

RXD_B

RXD_A

REFCLK from

CLOCK TREE

TRANSMITTER

RECEIVER

TRANSMITTER

CSPLL

RECEIVER

SERDES (HSI_A)

SS_CLKOUT

SS_CLKIN

SOUT_A

SIN_A

SOUT_B

SIN_B

Synchro-

nizer

Synchro-

nizer

SERDES (HSI_B)

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

and decoding is done outside of sysHSI Block where 10-bit wide data is expected at the low speed side of the

SERDES. This is wh y the n umber of data bits at the parallel interface f or 10B/12B and 8B/10B are same. In Source

Synchronous Mode, the low speed parallel data bits can be programmed to 4, 6 or 8.

The recovered clock is asynchronous to the on-chip reference clock. The solution to this problem is to use a syn-

chronizer. In systems where frequency deviation is not a problem this synchronizer can be bypassed.

CSPLL: Clock Synthesizer PLL

CSPLL (Clock Synthesizer PLL) multiplies low speed reference clock by the factor of v to achieve an high speed

serial data rate clock. The low speed reference clock input can be either from a chip internal clock, REFCLK, or

from an external LVDS clock input, SS_CLKIN. Also, there are 4 choices for the internal clock to increase the ﬂex-

ibility.

\The multiplication factor, v, is the ratio of high speed vs. low speed. It can be 4, 6, or 8 for Source Synchronous

mode, 12 for 10B/12B and 10 for 8B/10B mode. CSPLL contains a fully monolithic analog PLL which does not

require any external component. For transmitter, the HSTCLK (High Speed Transmit Clock) is gener ated from REF-

CLK multiplied by factor of 'v', and is used to clock the high speed Serial Data Output.

For CDR operation, the CSPLL combined with a phase interpolation circuit, generate 16- phase high speed Clocks ,

HSRCLK<0:15>(High Speed Receive Clock).

Figure 2. CSPLL

CSPLL HSRCLK (0:15)

1/16th

Phase

Shifter

Phase Select from CDR

M div

SS_CLKIN

REFCLK

HSRCLK

HSTCLK

V div

N div

VCO

SS_CLKOUT

CSLOCK

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

Clock and Data Recovery

Each receiver channel has its own CDRPLL (Digital Phase-Locked Loop: DPLL) for Clock Data Recovery. The

Clock Recovery module ﬁrst extracts the embedded high speed clock from the Input Serial Data Stream by means

of the CDRPLL. Then the Data Recovery Module uses the recovered clock to read the data from the high speed

Input Serial Data Stream.

The recovered high speed clock is divided by the factor, v, and aligned to produce the low speed clock, RECCLK

(RECovered CLocK). CDR then de-serializes the recovered high speed Serial Data into low speed Parallel Data.

This RECCLK and parallel data are sent to synchronizer or core logic.

Figure 3. Clock and Data Recovery Block

Serializer / De-Serializer(SER/DES)

Serializer

Transmitter receives low speed parallel Data, TXD, from the Synchronizer or Core Logic. TXD data is clocked by

REFCLK from clock tree (or SS_CLKIN in SS mode). The CSPLL multiplies REFCLK by factor of v to generate

HSTCLK. The Transmitter conver ts the low speed parallel Data, TXD, into high speed Serial Data Stream, SOUT,

that is running at HSTCLK. The alignment circuit synchronizes REFCLK and HSTCLK with edge detect circuit to

align SOUT with HSTCLK.

Figure 4. Serializer [SS, 8B/10B]

SIN

CDRRST

Clock / Data Recovery

Phase Select(0:15)

Recovered Serial Data

Align

CDRLOCK

EXLOSS LOSS

Recovered

HSR Clock

SYDT

1/ V

SYMBOL

DETECT

CDRPLL

Phase

Detect Digital

Filter Phase

Shift

RECCLK

HSTCLK from CSPLL

LS Clock

(HSTCLK ÷ v)

from CSPLL

SERIALIZER

[SS, 8B/10B]

(SOUT)

to sysIO

Differential

Output Buffer

Qv-1

Parallel Load

Qv-1

Parallel Sync

Qv-1

Shift Register

Align

Parallel Load

v Bit Wide Parallel Data (TXD)

from Synchronizer or Core Logic

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

De-Serializer

Receiver receives high speed serial data stream, SIN, from sysIO and de-ser ializes into low speed Parallel Data,

RXD, before it sends to Synchronizer or core logic.

Figure 5. De-Serializer [SS, 8B/10B]

Synchronizer

In the Receiver, the sysHSI Block writes with Recovered Clock (RECCLK) and the Core Logic uses system clock

(usually REFCLK) to read. Depending on devices, FIFO or Embedded Memory Block are used as a synchronizer.

The usage of a synchronizer is optional and may be bypassed if users performs synchronization outside of the

device.

Parallel Transmit Data enters Transmitter of sysHSI block from core logic clocked by REFCLK. The REFCLK at the

same time is fed to CSPLL to generate high speed clock to transmit serialized data (HSTCLK). In the Transmitter,

the REFCLK is re-aligned by high speed clock to generate parallel load clock to the Ser ializer shift register. If the

skew between REFCLK and high speed Clock at Transmitter is larger than one high speed Clock cycle then a syn-

chronizer is required. Since the CSPLL drives only two tr ansmitter and tw o receiver channels, the skew is manage-

able without synchronizer. Figure 6 shows the synchronizer interface between core logic and receiver.

Figure 6. Synchronizer

RXD

Qv-1

Shift Register

Recovered

Serial Data

Recovered

HSRCLK

Qv-1

Parallel Load

DE-SERIALIZER

[SS, 8B/10B]

LS Clock ( HSRCLK ÷ v = RECCLK)

One of 16

Phase-shift

CLK

(HSRCLK)

from CSPLL

(SIN)

from sysIO

Differential

Input Buffer

v Bit Wide Parallel Data (TXD)

from Synchronizer or Core Logic

Clock Data Recovery Circuit (CDRPLL)

Synchronizer

Write

Data Read

Data

Write

CLK Read

CLK

CORE

LOGIC

REFCLK from Clock Tree

SYNCHRONIZING RECOVERED DATA WITH CORE LOGIC

(SIN)

LVDS

Data

(SS_CLKIN)

LVDS

Clock

Receiver

RXD

RECCLK

CDRLOCK Write

CSPLL

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

sysHSI Block and Source-Synchronous Mode with Multiple Data Channels

Each chip includes 2 groups of sysHSI Blocks. All sysHSI Blocks of the same group share the same LVDS clock

input/output in Source Synchronous mode.

In this mode, a whole group or a portion of a group can be used. The LVDS Clocks, SS_CLKIN and SS_CLKOUT,

are connected to dedicated pins. Each group can be conﬁgured as either Receive mode or Transmit mode but not

both. In Receive mode, the incoming LVDS Clock (SS_CLKIN) is the input clock to CSPLL as a reference clock . In

Transmit mode, the reference clock source is one of four clocks from the Clock Tree. The LVDS output Clock,

SS_CLKOUT is generated from the CSPLL of the dedicated sysHSI Block in each group.

An e xample of Source-Synchronous Mode Block diagram is sho wn in Figure 7. Figure 7 illustrates how the HSI cir-

cuit is implemented in Source-Synchronous Receiver Mode.

Figure 7. Source-Synchronous Mode Example Diagram (CDRX_SS_8)

sysIO

6 DATA CHANNELS and 1 CLOCK CHANNEL for CDRX_SS_8 Mode

CSPLL

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_A

SIN_A

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_B

SIN_B

SS_CLKIN

CSPLL

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_A

SIN_A

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_B

SIN_B

CSPLL

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_A

SIN_A

CORE

LOGIC

TRANSMITTER

RECEIVER

HSI_BSIN_B

sysHSI Block_1

CSPLL

sysHSI Block_2

sysHSI Block_3

SYNCHRO

NIZER

RXD_A

RECCLK_A

SYNCHRO

NIZER

RXD_B

RECCLK_B

SYNCHRO

NIZER

RXD_A

RECCLK_A

SYNCHRO

NIZER

RXD_B

RECCLK_B

SYNCHRO

NIZER

RXD_B

RECCLK_B

SYNCHRO

NIZER

RXD_A

RECCLK_A

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

sysHSI Block Usage in CDR Mode

When both channels are used in a same sysHSI Block, the y m ust share the same REFCLK, HSRCLK (High Speed

Receiver Clock) and HSTCLK (High Speed Transmitter Clock) from the CSPLL. Multiple modes may be imple-

mented using different sysHSI Blocks but user must take phase jitter from different clock sources into consider-

ation. This jitter increase may both receiver and transmitter performance to fall outside the guaranteed

speciﬁcations.

The two SERDES Blocks, HSI_A and HSI_B, in the same sysHSI Block are independent from each other except

sharing the same REFCLK and CSPLL.

sysHSI Block USAGE in Source-Synchronous Mode

When sysHSI Blocks are conﬁgured as Source-Synchronous mode, the whole group is not available for other

modes. But the sysIOs of unused sysHSI channels are available for other general I/O uses.

Using sysHSI Blocks in Design Tools

Macro Symbols

Thirteen Functional Macro modules are available representing seven different applications. These programmable

modules are described in Table 2. Additionally, two macros are provided for high speed loop back testing and are

supported for 8B/10B and 10B/12B modes.

Table 2. Macro Deﬁnitions

sysHSI Usage with HDLs

Synthesis tools such as Synplicity and Exemplar "black-box" the VHDL and Verilog instantiations and pass them

through an EDIF netlist to the Lattice software. The Lattice software conver ts the "black-box" into the physical rep-

resentation of the sysHSI within the device using the macros deﬁned above. Verilog and VHDL pass the sysHSI

attributes through parameters and generics, respectively.

Unlike other HDLs , ABEL requires special additions to support sysHSI functionality, the Lattice design tools provide

direct support for ABEL and have been modiﬁed to support sysHSI functionality.

Mode Symbol Description

SS RX_SS_x1SS normal receive mode (no de-skew)

CDRX_ SS_x SS De-skew receive mode

TX_ SS_x SS transmit mode

10B12B CDRX_10B12B 10B/12B CDR receive mode

TX_10B12B 10B/12B transmit mode

8B10B CDRX_8B10B 8B/10B CDR receive mode

TX_8B10B 8B/10B transmit mode

8B10B HSLB_8B10B 8B/10B High Speed Loop Back mode

10B12B HSLB_10B12B 10B/12B High Speed Loop Back mode

1. x: Data width, 4, 6 or 8 resulting the total number of macros are 15.

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

ispXPGA Family

The block diagram of LFX1200 is shown in Figure 8.

Figure 8. ispXPGA-1200 Block Diagram

sysMEM™ Embedded RAM (EBR) Usage as FIFO

spXPGA Family includes sysMEM Embedded Block RAM that can be programmed as a FIFO for synchronization.

For macros available for the EBR, please refer to Lattice technical note number TN1028, ispXPGA sysMEM Mem-

ory Design and Usage Guidelines

PFU

62 PICs

sysIO BANK 3sysIO BANK 2

sysIO BANK 6sysIO BANK 7

sysIO BANK 0

62 PICs

sysIO BANK 1

8 Prgrammable sysIO banks

62 PICs per bank

2 sysHSI Groups (left and right side)

Each sysHSI Group has 5 sysHSI Blocks

sysHSI Block (0, 1, 2)

sysHSI Block (7, 8, 9)sysHSI Block (4, 5)

sysHSI Block (3, 4)

sysMEM Block

sysMEM Block sysMEM Block

sysMEM Block

sysMEM Block PLL PLL PLL PLL

PLL PLL PLL PLL

sysIO BANK 5sysIO BANK 4

62 PICs

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

ispGDX2 Family

sysIO Banks and sysHSI Blocks

The ispGDX2 family devices are designed to minimize clock tree skew for high speed interface applications. The

sysHSI sub-blocks, HSI_A and HSI_B are routed to nearest sysIO Bank.

The ispGDX2-256 has 8 sysHSI Blocks. Each sysHSI Block is divided to two SERDES blocks, HSI_A and HSI_B.

Each SERDES block occupies 16 IO Cell Block in the sysIO Bank.

Figure 9. ispGDX2 sysIO Bank and sysHSI Block

B sysHSI_2 A

B sysHSI_4 A

sysHSI_5

sysI/O Bank 5

sysI/O Bank 2

sysI/O Bank 6

sysI/O Bank 7 sysI/O Bank 0

sysI/O Bank 4 sysI/O Bank 3

sysI/O Bank 1

sysHSI_6

ispGDX2-256

Core

sys

CLOCK sys

CLOCK

sys

CLOCK sys

CLOCK

sysHSI_0

sysHSI_7

sysHSI_1 sysHSI_3

Lattice Semiconductor Introduction to the sysHSI Block / ispXPGA and ispGDX2

FIFO

sysHSI Block Interface with FIFO

The ispGDX2 Family includes dedicated FIFO for synchronization of recovered data. The FIFO is 15 x 10 and is

intended to support CDR. The usage of FIFO is optional.

Figure 10. sysHSI Block interface with FIFO in ispGDX2

HSTCLK

TXD

TRANSMITTER

RECEIVER

HSI

SOUT

SIN

HSRCLK

LOSS

SYDT

CDRRST

EXLOSS

REFCLK ( from Clock Tree)

SS_CLKIN

SS_CLKOUT

POR

RESETb

CDR/FIFO RESETb

sysIO Bank

CSLOCK

CSPLL

GDX

BLOCK

START READ

FIFO

15 x 10

RESETDATAOUT

RCLK

FULL

EMPTY

START READ

DATAIN

WCLK

RCLK

REN

FULL

EMPTY

RXD

RECCLK

CDRLOCK

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