++
+
VIN BST
RON
RTN
SW
VCC
FB
VIN VOUT
RFB1
RC
RUV1
RON
COUT
CBST
CIN
RFB2
RUV2
L1
UVLO
+
CVCC
LM5017
7.5V-100V
1
2
3
4
5
6
8
7
SD
LM5017
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SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
LM5017 100 V, 600 mA Constant On-Time Synchronous Buck Regulator
Check for Samples: LM5017
1FEATURES DESCRIPTION
2• Wide 7.5 V to 100 V Input Range The LM5017 is a 100 V, 600 mA synchronous step-
• Integrated 100 V, High and Low Side Switches down regulator with integrated high side and low side
• No Schottky Required MOSFETs. The constant-on-time (COT) control
scheme employed in the LM5017 requires no loop
• Constant On-time Control compensation, provides excellent transient response,
• No Loop Compensation Required and enables very low step-down ratios. The on-time
• Ultra-Fast Transient Response varies inversely with the input voltage resulting in
nearly constant frequency over the input voltage
• Nearly Constant Operating Frequency range. A high voltage startup regulator provides bias
• Intelligent Peak Current Limit power for internal operation of the IC and for
• Adjustable Output Voltage from 1.225 V integrated gate drivers.
• Precision 2% Feedback Reference A peak current limit circuit protects against overload
• Frequency Adjustable to 1 MHz conditions. The undervoltage lockout (UVLO) circuit
allows the input undervoltage threshold and
• Adjustable Undervoltage Lockout (UVLO) hysteresis to be independently programmed. Other
• Remote Shutdown protection features include thermal shutdown and
• Thermal Shutdown bias supply undervoltage lockout (VCC UVLO).
The LM5017 is available in WSON-8 and SO
APPLICATIONS PowerPAD-8 plastic packages.
• Smart Power Meters
• Telecommunication Systems
• Automotive Electronics
• Isolated Bias Supply
• Packages:
– WSON-8
– SO PowerPAD-8
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UVLO 3
RON 4
RTN 1
VIN 2
8 SW
7 BST
6 VCC
5 FB
SO
PowerPAD-
8Exp Pad
SW
BST
VCC
FB
8
7
6
5
1
2
3
4
UVLO
RON
RTN
VIN WSON-8
Exp Pad
LM5017
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
www.ti.com
Connection Diagram
Figure 1. Top View (Connect Exposed Pad to RTN) Figure 2. Top View (Connect Exposed Pad to RTN)
Pin Descriptions
Pin Name Description Application Information
1 RTN Ground Ground connection of the integrated circuit.
2 VIN Input Voltage Operating input range is 7.5 V to 100 V.
3 UVLO Input Pin of Undervoltage Comparator Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current
source is enabled when UVLO is above 1.225 V to
provide hysteresis. When UVLO pin is pulled below 0.66
V externally, the parts goes in shutdown mode.
4 RON On-Time Control A resistor between this pin and VIN sets the switch on-
time as a function of VIN. Minimum recommended on-
time is 100ns at max input voltage.
5 FB Feedback This pin is connected to the inverting input of the internal
regulation comparator. The regulation level is 1.225 V.
6 VCC Output from the Internal High Voltage Series Pass The internal VCC regulator provides bias supply for the
Regulator. Regulated at 7.6 V gate drivers and other internal circuitry. A 1.0 μF
decoupling capacitor is recommended.
7 BST Bootstrap Capacitor An external capacitor is required between the BST and
SW pins (0.01 μF ceramic). The BST pin capacitor is
charged by the VCC regulator through an internal diode
when the SW pin is low.
8 SW Switching Node Power switching node. Connect to the output inductor
and bootstrap capacitor.
EP Exposed Pad Exposed pad must be connected to RTN pin. Connect to
system ground plane on application board for reduced
thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
VIN, UVLO to RTN –0.3 V to 100 V
SW to RTN –1.5 V to VIN +0.3 V
SW to RTN (100 ns transient) –5 V to VIN +0.3 V
BST to VCC 100 V
BST to SW 13 V
RON to RTN –0.3 V to 100 V
VCC to RTN –0.3 V to 13 V
FB to RTN –0.3 V to 5 V
ESD Rating (Human Body Model(3) 2 kV
Lead Temperature (4) 200°C
Storage Temperature Range –55°C to +150°C
Maximum Junction Temperature 150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
The RTN pin is the GND reference electrically connected to the substrate.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5 kΩresistor into each pin.
(4) For detailed information on soldering plastic SO PowerPAD package, refer to the SNOA549 available from Texas Instruments. Max
solder time not to exceed 4 seconds.
Recommended Operating Conditions(1)
VIN Voltage 7.5 V to 100 V
Operating Junction Temperature −40°C to +125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
The RTN pin is the GND reference electrically connected to the substrate.
Thermal Characteristics(1)
WSON-8 SO PowerPAD-8 UNIT
θJA Junction-to-ambient thermal resistance 41.3 41.1 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 3.2 2.4 °C/W
ΨJB Junction-to-board thermal characteristic parameter 19.2 24.4 °C/W
θJB Junction-to-board thermal resistance 19.1 30.6 °C/W
θJCtop Junction-to-case (top) thermal resistance 34.7 37.3 °C/W
ΨJT Junction-to-top thermal characteristic parameter 0.3 6.7 °C/W
(1) The package thermal impedance is calculated in accordance with JESD 51.
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Electrical Characteristics
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48 V, unless otherwise stated. See (1).
Symbol Parameter Conditions Min Typ Max Units
VCC Supply
VCC Reg VCC Regulator Output VIN = 48 V, ICC = 20 mA 6.25 7.6 8.55 V
VCC Current Limit VIN = 48 V(2) 26 mA
VCC Undervoltage Lockout Voltage 4.15 4.5 4.9 V
(VCC increasing)
VCC Undervoltage Hysteresis 300 mV
VCC Drop Out Voltage VIN = 9 V, ICC = 20 mA 2.3 V
IIN Operating Current Non-Switching, FB = 3 V 1.75 mA
IIN Shutdown Current UVLO = 0 V 50 225 µA
Switch Characteristics
Buck Switch RDS(ON) ITEST = 200 mA, BST-SW = 7 0.8 1.8 Ω
V
Synchronous RDS(ON) ITEST = 200 mA 0.45 1Ω
Gate Drive UVLO VBST −VSW Rising 2.4 33.6 V
Gate Drive UVLO Hysteresis 260 mV
Current Limit
Current Limit Threshold 0.7 1.02 1.3 A
Current Limit Response Time Time to Switch Off 150 ns
OFF-Time Generator (Test 1) FB = 0.1 V, VIN = 48 V 12 µs
OFF-Time Generator (Test 2) FB = 1.0 V, VIN = 48 V 2.5 µs
On-Time Generator
TON Test 1 VIN = 32 V, RON = 100 k 270 350 460 ns
TON Test 2 VIN = 48 V, RON = 100 k 188 250 336 ns
TON Test 3 VIN = 75 V, RON = 250 k 250 370 500 ns
TON Test 4 VIN = 10 V, RON = 250 k 1880 3200 4425 ns
Minimum Off-Time
Minimum Off-Timer FB = 0 V 144 ns
Regulation and Overvoltage Comparators
FB Regulation Level Internal Reference Trip Point 1.2 1.225 1.25 V
for Switch ON
FB Overvoltage Threshold Trip Point for Switch OFF 1.62 V
FB Bias Current 60 nA
Undervoltage Sensing Function
UV Threshold UV Rising 1.19 1.225 1.26 V
UV Hysteresis Input Current UV = 2.5 V -10 -20 -29 µA
Remote Shutdown Threshold Voltage at UVLO Falling 0.32 0.66 V
Remote Shutdown Hysteresis 110 mV
Thermal Shutdown
Tsd Thermal Shutdown Temperature 165 °C
Thermal Shutdown Hysteresis 20 °C
(1) All limits are specified by design. All electrical characteristics having room temperature limits are tested during production at TA= 25°C.
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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Typical Characteristics
Figure 3. Efficiency at 200 kHz, 10 V Figure 4. VCC vs VIN
Figure 5. VCC vs ICC Figure 6. ICC vs External VCC
Figure 7. TON vs VIN and RON Figure 8. TOFF (ILIM) vs VFB and VIN
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Typical Characteristics (continued)
Figure 9. IIN vs VIN (Operating, Non Switching) Figure 10. IIN vs VIN (Shutdown)
Figure 11. Switching Frequency vs VIN
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0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 20 40 60 80 100 120 140
Output Current (A)
Ambient Temperature (C)
500LFM
200LFM
100LFM
No Flow
C003
VIN=54V
fsw=125kHz
VOUT=3.3V
L=220uH
LM5017
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SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
Thermal Curves
Figure 12. Thermal Derating Curve
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FB
VIN VCC
SW
RTN
BST
1.225V
VILIM
LM5017
RON
ILIM
COMPARATOR
+
-
V UVLO
ON/OFF
TIMERS
COT CONTROL
LOGIC
1.225V
START-UP
REGULATOR
VIN
FEEDBACK
DISABLE
THERMAL
SHUTDOWN
UVLO
OVER-VOLTAGE
1.62V
UVLO
4.5V
SD
SHUTDOWN
VDD REG
BG REF
0.66V
20 µA
CURRENT
LIMIT
ONE-SHOT
LM5017
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
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Functional Block Diagram
Figure 13. Functional Block Diagram
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=1.225V
RFB1
VOUT - 1.225V
RFB2
RFB2 + RFB1
VOUT = 1.225V x RFB1
VOUT
gsw = 10-10 x RON
LM5017
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SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
Functional Description
The LM5017 step-down switching regulator features all the functions needed to implement a low cost, efficient,
buck converter capable of supplying up to 0.6 A to the load. This high voltage regulator contains 100 V, N-
channel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced SO
PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme
using an on-time inversely proportional to VIN. This control scheme does not require loop compensation. The
current limit is implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short
circuit protection while providing minimum foldback. The simplified block diagram of the LM5017 is shown in
Figure 13.
The LM5017 can be applied in numerous applications to efficiently regulate down higher voltages. This regulator
is well suited for 48 V telecom and 42 V automotive power bus ranges. Protection features include: thermal
shutdown, Undervoltage Lockout (UVLO), minimum forced off-time, and an intelligent current limit.
Control Overview
The LM5017 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with the
output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225 V (typ).
In a synchronous buck converter, the low side (sync) FET is ‘on’ when the high side (buck) FET is ‘off’. The
inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be calculated as:
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is calculated
as:
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB) is
required for the LM5017. In cases where the capacitor ESR is too small, additional series resistance may be
required (RCin Figure 14).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 14 . However, RCslightly degrades the load regulation.
VCC Regulator
The LM5017 contains an internal high voltage linear regulator with a nominal output of 7.6 V. The input pin (VIN)
can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited to 30
mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to internal
circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the VCC pin
reaches the undervoltage lockout (VCC UVLO) threshold of 4.5 V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when SW pin is low.
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0.07 x VIN
TOFF(ILIM) = VFB + 0.2V Ps
10-10 x RON
TON = VIN
FB
SW L1
COUT
RFB2
VOUT
RC
LM5017
+
RFB1
VOUT
(low ripple)
LM5017
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
www.ti.com
At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator may supply up to 7 mA of current resulting in 48 V x 7 mA = 336 mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source, between 8 V and 13 V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
Figure 14. Low Ripple Output Configuration
Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225 V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high side switch will stay off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage will be
below 1.225 V at the end of each on-time, causing the high side switch to turn on immediately after the minimum
forced off-time of 144 ns. The high side switch can be turned off before the on-time is over, if the peak current in
the inductor reaches the current limit threshold.
Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62 V reference. If the voltage at FB rises above 1.62 V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225 V.
On-Time Generator
The on-time for the LM5017 is determined by the RON resistor, and is inversely proportional to the input voltage
(VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM5017 is:
See Figure 7. RON should be selected for a minimum on-time (at maximum VIN) greater than 100 ns, for proper
operation. This requirement limits the maximum switching frequency for high VIN.
Current Limit
The LM5017 contains an intelligent current limit off-timer. If the current in the buck switch exceeds 1.02 A the
present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is
controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, the
maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of
start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from the following equation:
The current limit protection feature is peak limited. The maximum average output will be less than the peak.
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+VIN
UVLO
VIN
RUV1
CIN RUV2
2
3
LM5017
LM5017
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SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
N-Channel Buck Switch and Driver
The LM5017 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01
uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver during
the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges from
VCC through the internal diode. The minimum off-timer, set to 144 ns , ensures a minimum time each cycle to
recharge the bootstrap capacitor.
Synchronous Rectifier
The LM5017 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads which would otherwise result in discontinuous operation.
Undervoltage Detector
The LM5017 contains a dual level undervoltage lockout (UVLO) circuit. When the UVLO pin voltage is below
0.66 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66V but
less than 1.225 V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the
regulator output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin
voltage is greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND
can be used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20 μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
UVLO VCC Mode Description
<0.66 V Shutdown VCC regulator disabled.
Switcher disabled.
0.66 V – 1.225 V Standby VCC regulator enabled
Switcher disabled.
>1.225 V VCC <4.5 V Standby VCC regulator enabled.
Switcher disabled.
VCC >4.5 V Operating VCC enabled.
Switcher enabled.
If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is
satisfied.
Figure 15. UVLO Resistor Setting
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Thermal Protection
The LM5017 should be operated so the junction temperature does not exceed 150°C during normal operation.
An internal Thermal Shutdown circuit is provided to protect the LM5017 in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state,
disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
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Product Folder Links: LM5017
ûIL(MAX)
ILI(peak) = IOUT + 2= 602 mA
VIN - VOUT
ûIL = L1 x gSW
VOUT
VIN
x
VOUT
gSW = K x RON
DMIN
gSW(MAX) = TON(MIN)
10/95
100 ns
= = 1.05 MHz
1 - DMAX
gSW(MAX) = TOFF(MIN)
1 - 10/12.5
200 ns
= = 1 MHz
LM5017
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SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
APPLICATION INFORMATION
Selection of External Components
Selection of external components is illustrated through a design example. The design example specifications are:
Buck Converter Design Specifications
Input voltage range 12.5 V to 95 V
Output voltage 10 V
Maximum Load current 500 mA
Switching Frequency 200 kHz
RFB1, RFB2:
VOUT = VFB x (RFB2/RFB1 + 1), and since VFB = 1.225 V, the ratio of RFB2 to RFB1 calculates as 7:1. Standard
values of 6.98 kΩand 1.00 kΩare chosen. Other values could be used as long as the 7:1 ratio is maintained.
Frequency Selection:
At the minimum input voltage, the maximum switching frequency of LM5017 is restricted by the forced minimum
off-time (TOFF(MIN)) as given by:
Similarly, at maximum input voltage, the maximum switching frequency of LM5017 is restricted by the minimum
TON as given by:
Resistor RON sets the nominal switching frequency based on the following equations:
(1)
where K = 1 x 10–10. Operation at high switching frequency results in lower efficiency while providing the smallest
solution. For this example a conservative 200 kHz was selected, resulting in RON = 504 kΩ. Selecting a standard
value for RON = 499 kΩresults in a nominal frequency of 202 kHz.
Inductor Selection:
The minimum inductance is selected to limit the output ripple to 20 to 40 percent of the maximum load current. In
addition, the peak inductor current at maximum load should be smaller than the minimum current limit as given in
Electrical Characteristics table. The inductor current ripple is given by:
The maximum ripple is observed at maximum input voltage. Substituting VIN = 95 V and ΔIL = 40 percent x IOUT
(max) results in L1 = 198.4 μH. The next higher standard value of 220 μH is chosen. The peak-to-peak minimum
and maximum inductor current ripples of 35 mA and 204 mA are given at minimum and maximum input voltages
respectively. The peak inductor and switch current is given by
which is smaller than the minimum current limit. The inductor should be able to withstand the maximum current
limit of 1.3 A, which can be reached during startup and overload conditions.
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Product Folder Links: LM5017
VIN(HYS) =IHYS x RUV2
IOUT(MAX)
CIN 8 x gSW x ûVIN
>
25 mV
RCûIL(MIN)
VOUT
VREF
x
>
ûIL
COUT = 8 x gsw x ûVripple
++
+
VIN BST
RON
RTN
SW
VCC
FB
VIN VOUT
RFB1
RC
RUV1
RON
COUT
CBST
CIN
RFB2
RUV2
L1
UVLO
+
CVCC
LM5017
7.5V-100V
1
2
3
4
5
6
8
7
Shutdown
+CBYP
LM5017
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
www.ti.com
Figure 16. Reference Schematic for Selection of External Components
Output Capacitor:
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by:
where ΔVripple is the voltage ripple across the capacitor. Substituting ΔVripple = 10 mV gives COUT = 12.64 μF. A
22 μF standard value is selected. An X5R or X7R type capacitor with a voltage rating 16 V or higher should be
selected.
Series Ripple Resistor RC:
The series resistor should be selected to produce sufficient ripple at the feedback node. The ripple produced by
RCis proportional to the inductor current ripple, and therefore RCshould be chosen for minimum inductor current
ripple which occurs at minimum input voltage. The RCis calculated by the equation:
This gives an RCof greater than or equal to 5.15 Ω. Selecting RC= 5.23 Ωresults in ~1 V of maximum output
voltage ripple. For applications requiring lower output voltage ripple, Type II or Type III ripple injection circuits
should be used as described in Ripple Configuration.
VCC and Bootstrap Capacitor:
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver.
The Bootstrap capacitor provides charge to high side gate driver. A good value for CVCC is 1 μF. A good value
for CBST is 0.01 μF.
Input Capacitor:
Input capacitor should be large enough to limit the input voltage ripple:
choosing a ΔVIN = 0.5 V gives a minimum CIN = 1.24 μF. A standard value of 2.2 μF is selected. The input
capacitor should be rated for the maximum input voltage under all conditions. A 100 V, X7R dielectric should be
selected for this design.
Input capacitor should be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is not possible to place
all of the input capacitor close to the IC, a 0.47 μF capacitor should be placed near the IC to provide a bypass
path for the high frequency component of the switching current. This helps limit the switching noise.
UVLO Resistors:
The UVLO resistors RFB1 and RFB2 set the UVLO threshold and hysteresis according to the following relationship:
14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LM5017
+
+
+
+
VIN
BST
RON
RTN
SW
VCC
FB
UVLO
VIN VOUT1
VOUT2
RFB1
RUV1
RON
COUT1
CBST
D1
CIN
COUT2
RFB2
RUV2
X1
RrNP
NS
LM5017
CVCC
+
D2
20V-100V
Cr
Cac
NS
VOUT2 = VOUT1 xNP- VF
++
+
VIN BST
RON
RTN
SW
VCC
FB
VIN
VOUT
R2
R7
R3
C9
C1
C4
R1
R5
L1
UVLO
C7
LM5017
12V-95V
1
2
3
4
5
6
8
7
(TP4)
+
C5
2.2 F 0.47 F127 N
14 N
499 N
GND
(TP1)
(TP2)
UVLO/SD
U1 R6
(TP3)
(TP5)
GND
R4 C6
C8
+
D2
R8
EXP
0
1 N
6.98 N 22 F
0
220 H
0.01 F
1 F
3300 pF
0.1 F
46.4 N
(TP6)
SW
RUV2
VIN (UVLO,rising) = 1.225V x RUV1 + 1
( )
LM5017
www.ti.com
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
and
where IHYS = 20 μA. Setting UVLO hysteresis of 2.5 V and UVLO rising threshold of 12 V results in RUV1 = 14.53
kΩand RUV2 = 125 kΩ. Selecting standard value of RUV1 = 14 kΩand RUV2 = 125 kΩresults in UVLO thresholds
and hysteresis of 12.4 V and 2.5 V respectively.
Application Circuit: 12 V TO 95 V Input and 10 V, 500 mA Output Buck Converter
The application schematic of a buck supply is shown in Figure 17. For output voltage (VOUT) above the maximum
regulation threshold of VCC (8.55 V, see Electrical Characteristics), the VCC pin can be connected to VOUT through
a diode (D2), as shown below, for higher efficiency and lower power dissipation in the IC.
Figure 17. Final Schematic for 12V to 95V Input, and 10V, 500mA Output Buck Converter
Isolated DC-DC Converter Using LM5017
An isolated supply using LM5017 is shown in Figure 18. Inductor (L) in a typical buck circuit is replaced with a
coupled inductor (X1). A diode (D1) is used to rectify the voltage on a secondary output. The nominal voltage at
the secondary output (VOUT2) is given by:
where VF is the forward voltage drop of D1, and NP, NS are the number of turns on the primary and secondary
of coupled inductor X1. For output voltage (VOUT1) above the maximum VCC (8.55 V), the VCC pin can be diode
connected to VOUT1 for higher effiicency and low dissipation in the IC. See AN-2204 (SNVA611) for a complete
isolated bias design with LM5017.
Figure 18. Typical Isolated Application Schematic
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5017
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
VFB = (VCC - VD) x
ûIL(MIN)
25 mV
RC
gsw(RFB2||RFB1)
>
5
C >
Cr = 3300 pF
RrCr<
Cac = 100 nF
(VIN(MIN) - VOUT) x TON
25 mV
25 mV
RCûIL(MIN)
VOUT
VREF
x
>
GND
To FB
L1
COUT
RFB2
RFB1
VOUT
RC
GND
To FB
L1
COUT
RFB2
RFB1
VOUT
RC
Cac
COUT
VOUT
GND
Rr
Cac
Cr
To FB
RFB2
RFB1
L1
LM5017
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
www.ti.com
Ripple ConfiguratioN
LM5017 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an on-timer, and
the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for
stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during
the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large enough to
suppress any noise component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rrand Crand the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See application note
AN-1481 (SNVA166) for more details for each ripple generation method.
Table 1.
Type 1 Type 2 Type 3
Lowest Cost Configuration Reduced Ripple Configuration Minimum Ripple Configuration
Soft Start
A soft-start feature can be implemented to the LM5017 using an external circuit. As shown in Figure 19, the soft-
start circuit consists of one capacitor, C1, two resistors, R1and R2, and a diode, D. During the initial start-up, the
VCC voltage is established prior to the VOUT voltage. D is thereby forward biased and the FB voltage is pulled up
above the reference voltage (1.225 V). The switcher is disabled. With the charging of the capacitor C1, the
voltage at node B gradually decreases. Due to the action of the control circuit, VOUT will gradually rise to maintain
the FB voltage at the reference voltage. Once the voltage at node B is lower than the FB voltage, plus the
voltage drop of D, the soft-start is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect
of R1has been ignored to simplify the calculation:
16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LM5017
VCC
To FB
RFB1
VOUT
R2
R1
RFB2 C1
DB
RFB1 x RFB2
RFB1 + RFB2
tS = C1 x (R2 + )
LM5017
www.ti.com
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
To achieve the desired soft-start, the following design guidance is recommended:
(1) R2is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB should not exceed 5 V at maximum VCC.
(2) C1is selected to achieve the desired start-up time that can be determined as:
(3) R1is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred.
Based on the schematic shown in Figure 17, selecting C1= 1 uF, R2=1kΩ, R1= 30 kΩresults in a soft-start
time of about 2 ms.
Figure 19. Soft-Start Circuit
Layout Recommendation
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1 μF or 0.47 μF capacitor directly across the VIN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 20).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (See Figure 20).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM5017. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5017
LM5017
www.ti.com
SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
REVISION HISTORY
Changes from Revision E (JULY 2013) to Revision F Page
• Added SW to RTN (100 ns transient) ................................................................................................................................... 3
Changes from Revision F (September 2013) to Revision G Page
• Changed formatting throughout document, to be TI compliant ............................................................................................ 1
• Changed minimum operating input voltage from 9 V to 7.5 V in "Features" ........................................................................ 1
• Changed minimum operating input voltage from 9 V to 7.5 V in "Typical Application" ........................................................ 1
• Changed minimum operating input voltage from 9 V to 7.5 V in "Pin Descriptions" ............................................................ 2
• Added Maximum Junction Temperature ............................................................................................................................... 3
• Changed minimum operating input voltage from 9 V to 7.5 V in "Recommended Operating Conditions" ........................... 3
• Changed minimum operating input voltage from 9 V to 7.5 V in "Reference Schematic" .................................................. 14
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5017
PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5017MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5017
MR
LM5017MRE/NOPB ACTIVE SO PowerPAD DDA 8 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5017
MR
LM5017MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR L5017
MR
LM5017SD/NOPB ACTIVE WSON NGU 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM L5017
LM5017SDX/NOPB ACTIVE WSON NGU 8 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM L5017
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2013
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5017MRE/NOPB SO
Power
PAD
DDA 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5017MRX/NOPB SO
Power
PAD
DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5017SD/NOPB WSON NGU 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5017SDX/NOPB WSON NGU 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5017MRE/NOPB SO PowerPAD DDA 8 250 213.0 191.0 55.0
LM5017MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0
LM5017SD/NOPB WSON NGU 8 1000 210.0 185.0 35.0
LM5017SDX/NOPB WSON NGU 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
www.ti.com
MRA08B (Rev B)
MECHANICAL DATA
NGU0008B
www.ti.com
SDC08B (Rev A)
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