MIC5891YWMTR - Micrel

May 2006 1 MIC5891

MIC5891 Micrel, Inc.

MIC5891

Features

• High-voltage, high-current outputs

• Output transient protection diodes

• CMOS-, PMOS-, NMOS-, and TTL-compatible inputs

• 5MHz typical data input rate

• Low-power CMOS latches

Applications

• Alphanumeric and bar graph displays

• LED and incandescent displays

• Relay and solenoid drivers

• Other high-power loads

General Description

The MIC5891 latched driver is a high-voltage, high current

integrated circuit comprised of eight CMOS data latches,

CMOS control circuitry for the common STROBE and OUT-

PUT ENABLE, and bipolar Darlington transistor drivers for

each latch.

Bipolar/MOS construction provides extremely low power

latches with maximum interface ﬂexibility.

The MIC5891 will typically operate at 5MHz with a 5V logic

supply.

The CMOS inputs are compatible with standard CMOS,

PMOS, and NMOS logic levels. TTL circuits may be used

with appropriate pull-up resistors to ensure a proper logic-

high input.

A CMOS serial data output allows additional drivers to be

cascaded when more than 8 bits are required.

The MIC5891 has open-emitter outputs with suppression

diodes for protection against inductive load transients. The

output transistors are capable of sourcing 500mA and will

sustain at least 35V in the on-state.

Simultaneous operation of all drivers at maximum rated

current requires a reduction in duty cycle due to package

power limitations. Outputs may be paralleled for higher load

current capability.

The MIC5891 is available in a 16-pin plastic DIP package

(N) and 16-pin wide SOIC package (WM).

8-Bit Serial-Input Latched Source Driver

Functional Diagram

Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

OUT1OUT2OUT3OUT4OUT5OUT6OUT7OUT8

SERIAL

DATA OUT

OUTPUT

ENABLE

CLOCK

SERIAL

DATA IN

STROBE

GROUND

8-BIT SERIAL PARALLEL SHIFT REGISTER

LATCHES

MOS

BIPOLAR

MIC5891 2 May 2006

MIC5891 Micrel, Inc.

Typical Circuits

VDD

Typical Output Circuit

VBB

VOUT

Typical Input Circuit

0.5

1.5

2.5

25 50 75 100 125 150

PACKAGE POWER DISSIPATION (W)

AMBIENT TEMPERATURE (°C)

Allowable Package Power

Dissipation vs. Temp.

PDIP

JA = 60°C/W

CerDIP

JA = 90°C/W

STROBE

SERIAL

DATA IN

CLOCK

GROUND

OUT3

OUT2

OUT1

OUT4

LOAD SUPPLY

OUTPUT

ENABLE

LOGIC SUPPLY

SERIAL

DATA OUT

OUT6

OUT7

OUT8

OUT5

VBB

VDD

SHIFT

LATCHES

Pin Conﬁguration

Ordering Information

Part Number Temperature Range Package

Standard Pb-Free

MIC5891BN MIC5891YN –40ºC to +85ºC 16-Pin Plastic DIP

MIC5891BWM MIC5891YWM –40ºC to +85ºC 16-Pin Wide SOIC

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MIC5891 Micrel, Inc.

Electrical Characteristics

VBB = 50V, VDD = 5V to 12V; TA = +25°C; unless noted.

Limits

Characteristic Symbol VBB Test Conditions Min. Max. Units

Output Leakage Current ICEX 50V TA = +25°C –50 µA

TA = +85°C –100 µA

Output Saturation Voltage VCE(SAT) 50V IOUT = –100mA, TA = +85°C 1.8 V

IOUT = –225mA, TA = +85°C 1.9 V

IOUT = –350mA, TA = +85°C 2.0 V

Output Sustaining Voltage VCE(SUS) 50V IOUT = –350mA, L = 2mH 35 V

Input Voltage VIN(1) 50V VDD = 5.0V 3.5 VDD+0.3 V

VDD = 12V 10.5 VDD+0.3 V

VIN(0) 50V VDD = 5V to 12V VSS–0.3 0.8 V

Input Current IIN(1) 50V VDD = VIN = 5.0V 50 µA

VDD = 12V 240 µA

Input Impedance ZIN 50V VDD = 5.0V 100 kΩ

VDD = 12V 50 kΩ

Maximum Clock Frequency fc 50V 3.3 MHz

Serial Data Output Resistance ROUT 50V VDD = 5.0V 20 kΩ

VDD = 12V 6.0 kΩ

Turn-On Delay tPLH 50V Output Enable to Output, IOUT = –350mA 2.0 µs

Turnoff Delay tPHL 50V Output Enable to Output, IOUT = –350mA 10 µs

Supply Current IBB 50V all outputs on, all outputs open 10 mA

all outputs off 200 µA

IDD 50V VDD = 5V, all outputs off, inputs = 0V 100 µA

VDD = 12V, all outputs off, inputs = 0V 200 µA

VDD = 5V, one output on, all inputs = 0V 1.0 mA

VDD = 12V, one output on, all inputs = 0V 3.0 mA

Diode Leakage Current IH Max TA = +25°C 50 µA

TA = +85°C 100 µA

Diode Forward Voltage VF Open IF = 350mA 2.0 V

Note 4: Positive (negative) current is deﬁned as going into (coming out of) the speciﬁed device pin.

Note 5: Operation of these devices with standard TTL may require the use of appropriate pull-up resistors.

Absolute Maximum Ratings (Notes 1, 2, 3)

Output Voltage (VOUT) .................................................50V

Logic Supply Voltage Range (VDD) ................ 4.5V to 15V

Load Supply Voltage Range (VBB) ................. 5.0V to 50V

Input Voltage Range (VIN) ...................................–0.3V to VDD+0.3V

Continuous Collector Current (IC) ..........................500mA

Package Power Dissipation .............................. see graph

Operating Temperature Range (TA) ....... –55°C to +125°C

Storage Temperature Range (TS) ..........–65°C to +150°C

Note 1: TA = 25°C

Note 2: Derate at the rate of 20mW/°C above TA = 25°C.

Note 3: Micrel CMOS devices have input-static protection but are

susceptible to damage when exposed to extremely high static

electrical charges.

8 53% 47% 41%

7 60% 54% 48%

6 70% 64% 56%

5 83% 75% 67%

4 100% 94% 84%

3 100% 100% 100%

2 100% 100% 100%

1 100% 100% 100%

50°C 60°C 70°C

Number of

Outputs ON at

IOUT = –200 mA

Max. Allowable Duty Cycles

at TA of:

Allowable Duty Cycles

MIC5891 4 May 2006

MIC5891 Micrel, Inc.

CLOCK

DATA IN

STROBE

OUTPUT

ENABLE

OUTN

Timing Conditions

(VDD = 5.0V, Logic Levels are VDD and Ground)

A. Minimum data active time before clock pulse (data set-up time) .........................................................................75ns

B. Minimum data active time after clock pulse (data hold time) ...............................................................................75ns

C. Minimum data pulse width .................................................................................................................................150ns

D. Minimum clock pulse width ................................................................................................................................150ns

E. Minimum time between clock activation and strobe ..........................................................................................300ns

F. Minimum strobe pulse width ..............................................................................................................................100ns

G. Typical time between strobe activation and output transition .............................................................................1.0µs

H. Turnoff delay ................................................................................................................. see Electrical Characteristics

I. Turn-on delay ................................................................................................................ see Electrical Characteristics

May 2006 5 MIC5891

MIC5891 Micrel, Inc.

Applications Information

Serial data present at the input is transferred into the shift

CLOCK pulses shift data information towards the SERIAL

DATA OUTPUT. The serial data must appear at the input prior

to the rising edge of the CLOCK input waveform.

The 8 bits present in the shift register are transferred to the

respective latches when the STROBE is high (serial-to-parallel

conversion). The latches will continue to accept new data as

Truth Table

Serial Shift Register Contents Serial Latch Contents Output Content

Data Clock Data Strobe Output

Input Input I1 I2 I3 … IN-1 IN Output Input I1 I2 I3 … IN-1 In Enable I1 I2 I3 … IN-1 In

H H R1 R2 … RN-2 RN-1 RN-1

L L R1 R2 … RN-2 RN-1 RN-1

X R1 R2 R3 … RN-1 RN RN

X X X … X X X L R1 R2 R3 … RN-1 RN

P1 P2 P3 … PN-1 PN PN H P1 P2 P3 … PN-1 PN L P1 P2 P3 … PN-1 PN

X X X … X X H L L L … L L

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

long as the STROBE is held high. Most applications where the

latching feature is not used (STROBE tied high) require the

OUTPUT ENABLE input to be high during serial data entry.

Outputs are active (controlled by the latch state) when the

OUTPUT ENABLE is low. All Outputs are low (disabled) when

the OUTPUT ENABLE is high. OUTPUT ENABLE does not

affect the data in the shift register or latch.

MIC5891 6 May 2006

MIC5891 Micrel, Inc.

Package Information

0.020

(0.508)

0.018±0.003

(0.457±0.076)

LEAD #1

0.780

(19.812)

.250±0.005

(6.350±0.127)

0.025±0.015

(0.635±0.381)

0.100±0.010

(2.540±0.254)

MAX

0.030-0.1 10

(0.762-2.794) RAD

0.125

(3.175) MIN

0.020

(0.508) MIN

0.130±0.005

(3.302±0.127)

+0.025

–0.015

+0.635

–0.381

0.325

8.255

( )

0.009-0.015

(0.229-0.381)

0°-10°

0.290-0.320

(7.336-8.128)

0.040

(1.016) TYP

16-Pin Plastic DIP (N)

16-Pin Wide SOIC (WM)

May 2006 7 MIC5891

MIC5891 Micrel, Inc.

MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and speciﬁcations at any time without notiﬁcation to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signiﬁcant injury to the user. A Purchaser's

use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.