1. General description
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output port s (pins An and Bn), a direction con trol input (DIR), an output enable input
(OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at
any voltage between 1.2 V and 5.5 V making the device suitable for translating between
any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and
DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows
transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The
output enable input (OE) can be used to disable the outputs so the buses are effectively
isolated.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a
valid logic level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1. 95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Rev. 3 — 12 December 2011 Product data sheet
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 2 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up pe rform a nc e exceeds 100 mA per JESD 78B Class II
24 mA output drive (VCC =3.0V)
Inputs accept voltages up to 5.5 V
Low power consum ption: 30 A maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
74LVCH8T245PW
74LVC8T245BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
74LVCH8T245BQ
Fig 1. Logic symbol
001aai472
OE
DIR
VCC(A) VCC(B)
22
2
3
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
45678910
21 20 19 18 17 16 15 14
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Product data sheet Rev. 3 — 12 December 2011 3 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
Fig 2. Logic diag ra m (one ch an nel)
001aai473
to other seven channels
DIR
A1
V
CC(A)
V
CC(B)
OE
B1
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SOT 355-1 (TSSOP24) Fig 4. Pin co nfiguration SOT815-1 (DHVQFN24)
74LVC8T245
74LVCH8T245
VCC(A) VCC(B)
DIR VCC(B)
A1 OE
A2 B1
A3 B2
A4 B3
A5 B4
A6 B5
A7 B6
A8 B7
GND B8
GND GND
001aak436
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aak437
74LVC8T245
74LVCH8T245
Transparent top view
B8
A8
GND
B7
A7 B6
A6 B5
A5 B4
A4 B3
A3 B2
A2 B1
A1 OE
DIR V
CC(B)
GND
GND
V
CC(A)
V
CC(B)
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
GND
(1)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 4 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
5.2 Pin description
[1] All GND pins must be connected to ground (0 V).
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The An inputs/outputs, DIR and OE input circuit is referenced to VCC(A); The Bn inputs/outputs circuit is referenced to VCC(B).
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
7. Limiting values
Table 2. Pin description
Symbol Pin Description
VCC(A) 1 supply voltage A (An inputs/outputs, OE and DIR inputs are referenced to VCC(A))
DIR 2 direction control
A1 to A8 3, 4, 5, 6, 7, 8, 9, 10 data input or output
GND[1] 11 ground (0 V)
GND[1] 12 ground (0 V)
GND[1] 13 ground (0 V)
B1 to B8 21, 20, 19, 18, 17, 16, 15, 14 data input or output
OE 22 output enable input (active LOW)
VCC(B) 23 supply voltage B (Bn inputs/outputs are referenced to VCC(B))
VCC(B) 24 supply voltage B (Bn inputs/outputs are referenced to VCC(B))
Table 3. Function table[1]
Supply voltage Input Input/output[3]
VCC(A), VCC(B) OE[2] DIR[2] An[2] Bn[2]
1.2 V to 5.5 V L L An = Bn input
1.2 V to 5.5 V L H input Bn = An
1.2 V to 5.5 V H X Z Z
GND[3] XXZZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 0.5 +6.5 V
VCC(B) supply voltage B 0.5 +6.5 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO<0V 50 - mA
VOoutput voltage Active mode [1][2][3] 0.5 VCCO +0.5 V
Suspend or 3-state mode [1] 0.5 +6.5 V
IOoutput current VO=0VtoV
CCO [2] -50 mA
ICC supply current ICC(A) or ICC(B); per VCC pin - 100 mA
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 5 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
8. Recommended operating conditions
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. Static characteristics
IGND ground current per GND pin 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[4] -500mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC(A) supply voltage A 1.2 5.5 V
VCC(B) supply voltage B 1.2 5.5 V
VIinput voltage 0 5.5 V
VOoutput voltage Active mode [1] 0V
CCO V
Suspend or 3-state mode 0 5.5 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCCI = 1.2 V [2] - 20 ns/V
VCCI = 1.4 V to 1.95 V - 20 ns/V
VCCI = 2.3 V to 2.7 V - 20 ns/V
VCCI = 3 V to 3.6 V - 10 ns/V
VCCI = 4.5 V to 5.5 V - 5 ns/V
Table 6. Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage VI = VIH or VIL [1]
IO=3 mA; VCCO = 1.2 V - 1.09 - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO =1.2V [1] -0.07-V
IIinput leakage current DIR, OE input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V [2] -- 1A
IBHL bus hold LOW current A or B port; VI=0.42V;V
CCI =1.2V [2] -19-A
IBHH bus hold HIGH current A or B port; VI=0.78V;V
CCI =1.2V [2] -19 - A
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 6 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.
IBHLO bus hold LOW overdrive
current A or B port; VCCI = 1.2 V [2][3] -19-A
IBHHO bus hold HIGH overdrive
current A or B port; VCCI = 1.2 V [2][3] -19 - A
IOZ OFF-state output current A or B port; VO=0 Vor V
CCO;
VCCO = 1.2 V to 5.5 V [1] -- 1A
suspend mode A port; VO=0VorV
CCO;
VCC(A) = 5.5 V; VCC(B) =0V [1] -- 1A
suspend mode B port; VO=0VorV
CCO;
VCC(A) =0 V; V
CC(B) =5.5V [1] -- 1A
IOFF power-off leakage current A port; VI or VO = 0 V to 5.5 V;
VCC(A) =0V;V
CC(B) = 1.2 V to 5.5 V -- 1A
B port; VI or VO = 0 V to 5.5 V;
VCC(B) =0V;V
CC(A) = 1.2 V to 5.5 V -- 1A
CIinput capacitance DIR, OE input; VI= 0 V or 3.3 V; VCC(A) =3.3V - 3 - pF
CI/O input/output capacitance A and B port; VO=3.3Vor0V;
VCC(A) =V
CC(B) =3.3V -6.5-pF
Table 6. Typical static characteristics at Tamb = 25 C …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
VIH HIGH-level
input voltage data input [1]
VCCI = 1.2 V 0.8VCCI -0.8V
CCI -V
VCCI = 1.4 V to 1.95 V 0.65VCCI -0.65V
CCI -V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCCI -0.7V
CCI -V
DIR, OE input
VCCI = 1.2 V 0.8VCC(A) -0.8V
CC(A) -V
VCCI = 1.4 V to 1.95 V 0.65VCC(A) -0.65V
CC(A) -V
VCCI = 2.3 V to 2.7 V 1.7 - 1.7 - V
VCCI = 3.0 V to 3.6 V 2.0 - 2.0 - V
VCCI = 4.5 V to 5.5 V 0.7VCC(A) -0.7V
CC(A) -V
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 7 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
VIL LOW-level
input voltage data input [1]
VCCI = 1.2 V - 0.2VCCI -0.2V
CCI V
VCCI = 1.4 V to 1.95 V - 0.35VCCI -0.35V
CCI V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCCI -0.3V
CCI V
DIR, OE input
VCCI = 1.2 V - 0.2VCC(A) -0.2V
CC(A) V
VCCI = 1.4 V to 1.95 V - 0.35VCC(A) - 0.35VCC(A) V
VCCI = 2.3 V to 2.7 V - 0.7 - 0.7 V
VCCI = 3.0 V to 3.6 V - 0.8 - 0.8 V
VCCI = 4.5 V to 5.5 V - 0.3VCC(A) -0.3V
CC(A) V
VOH HIGH-level
output voltage VI = VIH
IO=100 A;
VCCO = 1.2 V to 4.5 V [2] VCCO 0.1 - VCCO 0.1 - V
IO = 6mA; V
CCO = 1.4 V 1.0 - 1.0 - V
IO = 8mA; V
CCO = 1.65 V 1.2 - 1.2 - V
IO = 12 mA; VCCO = 2.3 V 1.9 - 1.9 - V
IO = 24 mA; VCCO = 3.0 V 2.4 - 2.4 - V
IO = 32 mA; VCCO = 4.5 V 3.8 - 3.8 - V
VOL LOW-level
output voltage VI = VIL [2]
IO = 100 A;
VCCO = 1.2 V to 4.5 V - 0.1 - 0.1 V
IO = 6 mA; VCCO = 1.4 V - 0.3 - 0.3 V
IO = 8 mA; VCCO = 1.65 V - 0.45 - 0.45 V
IO = 12 mA; VCCO = 2.3 V - 0.3 - 0.3 V
IO = 24 mA; VCCO = 3.0 V - 0.55 - 0.55 V
IO = 32 mA; VCCO = 4.5 V - 0.55 - 0.55 V
IIinput leakage
current DIR, OE input; VI= 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V -2-10 A
IBHL bus hold LOW
current A or B port [1]
VI = 0.49 V; VCCI =1.4V 15 - 10 - A
VI = 0.58 V; VCCI =1.65V 25 - 20 - A
VI = 0.70 V; VCCI =2.3V 45 - 45 - A
VI = 0.80 V; VCCI =3.0V 100 - 80 - A
VI = 1.35 V; VCCI =4.5V 100 - 100 - A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 8 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
IBHH bus hold HIGH
current A or B port [1]
VI = 0.91 V; VCCI =1.4V 15 - 10 - A
VI = 1.07 V; VCCI =1.65V 25 - 20 - A
VI = 1.70 V; VCCI =2.3V 45 - 45 - A
VI = 2.00 V; VCCI =3.0V 100 - 80 - A
VI = 3.15 V; VCCI =4.5V 100 - 100 - A
IBHLO bus hold LOW
overdrive
current
A or B port [1][3]
VCCI = 1.6 V 125 - 125 - A
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IBHHO bus hold HIGH
overdrive
current
A or B port [1][3]
VCCI = 1.6 V 125 - 125 - A
VCCI = 1.95 V 200 - 200 - A
VCCI = 2.7 V 300 - 300 - A
VCCI = 3.6 V 500 - 500 - A
VCCI = 5.5 V 900 - 900 - A
IOZ OFF-state
output current A or B port ; VO=0VorV
CCO;
VCCO = 1.2 V to 5.5 V [2] -2-10 A
suspend mode A port;
VO=0VorV
CCO; VCC(A) = 5.5 V;
VCC(B) =0V
[2] -2-10 A
suspend mode B port;
VO=0VorV
CCO; VCC(A) =0 V;
VCC(B) =5.5V
[2] -2-10 A
IOFF power-off
leakage
current
A port; VIor VO=0Vto5.5V;
VCC(A) =0V;
VCC(B) = 1.2 V to 5.5 V
-2-10 A
B port; VIor VO=0Vto5.5V;
VCC(B) =0V;
VCC(A) = 1.2 V to 5.5 V
-2-10 A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 9 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC8T245).
ICC supply current A port; VI = 0 V or VCCI; IO = 0 A [1]
VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 A
VCC(A) = 5.5 V; VCC(B) = 0 V - 15 - 20 A
VCC(A) = 0 V; VCC(B) = 5.5 V 2-4-A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V - 15 - 20 A
VCC(B) = 0 V; VCC(A) = 5.5 V 2-4-A
VCC(B) = 5.5 V; VCC(A) = 0 V - 15 - 20 A
A plus B port (ICC(A) + ICC(B));
IO=0A; V
I=0 Vor V
CCI
VCC(A), VCC(B) = 1.2 V to 5.5 V - 25 - 30 A
ICC additional
supply current per input;
VCC(A),V
CC(B) = 3.0 V to 5.5 V
DIR and OE input; DIR or OE
input at VCC(A) 0.6 V;
AportatV
CC(A) or GND;
B port = open
-50-75A
A port; A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open [4] -50-75A
B port; B port at VCC(B) 0.6 V;
DIR at GND; A port = open [4] -50-75A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
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Product data sheet Rev. 3 — 12 December 2011 10 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
[2] fi = 10 MHz; VI=GNDtoV
CC; tr = tf = 1 ns; CL = 0 pF; RL = .
Table 8. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Symbol Parameter Conditions VCC(B) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tpd propagation delay An to Bn 11.0 8.5 7.4 6.2 5.7 5.4 ns
Bn to An 11.0 10.0 9.5 9.1 8.9 8.9 ns
tdis disable time OE to An 9.5 9.5 9.5 9.5 9.5 9.5 ns
OE to Bn 10.2 8.2 7.8 6.7 7.3 6.4 ns
ten enable time OE to An 13.5 13.5 13.5 13.5 13.5 13.5 ns
OE to Bn 13.6 10.3 8.9 7.5 7.1 7.0 ns
Table 9. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Symbol Parameter Conditions VCC(A) Unit
1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
tpd propagation delay An to Bn 11.0 10.0 9.5 9.1 8.9 8.8 ns
Bn to An 11.0 8.5 7.3 6.2 5.7 5.4 ns
tdis disable time OE to An 9.5 6.8 5.4 3.8 4.1 3.1 ns
OE to Bn 10.2 9.1 8.6 8.1 7.8 7.8 ns
ten enable time OE to An 13.5 9.0 6.9 4.8 3.8 3.2 ns
OE to Bn 13.6 12.5 12.0 11.5 11.4 11.4 ns
Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C[1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions VCC(A) and VCC(B) Unit
1.8 V 2.5 V 3.3 V 5.0 V
CPD power dissipation
capacitance A port: (direction A to B);
B port: (direction B to A) 1112pF
A port: (direction B to A);
B port: (direction A to B) 13 13 13 13 pF
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 11 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
Table 11. Dynamic characteristics for temperature range 40 C to +85 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.5 V 0.1 V
tpd propagation
delay An to Bn 1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 ns
Bn to An 0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns
tdis disable time OE to An 1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 ns
OE to Bn 2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns
ten enable time OE to An 0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 ns
OE to Bn 1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns
VCC(A) = 1.8 V 0.15 V
tpd propagation
delay An to Bn 1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 ns
Bn to An 0.9 23 0 .9 2 3.8 0.8 23.6 0.7 23.4 0.7 23.4 ns
tdis disable time OE to An 1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns
OE to Bn 2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns
ten enable time OE to An 0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 ns
OE to Bn 1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns
VCC(A) = 2.5 V 0.2 V
tpd propagation
delay An to Bn 1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 ns
Bn to An 1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns
tdis disable time OE to An 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 ns
OE to Bn 2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns
ten enable time OE to An 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 ns
OE to Bn 1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns
VCC(A) = 3.3 V 0.3 V
tpd propagation
delay An to Bn 1.5 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns
Bn to An 0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns
tdis disable time OE to An 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns
OE to Bn 2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns
ten enable time OE to An 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns
OE to Bn 1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns
VCC(A) = 5.0 V 0.5 V
tpd propagation
delay An to Bn 1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 ns
Bn to An 0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns
tdis disable time OE to An 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns
OE to Bn 2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns
ten enable time OE to An 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns
OE to Bn 1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 12 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
Table 12. Dynamic characteristics for temperatu re range 40 C to +125 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter Conditions VCC(B) Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.5 V 0.1 V
tpd propagation
delay An to Bn 1.7 32 1.7 27 1.3 21 1.0 18 0.8 16 ns
Bn to An 0.9 32 0.9 30 0.8 28 0.7 28 0.7 26 ns
tdis disable time OE to An 1.5 34 1.5 34 1.5 34 1.5 34 1.4 34 ns
OE to Bn 2.4 41 2.4 40 1.9 18 1.7 17 1.3 15 ns
ten enable time OE to An 0.4 40 0.4 40 0.4 40 0.4 40 0.4 40 ns
OE to Bn 1.8 43 1.8 41 1.5 22 1.2 18 0.9 16 ns
VCC(A) = 1.8 V 0.15 V
tpd propagation
delay An to Bn 1.7 30 1 .7 2 5.9 1.3 13.2 1.0 11.4 0.8 11.1 ns
Bn to An 0.9 27 0.9 28.8 0.8 27.6 0.7 27.4 0.7 2 7.4 ns
tdis disable time OE to An 1.5 34 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 ns
OE to Bn 2.4 40 2.4 36.2 1.9 17.1 1.7 16.0 1.3 14.3 ns
ten enable time OE to An 0.4 28 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 ns
OE to Bn 1.8 41 1.8 40 1.5 20 1.2 16.6 0.9 14.8 ns
VCC(A) = 2.5 V 0.2 V
tpd propagation
delay An to Bn 1.5 28 1.5 25.4 1.2 13 0.8 10.2 0.6 8.8 ns
Bn to An 1.2 23 1.2 13.3 1.0 13.1 1.0 12.9 0.9 1 2.8 ns
tdis disable time OE to An 1.4 13 1.4 13 1.4 13 1.4 13 1.4 13 ns
OE to Bn 2.3 37 2.3 33.6 1.8 15 1.7 14.3 0.9 10.9 ns
ten enable time OE to An 1.0 17.2 1.0 17.2 1.0 17.3 1.0 17.2 1.0 17.3 ns
OE to Bn 1.7 38 1.7 32.2 1.5 18.1 1.2 14.1 1.0 11.2 ns
VCC(A) = 3.3 V 0.3 V
tpd propagation
delay An to Bn 1.5 28 1.5 25.2 1.1 12.8 0.8 10.3 0.5 10.4 ns
Bn to An 0.8 18 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns
tdis disable time OE to An 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 ns
OE to Bn 2.1 36 2.1 33 1.7 14.3 1.5 12.6 0.8 10.3 ns
ten enable time OE to An 0.8 14.1 0.8 14.1 0.8 13.6 0.8 13.2 0.8 13.6 ns
OE to Bn 1.8 37 1.8 31.7 1.4 18.4 1.1 12.9 0.9 10.9 ns
VCC(A) = 5.0 V 0.5 V
tpd propagation
delay An to Bn 1.5 26 1.5 25.4 1.0 12.8 0.7 10 0.4 8.2 ns
Bn to An 0.7 16 0.7 11 0.4 8 .8 0.3 8.5 0.3 8.3 ns
tdis disable time OE to An 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 ns
OE to Bn 2.0 36 2.0 32.7 1.6 13.7 1.4 12 0.7 9.7 ns
ten enable time OE to An 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 0.7 10.9 ns
OE to Bn 1.5 37 1.5 31.6 1.3 18.4 1.0 13.7 0.9 10.7 ns
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 13 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
11. Waveforms
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
Measurement points are given in Table 13.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times
001aai475
VM
VM
VI
An, Bn input
GND
VOH
Bn, An output
VOL
tPHL tPLH
Measurement points are given in Table 13.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
001aai474
t
PLZ
t
PHZ
outputs
disabled outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
OL
V
OH
V
CCO
V
I
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 13. Measurement points
Supply voltage Input[1] Output[2]
VCC(A), VCC(B) VMVMVXVY
1.2 V to 1.6 V 0.5VCCI 0.5VCCO VOL +0.1V V
OH 0.1 V
1.65 V to 2.7 V 0.5VCCI 0.5VCCO VOL +0.15V V
OH 0.15 V
3.0 V to 5.5 V 0.5VCCI 0.5VCCO VOL +0.3V V
OH 0.3 V
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 14 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns.
[3] VCCO is the supply voltage associated with the output port.
Test data is given in Table 14.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 14. Test data
Supply voltage Input Load VEXT
VCC(A), VCC(B) VI[1] t/V[2] CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3]
1.2 V to 5.5 V VCCI 1.0ns/V 15pF 2kopen GND 2VCCO
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 15 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 8. Typical pr opagation delay versus load capacitance; Tamb = 25 C; VCC(A) =1.2V
CL (pF) 35255302010015
001aal268
6
2
10
14
4
8
12
tPHL
(ns)
0
(3)
(4)
(5)
(6)
(1)
(2)
CL (pF) 35255302010015
001aal269
6
2
10
14
4
8
12
tPLH
(ns)
0
(4)
(5)
(6)
(1)
(3)
(2)
CL (pF) 35255302010015
001aal270
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal271
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 16 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 9. Typical pr opagation delay versus load capacitance; Tamb = 25 C; VCC(A) =1.5V
CL (pF) 35255302010015
001aal272
6
2
10
14
4
8
12
tPHL
(ns)
0
(3)
(4)
(5)
(6)
(1)
(2)
CL (pF) 35255302010015
001aal273
6
2
10
14
4
8
12
tPLH
(ns)
0
(3)
(4)
(5)
(6)
(1)
(2)
CL (pF) 35255302010015
001aal274
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal275
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 17 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) =1.8V
CL (pF) 35255302010015
001aal276
6
2
10
14
4
8
12
tPHL
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal277
6
2
10
14
4
8
12
tPLH
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal278
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal279
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 18 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 11. Typica l propagation delay versus load capacitance; Tamb = 25 C; VCC(A) =2.5V
CL (pF) 35255302010015
001aal280
6
2
10
14
4
8
12
tPHL
(ns)
0
(4)
(5)
(6)
(1)
(3)
(2)
CL (pF) 35255302010015
001aal281
6
2
10
14
4
8
12
tPLH
(ns)
0
(4)
(5)
(6)
(1)
(3)
(2)
CL (pF) 35255302010015
001aal282
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal283
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 19 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) =3.3V
CL (pF) 35255302010015
001aal284
6
2
10
14
4
8
12
tPHL
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal285
6
2
10
14
4
8
12
tPLH
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal286
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal287
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 20 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
a. HIGH to LOW propagation delay (A to B) b. LOW to HIGH propagation delay (A to B)
c. HIGH to LOW propagation delay (B to A) d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 13. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) =5V
CL (pF) 35255302010015
001aal288
6
2
10
14
4
8
12
tPHL
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal289
6
2
10
14
4
8
12
tPLH
(ns)
0
(4)
(5)
(6)
(1)
(2)
(3)
CL (pF) 35255302010015
001aal290
6
2
10
14
4
8
12
tPHL
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
CL (pF) 35255302010015
001aal291
6
2
10
14
4
8
12
tPLH
(ns)
0
(1)
(2)
(3)
(4)
(5)
(6)
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 21 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 14 is an example of the 74LVC8T245; 74LVCH8T2 45 be i ng
used in an unidirectional logic level-shifting application.
Schematic given for one channel.
Fig 14. Unidirectional logic level-shifting application
Table 15. Description unidirectional logic level-shifting application
Name Function Description
VCC(A) VCC1 supply voltage of system-1 (1.2 V to 5.5 V)
GND GND device GND
A OUT output level depends on VCC1 voltage
B IN input threshold value depends on V CC2 voltage
DIR DIR the GND (LOW level) determines B port to A port direction
VCC(B) VCC2 supply voltage of system-2 (1.2 V to 5.5 V)
OE OE The GND (LOW level) enables the output ports
001aak438
74LVC8T245
74LVCH8T245
V
CC1
system-1 system-2
V
CC1
V
CC2
V
CC2
V
CC(A)
V
CC(B)
GND DIR
Bn
OE
An
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 22 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 15 shows the 74LVC8T245; 74LVCH8T245 being used in a bidirectional logic
level-shifting application.
Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Schematic given for one channel.
Pull-up or pull-down only needed for 74LVC8T245.
Fig 15. Bidirectional lo gic level-shifting application
Table 16. Description bidirect ional logic level-shifting application[1]
State DIR CTRL OE I/O-1 I/O-2 Description
1 H L output input system-1 data to system-2
2 H H Z Z system-2 is getting ready to send data to
system-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on bus hold.
3 L H Z Z DIR bit is set LOW. I/O-1 an d I/O-2 still are
disabled. The bus-line state depends on bus
hold.
4 L L input output system-2 data to system-1
001aak439
PULL-UP/DOWN PULL-UP/DOWN
74LVC8T245
74LVCH8T245
VCC1
VCC1 VCC2 VCC2
I/O-2I/O-1
DIR CTRL
system-2system-1
VCC(A) VCC(B)
GND DIR
B
OE
A
OE
Table 17. Typical total supply current (ICC(A) + ICC(B))
VCC(A) VCC(B) Unit
0 V 1.8 V 2.5 V 3.3 V 5.0 V
0 V0 < 1< 1< 1< 1A
1.8 V < 1 < 2 < 2 < 2 2 A
2.5 V < 1 < 2 < 2 < 2 < 2 A
3.3 V < 1 < 2 < 2 < 2 < 2 A
5.0 V < 1 2 < 2 < 2 < 2 A
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 23 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
14. Package outline
Fig 16. Package outline SOT355-1 (TSSOP24)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 7.9
7.7 4.5
4.3 0.65 6.6
6.2 0.4
0.3 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153 99-12-27
03-02-19
0.25 0.5
0.2
wM
bp
Z
e
112
24 13
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
A
max.
1.1
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 24 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Fig 17. Package outline SOT815-1 (DHVQFN24)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
SOT815-1 - - - - - - - - - 03-04-29
SOT815-1
0 2.5 5 mm
scale
by
y1C
C
AC
CB
vM
wM
e1
e2
terminal 1
index area
terminal 1
index area
X
UNIT A(1)
max. A1bc eEhLe1ywv
mm 10.05
0.00 0.30
0.18 0.5 4.5
e2
1.50.2 2.25
1.95
Dh
4.25
3.95 0.05 0.05
y1
0.10.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
D(1)
5.6
5.4
E(1)
3.6
3.4
D
E
BA
e
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
AA1c
detail X
Eh
L
Dh
2
23
11
14
13
12
1
24
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 25 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
15. Abbreviations
16. Revision history
Table 18. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
HBM Human Body Model
MM Machine Model
Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_ LVCH8T245 v.3 20111212 Product data sheet - 74LVC_LVCH8T245 v.2
Modifications: •Legal pages updated.
74LVC_ LVCH8T245 v.2 20110211 Product data sheet - 74LVC_LVCH8T245 v.1
74LVC_ LVCH8T245 v.1 20100111 Product data sheet - -
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 26 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whet her the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document cont ains data from the pre liminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC_LVCH8T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 12 December 2011 27 of 28
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2011
Document identifier: 74LVC_LVCH8T245
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Typical propagation delay characteristics . . 15
13 Application information. . . . . . . . . . . . . . . . . . 21
13.1 Unidirectional logic level-shifting application . 21
13.2 Bidirectional logic level-shifting application. . . 22
13.3 Power-up considerations . . . . . . . . . . . . . . . . 22
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
18 Contact information. . . . . . . . . . . . . . . . . . . . . 27
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
