19-0094; Rev ra; 12/96 MA AALIV Microprocessor Supervisory Circuits General Description The MAX691 A/MAX693A/MAX800L/MAX800M micro- processor (UP) supervisory circuits are pin-compatible upgrades to the MAX691, MAX693, and MAX695. They improve performance with 30UA supply current, 200ms typ reset active delay on power-up, and 6ns chip- enable propagation delay. Features include write pro- tection of CMOS RAM or EEPROM, separate watchdog outputs, backup-battery switchover, and a RESET out- put that is valid with Vee down to 1V. The MAxX691A/ MAXS800L have a 4.65 typical reset-threshold voltage, and the MAX693A/MAX800Ms reset threshold is 4.4V typical. The MAX800L/MAX800M guarantee power-fail accuracies to +2%. Applications Computers Controllers Intelligent Instruments Automotive Systems Critical uP Power Monitoring Typical Operating Circuit 5 REGULATOR +8V CEQUT MAXIAN MAX691A MAX693A = PFI ssayaoa, CEN MAX800M GND A0-A15 WD a 2 oscin pP Pro} 2 A 5 z = 4 osc sa Peser U5 i LOW LINE WDO a) 14 AUDIBLE ALARM Features # 200ms Power-OK/Reset Timeout Period # 1pA Standby Current, 302A Operating Current # On-Board Gating of Chip-Enable Signals, 10ns Max Delay # MaxCap or SuperCap Compatible # Guaranteed RESET Assertion to Vog = +1V # Voltage Monitor for Power-Fail or Low-Battery Warning # Power-Fail Accuracy Guaranteed to +2% (MAX800L/M) Available in 16-Pin Narrow SO and Plastic DIP Packages Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX691ACPE OT to +70C 16 Plastic DIP MAX691ACSE 0 to +70C 16 Narrow SO MAX691ACWE 0 to +70C 16 Wide SO MAX691AC/D 0 to +70C Dice* MAX691 AEPE -40 to +85C 16 Plastic DIP MAX691AESE -40T to +85 16 Narrow SO MAX691 AEWE -40S to +85C 16 Wide SO MAX691AEJE -40S to +85C 16 CERDIP MAX691AMJE -55T to +125C 16 CERDIP *"MaxGap SYSTEM STATUS INDICATORS Ordering Information continued on lasi page. * Dice are specified at T, = +25 C, DC parameters only. Pin Configuration TOP VIEW J veaTt [7 lg) RESET Vour [2 15] RESET vec [3] Anaxian [14] 5 eo [4] maxeg1a [3] TEN ston [S| fiaxsoor [2] TEour TOW UNE [6 MAX800M im WDl osc In [7] 10] PFO OSC SEL [a| re] PA DIP/SO SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of The Carborundum Corp. MAXIMA Maxim Iniegrated Producis 1 For free samples & the latest literature: hitp:/www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) Vec Le nnn nn nnn reer ene eens teas anes -0.3V to +6V bedecueeeeaseeeeeeeeeeees -0.3V to +6V -0.3V to (Vout + 0.3V) All Other Inputs Input Current Vec PAK occ ceccececeece cesses cee seaeseeeeceeeceeeetnnneteernnnnanees 1.0A Vec Continuous... 250mA VBATT Peak... 250mA VBATT Continuous ...0..0. 0 cece cece eeeeeeeeeeeeteenreaes 25mA GND, BATT ON... ce eee etree terre teen tetera 100mA All Other Outputs occ ceeeeneeteereeeneees 25mA Continuous Power Dissipation (Ta = +70C) Plastic DIP (derate 10. 53mW/%S above +70) 0.0... 842mW Narrow SQ (derate 8.70mW/C above +70C}........... 696mW Wide SO (derate 9. 52mW/C above +70C)..... 762mW CERDIP (derate 10.00mW/C above +70)... soomw Operating Temperature Ranges MAX69_AC /MAX800 Co. eee OT to +70T MAX69_AE__/MAX800_E _ -40% to +85C MAX69_AMJE oo... ee cereternerees -55C to +125 Storage Temperature Range ..........0...c eee -65C to +160 Lead Temperature (soldering, 10sec)... ee +300C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of ihe device at these or any olher conditions beyond those indicated in the operational sections of the specifications is nol implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX691A, MAX800L: Voc = +4.75V to +5.5V, MAX693A, MAX800M: Vee = +4.5V to +5.5V, VBATT = 2.8V, Ta = Twn to Tuax, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range, 0 55 Vv Voc, VBATT (Note 1) louT = 25mA Voc-0.02 Veo -0.05 MAX69_AC Vec-0.2 Voco-03 MAX69_ AE, | = 250mA ay Voc-0.2 Voec-0.35 Vout Output Voc = 4.5V Our = sok") MAX800_C/E ce ce V MAX69_A/M Voc - 0.40 MAX69_AC/AE, lout = 210mA MAX800_ C/E Vec-017 Veco-0.3V MAX69_AC, MAX800_C 0.8 1.2 Vec-to-VouT On-Resistance | Voc = 4.5V MAX69_ AE, MAX800.E 08 1.4 Q MAX69_A/M 0.8 1.6 V a B Back VBATT = 4.5V, lOUT= 20mA VBATT - 0.3 ey auenreackup | VBATT = 2.8V, louT= 10mA VBATT - 0.25 V VBATT = 2.0V, louT= 5mA VBATT - 0.15 VBATT = 4.5V 15 VBATT-to-VOuT VBATT = 2.8V 25 Q On-Resistance VBATT = 2.0V 30 Supply Current in Normal Operating Mode Voc > VBATT - 1V 30 100 pA {Excludes lout) Supply Current in . Ta = +25 0.04 1 Battery-Backup Mode (oe Ea 1.2V pA (Excludes lout) (Note 2) = Ta = TMIN + TMIN 5 VBATT Standby Current Ta = +25 -0.1 0.02 VBATT + 0.2V< (Note 3) * oC Ta = TMIN + TMIN -1.0 0.02 HA Battery Switchover Power-up VBATT + 0.3 V Threshold Power-down VBATT -0.3 2 MAAXIMAMicroprocessor Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (MAX691A, MAX800L: Vog = +4.75V to +5.5V, MAX693A, MAX800M: Veg = +4.5V to +5.5V, VBATT = 2.8V, Ta = Try to Tax: unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Swite hover 60 mV Hysteresis BATT ON Output ISINK = 3.2mA 0.1 0.4 V Low Voltage IsINK = 25mA 0.7 1.5 BATT ON Output Sink current 60 mA Short-Circuit Current Source current 1 15 100 LA RESET AND WATCHDOG TIMER MAX691A, MAX800L 4.50 4.65 475 Reset Threshold Volt MAX693A, MAX800M 4.25 4.40 4.50 V eS eS TONG MONAT? | MAXBOOL, Ta = +25C, Voc falling 4.55 4.70 MAX800M, Ta = +25C, Voc falling 4.30 4.45 Reset Threshold Hysteresis 15 mV Vec to RESET Delay Power-down 80 us LOW LINE-to-RESET Delay 800 ns Reset Active Timeout Period, Power-up 140 200 280 ms Internal Oscillator Reset Active Timeout Period, Clock Extemal Clock (Note 4) Power-up 2048 Cycles Watchdog Timeout Period, | Long period 1.9 1.6 2.25 sec Internal Oscillator Short period 70 100 140 ms Watchdog Timeout Period, | Long period 4096 Clock Extemal Clock (Note 4) Short period 1024 Cycles Minimum Watchdog Input _ _ Pulse Width VIL = 0.8V, Viyq = 0.75 x Voc 100 ns IsInK = 50HA, Voc = 1V, VBATT = OV, Voc falling 0.004 0.3 RESET Output Voltage ISINK = 3.2mA, Voc = 4.25V 0.1 0.4 V ISOURGE = 1.6mA, Veco = 5V 35 RESET Output Short-Circuit Output source current 7 20 mA Current RESET Output Voltage Low _ (Note 5) ISINK = 3.2mA 0.1 0.4 Vv a ISINK = 3.2mA, Veo = 4.25V 0.4 LOW LINE Gutput Voltage V p g ISOURCE = 1HA, Voc = 5V 3.5 LOW LINE Output Short-Circuit Current Output source current 1 15 100 LA ____ ISINK = 3.2mA 0.4 V WDO Output Voltage ISOURCE = 500UA, Veo = 5V 45 WDO Output Short-Circuit Current Output source current 3 10 mA WDI Threshold Voltage VIH 0.75 x Voc V (Note 6) VIL 0.8 WDI = oV -50 -10 WDI | Cc nput Current WDl= Vour 30 50 pA MAAXILM 3 NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) (MAX691A, MAX800L: Voc = +4.75V to +5.5V, MAX693A, MAX800M: Voc = +4.5V to +5.5V, VBATT = 2.8V, Ta, = Try to Trax unless otherwise noted.) PARAMETER | CONDITIONS MIN TYP MAX UNITS POWER-FAIL COMPARATOR MAX69_AC/AE/AM, Voc = 5V 1.2 1.25 1.3 PFI Input Threshold Vv MAX800 C/E, Vcc = 5V 1.225 1.25 1.275 PFI Leakage Current +0.01 +25 nA _ IsINK = 3.2mA 0.4 PFO Cutp ut Voltage V ISoURCE = 1HA, Voc = 5V 3.5 PFO Qutp ut Short-Circuit Current Output source current 1 15 100 pA VIN = -20mV, Vop = 15mV 25 PFl-tc-PFO Delay Ls VIN = 20mV, Vop = 15mV 60 CHIP-ENABLE GATING CE IN Leakage Current Disable mode +0.005 +1 CE IN-to-CE OUT Resistance Enable mode 75 150 QO (Note 7) CE OUT Short-Circult Current | Disable mode, CE OUT = OV 0.1 0.75 2.0 mA (Reset Active) CE IN-to-CE OUT Propagation ; ; _ Delay (Note 8) 500 source impedance driver, CLoap = 50pF 6 10 ns CE QUT Output Voltage High =| Yoo = 5Y, louT= -100pA 3.5 V (Reset Active) Voc = OV, VBATT = 2.8V, louT= 1pA 27 RESET-to-CE OUT Delay Power-down 12 Us INTERNAL OSCILLATOR OSC IN Leakage Current OSC SEL = oV 0.10 +5 pA OSG IN Input Pull-Up Current OSG SEL = Vout or floating, OSC IN = OV 16 100 LA OSG SEL Input Pull-Up Current | OSG SEL = 0oV 10 160 LA OSC IN Frequency Range OSG SEL = OV 50 kHz OSC IN External Oscillator VIH VouT-0.38 Vout - 0.6 V Threshold Voltage VIL 3.65 2.00 OSC IN Frequency with OSC SEL = OV, COSC = 47pF 100 kHz Extermal Capacitor Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Either Vec or VBATT can go to OV, if the other is greater than 2.0V. The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding lout typically goes to 10A when (VBATT - 1) < Vcc < VBATT. In most applications, this is a brief period as Vcc falls through this region. +" = battery-discharging current, --" = battery-charging current. Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. RESET is an open-drain output and sinks current only. WD1 is internally connected to a voltage divider between Vout and GND. If unconnected, WDI is driven to 1.6 (typ), disabling the watchdog function. The chip-enable resistance is tested with Vcc = +4.75V for the MAX691A/MAX800L and Vcc = +4.5V for the MAX693A/MAX800M. CE IN = CE OUT = Vac /2. The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. MAAXIAAMicroprocessor Supervisory Circuits (TA = +25, unless otherwise noted.) Vee SUPPLY CURRENT vs. TEMPERATURE (NORM AL CPERATING MODE) 8 Negev g VBATT=2.8V 5 gs PFI, CE IN=0 z % = ao SN oc vm 3 mh > hn a pon 2 30 ae a 8 > 98 26 60 -30 08 30 680 90 i120 150 TEM PERATURE (C) VBATT to Vout ON- RESISTANCE vs. TEMPERATURE 20 L B Le] i 9 VEATT = 2.0 en <= fa 46 | _ Z VEATT =2.8 at 2 2 |] L 7 10 2 Ln = VBATT=4.5 > Voc = OV an -60 -3000 0 30 60 90 TEM PERATURE (C) RESET THRESHCLD vs. TEMPERATURE 4.75 VBATT =2.8 3 4.70 Z a = 465 . = MAX6S1A 4 4.60 [- MAX800L a 4 SE oc FE 4.50 bi 4.45 rc 4.40 MAX693A 4.35 F-maxsoom 4.30 60 -30 0 30. 60 90 TEM PERATURE (C} MA AXIMA BATTERY SUPPLY CURRENT (1A) Vog-to-VoLiT ON- RESISTANCE (2) RESET QUTPUT RESISTANGE (Q)} tn a an no ial > S w S fos] S I S a 5 - on o a Re oo oS S 00 So So ao a ao a 0 -60 -30 0 30 60 90 a a 60 -30 0 30 60 90 BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP M CDE) Voc =5 VBATT=2.8V NO LOAD axea 14 TOC-C2 120 150 TEM PERATURE (C) Veo to Vout ON-RESISTANCE vs. TEMPERATURE Veo = 5, VBATT = OV MAXEDIA TEC-05 LZ \Y 4 / / 30 (0 30 60 90 TEM PERATURE (C) RESET QUTPUT RESISTANCE vs. TEMPERATURE MARBO1A TOC-C8 Vee=5V, VBATT=2.8V SOURCING CURRENT. Voc = OV, VBATT = 2.8V SINKING CURRENT. TEM PERATURE (C) PFI THRESHOLD () RESET DELAY (ms) CEON-RESISTANCE (2) oo a oD a 40 190 180 170 60 -30 0 30 60 8690 Typical Operating Characteristics CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE Veco =4.75 VBATT =2.8 VCEIN = Vee/2 MAxE@1ATOC-03 NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVN oa -60 -30 O 30 60 $0 120 150 180 TEMPERATURE (C) PFI THRESHOLD vs. TEMPERATURE MARED1A TOC-06 Veo =+5, VBATT=0 | NO LOAD ON PFO 120 150 TEM PERATURE (C) RESET DELAY vs. TEMPERATURE Veo = OV TOSV STEP VBATT =2.8V MARGO1 a TOC-C2 ra va 80-30 Q so 60 90 TEM PERATURE (C)MAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits (TA = +25, unless otherwise noted.) MANeO1A TOC-10 MAXEOTA TOC 13 BATTERY CURRENT vs. INPUT SUPPLY VCLTAGE 20 VBATT=2.8 Igy =0A 16 = te : ~ 8 4 0 0 1 2 3 4 5 Voc () Vecto Vout vs. CUTPUT CURRENT (NORM AL OPERATING MODE) 1000 Veo=4.6V VBATT = OV z 400 = a a 40 SLOPE = 0.802 1 1 10 100 1000 lout (MA) 6 WATCHDOG AND RESET TIMECUT PERICD ys. OSC IN TIMING CAPACITOR (COSC) a ao Veo = 5V VBATT =2 8V LONG WATCHDOG TIMEOUT PERIOD MAKEOIA TOC. 11 Q RESET ACTIVE MEOUT PERIOD SHORT WATCHDOG TIMEOUT PERIOD WATGHDOG AND RESET TIM GOUT PERIOD (sec) o oS 100 1000 COSC (pF) VBATT to Vout vs. QUTPUT CURRENT (BATTERY-BACKUP M CDE} 1000 Veo = OV VBATT =4.5 MARBOTATOC-14 100 YBATT to Vour (m} 1 10 100 lout (mA) Typical Operating Characteristics (continued) CHIP-ENABLE PROPAGATION DELAY vs. CE QUT LOAD CAPACITANCE Voo=5 | x CEIN=0 TOS5V _ DRIVER SOURCE f 18 | IMPEDANCE =s00 YY Pe x= a 4g / 3 y 5 Z 8 x \/ Qo he / 4 7 0 0 SO 100 150 200 260 300 Coan (pF) Veote LOW LINE AND CE QUT DELAY 5Y Voc RESET THRESHOLD | COW LINE Lo HI RESET Lo HI GE OUT MAAXLAA MAXEOTA TEC-15,Microprocessor Supervisory Circuits Pin Description PIN NAME FUNCTION VBATT Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not used, connect to GND. Qutput Supply Voltage. When Voc is greater than VBATT and above the reset threshold, Vout connects to 2 Vout Voc. When Voc falls below VBATT and is below the reset threshold, Vout connects to VBATT. Connect a 0.1 pF capacitor from Vout to GND. Connect Vout to Voc if no backup battery is used. 3 Voc Input Supply Voltage, 5V input. GND Ground. OV reference fer all signals. 5 | BATTON ments greater than 250mA. Battery On Output. When Vout switches to VBATT, BATT ON goes high. When Vout switches to Vcc, BATT ON goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for Vout current require- 6 LOW LINE the reset threshold. LOW LINE output goes low when Vcc falls below the reset threshold. It returns high as soon as Vcc rises above ? OSC IN External Oscillator Input. When OSC SEL is unconnected or driven high, a 10yA pull-up connects from VoQuT to OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast and slow watchdog timeout periods. When OSG SEL is driven low, the reset and watchdog timeout periods may be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3). 8 | OSC SEL OSC SEL has a 10,A internal pull-up. Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1). 9 PFI Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. When PFI is not used, connect PFI to GND or Vout. 10 | PFO Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PF is less than 1.25V. This is an uncommitted comparator, and has no effect.on any other internal circuitry. 11 WDI Watchdog Input. WDI is a three-level input. If WD! remains either high or low for longer than the watchdog time- out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran- sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage divider between Vout and GND, which sets it to mid-supply when left unconnected. 42 | GeouT | Chip-Enable Output. CE OUT goes low only when CE IN is low and Voc is above the reset threshold. If CE IN is low when reset is asserted, CE OUT will stay low for 15s or until CE IN goes high, whichever occurs first. 13 CEIN | Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or Vout. Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset 14 WDO is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if WDI is unconnected. 15 RESET RESET Output goes low whenever Vcc falls below the reset threshold. RESET will remain low typically for 200ms after Vcc crosses the reset threshold on power-up. 16 RESET RESET is an active-high output. It is open drain, and the inverse of RESET. Detailed Description RESET and RESET Outputs The MAX691 A/MAX693A/MAX800L/MAX800M's RESET and RESET outputs ensure that the uP (with reset inputs asserted either high or low} powers up ina known state, and prevents code-execution errors dur- ing power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at typically Vout - 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is MA AXIMA guaranteed to be valid down to Vec = 1V, and an external 10k pull-down resistor on RESET insures that it will be valid with Voc down to GND (Figure 1). AS Veco goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the Rpson) and the saturation voltage. The 10k pull- down resistor insures the parallel combination of switch plus resistor is around 10k9 and the output saturation voltage is below 0.4V while sinking 40WA. When using a 10kQ external pull-down resistor, the high state for RESET output with Voc = 4.75V will be 4.5 typical. For battery voltages > 2V connected to VBATT, RESET and RESET remain valid for Vee from OV to 5.5V. NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits PESET TO uP RESET MNAXLM MAX691A k MAX693A RESET } yy EY t, = RESET TIMEQUT PERIOD t2 = NORMAL WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEQUT PERIOD IMMEDIATELY AFTER RESET Figure 1. Adding an external pull-down resistor ensures RESET is valid with Veco down to GND. RESET and RESET are asserted when Veg falls below the reset threshold (4.65V for the MAX691A/MAX800L, 4.4V for the MAX693A/MAX800M) and remain asserted for 200ms typ after Veg rises above the reset threshold on power-up (Figure 5). The devices battery- switchover comparator does not affect reset assertion. However, both reset outputs are asserted in battery- backup mode since Vere must be below the reset threshold to enter this mode. Watchdog Function The watchdog monitors yP activity via the Watchdog Input (WDI). If the WP becomes inactive, RESET and RESET are asserted. To use the watchdog function, connect WDI to a bus line or pP I/O line. If WDI remains high or low for longer than the watchdog time- out period (1.6sec nominal), WDO, RESET, and RESET are asserted (see RESET and RESET Outputs section, and the Watchdog Output discussion on this page). Watehdog Input A change of state (high to low, low to high, or a mini- mum 100ns pulse} at the WDI during the watchdog period resets the watchdog timer. The watchdog default timeout is 1.6sec. To disable the watchdog function, leave WDI floating. An internal resistor network (100kQ equivalent imped- ance at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When Voc is below the reset thresh- old, the watchdog function is disabled and WD! is dis- connected from its internal resistor network, thus becoming high impedance. Figure 2. Waichdog Timeout Period and Reset Active Time Watchdog Output The Watchdog Output (WDO) remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when Vec is below the reset threshold, bat- tery-backup mode is enabled, or WDI is an open circuit. In watchdog mode, if no transition occurs at WDI during the watchdog timeout period, RESET and RESET are asserted for the reset timeout period (200ms typical}. WDO goes low and remains low until the next transition at WDI (Figure 2). If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6sec. WDO has a 2 x TTL output characteristic. Selecting an Alternative Watchdog and Reset Timeout Period The OSG SEL and OSC IN inputs control the watchdog and reset timeout periods. Floating OSC SEL and OSC IN or tying them both to Voy selects the nominal 1.6sec watchdog timeout period and 200ms reset timeout peri- od. Gonnecting OSC IN to GND and floating or connect- ing OSC SEL to Vayr selects the 100ms normal watchdog timeout delay and 1.6sec delay immediately after reset. The reset timeout delay remains 200ms (Figure 2}. Select alternative timeout periods by con- necting OSC SEL to GND and connecting a capacitor between OSC IN and GND, or by externally driving OSC IN (Table 1 and Figure 3). OSC IN is internally connect- ed to a +100nA (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watchdog timeout periods (see Connecting a Timing Capacitor at OSC IN in the Applications information section). MAAXIAAMicroprocessor Supervisory Circuits Table 1. Reset Pulse Width and Watchdog Timeout Selections Figure 3. Oscillator Circuits Chip-Enable Signal Gating The MAX691 A/MAX693A/MAX800L/MAX800M provide internal gating of chip-enable (CE) signals to prevent erroneous cata from being written to CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, prevent- ing erroneous data from corrupting the CMOS RAM. All these parts use a series transmission gate from CE IN to CE OUT (Figure 4). The 10ns max CE propagation delay from CE IN to CE OUT enables the parts to be used with most pPs. Chip-Enabie input The Chip-Enable Input (CE IN) is high impedance (dis- abled mode) while RESET and RESET are asserted. During a power-down sequence where Vcc falls below the reset threshold or a watchdog fault, CE IN assumes a high-impedance state when the voltage at CE IN goes high or 15us after reset is asserted, whichever occurs first (Figure 5). During @ power-up sequence, CE IN remains high impedance, regardless of CE IN activity, until reset is deasserted following the reset timeout period. MA AXIMA Watchdog Timeout Period . . osc SEL Osc IN Normal immediately After Reset Reset Timeout Period Low External Clock Input 1024 clks 4096 clks 2048 clks Low External Capacitor {600/47pF x C)ms {2.4/47pF x C)sec (1200/47pF x C)ms Floating Low 100ms 1.6sec 200ms Floating Floating 1.6sec 1.6sec 200ms In the high-impedance mode, the leakage currents into MAXLSVI EXTERNAL EXTERNAL this terminal are +1yWA max over temperature. In the MAX691A CLOCK OSCILLATOR low-impedance mode, the impedance of CE IN appears MAXE93A 8) osc se. ol er as a 75 resistor in series with the load at CE OUT. MAXBOOL LC et MAXYQOOM = The propagation delay through the CE transmission 7 oscin co OSC IN gate depends on both the source impedance of the on = drive to CE IN and the capacitive loading on the Chip- = = Enable Output (CE OUT) (see Chip-Enable Propagation Delay vs. CE OUT Load Capacitance in the Typical INTERNAL OSCILLATOR INTERNAL OSCILLATOR Operating Characteristics). The CE propagation delay 16sec WATCHDOG 100ms WATCHDOG is production tested from the 50% point of CE IN to the no fose se. no J oscse. 50% point of CE OUT using a 50Q driver and 50pF of load capacitance (Figure 6). For minimum propagation 7 7 delay, minimize the capacitive load at CE GUT, and N.C, =] OSC IN Cy use a low output-impedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75Q in series with the source driving CE IN. In the disabled mode, the 75Q transmission gate is off and CE OUT is actively pulled to Vgy7. This source turns off when the transmission gate is enabled. LOW LINE Output LOW LINE is the buffered output of the reset threshold comparator. LOW LINE typically sinks 3.2@mA at 0.1V. For nermal operation (Voc above the LOW LINE thresh- old), LOW LINE is pulled to Voyr. Power-Fail Comparator The power-fail comparator is an uncommitted comparator that has no effect on the other functions of the IC. Gommon uses include low-battery indication (Figure 7), and early power-fail warning (see Typical Operating Circuid. Power-Fail Input Power Fail Input (PFI) is the input to the power-fail com- parator. It has a guaranteed input leakage of +25nA max over temperature. The typical comparator delay is 25us from VIL to VoL (power failing), and 60us from Viz to Voy (power being restored). If PFI is not used, con- nect it to ground. NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits 5 | BATTON SS By LOW LINE | Vec pe 2 + Vou CHIP-ENABLE | 4 OUTPUT -] Pn VBATT I CONTROL =m ol3 Ho 12, = CEIN CEQUT Te 6, RESET MAXIAA MAX691A Cd MAXBQ3A 2 MAX800L RESET _L ; MAXB00M GENERATOR } >> =} Sr OSC IN TIMEBASE FOR 8 RESET AND | OSC SEL WATCHDOG "1 WATCHDOG _ DI TRANSITION allie 13 y-DO PF = DETECTOR PFO DS 4] GND * 4.4V FOR THE MAX693A/ MAX800M Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram 5.0V 4.0V 5.0V ov 5Y ov CEOUT | | | | | | | LU one et be {001s 5Y ov 5Y ov RESET = | LOGIC LEVELS SHOWN ARE FROM OV TO 5. Figure 5. Reset and Chip-Enabie Timing 10 MAAXIAAMicroprocessor Supervisory Circuits +5 l VBATT Yec | + MAXLAM 28 _ MAX691A MAX693A Lt MAX800L MAX800M CEIN CECUT . 50 GND QUTPUT CLeap IMPEDANCE iL L +5 l Vec YBATT sAAXLAA MAX691A MAX693A MAXB00L s Tow BATT PF MAXBOOM PFO -#-_ LOW BATT 20V0 ssv Figure 6. CE Propagation Delay Test Circuit Table 2. Input and Output Status in Battery-Backup Mode PIN NAME STATUS 1 VBATT Supply current is 1A max. Vout is connected to VBATT through an 2 VOUT internal PMO&S switch. 3 Vv Battery switchover comparator monitors cc Voc for active switchover. 4 GND GND OV, OV reference for all signals. 5 BATT ON Logic high. The open-circuit output is equal to Vout. 6 LOWLINE | Logic low* OSC IN OSG IN is ignored. 8 OS SEL | OSC SEL is ignored. The power-fail comparator remains 9 PFI active inthe battery-backup mode for Voc = VBATT - 1.2 typ. The power-fail comparator remains 10 PEO active inthe battery-backup mode for Voc > VBATT - 1.2V typ. Below this volt- age, PFO is forced low. if WDI Watchdog is ignored. 42 CE OUT Logic high. The open-circuit voltage is equal to Vout. 13 CE IN High impedance 14 Woo Logic high. The open-circuit voltage is equal to Your. 15 RESET Logic low" 16 RESET High impedance * Veo must be below the reset threshold to enter battery-backup mode. MA AXIMA Figure 7. Low-Battery Indicator Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below 1.25V. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFl above 1.25V, PFO is actively pulled to Vout. Battery-Backup Mode Two conditions are required to switch to battery-back- up mode: 1) Vee must be below the reset threshold, and 2) Voc must be below VBATT. Table 2 lists the sta- tus of the inputs and outputs in battery-backup mode. Battery On Output The Battery On (BATT ON) output indicates the status of the internal Vec/battery-switchover comparator, which controls the internal Veo and VBATT switches. For Vee greater than VBATT {ignoring the small hys- teresis effect}, BATT ON typically sinks 3.2mA at 0.1V saturation voltage. In battery-backup mode, this termi- nal sources approximately 19UA from Voy7. Use BATT ON to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-cur- rent applications (see Typical Operating Circuit). input Supply Voltage The Input Supply Voltage (Voc) should be a regulated 5V. Vee connects to Voy7 via a parallel diode and a large PMOS switch. The switch carries the entire cur- rent load for currents less than 250mA. The parallel diode carries any current in excess of 250mA. Both the switch and the diode have impedances less than 10 each. The maximum continuous current is 250mA, but power-on transients may reach a maximum of 1A. 11 NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits Battery-Backup Input The Battery-Backup Input (VBATT) is similar to the Vee input except the PMOS switch and parallel diode are much smaller. Accordingly, the on-resistances of the diode and the switch are each approximately 10Q. Continuous current should be limited to 25mA and peak currents (only during power-up) limited to 250mA. The reverse leakage of this input is less than 1HA over temperature and supply voltage (Figure 8). Output Supply Voltage The Output Supply Voltage (Voyq) pin is internally con- nected to the substrate of the IC and supplies current to the external system and internal circuitry. All open- circuit outputs will, for example, assume the Voy volt ade in their high states rather than the Vee voltage. At the maximum source current of 250mA, Veyr will typi- cally be 200mV below Vec. Decouple this terminal with a 0.1puF capacitor. Applications Information The MAX691A/MAX693A/MAX800L/MAX800M are not short-circuit protected. Shorting Voy7 to ground, other than power-up transients such as charging a decou- pling capacitor, destroys the device. All open-circuit outputs swing between Vour and GND rather than Veg and GND. If long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chips protection diodes. There are three distinct modes of operation: 1) Normal operating mode with all circuitry powered up. Typical supply current from Voc is 35yA while only leakage currents flow from the battery. 2) Battery-backup mode where Voz is typically within 0.7V below VBATT. All circuitry is powered up and the supply current from the battery is typically less than 6OUA. 3) Battery-backup mode where Vcc is less than VBATT by at least 0.7V. VBATT supply current is 1A max. Using SuperCap or MaxCap with the MAX69 1 A/MAX693A/MAX800L/MAX800M VBATT has the same operating voltage range as Vec, and the battery switchover threshold voltages are typi- cally t30mV centered at VBATT, allowing use of a SuperCap and a simple charging circuit as a backup source (Figure 9). If Vee is above the reset threshold and VBATT is 0.5V above Vcc, current flows to Vey7 and Ver from VBATT until the voltage at VBATT is less than 0.5V above Vee. For example, with a SuperGap connected to VBATT and through a diode to Veg, if Vee quickly changes from 5.4V to 4.9V, the capacitor discharges through Voy and Voc until VBATT reaches .1V typ. Leakage current through the SuperGap charging diode and the internal power diode eventually discharges the SuperCap to Voc. Also, if Vec and VBATT start from 0.1V above the reset threshold and power is lost at Vec, the SuperCap on VBATT dis- charges through Vee until VBATT reaches the reset threshold; then the battery-backup mode is initiated and the current through Vec goes to zero. VBATT | Pp MAAXILAA MAX691A MAX693A MAXB00L MAX800M +5 1N4148 Voc VBATT Your (7 MAAXLAA a4 MAXB9TA T MAXB93A = MAXB00L MAXSO0M GND * MaxCap | Figure 8. Veco and VBATT to Vour Switch 12 Figure 9. SuperCap or MaxCap on VBATT MAAXIAAMicroprocessor Supervisory Circuits Po pA 7 cE RAM 1 Vout CE OC CEIN CEOUT + CE MAAXIAA RAM 2 MAXE91A cE MAX693A MAXB800L MAXS800M AE I RAM 3 cnn CE 2 |__ICE RAM 4 cE AAAA *MAXIMUM Ro VALUE DEPENDS ON ACTIVE-HIGH THE NUMBEROF RAMS. CELINES MINIMUM Ro VALUEIS 1k02, FROM LOGIC Vec PFI SVLAXLAA MAX691A MAX693A MAX800L MAX800M TOuP i OPTIONAL Sv PFO A ov | _ ov VL Vip YH AL + Fe Viap = 125 Fe 11 R3 VH= 125 Er ROIS Ri RB Figure 10. Alternate CE Gating Using Separate Power Supplies for VBATT and Voce If using separate power supplies for Vec and VBATT, VBATT must be less than 0.3V above Voc when Veg is above the reset threshold. As described in the previ- ous section, if VBATT exceeds this limit and power is lost at Veco, current flaws continuously from VBATT to Veo via the VBATT-to-Vout diode and the Vout to-Vec switch until the circuit is broken (Figure 8). Alternate Chip-Enable Gating Using memory devices with beth CE and CE inputs allows the CE loop to be bypassed. To do this, con- nect CE IN to ground, pull up CE OUT to Vout, and connect CE OUT to the CE input of each memory device (Figure 10). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated. Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail com- parator and prevents repeated triggering of PFO when Vin is near the power-fail comparator trip point. Figure 11 shows how to add hysteresis to the power-fail com- MA AXIMA Figure 11. Adding Hysteresis to the Power-Fail Comparator +5V' Ri Vee PA PRO MAXIMA MAX691A MAX693A Re MAX800L MAX800M GND Sv PFO ov i Vip ov y- 6-125 1.25- VAP Ri Fe NOTE Viap IS NEGATIVE Figure 12. Monitoring a Negative Voltage 13 NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits 100 7 TTT TT 2 z Vee = 5V | z = Ta=+28C 2 S a0 O.1 uF CAPACIT = N FROM Vor TO GND = x N - 60 Mt mn i Z N ao 40 Ee DN = MW a wl 2 20 Fi =< = My o 10 100 1000 10000 RESET COMPARATOR OVERDRIVE, (Reset Threshold Voltage - Vcc) (mV) Figure 13. Maximum Transient Duration without Causing a Reset Pulse vs. Reset Comparator Overdrive parator. Select the ratio of Ri and Re such that PFI sees 1.25V when Vy falls to the desired trip point (Vypip}. Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than Ri or R2. The current through Ri and Re should be at least 1A to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k to prevent it from loading down the PFO pin. Gapacitor C1 adds noise rejection. Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply voltage using Figure 12s circuit. When the negative supply is valid, PFO is low. When the neg- ative supply voltage drops, PFO goes high. This cir- cuits accuracy is affected by the PFI threshold tolerance, the Veg voltage, and resistors Ri and Re. 14 Backup-Battery Replacement The backup battery may be disconnected while Veg is above the reset threshold. No precautions are neces- sary to avoid spurious reset pulses. Negative-Going Vcc Transients While issuing resets to the uP during power-up, power- down, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going Voc transients (glitches). It is usually undesirable to reset the WP when Vec experiences only small glitches. Figure 13 shows maximum transient duration vs. reset- comparator overdrive, for which reset pulses are not generated. The graph was produced using negative- going Veg pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset com- parator overdrive). The graph shows the maximum pulse width a negative-going Vec transient may typical- ly have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes far- ther below the reset threshold), the maximum allowable pulse width decreases. Typically, a Veg transient that goes 100mV below the reset threshold and lasts for 40us or less will not cause a reset pulse to be issued. A 100nF bypass capacitor mounted close to the Voc pin provides additional transient immunity. Connecting a Timing Capacitor at OSC IN When OSC SEL is connected to ground, OSC IN dis- connects from its internal 10uA (typ) pull-up and is internally connected to a +100nA current source. When a capacitor is connected from OSC IN to ground (to select alternative reset and watchdog timeout peri- ods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. To prevent timing errors or oscillator start-up problems, minimize external current leakage sources at this pin, and locate the capacitor as close to OSC IN as possible. The sum of PC-board leakage plus OSC capacitor leakage must be small compared to +100nA. MAAXIAAMicroprocessor Supervisory Circuits Maximum Voc Fall Time The Vee fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/us. A standard rule of thumb for filter capacitance on most regulators is on the order of 100UF per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial Ver fall rate is just the inverse or 1A/100UF = 0.01V/us. The Voc fall rate decreases with time as Voc falls expo- nentially, which more than satisfies the maximum fall-time requirement. Watchdog Software Considerations A way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than pulsing the watchdog input high-low-high or low-high-low. This technique avoids a stuck loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 14 shows an example flow diagram where the I/O dri- ving the watchdog input is set high at the beginning of the program, set low at the beginning of every subrou- tine or loop, then set high again when the program returns to the beginning. If the program should hang in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. MA AXIMA START SET WDI Low RETURN == Figure 14. Waichdog Flow Diagram 15 NWOO8XVW/ 1008XVW/VEEBIUXVW/VLE9OXVNMAX691A/MAX693A/MAX800L/MAX800M Microprocessor Supervisory Circuits _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX693ACPE OT to 4+70T 16 Plastic DIP MAX693ACSE 0 to +70T 16 Narrow SO MAX693ACWE 0T to +70T 16 Wide SO MAX693AC/D 0T to +70 Dice MAX693AEPE 40% to +85 16 Plastic SO MAX693AESE 40C to +85 16 Narrow SO MAX693AEWE 40 to +85 16 Wide SO MAX693AEJE 40 to +85 16 CERDIP MAX693AMJE 55 to 4125 16 CERDIP MAXs00LCPE OT to 4+70T 16 Plastic DIP MAX800LCSE 0 to +70 16 Narrow SO MAX800LEPE 40% to +85 16 Plastic DIP MAX800LESE 40 to +85 16 Narrow SO MAXS00MCPE 0T to +70T 16 Plastic DIP MAX800MCSE OT to +70T 16 Narrow SO MAX800MEPE 40% to +85 16 Plastic DIP MAX800MESE 40C to +85 16 Narrow SO * Dice are specified at T, = +25C, DC parameters only. Chip Topography VBATT RESET RESET Vour 4mm) BATT ON LOW LINE woDl OSCIN | PFI PFO OSC SEL 0.07" (1.778mm) TRANSISTOR COUNT: 729 SUBSTRATE CONNECTED TO VouT Package Information NOTES! 1, DRE 2@ MOLD FL TO EXCEED 15h 10067" 2, LEADS 10 BE COPLANAR wITHIN 2mm 0044: 4. CONTFOLLING DIMENTION: HILLINETER 5, HEETS JEDEC Mi0le-as a2 CHDwhl IN ABOVE TABLE 6 N= NUMBER OF PIN + a uo a BO NOT INCLUDE MOLD FLA=H 63H OF PROTPUSIONS HOT AA ADL ference FenLy OUTLINE: SOIC ast |; fet-anst ay DM a ATTN rire Tren Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim tntegrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 16 1996 Maxim Integrated Products Printed USA MAXLM js a registered trademark of Maxim Integrated Products.