ADS901E/1KG4 - Texas Instruments

Pipeline

A/D

Reference

Ladder

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H 10-Bit

Digital

Data

CLK

ADS901

LVDD

OEPwrdn

REFBCMREFT

DESCRIPTION

The ADS901 is a high-speed pipelined analog-to-digital

converter that operates from a +3V power supply. This

complete converter includes a wide bandwidth track/hold

and a 10-bit quantizer. The full scale input range is set by

external references.

The ADS901 employs digital error correction techniques to

provide excellent differential linearity for demanding imag-

ing applications. Its low distortion and high SNR give the

extra margin needed for telecommunications, video and test

instrumentation applications. The ADS901 is available in an

SSOP-28 package.

10-Bit, 20MHz, +3V Supply

ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

●BATTERY POWERED EQUIPMENT

●CAMCORDERS

●DIGITAL CAMERAS

●COMPUTER SCANNERS

●COMMUNICATIONS

FEATURES

●LOW POWER: 48mW at +3V

●SUPPLY RANGE: +2.7V to +3.7V

●ADJUSTABLE FULL SCALE RANGE WITH

EXTERNAL REFERENCES

●NO MISSING CODES

●WIDEBAND TRACK/HOLD: 350MHz

●POWER DOWN: 15mW

●SSOP-28 PACKAGE

ADS901E

ADS901

SBAS054A – MAY 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS901

2SBAS054A

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.

+VS....................................................................................................... +6V

Logic VDD ............................................................................................. +6V

Analog Input............................................................................... +VS +0.3V

Logic Input ................................................................................. +VS +0.3V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +125°C

ABSOLUTE MAXIMUM RATINGS

ADS901E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

Resolution 10 Bits

Specified Temperature Range Ambient Air –40 +85 °C

ANALOG INPUT

Specified Full Scale Input Range

(1)

1Vp-p V

Common-Mode Voltage (Midscale) 1.5 V

Analog Input Bias Current 1µA

Input Impedance 1.25 || 5 MΩ || pF

DIGITAL INPUT

Logic Family CMOS Compatible

Convert Command (Start Conversion) Start Conversion Rising Edge of Convert Clock

CONVERSION CHARACTERISTICS

Sample Rate Full 10k 20M Samples/s

Data Latency 5 Clk Cyc

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

ADS901E SSOP-28 324 –40°C to +85°C ADS901E ADS901E Rail

ADS901E SSOP-28 324 –40°C to +85°C ADS901E ADS901E/1K Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces

of “ADS901E/1K” will get a single 1000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

ADS901 3

SBAS054A

ADS901E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = LVDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 500kHz Full ±0.8 LSB

f = 9MHz Full ±0.9 ±1.0 LSB

No Missing Codes Full Guaranteed

Integral Nonlinearity Error, f = 500kHz Full ±3.5 LSB

Spurious Free Dynamic Range(2)

f = 500kHz (–1dBFS(3) input) Full 50 dBFS(3)

f = 9MHz (–1dBFS input) Full 45 49 dBFS

Signal-to-Noise Ratio (SNR) Referred to Sinewave Input Signal

f = 500kHz (–1dBFS input) Full 53 dB

f = 9MHz (–1dBFS input) Full 48 53 dB

Maximum SNR

Referred to DC Full Scale Input Signal

f = 9MHz (–1dBFS input) 62 dB

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input) Full 50 dB

f = 3.58MHz (–1dBFS input) Full 50 dB

f = 9MHz (–1dBFS input) Full 45 49 dB

Effective Number of Bits(4) fIN = 3.58MHz 8.0 Bits

Differential Gain Error NTSC, PAL 2.3 %

Differential Phase Error NTSC, PAL 1.0 degrees

Output Noise Input Grounded 0.2 LSB rms

Aperture Delay Time 3ns

Aperture Jitter 7 ps rms

Analog Input Bandwidth

Small Signal –20dBFS Input 350 MHz

Full Power 0dBFS Input 100 MHz

Overvoltage Recovery Time(5) 2ns

DIGITAL OUTPUTS CL = 15pF

Logic Family CMOS Compatible

Logic Coding Straight Offset Binary

High Output Voltage, VOH +2.4 LVDD V

Low Output Voltage, VOL +0.4 V

3-State Enable Time OE = L 20 40 ns

3-State Disable Time OE = H 18 10 ns

Internal Pull-Down to Gnd 50 kΩ

Power-Down Enable Time Pwrdn = L 133 ns

Power-Down Disable Time Pwrdn = H 18 ns

Internal Pull-Down to Gnd 50 kΩ

ACCURACY fS = 2.5MHz

Gain Error Full 2.5 %FS

Input Offset(6) Full 0.4 %FS

Power Supply Rejection (Gain) ∆ VS = +10% Full 56 dB

Power Supply Rejection (Offset) Full 68 dB

External REFT Voltage Range Full REFB +0.5 2 VS–0.8 V

External REFB Voltage Range Full 0.8 1 REFT –0.5 V

Reference Input Resistance 4kΩ

POWER SUPPLY REQUIREMENTS

Supply Voltage: +VSOperating Full +2.7 +3.0 +3.7 V

Supply Current: +ISOperating Full 16 mA

Power Dissipation Operating Full 49 60 mW

Power Dissipation (Power Down) Operating Full 15 mW

Thermal Resistance,

28-Lead SSOP 89 °C/W

NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic.

(3) dBFS is dB relative to full scale. (4) Based on (SINAD - 1.76)/6.02. (5) No “Rollover” of bits. (6) Offset Deviation from Ideal Negative Full Scale.

ADS901

4SBAS054A

5 Clock Cycles

Data Invalid

CONV

N–5N–4N–3N–2N–1 N N+1 N+2

Data Out

Clock

Analog In N

N+1 N+2 N+3 N+4 N+5 N+6 N+7

TOP VIEW SSOP

PIN CONFIGURATION

PIN DESIGNATOR DESCRIPTION

1+V

SAnalog Supply

2LV

DD Output Logic Driver Supply Voltage

3 Bit 10 Data Bit 10 (D0) (LSB)

4 Bit 9 Data Bit 9 (D1)

5 Bit 8 Data Bit 8 (D2)

6 Bit 7 Data Bit 7 (D3)

7 Bit 6 Data Bit 6 (D4)

8 Bit 5 Data Bit 5 (D5)

9 Bit 4 Data Bit 4 (D6)

10 Bit 3 Data Bit 3 (D7)

11 Bit 2 Data Bit 2 (D8)

12 Bit 1 Data Bit 1 (D9) (MSB)

13 GND Analog Ground

14 GND Analog Ground

15 CLK Convert Clock Input

16 OE Output Enable, Active Low

17 Pwrdn Power Down Pin

18 +VSAnalog Supply

19 GND Analog Ground

20 GND Analog Ground

21 LpBy Positive Ladder Bypass

22 REFT Top Reference Input

23 NC No Connection

24 REFB Bottom Reference Input

25 LnBy Negative Ladder Bypass

26 CM Common-Mode Voltage Output

27 IN Analog Input

28 +VSAnalog Supply

PIN DESCRIPTIONS

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tCONV Convert Clock Period 50 100µsns

tLClock Pulse Low 24 25 ns

tHClock Pulse High 24 25 ns

tDAperture Delay 3 ns

t1Data Hold Time, CL = 0pF 3.9 ns

t2New Data Delay Time, CL = 15pF max 12 ns

(LSB) Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

(MSB) Bit 1

GND

LnBy

REFB

REFT

LpBy

GND

Pwrdn

CLK

ADS901

ADS901 5

SBAS054A

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 9MHz

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 500kHz

DIFFERENTIAL LINEARITY ERROR

Output Code

–1

–20 256 512 768 1024

DLE (LSB)

= 500kHz

TYPICAL CHARACTERISTICS

At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.

SPECTRAL PERFORMANCE

Frequency (MHz)

–20

–40

–60

–80

–100 0246810

Amplitude (dB)

= 3.58MHz

TWO-TONE INTERMODULATION

Frequency (MHz)

–20

–40

–60

–80

–100 0 2.5 5 7.5 10

Amplitude (dB)

f1 = 4.5MHz

f2 = 5.0MHz

DIFFERENTIAL LINEARITY ERROR

Output Code

–1

–2

DLE (LSB)

= 9MHz

0 256 512 768 1024

ADS901

6SBAS054A

UNDERSAMPLING

Frequency (MHz)

–20

–40

–60

–80

–100

–120 0 16.2 32.4 48.6 64.8 81.0

Amplitude (dB)

= 20MHz

= 16MHz

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS = Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.

INTEGRAL LINEARITY ERROR

Output Code

–5

–10

ILE (LSB)

fIN = 500kHz

0 256 512 768 1024

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

Temperature (°C)

0.9

0.8

0.7

0.6–50 0 25–25 50 75 100

DLE (LSB)

fIN = 9MHz

fIN = 500kHz

SWEPT POWER SFDR

Input Amplitude (dBFS)

100

0–60 –40–50 –30 –20 –10 0

SFDR (dBc, dBFS)

dBFS

dBc

SPURIOUS FREE DYNAMIC RANGE (SFDR)

vs TEMPERATURE

Temperature (°C)

48–50 0 25–25 50 75 100

SFDR (dBFS)

fIN = 500kHz

fIN = 9MHz

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Frequency (MHz)

500.1 1 10

SFDR (dBFS), SNR (dB)

SNR

SFDR

ADS901 7

SBAS054A

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VS, Logic VDD = +3V, REFB = 1V, REFT = 2V, Specified Input Range = 1V to 2V, Sampling Rate = 20MHz, unless otherwise specified.

POWER DISSIPATION vs TEMPERATURE

Temperature (°C)

45–50 0 25–25 50 75 100

Power Dissipation (mW)

OFFSET ERROR vs TEMPERATURE

Temperature (°C)

–50 0 25–25 50 75 100

Offset Error (% FS)

0.6

0.5

0.4

0.3

OUTPUT NOISE HISTOGRAM (DC Input)

Output Code

0N-2 N-1 N+1N N+2

Counts (x105)

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

Temperature (°C)

52–50 0 25–25 50 75 100

SNR (dB)

= 9MHz

= 500kHz

GAIN ERROR vs TEMPERATURE

Temperature (°C)

2.8

2.7

2.6

2.5

2.4–50 0 25–25 50 75 100

Gain Error (%FS)

POWER DISSIPATION vs SAMPLING FREQUENCY

Frequency (MHz)

35 1 10 100

Power Dissipation (mW)

ADS901

8SBAS054A

402Ω

1kΩ

0.1µF

+5V R

50Ω

–5V

+3V

ADS901

THEORY OF OPERATION

The ADS901 is a high speed sampling analog-to-digital

converter that utilizes a pipeline architecture. The fully

differential topology and digital error correction guarantee

10-bit resolution. The differential track/hold circuit is shown

in Figure 1. The switches are controlled by an internal clock

which has a non-overlapping two phase signal, φ1 and φ2. At

the sampling time the input signal is sampled on the bottom

plates of the input capacitors. In the next clock phase, φ1, the

bottom plates of the input capacitors are connected together

and the feedback capacitors are switched to the op amp

output. At this time the charge redistributes between CI and

CH, completing one track/hold cycle. The differential output

is a held DC representation of the analog input at the sample

time. The track/hold circuit can also convert a single-ended

input signal into a fully differential signal for the quantizer.

Consequently, the input signal-to-noise performance. Other

parameters such as small-signal and full-power bandwidth,

and wideband noise are also defined in this stage.

To accommodate a bipolar signal swing, the ADS901 oper-

ates with a common-mode voltage (VCM) which is derived

from the external references. Due to the symmetric resistor

ladder inside the ADS901, the VCM is situated between the

top and bottom reference voltage. Equation (1) can be used

for calculating the common-mode voltage level.

VCM = (REFT +REFB)/2 (1)

There is a 5.0 clock cycle data latency from the start convert

signal to the valid output data. The standard output coding

is Straight Offset Binary where a full scale input signal

corresponds to all “1’s” at the output. The digital outputs of

the ADS901 can be set to a high impedance state by driving

the three-state (pin 16) with a logic “HI”. Normal operation

is achieved with pin 16 “LO” or Floating due to internal

pull-down resistors. This function is provided for testability

purposes but is not recommended to be used dynamically.

APPLICATIONS

SIGNAL SWING AND COMMON-MODE

CONSIDERATIONS

The ADS901 is designed to operate on a +3V single supply

voltage. The nominal input signal swing is 1Vp-p, situated

between +1V and +2V. This means that the signal swings

±0.5V around a common-mode voltage of +1.5V, which is

half the supply voltage (VCM = VS/2). In some applications

it might be advantageous to increase the input signal swing.

This will improve the achievable signal-to-noise perfor-

mance. However, considerations should be made to keep the

signal swing within the linear range of operation of the

driving circuitry to avoid any excessive distortion. In ex-

treme situations the performance of the converter will start

to degrade due to variations of the input’s switch on-

resistance over the input voltage. Therefore, the signal swing

should remain approximately 0.5V away from each rail

during normal operation.

DRIVING THE ANALOG INPUTS

AC-COUPLED DRIVER

Figure 2 shows an example of an ac-coupled, single-ended

interface circuit using a high-speed op amp that operates on

OUT

Op Amp

Bias V

Op Amp

Bias V

Input Clock (50%)

Internal Non-overlapping Clock

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

The pipelined quantizer architecture has 9 stages with each

stage containing a two-bit quantizer and a two bit digital-

to-analog converter, as shown in Figure 2. Each two-bit

quantizer stage converts on the edge of the sub-clock, which

is the same frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to

time-align it with the data created from the following quan-

tizer stages. This aligned data is fed into a digital error

correction circuit which can adjust the output data based on

the information found on the redundant bits. This technique

provides the ADS901 with excellent differential linearity

and guarantees no missing codes at the 10-bit level. FIGURE 2. AC-Coupled, Single-Ended Interface Circuit.

ADS901 9

SBAS054A

1kΩ

OPA680

402Ω

0.1µF

+5V

50Ω

+3V

402Ω

0.1µF

402Ω

22pF ADS901

FIGURE 4. DC-Coupled Interface Circuit for +3V Single-Supply Operation.

dual supplies (OPA650, OPA658). The mid-point reference

voltage, VCM, biases the bipolar, ground-referenced input

signal. The capacitor C1 and resistor R1 form a high-pass

filter with the –3dB frequency set at

f–3dB = 1/(2 π R1 C1) (2)

The values for C1 and R1 are not critical in most applications

and can be set freely. The values shown correspond to a

frequency of 1.6kHz.

Figure 3 depicts a circuit that can be used in single-supply

applications. The mid-reference voltage biases the op amp

up to the appropriate common-mode voltage, for example

VCM = +1.5V. With the use of capacitor CG the DC gain for

the non-inverting op amp input is set to +1V/V. As a result

the transfer function is modified to

VOUT = VIN {(1 + RF/RG) + VCM} (3)

Again, the input coupling capacitor C1 and resistor R1 form

a high-pass filter. At the same time the input impedance is

defined by R1. Resistor RS isolates the op amp’s output from

the capacitive load to avoid gain peaking or even oscillation.

It can also be used to establish a defined bandwidth to reduce

the wideband noise. The recommended value is usually

between 10Ω and 100Ω.

DC-COUPLED INTERFACE CIRCUIT

Many systems are now requiring +3V single supply capabil-

ity of both the A/D converter and its driver. Figure 4 shows

an example for DC-coupled configuration operating solely

on a +3V supply voltage. The OPA632 provides excellent

performance in this demanding application. Its wide input

and output voltage ranges, an low distortion, supports the

ADS901 well. The OPA632 is configured for a gain of +2.

The 374Ω and 2.26kΩ resistors at the input level-shift VIN

so that VOUT is within the allowed output voltage range

when VIN = 0. The input impedance of the driver circuit is

set to match to a 50Ω source impedance. The input level-

shifting was designed that VIN can be between 0V and 5V,

while delivering an output voltage of 1V to 2V into the

ADS901. Both the OPA632 and ADS901 have a power-

down function pin with the same polarity for those systems

the need to conserve power.

EXTERNAL REFERENCE

The ADS901 requires external references on pin 22 (REFT)

and 24 (REFB). Internally those pins are connected through a

resistor ladder, which has a nominal resistance of 4kΩ

(±15%). In order to establish a correct voltage drop across the

ladder the external reference circuit must be able to typically

supply 250µA of current. With this current the full-scale input

range of the ADS901 is set between +1V and +2V, or 1Vp-p.

In general, the voltage drop across REFT and REFB deter-

mines the input full-scale range (FSR) of the ADS901. Equa-

tion (4) can be used to calculate the span.

FSR = REFT - REFB (4)

Depending on the application, several options are possible to

supply the external reference voltages to the ADS901 without

degrading the typical performance.

FIGURE 3. Interface Circuit. Example using the voltage feedback amplifier OPA680.

OPA632

750Ω562Ω

2.26kΩ

374Ω

22pF

+3V

100ΩPwrdn

DIS

Disable +3V

ADS901

10-Bit

20Msps

57.6Ω

ADS901

10 SBAS054A

1kΩ

1kΩLpBy

+2V

+1V

REFT

REFB

LnBy

+VS

4kΩ

1kΩ

4kΩ

1kΩ

0.1µF

+3V

VIN

ADS901

0.1µF

1kΩ

0.1µF10µF

LOW-COST REFERENCE SOLUTION

The easiest way to achieve the required reference voltages is

to place the reference ladder of the ADS901 between the

supply rails, as shown in Figure 5. Two additional resistors

(RT, RB) are necessary to set the correct current through the

ladder. However depending on the desired full-scale swing

and supply voltage different resistor values might be se-

lected.

The trade-offs, when selecting this reference circuit, are

variations in the reference voltages due to component toler-

ances and power supply variations. In any case, it is recom-

mended to bypass the reference ladder with at least 0.1µF

ceramic capacitors, as shown in Figure 5. The capacitors

serve a dual purpose. They will bypass most of the high

frequency transient noise which results from feedthrough of

the clock and switching noise from the T/H stages. Sec-

ondly, they serve as a charge reservoir to supply instanta-

neous current to internal nodes.

FIGURE 5. Low Cost Solution to Supply External Reference Voltages and Recommended Reference Bypassing.

PRECISE REFERENCE SOLUTION

For those applications requiring a higher level of dc accu-

racy and drift, a reference circuit with a precision reference

element might be used (see Figure 6). A stable +1.2V

reference voltage is established by a two terminal bandgap

reference diode, the REF1004-1.2. Using a general-purpose

single-supply dual operational amplifier (A1), like an

OPA2237, OPA2234 or OPA2343, the two required refer-

ence voltages for the ADS901 can be generated by setting

each op amp to the appropriate gain; for example: set REFT

to +2V and REFB to +1V.

CLOCK INPUT

The clock input of the ADS901 is designed to accommodate

either +5V or +3V CMOS logic levels. To drive the clock

input with a minimum amount of duty cycle variation and

support maximum sampling rates (20Msps), high speed or

advanced CMOS logic should be used (HC/HCT, AC/ACT).

When digitizing at high sampling rates, a 50% duty cycle

clock with fast rise and fall times (2ns or less) are recom-

mended to meet the rated performance specifications. How-

ever, the ADS901 performance is tolerant to duty cycle

variations of as much as ±10% without degradation. For

applications operating with input frequencies up to Nyquist

or undersampling applications, special consideration must

be made to provide a clock with very low jitter. Clock jitter

leads to aperture jitter (tA) which can be the ultimate limita-

tion to achieving good SNR performance. Equation (5)

shows the relationship between aperture jitter, input fre-

quency and the signal-to-noise ratio:

SNR = 20log10 [1/(2 π fIN tA)] (5)

For example, with a 10MHz full-scale input signal and an

aperture jitter of tA = 20ps, the SNR is clock jitter limited to

58dB.

+FS (IN = +2V) 1111111111

+FS –1LSB 1111111111

+FS –2LSB 1111111110

+3/4 Full Scale 1110000000

+1/2 Full Scale 1100000000

+1/4 Full Scale 1010000000

+1LSB 1000000001

Bipolar Zero (IN +1.5V) 1000000000

–1LSB 0111111111

–1/4 Full Scale 0110000000

–1/2 Full Scale 0100000000

–3/4 Full Scale 0010000000

–FS +1LSB 0000000001

–FS (IN = +1V) 0000000000

STRAIGHT OFFSET BINARY

(SOB)

PIN 12

SINGLE-ENDED INPUT FLOATING or LO

TABLE I. Coding Table for the ADS901.

ADS901 11

SBAS054A

DIGITAL OUTPUTS

There is a 5.0 clock cycle data latency from the start convert

signal to the valid output data. The standard output coding

is Straight Offset Binary where a full scale input signal

corresponds to all “1’s” at the output. The digital outputs of

the ADS901 can be set to a high impedance state by driving

the three-state (pin 16) with a logic “HI”. Normal operation

is achieved with pin 16 “LO” or Floating due to internal

pull-down resistors. This function is provided for testability

purposes but is not recommended to be used dynamically.

The digital outputs of the ADS901 are standard CMOS

stages and designed to be compatible to both high speed

TTL and CMOS logic families. The logic thresholds are for

low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows

the ADS901 to directly interface to 3V-logic. The digital

outputs of the ADS901 use a dedicated digital supply pin

(pin 2, LVDD). By adjusting the voltage on LVDD, the digital

output levels will vary respectively. In any case, it is recom-

mended to limit the fan-out to one, to keep the capacitive

loading on the data lines below the specified 15pF. If

necessary, external buffers or latches may be used to provide

the added benefit of isolating the A/D converter from any

digital activities on the bus coupling back high frequency

noise and degrading the performance.

POWER-DOWN MODE

The ADS901’s low power consumption can be further

reduced by initiating a power down mode. For this, the

Pwrdn-Pin (Pin 17) must be tied to a logic “High” reducing

the current drawn from the supply by approximately 70%. In

normal operation the power-down mode is disabled by an

internal pull-down resistor (50kΩ).

FIGURE 6. Precise Solution to Supply External Reference

Voltages.

+LV

ADS901 Digital

Output

Stage

FIGURE 7. Independent Supply Connection for Output

Stage.

During power-down the digital outputs are set in 3-state.

With the clock applied, the converter does not accurately

process the sampled signal. After removing the power-down

condition the output data from the following 5 clock cycles

is invalid (data latency).

DECOUPLING AND GROUNDING

CONSIDERATIONS

The ADS901 converter have several supply pins, one of

which is dedicated to supply only the output driver. The

remaining supply pins are not, as is often the case, divided

into analog and digital supply pins since they are internally

connected on the chip. For this reason it is recommended to

treat the converter as an analog component and to power it

from the analog supply only. Digital supply lines often carry

high levels of noise which can couple back into the converter

and limit the achievable performance.

Because of the pipeline architecture, the converter also

generates high frequency transients and noise that are fed

back into the supply and reference lines. This requires that

the supply and reference pins be sufficiently bypassed.

Figure 8 shows the recommended decoupling scheme for the

analog supplies. In most cases 0.1µF ceramic chip capacitors

are adequate to keep the impedance low over a wide fre-

quency range. Their effectiveness largely depends on the

proximity to the individual supply pin. Therefore they should

be located as close to the supply pins as possible.

FIGURE 8. Recommended Bypassing for Analog Supply

Pins.

113 14

GND

ADS901

0.1µF

18 19 20

GND

0.1µF

1/2 A

3kΩ

5kΩ

REF1004

+1.2V

10kΩ

10ΩTop

Reference

(REFT)

1/2 A

10ΩBottom

Reference

(REFB)

= OPA2237 or Equivalent.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS901E ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

ADS901EG4 ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 26-Aug-2009

Addendum-Page 1

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