LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 LM118-N/lm218-N/LM318-N Operational Amplifiers Check for Samples: LM118-N, LM218-N, LM318-N FEATURES DESCRIPTION * * * * * * * The LM118 series are precision high speed operational amplifiers designed for applications requiring wide bandwidth and high slew rate. They feature a factor of ten increase in speed over general purpose devices without sacrificing DC performance. 1 2 15 MHz Small Signal Bandwidth Ensured 50V/s Slew Rate Maximum Bias Current of 250 nA Operates from Supplies of 5V to 20V Internal Frequency Compensation Input and Output Overload Protected Pin Compatible with General Purpose Op Amps The LM118 series has internal unity gain frequency compensation. This considerably simplifies its application since no external components are necessary for operation. However, unlike most internally compensated amplifiers, external frequency compensation may be added for optimum performance. For inverting applications, feedforward compensation will boost the slew rate to over 150V/s and almost double the bandwidth. Overcompensation can be used with the amplifier for greater stability when maximum bandwidth is not needed. Further, a single capacitor can be added to reduce the 0.1% settling time to under 1 s. The high speed and fast settling time of these op amps make them useful in A/D converters, oscillators, active filters, sample and hold circuits, or general purpose amplifiers. These devices are easy to apply and offer an order of magnitude better AC performance than industry standards such as the LM709. The LM218-N is identical to the LM118 except that the LM218-N has its performance specified over a -25C to +85C temperature range. The LM318-N is specified from 0C to +70C. Fast Voltage Follower Do not hard-wire as voltage follower (R1 5 k) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2013, Texas Instruments Incorporated LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage 20V Power Dissipation (3) Differential Input Current Input Voltage 500 mW (4) 10 mA (5) 15V Output Short-Circuit Duration Continuous Operating Temperature Range lm118-n -55C to +125C LM218-N -25C to +85C LM318-N 0C to +70C -65C to +150C Storage Temperature Range Lead Temperature (Soldering, 10 sec.) TO-99 Package 300C PDIP Package 260C Soldering Information Dual-In-Line Package Soldering (10 sec.) 260C SOIC Package Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C ESD Tolerance (1) (2) (3) (4) (5) (6) (6) 2000V Refer to RETS118X for LM118H and LM118J military specifications. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. The maximum junction temperature of the lm118-n is 150C, the LM218-N is 110C, and the LM318-N is 110C. For operating at elevated temperatures, devices in the LMC package must be derated based on a thermal resistance of 160C/W, junction to ambient, or 20C/W, junction to case. The thermal resistance of the dual-in-line package is 100C/W, junction to ambient. The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input voltage in excess of 1V is applied between the inputs unless some limiting resistance is used. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. Human body model, 1.5 k in series with 100 pF. Electrical Characteristics (1) Parameter Conditions LM118-N/LM218-N Min Typ Max 2 4 LM318-N Min Units Typ Max 4 10 mV nA Input Offset Voltage TA = 25C Input Offset Current TA = 25C 6 50 30 200 Input Bias Current TA = 25C 120 250 150 500 Input Resistance TA = 25C Supply Current TA = 25C Large Signal Voltage Gain TA = 25C, VS = 15V 1 3 50 50 nA 0.5 3 200 25 200 V/mV 70 50 70 V/s 5 8 5 M 10 mA VOUT = 10V, RL 2 k Slew Rate TA = 25C, VS = 15V, AV = 1 Small Signal Bandwidth TA = 25C, VS = 15V (2) 15 15 MHz Input Offset Voltage 6 15 mV Input Offset Current 100 300 nA (1) (2) 2 These specifications apply for 5V VS 20V and -55C TA +125C (lm118-n), -25C TA +85C (LM218-N), and 0C TA +70C (LM318-N). Also, power supplies must be bypassed with 0.1 F disc capacitors. Slew rate is tested with VS = 15V. The lm118-n is in a unity-gain non-inverting configuration. VIN is stepped from -7.5V to +7.5V and vice versa. The slew rates between -5.0V and +5.0V and vice versa are tested and specified to exceed 50V/s. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 Electrical Characteristics (1) (continued) Parameter Conditions LM118-N/LM218-N Min Typ Input Bias Current Max LM318-N Min Typ 500 Supply Current TA = 125C Large Signal Voltage Gain VS = 15V, VOUT = 10V 4.5 25 Units Max 750 7 nA mA 20 V/mV RL 2 k Output Voltage Swing VS = 15V, RL = 2 k Input Voltage Range VS = 15V 12 13 11.5 12 13 11. 5 V V Common-Mode Rejection Ratio 80 100 70 100 dB Supply Voltage Rejection Ratio 70 80 65 80 dB Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 3 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS LM118-N, LM218-N 4 Input Current Voltage Gain Figure 1. Figure 2. Power Supply Rejection Input Noise Voltage Figure 3. Figure 4. Common Mode Rejection Supply Current Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM118-N, LM218-N Closed Loop Output Impedance Current Limiting Figure 7. Figure 8. Input Current Unity Gain Bandwidth Figure 9. Figure 10. Voltage Follower Slew Rate Inverter Settling Time Figure 11. Figure 12. Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 5 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) LM118-N, LM218-N 6 Large Signal Frequency Response Open Loop Frequency Response Figure 13. Figure 14. Voltage Follower Pulse Response Large Signal Frequency Response Figure 15. Figure 16. Open Loop Frequency Response Inverter Pulse Response Figure 17. Figure 18. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 Typical Performance Characteristics LM318-N Input Current Voltage Gain Figure 19. Figure 20. Power Supply Rejection Input Noise Voltage Figure 21. Figure 22. Common Mode Rejection Supply Current Figure 23. Figure 24. Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 7 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) LM318-N 8 Closed Loop Output Impedance Current Limiting Figure 25. Figure 26. Input Current Unity Gain Bandwidth Figure 27. Figure 28. Voltage Follower Slew Rate Inverter Settling Time Figure 29. Figure 30. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 Typical Performance Characteristics (continued) LM318-N Large Signal Frequency Response Open Loop Frequency Response Figure 31. Figure 32. Voltage Follower Pulse Response Large Signal Frequency Response Figure 33. Figure 34. Open Loop Frequency Response Inverter Pulse Response Figure 35. Figure 36. Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 9 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com AUXILIARY CIRCUITS Figure 39. Offset Balancing *Balance circuit necessary for increased slew. Slew rate typically 150V/s. Figure 37. Feedforward Compensation for Greater Inverting Slew Rate Figure 40. Isolating Large Capacitive Loads Slew and settling time to 0.1% for a 10V step change is 800 ns. Figure 41. Overcompensation Figure 38. Compensation for Minimum Settling Time 10 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 TYPICAL APPLICATIONS Do not hard-wire as voltage follower (R1 5 k) Figure 42. Fast Voltage Follower CF = Large (CF 50 pF) *Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent oscillation. Do not hard-wire as voltage follower (R1 5 k) Figure 43. Figure 44. Fast Summing Amplifier Figure 45. Differential Amplifie Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 11 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com Figure 46. Fast Sample and Hold *Optional--Reduces settling time. Figure 47. D/A Converter Using Ladder Network 12 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 Output zero. *"Y" zero +"X" zero Full scale adjust. Figure 48. Four Quadrant Multiplier *Optional--Reduces settling time. Figure 49. D/A Converter Using Binary Weighted Network Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 13 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com Figure 50. Fast Summing Amplifier with Low Input Current Figure 51. Wein Bridge Sine Wave Oscillator Figure 52. Instrumentation Amplifier 14 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 Schematic Diagram Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 15 LM118-N, LM218-N, LM318-N SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 www.ti.com Pin Diagram Available per JM38510/10107. Dual-In-Line Package (Top View) See Package Number J (R-GDIP-T14) Available per JM38510/10107. Dual-In-Line Package (Top View) See Package Number NAB008A, D (R-PDSO-G8), or P (R-PDIP-T8) Pin connections shown on schematic diagram and typical applications are for TO-99 package. TO-99 Package (Top View) See Package Number LMC (O-MBCY-W8) 16 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N LM118-N, LM218-N, LM318-N www.ti.com SNOSBS8C - MARCH 1998 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 16 Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: LM118-N LM218-N LM318-N Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM118H ACTIVE TO-99 LMC 8 500 TBD Call TI Call TI -55 to 125 ( LM118H, LM118H) LM118H/NOPB ACTIVE TO-99 LMC 8 500 Green (RoHS & no Sb/Br) POST-PLATE Level-1-NA-UNLIM -55 to 125 ( LM118H, LM118H) LM318M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM 318M LM318M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 LM 318M LM318MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 LM 318M LM318N/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM 0 to 70 LM 318N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM318MX/NOPB Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 5.4 2.0 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM318MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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