© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 6
1Publication Order Number:
MC14518B/D
MC14518B, MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P−channel and N−channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4−stage
counters. The counter stages are type D flip−flops, with interchangeable
Clock and Enable lines for incrementing on either the positive−going or
negative−going transition as required when cascading multiple stages.
Each counter can be cleared by applying a high level on the Reset line.
In addition, the MC14518B will count out of all undefined states within
two clock periods. These complementary MOS up counters find
primary use in multi−stage synchronous or ripple counting applications
requiring low power dissipation and/or high noise immunity.
Features
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Internally Synchronous for High Internal and External Speeds
•Logic Edge−Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition on Enable
•Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10 mA
PDPower Dissipation,
per Package (Note 2.)
500 mW
TAOperating Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature
(8−Second Soldering)
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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xx = 18 or 20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Indicator
MARKING
DIAGRAMS
1
16
PDIP−16
P SUFFIX
CASE 648
MC145xxBCP
AWLYYWWG
SO−16 WB
DW SUFFIX
CASE 751G
1
16
145xxB
AWLYYWWG
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC145xxB
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
MC14518B, MC14520B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q1B
Q2B
Q3B
RB
VDD
CB
EB
Q0B
Q1A
Q0A
EA
CA
VSS
RA
Q3A
Q2A
BLOCK DIAGRAM
VDD = PIN 16
VSS = PIN 8
3
4
5
6
14
13
12
11
C
C
R
RQ3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
CLOCK
1
2
CLOCK
ENABLE
ENABLE
7
9
10
15
TRUTH TABLE
Clock Enable Reset Action
1 0 Increment Counter
0 0 Increment Counter
X 0 No Change
X 0 No Change
0 0 No Change
1 0 No Change
X X 1 Q0 thru Q3 = 0
X = Don’t Care
MC14518B, MC14520B
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3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min Typ (3.) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ± 0.1 —±0.00001 ± 0.1 —± 1.0 μAdc
Input Capacitance
(Vin = 0)
Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
μAdc
Total Supply Current (4.) (5.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.6 μA/kHz) f + IDD
IT = (1.2 μA/kHz) f + IDD
IT = (1.7 μA/kHz) f + IDD
μAdc
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
MC14518B, MC14520B
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4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD
All Types
Unit
Min Typ (7.) Max
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q/Enable to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Reset to Q
tPHL = (1.7 ns/pF) CL + 265 ns
tPHL = (0.66 ns/pF) CL + 117 ns
tPHL = (0.66 ns/pF) CL + 95 ns
tPLH,
tPHL
5.0
10
15
—
—
—
280
115
80
560
230
160
ns
tPHL
5.0
10
15
—
—
—
330
130
90
650
230
170
ns
Clock Pulse Width tw(H)
tw(L)
5.0
10
15
200
100
70
100
50
35
—
—
—
ns
Clock Pulse Frequency fcl 5.0
10
15
—
—
—
2.5
6.0
8.0
1.5
3.0
4.0
MHz
Clock or Enable Rise and Fall Time tTHL, tTLH 5.0
10
15
—
—
—
—
—
—
15
5
4
μs
Enable Pulse Width tWH(E) 5.0
10
15
440
200
140
220
100
70
—
—
—
ns
Reset Pulse Width tWH(R) 5.0
10
15
280
120
90
125
55
40
—
—
—
ns
Reset Removal Time trem 5.0
10
15
– 5
15
20
– 45
– 15
– 5
—
—
—
ns
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
VARIABLE
WIDTH
CL
CL
CL
CL
VDD
VSS
VSS
500 μF0.01 μF
CERAMIC
20 ns
50% 10%
90%
20 ns
ID
Q3
Q2
Q1
Q0
C
E
R
MC14518B, MC14520B
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5
Figure 2. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
CL
CL
CL
CL
VDD
VSS
Q3
Q2
Q1
Q0
C
E
R
20 ns
Q
trtf
VDD
VSS
20 ns
CLOCK
INPUT
90%
50%
10%
tWL
tWH
90% 50%
10%
tPLH tPHL
Figure 3. Timing Diagram
18
1716151413121110987654321
0987654321
2
101514
1312111098765432143
0987654321
CLOCK
ENABLE
RESET
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
MC14518B
MC14520B
MC14518B, MC14520B
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6
Figure 4. Decade Counter (MC14518B) Logic Diagram
(1/2 of Device Shown)
D
CR
Q
Q
D
CR
Q
Q
D
CR
Q
Q
D
CR
Q
Q
Q0 Q1 Q2 Q3
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram
(1/2 of Device Shown)
D
CR
Q
Q
D
CR
Q
Q
D
CR
Q
Q
D
CR
Q
Q
Q0 Q1 Q2 Q3
RESET
ENABLE
CLOCK
MC14518B, MC14520B
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7
ORDERING INFORMATION
Device Package Shipping†
MC14518BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14518BDWG SO−16 WB
(Pb−Free)
47 Units / Rail
MC14518BDWR2G SO−16 WB
(Pb−Free)
1000 Units / Tape & Reel
MC14518BFELG SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
MC14520BCPG PDIP−16
(Pb−Free)
500 Units / Rail
MC14520BDWG SO−16 WB
(Pb−Free)
47 Units / Rail
MC14520BDWR2G SO−16 WB
(Pb−Free)
1000 Units / Tape & Reel
MC14520BFELG SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14518B, MC14520B
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8
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
SO−16 WB
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
MC14518B, MC14520B
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9
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
MC14518B/D
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