82527 - Express INTRODUCTION The 82527 serial communications controller is a highly integrated device that performs serial communication according to the CAN protocol. It performs all serial communication functions such as transmission and reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from the host microcontroller, or CPU. The 82527 is Intels first device to support the standard and extended message frames in CAN Specification 2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the standard message frames in CAN Specification 2.0 Part A. The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-multiplexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SPI) is also available when a parallel CPU interface is not required. The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be configured as either transmit or receive except for the last message object. The last message object is a receive-only buffer with a special mask design to allow select groups of different message identifiers to be received. The 82527 also implements a global masking feature for message filtering. This feature allows the user to globally mask any identifier bits of the incoming message. The programmable global mask can be used for both standard and extended messages. The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the 82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as CPU interface mode selection pins on the 82527. The 82527 is fabricated using Intels reliable CHMOS III 5V technology and is available in 44-lead PLCC for the express temperature range (40C to +85C). ADVANCE INFORMATION Datasheet 182527 - Express In Piqure 1, TNS2527 - Express Block Diegram Port 1 Port 2 > T XO Address/ a 1X1 Data Bus CAN CPU Controller Interface Control Bus wae RX1 Mode 0 Mode 1 CLKOUT 4577-01 Figure 2. TN62527 44-Pin PLCC Package rn wn 7) Qo 5 We a = a = woo A4B8aA 8o8aas Ctteaq> scarce Doon lf oornnr~ sagre evyrds (WR# / WRL#)/(R/AW#) 7 39 1 AD7 cs#e]8 38 I P1.0/ AD8 DSACKO 9 37(9P1.1/ AD9 P2.7 / WRH# Eq 10 36 P1.2/ AD10 P2.6/ INTHE 11 TN82527 35 P1.3/AD11 P2.5E4 12 34, P1.4/ AD12 P24] 13 339 P1.5/ AD13 P23E)14 View of component as 32-IP1.6/AD14 P2.2 Ey 15 mounted on PC board 319 P1.7/ AD15 P2.1 1] 16 30, MODE1 P2.0 G4 17 29 RESET# OAMOrKNMTN OR TKHeHNNNNNNNN SN UOOUQUUODUUUUU TN NT OY AT OEKEO a31exx 9Sxxaq ttre SFrFOE Keo SS Fs om e qa zZ hi oc 4578-01 2 ADVANCE INFORMATION Datasheetintel : 82527 - Express 2.0 PIN DESCRIPTIONS The 82527 - Express pins are described in this section. Table 1 presents the legend for interpreting the pin types. Table 1. Pin Type Legend Symbai Description I Input Only Pin oO Output Only Pin VO Pin can be either Input or Output Table 2. Pin Descriptions (Sheet 1 of 23 Name Type Description GROUND connection must be connected externally to a Vgg board Vssi Ground plane. Provides digital ground. Vv G d GROUND connection must be connected externally to a Vgg board 8S2 roun plane. Provides ground for analog comparator. Vv Pp POWER connection must be connected externally to +5 V DC. Provides ce ower power for entire device. Input for an external clock. XTAL1 (along with XTAL2) are the crystal XTALI connections to an internal oscillator. Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) XTAL2 O are the crystal connections to an internal oscillator. If an external oscillator is used, XTAL2 must be floated, or not be connected. XTAL2 must not be used as a clock output to drive other CPUs. CLKOUT O Programmable clock output. This output may be used to drive the oscillator of the host microcontroller. Warm Reset: (Vcc remains valid while RESET# is asserted), RESET# must be driven to a valid low level for 1 ms minimum. RESET# Cold Reset: (Vcc is driven to a valid level while RESET# is asserted), RESET# must be driven low for 1 ms minimum measured from a valid Voc level. No falling edge on the reset pin is required during a cold reset event. CSH## A low level on this pin enables CPU access to the 82527 device. The interrupt pin is an open-drain output to the host microcontroller. Vec/2 is the power supply for the ISO low speed physical layer. The INT# oO function of this pin is determined by the MUX bitin the CPU Interface Register (Address 02H) as follows: (Vec/2) O ; MUX e 1: pin 24 (PLCC) = Ve /2, pin 11 = INT# MUX e 0: pin 24 (PLCC) = INT# Inputs from the CAN bus line(s) to the input comparator. A recessive level RXO | is read when RXO > RX1. A dominant level is read when RX1 > RXO. RX1 | When the CoBy bit (Bus Configuration register) is programmed as a 1, the input comparator is bypassed and RX0O is the CAN bus line input. TXO Oo Serial data push-pull output to the CAN bus line. During a recessive bit TXO TX1 oO is high and TX1 is low. During a dominant bit TXO is low and TX1 is high. ADVANCE INFORMATION Datasheet 3a 82527 - Express I ntel Table 2. Pin Descriptions (Sheet 2 of 2) Name Type Description Address/Data bus in 8-bit multiplexed mode. ADO/AO/ICP VO-l-I Address bus in 8-bit non-multiplexed mode. AD1/A1/CP VO-I-I Low byte of A/D bus in 16-bit multiplexed mode. ADGIAGISTE MO In Serial Interface mode, the following pins have the following meaning: AD5/A5 V/Oo-l AD1: CP Clock Phase AD7/A7 VO- ADS: STE Sync Transmit Enable AD6: SCLK Serial Clock Input AD4: MOSI Serial Data Input AD8/D0/P1.0 V/0-O0-1/0 AD9/D1/P1.1 V/0-O0-1/0 High byte of A/D bus in 16-bit multiplexed mode. AD10/D2/P1.2 VO-0-/O Data bus in 8-bit non-multiplexed mode. AD11/D3/P1.3 V/0-O0-1/0 ar : : . AD12/D4/P1.4 /0-0-V/O Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode. AD13/D5/P1.5 V/0-O0-1/0 Port pins have weak pullups until the port is configured by writing to 9FH AD14/D6/P1.6 V/0-O0-1/0 and AFH. AD15/D7/P1.7 V/0-O0-1/0 P2.0 0 P2.1 0 P2.2 VO P2 in all modes. Cee WO P2.6 is INT# when MUX = 1 and is open-drain. P25 0 P2.7 is WRH# in 16-bit multiplexed mode. P2.6/INT# 0-0 P2.7/WRH# V/O-| These pins select one of the four parallel interfaces. These pins are weakly held low during reset. Mode1 ModeO Modeo | 0 0 8-bit multiplexed Intel Mode1 | 0 0 Serial Interface mode entered when RD# = 0, WR# = 0 upon reset. 0 1 16-bit multiplexed Intel 1 0 8-bit multiplexed non-Intel 1 1 8-bit non-multiplexed ALE used for Intel modes. ALE/AS I-| . . : AS used for non-Intel modes, except Mode 3 this pin must be tied high. RD# | RD#used for Intel modes. E | E used for non-Intel modes, except Mode 3 Asynchronous this pin must be tied high. WR#/WRL# | WRi#in 8-bit Intel mode and WRL# in 16-bit Intel mode. RIW# | R/W# used for non-Intel modes. READY is an output to synchronize accesses from the host READY oO microcontroller to the 82527. READY is an open-drain output to the host MISO oO microcontroller. MISO is the serial data output for the serial interface mode. DSACKO# O DSACKO# is an open-drain output to synchronize accesses from the host microcontroller to the 82527. 4 ADVANCE INFORMATION DatasheetELECTRICAL CHARACTERISTICS 82527 - Express ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Storage Temperature 60C to +150C Voltage from Any Pin to Vss eee rrr -0.5 V to +7.0 V Laboratory testing shows the 82527 will withstand up to 10 mA of injected current into both RXO and RX1 pins fora total of 20 days without sustaining permanent damage. This high current condition may be the result of shorted signal lines. The 82527 will not function properly if the RX0/RX1 input voltage exceeds Vo+0.5 V. DC CHARACTERISTICS Operating Conditions: Vec = 5 Vv +10% Ta =40C to +85C Table 3. OC Characteristics *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. Sym Parameter Min Max CoandHions Vib Input Low Voltage (All except RX0, RX1, ADOAD7 05 o8Vv in Mode 3) Vitd Input Low Voltage for ADOOD7 in Mode 3 0.5 O.5V Vio Input Low Voltage (RX0) for Comparator Bypass O5V Mode Vv Input Low Voltage for Port 1 and Port 2 Pins Not 03V IL3 Used for Interface to Host CPU nee Vin Input High Voltage (All except RXO, RX1, RESET#) 3.0V Veco +0.5 V Input High Voltage (RESET#) Hysteresis on 3.0V Viet | RESET# 200 mv _| Yeo +08 V Vino Input High Voltage (RX0O) for Comparator Bypass 40V Mode Vv Input High Voltage for Port 1 and Port 2 Pins Not O7V IHS Used for Interface to Host CPU free VoL Output Low Voltage (All Outputs except TXO, TX1) 0.45 V lol =1.6 mA Output High Voltage (All Outputs except TXO, TX1, _ __ Vou CLOCKOUT) Vec 0.8 V lou = -200 pA Vouri | Output High Voltage (CLOCKOUT) 0.8V loy = 80 HA lk Input Leakage Current +10 PA Vss < Vin < Veco Cn PIN Capacitance** 10 pF Fytat = 1 KHz lec Supply Current 50 mA Fytap = 16 KHz!) Sleep Current Isteep | with Voc/2 Output Enabled, No Load 700 pA | with Voc/2 Output Disabled 100 pA Ipp Powerdown Current 25 pA XTAL1 Clocked'") NOTES: **Typical value based on characterization data. Port pins are weakly held after reset until the port configuration registers are written (9FH, AFH). 1. All pins are driven to Vgg or Veg including RXO and RX1. ADVANCE INFORMATION Datasheeta 82527 - Express I ntel et PHYSICAL LAYER SPECIFICATIONS Operating Conditions: * Load = 100 pF * Voc =5 V 10% Ty =40C to +85C Table 4. DC Characteristics RAO/RMA and TXO/TH1 Min Max Conditions Input Voltage -0.5V Veco +0.5V Common Mode Range Vgg +1V Vec-1V Differential Input Threshold +100 mV Internal Delay 1: Sum of the Comparator Load on TX0, TX1 = 100 pF, Input Delay and the TX0/TX1 Output Driver 60 ns +100 mV to -100 mV RX0/RX1 Delay differential Internal Delay 2: Sum of the RXO Pin Delay (if the Comparator is Bypassed) and the 50 ns Load on TXO, TX1 = 100 pF TXO/TX1 Output Driver Delay Source Current on Each TXO, TX1 -10 mA Vout = Vee -1V Sink Current on Each TXO, TX1 10mA VouTtT=1V Input Hysteresis for RXO/RX12 OV Veel2 Voc/2 | 2.38 V | 2.62V | Igy S75 WA, Vo = BV Bad CLOCKOUT SPECIFICATIONS Operating Conditions: * Load =50 pF Table 8. Hockout SpecHications Parameter Min Max CLOCKOUT Frequency XTAL/15 XTAL 6 ADVANCE INFORMATION Datasheet3.4 AC CHARACTERISTICS 3.4.1 6/16-Bit Mullipiexed intel Modes (Modes 0, 7) Operating Conditions: Veco =5V 410% Vgg =O0V 82527 - Express Ta = 40C to +85C * G = 100 pF Table 6. AC Characteristics /16-Bi Multiplexed intel Modes (Modes 0, 1} (Sheet 1 of 23 Symbol Parameter Alin Max Conditions 1/TytaL | Oscillator Frequency 8 MHZ 16 MHz 1/Tge_ | System Clock Frequency 4 MHZ 10 MHZ 1/TyiciK | Memory Clock Frequency 2 MHZ 8 MHZ TAVLL Address Valid to ALE Low 7.5ns TLLAX Address Hold after ALE Low 10 ns Tru, | ALE High Time 30 ns TLLRL ALE Low to RD# Low 20 ns TeLLL CS# Low to ALE Low 10 ns TovwuH _ | Data Setup to WR# High 27 ns TwHaox | Input Data Hold after WR# High 10 ns TwiwH | WR# Pulse Width 30 ns TWHLH WR# High to Next ALE High 8ns TwueH | WR# High to CS# High Ons RD# Pulse Width 40 ns This time is long enough to initiate a double TreRH read cycle by loading the High Speed Registers (04H, 05H), but is too short to READ from 04H and 05H (See t RLDV ) T RD# Low to Data Valid (Only for Registers Ons 55 ns RLDV 02H, 04H, 05H) RD# Low Data to Data Valid (for Registers 1.5 Tyc_ik + 100 ns T except 02H, 04H, 05H) 35T +100 ns RLDV1 | for Read Cycle without a Previous Write (1) ~~ 'MCLK for Read Cycle with a Previous Write (1) TRHDz Data Float after RD# High Ons 45 ns CS# Low to READY Setup Condition: 32 ns Vo_=1 V TeLyy or Capacitance on the READY Output: 50 40 ns Vo =0.45 V T, WR# Low to READY Float for a Write Cycle if 145 ns WLYZ No Previous Write is Pending (2) T, End of Last Write to READY Float for a Write 2 Twiclk + 100 ns WHYZ Cycle if a Previous Write Cycle is Active (2) NOTES: References to WR# also pertain to WRH#. 1. Definition of read cycle without a previous write: The time between the rising edge of WR#/WRH# (for the previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 Tycik. 2. Definition of write cycle with a previous write. The time between the rising edge of WR#/WRH# (for the previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 Tyc1K. 3. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. ADVANCE INFORMATION Datasheet82527 - Express intel. Table 6. AC Characteristics /16-Bit Muliiplexed Intel Modes (Modes 0, 1) (Sheet 2 of 2) Symbal Parameter Rin Max Combitions Triyz RD# Low to READY Float (for registers except 02H, 04H, 05H) for Read Cycle without a Previous Write (1) for Read Cycle with a Previous Write (1) 2 TmcLk +100 ns 4 TmcLk +100 ns TwHDVv WR# High ti Output Data Valid on Port 1/2 TMCLK 2 TMCLK +100 ns Tcopro CLKOUT Period (CDy+1) * Toge (3) TCHCL CLKOUT High Period (CDy+1) * YToge -10 | (CDy+1) * Tage -15 NOTES: References to WR# also pertain to WRH#. 1. Definition of read cycle without a previous write: The time between the rising edge of WR#/WRHi (for the previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 Tyo, . 2. Definition of write cycle with a previous write. The time between the rising edge of WR#AVRH# (for the previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 Tyo) x. 3. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. Figure 3. 82527 - Express System Timings (Modes 0, 1} PORT 1/2 | < the ALE \ j tax >| tavit k BUS + Address Data Out i tRLDV >| tRHDz be RD# \_ / tLLRL tRLRH teu > ___ CS# twowH twHtH | WR# L_ | >| town ke > twHax >| l< twHpv A4580-01 ADVANCE INFORMATION Datasheetintel : 82527 - Express Figure 4. Ready Output Timing for a Write Cycle if No Previous Write is Pending (Modes 0, 1} CS# \ WR# R \ eady ; lV, >| twLyz Figure . Ready Output Timing for Write Cycle if Previous Write Cycle is Active (Modes 0, 7) cw \ r << twyyz ____> Figure 6. Ready Output Timing for Read Cycle (Modes 6, 1) tclyv> CS# ALE J \ [ RD# \ / Ready ' }<_. tri yz ADVANCE INFORMATION Datasheet 982527 - Express a -Bit Mullipiexed Non-intel Mode (Mode 2) Operating Conditions:: * Veco =5V 410% * Vgg=0V * Ty =40C to +85C + G =100 pF Table 7. AC Characteristics 6-BR Multiplexed Non-intel Mode (Mode 2} Symbai Parameter Min Max 1/TytaL | Oscillator Frequency 8 MHZ 16 MHz 1/Tge_k | System Clock Frequency 4 MHZ 10 MHZ 1/Tyicik | Memory Clock Frequency 2 MHZ 8 MHZ TaVLL Address Valid to AS Low 7.5 ns TsLax Address Hold after AS Low 10 ns TeLpz Data Float after E Low Ons 45 ns E High to Data Valid for Registers 02H, 04H, 05H Ons 45 ns TEHDy for Read Cycle without a Previous Write (1) 1.5 TyciK + 100 ns for Read Cycle with a Previous Write (for Registers except for 3.5 Tuck + 100 ns 02H, 04H, 05H) TaveL Data Setup to E Low 30 ns TELax Input Data Hold after E Low 20 ns TeLpv E Low to Output Data Valid on Port 1/2 TmcLk 2 Tuck + 500 ns TEHEL E High Time 45 ns TELEL End of Previous Write (Last E Low) to E Low for a Write Cycle 2 Tuck TsHs- AS High Time 30 ns TRseH Setup Time of R/W# to E High 30 ns Ts LEH AS Low to E High 20 ns TeLsi CS# Low to AS Low 20 ns TELCH E Low to CS# High Ons Teopp _ | CLKOUT Period (CDy+1) * Tose (3) Tone, | CLKOUT High Period (CDy+1) * %Tog 10 | (CDy+t) * Toso + 15 NOTES: 1. Definition of Read Cycle without a Previous Write: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 Tyco, K. 2. Definition of Write Cycle with a Previous Write. The time between the falling edge of E (for the previous write cycle) and the falling edge of E (for the current write cycle) is less than 2 Tyc_k. 3. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. 10 ADVANCE INFORMATION Datasheetintel . 82527 - Express Figure 7. 82527 - Express System Bus Timing (Mode 2) tsHsL. T AS TAVSL Data Out < tsLEH teHDv betELpz R/W# tRSEH>| ~< test >| ke tecr -_ | 2 oh | CS# R/W# Port 1/2 A4588-01 ADVANCE INFORMATION Datasheet 1182527 - Express 3.4.35 Operating Conditions: Veco = 5 V 10% Vsg =OV Table &. AC Characteristics 8-3 Nen-Multiplexed Asynchronous Mode (Made 3) -EBit Non-Muliplexed Asynchronous Mode (Moce 3) * Ty =40C to +85C G = 100 pF Sym Parameler Min Max 1/TxtaL | Oscillator Frequency 8 MHZ 16 MHz 1/Tgo_k | System Clock Frequency 4 MHZ 10 MHZ 1/Twetk | Memory Clock Frequency 2 MHZ 8 MHZ TavLe Address or R/W# Valid to CS# Low Setup 3ns CS# Low to Data Valid for High Speed Registers (02H, 04H, 05H) Ons 55 ns ToLpv For Low Speed Registers (Read Cycle without Previous Write) (1) Ons 1.5 TycLk + 100 ns For Low Speed Registers (Read Cycle with Previous Write) (1) Ons 3.5 TycLk + 100 ns DSACKO# Low to Output Data Valid for High Speed Read 23 ns TkLpy Register For Low Speed Read Register <Ons Toupv 82527 Input Data Hold after CS# High 15 ns TCHDH 82527 Output Data Hold after CS# High Ons Teupz CS# High to Output Data Float 35 ns Touky1 | CS# High to DSACKO# = 2.4V (3) Ons 55 ns TouKHe | CS# High to DSACKO# = 2.8V 150 ns ToHKz CS# High to DSACKO# Float Ons 100 ns ToueL CS# Width between Successive Cycles 25 ns ToHAI CS# High to Address Invalid 7ns TourI CS# High to R/W# Invalid 5Sns ToLcH CS# Width Low 65 ns TpvcH CPU Write Data Valid to CS# High 20 ns Tou. CS# Low to DSACKO# Low for High Speed Registers and Low Ons 67 ns Speed Registers Write Access without Previous Write (2) Tou. End of Previous Write (CS# High) to DSACKO# Low for a Write Ons 2 Tucik + 145 ns Cycle with a Previous Write (2) Tcopp | CLKOUT Period (CDy+1) * Toge (4) TcHo | CLKOUT High Period (CDy+1) * Toge-10 | (CDy+1) * YeTogot 15 NOTES: E and AS must be tied high in this mode. 1. Definition of Read Cycle without a Previous Write: The time between the rising edge of CS# (for the previous write cycle) and the falling edge of CS# (for the current read cycle) is greater than 2 Tycik. 2. Definition of Write Cycle with a Previous Write write cycle) and the rising edge of CS# (for the current write cycle) is less than 2 Tyco) K. . The time between the rising edge of CS# (for the previous 3. An on-chip pullup will drive DSACKO# to approximately 2.4 V. An external pullup is required to drive this signal to a higher voltage. 4. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. 12 ADVANCE INFORMATION Datasheetintel : 82527 - Express Figure 8. Timing of the Asynchronous Mode Read Cycle (Mode 3} Address x x jae} tCHAI RW# y \ tavcL | be be tCHCL: toLcH cs# \ y toupz toLpv _ICHDH, Data A KG - {-_____ tkLDv betoHKz tok. tcHKH DSACKO# \ A4589-01 Figure 9. Timing of the Asynchronous Mode Write Cycle (Mode 3} J Address x x be} ECHL yy, R/W# N t 1 AVCL >] teron CHCL>| CS# \ y \ toveu>| Daa _ }_ toLKL >| toHKH DSACKo# TN NW A4590-01 ADVANCE INFORMATION Datasheet 1382527 - Express In 3.44 &-Bit Non-Multiplexed Synchronous Mode (Mode 3) Operating Conditions: * Voo =5V +10% * Vgg =0V * Ty =40C to +85C * G =100pF Table 9. AC Characteristics 8-31 Nen-Muliplexed Synchronous Mode (Mode 3) Sym Parameler Min Max 1/TxtaL | Oscillator Frequency 8 MHZ 16 MHz 1/Tgo_k | System Clock Frequency 4 MHZ 10 MHZ 1/Twetk | Memory Clock Frequency 2 MHZ 8 MHZ E High to Data Valid out of High Speed Register (02H, 04H, 05H) 55 ns TEHDV Read Cycle without Previous Write for Low Speed Registers) 1.5 TyeLk + 100 ns Read Cycle with Previous Write for Low Speed Registers) 3.5 TucLk + 100 ns TELDH Data Hold after E Low for a Read Cycle 5ns TeLpz Data Float after E Low 35 ns TELbv Data Hold after E Low for a Write Cycle 15 ns TaVveH Address and R/W# to E Setup 25 ns TELAV Address and R/W# Valid after E Falls 15 ns TovEH CS# Valid to E High Ons TeLcv CS# Valid after E Low Ons TpveL Data Setup to E Low 55 ns TEHEL E Active Width 100 ns Tavay Start of a Write Cycle after a Previous Write Access 2 Tucik TaVcL Address or R/W# to CS# Low Setup 3ns Tonal CS# High to Address Invalid 7ns Tcopp | CLKOUT Period (CDy+1) * Toge (2) TcHo | CLKOUT High Period (CDy+1) * Toge-10 | (CDy+1) * YeTogot 15 NOTES: 1. Definition of Read Cycle without a Previous Write: The time between the falling edge of E (for the previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 Tyo) x. 2. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. 14 ADVANCE INFORMATION Datasheetintel . 82527 - Express Figure 10. Timing of the Synchronous Read Cycle (Mode 3) TAVAV J | Address x X teLav R/W# \ V TAVEH teELcv taveL >| he tCHAl tovEH CS# tEHEL >} Da tpvEL > tELDV Data A4592-01 Figure 11. Timing of the Synchronous Write Cycle (Made 3) TAVAV Address x X tELAV R/W# \ y TAVEH teELcv taveL >| he tCHAl tovEH CS# tEHEL >} E ________ Ra tpvEL > tELDV Data A4591-01 ADVANCE INFORMATION Datasheet 1582527 - Express In oA Seria! interface Vode Operating Conditions: Vec = 5.0 Vv +10% Ves =0V T, =-40C +85C C= 100 pF Table 10. AC Characteristics for Serial interlace Mode Sym Parameter Min Max 1/Tycik | SPI Clock 0.5 MHZ 8 MHZ TELDH 1/SCLK 125 ns 2000 ns TeLpz Minimum Clock High Time 84 ns TeLpy Minimum Clock Low Time 84 ns TaVveH ENABLE Lead Time 70 ns TELAV Enable Lag Time 109 ns TeveH Access Time 60 ns TeLcv Maximum Data Out Delay Time 59 ns TDVEL Minimum Data Out Hold Time Ons TEHEL Maximum Data Out Disable Time 665 ns Tavav Minimum Data Setup Time 35 ns TaVcL Minimum Data Hold Time 84 ns Tonal Maximum Time for Input to go from Vo, to Voy 100 ns Tonal Maximum Time for Input to go from Vox to VoL 100 ns ToHAI Minimum Time between Consecutive CS# Assertions 670 ns Toopp | CLKOUT Period (CDy+1) * Togo") Toe. | CLKOUT High Period (CDy+1) * Toge-10 | (CDy+1) * Toge+15 NOTE: 1. Definition of CDy is the value loaded in the CLKOUT register representing the CLKOUT divisor. 16 ADVANCE INFORMATION Datasheetintel . 82527 - Express Figure 12. Serial interface Mode (Priority 6, Phase tes ea] tL EAD tLac CS# \ tskHI tsko >| be tRise eye < SCLK V N \ tacc > < >| tho ol te00 f= tois Miso _{ X x +> S., NOTE: Polarity = 0, Phase =0 A4593-01 Figure 13. Serial interlace Mode (Priority = 1, Phase = 1) tes ~< tLEAD >} tLac CS# \ y \ 'SKLO] text tRISE teye | = hm teal SCLK . V N / t acc <> >| [<= tho t< tPDo je so { X XX ~} tgETUP Le tHoLD MOS! - ---- NOTE: Polarity = 1, Phase =1 A4594-01 ADVANCE INFORMATION Datasheet 17a 82527 - Express I ntel 3.4.6 AC Testing Input Figure 1. Inpul, Ouipul Wavetorms Veo 0.5 Voo 0.8V otV ) ( 0.45V ) ( NOTE: AC inputs during testing are driven at Voc - 0.5V for a Logic "1" and 0.1V for a Logic "0". Timing measurements are made at Vou Min for a Logic "1" and VoL Max for a Logic "0". A4598-01 4.0 DATASHEET REVISION HISTORY This is the -001 revision of the 82527 - Express datasheet. 18 ADVANCE INFORMATION Datasheet