54ACT573
Octal Latch with TRI-STATE®Outputs
General Description
The ’ACT573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output Enable
(OE) inputs.
The ’ACT573 is functionally identical to the ’ACT373 but has
inputs and outputs on opposite sides.
Features
nI
CC
and I
OZ
reduced by 50%
nInputs and outputs on opposite sides of package
allowing easy interface with microprocessors
nUseful as input or output port for microprocessors
nFunctionally identical to ’ACT373
nTRI-STATE outputs for bus interfacing
nOutputs source/sink 24 mA
n’ACT573 has TTL-compatible inputs
nStandard Military Drawing (SMD)
— ’ACT573: 5962-87664
Logic Symbols
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE TRI-STATE Output Enable Input
O
0
–O
7
TRI-STATE Latch Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT®is a registered trademark of Fairchild Semiconductor Corporation.
DS100332-1
IEEE/IEC
DS100332-2
August 1998
54ACT573 Octal Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100332 www.national.com
Connection Diagrams
Pin Assignment for DIP
and Flatpak
DS100332-3
Pin Assignment for LCC
DS100332-4
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Functional Description
The ’ACT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are enabled. When OE
is HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs Outputs
OE LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
H
=
HIGH Voltage
L=LOW Voltage
Z=High Impedance
X=Immaterial
O0=Previous O0before HIGH-to-LOW transition of Latch Enable
Logic Diagram
DS100332-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)±50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
)
54ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT®circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
54ACT
Symbol Parameter V
CC
T
A
=Units Conditions
(V) −55˚C to +125˚C
Guaranteed
Limits
V
IH
Minimum High
Level Input
Voltage
4.5 2.0 VV
OUT
=0.1V
5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low
Level Input
Voltage
4.5 0.8 V V
OUT
=0.1V
5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High
Level Output
Voltage
4.5 4.4 V I
OUT
=−50 µA
5.5 5.4 (Note 2)
V
IN
=V
IL
or V
IH
4.5 3.70 V I
OH
−24 mA
5.5 4.70 −24 mA
V
OL
Maximum Low
Level Output
Voltage
4.5 0.1 V I
OUT
=50 µA
5.5 0.1 (Note 2)
V
IN
=V
IL
or V
IH
4.5 0.50 V I
OL
24 mA
5.5 0.50 24 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
OZ
Maximum TRI-STATE 5.5 ±5.0 µA V
I
=V
IL
,V
IH
Leakage Current V
O
=V
CC
, GND
I
CCT
Maximum 5.5 1.6 mA V
I
=V
CC
− 2.1V
I
CC
/Input
I
OLD
(Note 3) Minimum
Dynamic Output
Current
5.5 50 mA V
OLD
=1.65V Max
I
OHD
5.5 −50 mA V
OHD
=3.85V Min
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DC Characteristics for ’ACT Family Devices (Continued)
54ACT
Symbol Parameter V
CC
T
A
=Units Conditions
(V) −55˚C to +125˚C
Guaranteed
Limits
I
CC
Maximum Quiescent
Supply Current 5.5 80.0 µA V
IN
=V
CC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: ICC for 54ACT @25˚C is identical to 74ACT @25˚C.
AC Electrical Characteristics
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 5) C
L
=50 pF
Min Max
t
PLH
Propagation Delay 5.0 1.5 13.5 ns
D
m
to O
n
t
PHL
Propagation Delay 5.0 1.5 13.5 ns
D
n
to O
n
t
PLH
Propagation Delay 5.0 1.5 13.0 ns
LE to O
n
t
PHL
Propagation Delay 5.0 1.5 12.0 ns
LE to O
n
t
PZH
Output Enable Time 5.0 1.5 11.5 ns
t
PZL
Output Enable Time 5.0 1.5 11.0 ns
t
PHZ
Output Disable Time 5.0 1.5 13.5 ns
t
PLZ
Output Disable Time 5.0 1.5 10.5 ns
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements
54ACT
V
CC
T
A
=−55˚C Fig.
Symbol Parameter (V) to +125˚C Units No.
(Note 6) C
L
=50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW 5.0 4.5 ns
D
n
to LE
t
h
Hold Time, HIGH or LOW 5.0 1.0 ns
D
n
to LE
t
w
LE Pulse Width, HIGH 5.0 5.0 ns
Note 6: Voltage Range 5.0 is 5.0V ±0.5V
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Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 5.0 pF V
CC
=OPEN
C
PD
Power Dissipation 25.0 pF V
CC
=5.0V
Capacitance
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7
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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1. Life support devices or systems are devices or sys-
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the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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54ACT573 Octal Latch with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
