5P49V5913A001NLGI8 - IDT, Integrated Device Technology Inc

DATASHEET

Programmable Clock Generator 5P49V5913

Description

The 5P49V5913 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I2C

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock®5).

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

The device may be configured to use one of two I2C

addresses to allow multiple devices to be used in a system.

Pin Assignment

Features

•Generates up to two independent output frequencies

•High performance, low phase noise PLL, < 0.7ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1GbE and 10GbE

•Two fractional output dividers (FODs)

•Independent Spread Spectrum capability on each output

pair

•Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

•I2C serial programming interface

•One reference LVCMOS output clock

•Two universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

•I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os: LVPECL, LVDS and HCSL

•Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

•Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

•Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

•Redundant clock inputs with manual switchover

•Programmable loop bandwidth

•Programmable slew rate control

•Programmable crystal load capacitance

•Individual output enable/disable

•Power-down mode

•1.8V, 2.5V or 3.3V core VDDD, VDDA

•4 × 4 mm 24-VFQFPN package

•-40° to +85°C industrial temperature operation

24-pin VFQFPN

XOUT

XIN/REF

CLKIN

OUT2

CLKINB

CLKSEL

OUT2B

VDDO2

VDDA

SD/OE

SEL1/SDA

SEL0/SCL

VDDA

OUT1B

OUT1

VDDO1

VDDD

VDDO0

OUT0_SEL_I2CB

EPAD

GND

8910 11 12

2021222324

VDDA

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Functional Block Diagram

Applications

•Ethernet switch/router

•PCI Express 1.0/2.0/3.0

•Broadcast video/audio timing

•Multi-function printer

•Processor and FPGA clocking

•Any-frequency clock conversion

•MSAN/DSLAM/PON

•Fiber Channel, SAN

•Telecom line cards

•1 GbE and 10 GbE

XIN/REF

XOUT

CLKIN

CLKINB

CLKSEL

SD/OE

SEL1/SDA

SEL0/SCL

VDDA

VDDD

VDDO0

OUT0_SEL_I2CB

VDDO1

OUT1

OUT1B

VDDO2

OUT2

OUT2B

FOD1

FOD2

PLL

OTP

and

Control Logic

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Table 1:Pin Descriptions

Number Name Type Description

1 CLKIN Input Internal

Pull-down Differential clock input. Weak 100kohms internal pull-down.

2 CLKINB Input Internal

Pull-down Complementary differential clock input. Weak 100kohms internal pull-down.

3 XOUT Input Crystal Oscillator interface output.

4 XIN/REF Input

Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that

the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF

Interface”.

DDA Power Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD should

have the same voltage applied.

6 CLKSEL Input Internal

Pull-down

Input clock select. Selects the active input reference source in manual switchover

mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as shown in Table 4.

7 SD/OE Input Internal

Pull-down

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE

pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be

either active HIGH or LOW only when pin is configured as OE (Default is active

LOW.) Weak internal pull down resistor. When configured as SD, device is shut

down, differential outputs are driven high/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs are disabled, the

outputs can be selected to be tri-stated or driven high/low, depending on the

programming bits as shown in the SD/OE Pin Function Truth table.

8 SEL1/SDA Input Internal

Pull-down

Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak

internal pull down resistor.

9 SEL0/SCL Input Internal

Pull-down

Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak

internal pull down resistor.

10 VDDA Power Analog functions power supply pin.Connect to 1.8V to 3.3V. VDDA and VDDD should

have the same voltage applied.

11 NC – – No connect.

12 NC – – No connect.

13 NC – – No connect.

14 NC – – No connect.

15 VDDA Power Analog functions power supply pin.Connect to 1.8V to 3.3V. VDDA and VDDD should

have the same voltage applied.

16 OUT2B Output Complementary Output Clock 2. Please refer to the Output Drivers section for more

details.

17 OUT2 Output Output Clock 2. Please refer to the Output Drivers section for more details.

18 VDDO2Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT2/OUT2B.

19 OUT1B Output Complementary Output Clock 1. Please refer to the Output Drivers section for more

details.

20 OUT1 Output Output Clock 1. Please refer to the Output Drivers section for more details.

21 VDDO1Power Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT1/OUT1B.

22 VDDD Power Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDD should

have the same voltage applied.

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23 VDDO0Power Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage

levels for OUT0.

24 OUT0_SEL_I2CB Input/

Output

Internal

Pull-down

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9.

If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be

configured as hardware select pins, SEL1 and SEL0. If a weak pull down (10Kohms)

is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA

and SCL pins of an I2C interface. After power up, the pin acts as a LVCMOS

reference output.

EPAD GND GND Connect to ground pad.

Number Name Type Description

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PLL Features and Descriptions

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5913 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5913 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300ns

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as

shown in Table 4.

PRIMSRC is bit 1 of Register 0x13.

Input Reference

Frequency–Fref

(MHz)

Loop

Bandwidth

Min (kHz)

Loop

Bandwidth

Max (kHz)

540126

350 300 1000

OUT0_SEL_I2CB

@ POR SEL1 SEL0 I2C

Access REG0:7 Config

100No00

101No01

110No02

111No03

0 X X Yes 1 I2C

defaults

0XXYes00

PRIMSRC CLKSEL Source

0 0 XIN/REF

0 1 CLKIN, CLKINB

1 0 CLKIN, CLKINB

1 1 XIN/REF

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5P49V5913 DATASHEET

Reference Clock Input Pins and

Selection

The 5P49V5913 supports up to two clock inputs. One input

supports a crystal between XIN and XOUT. XIN can also be

driven from a single ended reference clock. XIN can accept

small amplitude signals like from TCXO or one channel of a

differential clock.

The second clock input (CLKIN, CLKINB) is a fully differential

input that only accepts a reference clock. The differential input

accepts differential clocks from all the differential logic types

and can also be driven from a single ended clock on one of the

input pins.

The CLKSEL pin selects the input clock between either

XTAL/REF or (CLKIN, CLKINB).

Either clock input can be set as the primary clock. The primary

clock designation is to establish which is the main reference

clock to the PLL. The non-primary clock is designated as the

secondary clock in case the primary clock goes absent and a

backup is needed. See the previous page for more details

about primary versus secondary clock operation.

The two external reference clocks can be manually selected

using the CLKSEL pin. The SM bits must be set to “0x” for

manual switchover which is detailed in Manual Switchover

Mode section.

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

A crystal manufacturer will calibrate its crystals to the nominal

frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load

capacitance, the oscillation frequency will be accurate. When

the oscillator load capacitance is lower than the crystal load

capacitance, the oscillation frequency will be higher than

nominal and vice versa so for an accurate oscillation

frequency you need to make sure to match the oscillator load

capacitance with the crystal load capacitance.

To set the oscillator load capacitance there are two tuning

capacitors in the IC, one at XIN and one at XOUT. They can

be adjusted independently but commonly the same value is

used for both capacitors. The value of each capacitor is

composed of a fixed capacitance amount plus a variable

capacitance amount set with the XTAL[5:0] register.

Adjustment of the crystal tuning capacitors allows for

maximum flexibility to accommodate crystals from various

manufacturers. The range of tuning capacitor values available

are in accordance with the following table.

XTAL[5:0] Tuning Capacitor Characteristics

The capacitance at each crystal pin inside the chip starts at

9pF with setting 000000b and can be increased up to 25pF

with setting 111111b. The step per bit is 0.5pF.

You can write the following equation for this capacitance:

Ci = 9pF + 0.5pF × XTAL[5:0]

The PCB where the IC and the crystal will be assembled adds

some stray capacitance to each crystal pin and more

capacitance can be added to each crystal pin with additional

external capacitors.

You can write the following equations for the total capacitance

at each crystal pin:

CXIN = Ci1 + Cs1 + Ce1

CXOUT = Ci2 + Cs2 + Ce2

Ci1 and Ci2 are the internal, tunable capacitors. Cs1 and Cs2

are stray capacitances at each crystal pin and typical values

are between 1pF and 3pF.

Ce1 and Ce2 are additional external capacitors that can be

added to increase the crystal load capacitance beyond the

tuning range of the internal capacitors. However, increasing

the load capacitance reduces the oscillator gain so please

consult the factory when adding Ce1 and/or Ce2 to avoid

crystal startup issues. Ce1 and Ce2 can also be used to adjust

for unpredictable stray capacitance in the PCB.

The final load capacitance of the crystal:

CL = CXIN × CXOUT / (CXIN + CXOUT)

For most cases it is recommended to set the value for

capacitors the same at each crystal pin:

CXIN = CXOUT = Cx → CL = Cx / 2

The complete formula when the capacitance at both crystal

pins is the same:

CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2

Parameter Bits Step (pF) Min (pF) Max (pF)

XTAL 6 0.5 9 25



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Example 1: The crystal load capacitance is specified as 8pF

and the stray capacitance at each crystal pin is Cs=1.5pF.

Assuming equal capacitance value at XIN and XOUT, the

equation is as follows:

8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →

0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)

Example 2: The crystal load capacitance is specified as 12pF

and the stray capacitance Cs is unknown. Footprints for

external capacitors Ce are added and a worst case Cs of 5pF

is used. For now we use Cs + Ce = 5pF and the right value for

Ce can be determined later to make 5pF together with Cs.

12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →

XTAL[5:0] = 20 (decimal)

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to switch

between the primary and secondary clock sources. The

primary and secondary clock source setting is determined by

the PRIMSRC bit. During the switchover, no glitches will occur

at the output of the device, although there may be frequency

and phase drift, depending on the exact phase and frequency

relationship between the primary and secondary clocks.

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OTP Interface

The 5P49V5913 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

To initiate a save or restore using I2C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5913 will

not generate Acknowledge bits. The 5P49V5913 will

acknowledge the instructions after it has completed execution

of them. During that time, the I2C bus should be interpreted as

busy by all other users of the bus.

On power-up of the 5P49V5913, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5913 will be ready to

accept a programming instruction once it acknowledges its

7-bit I2C address.

Availability of Primary and Secondary I2C addresses to allow

programming for multiple devices in a system. The I2C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

Programming Guide provides detailed I2C programming

guidelines and register map.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

Table 5: SD/OE Pin Function Truth Table

Output Alignment

Each output divider block has a synchronizing POR pulse to

provide startup alignment between outputs. This allows

alignment of outputs for low skew performance. The phase

alignment works both for integer output divider values and for

fractional output divider values.

Besides the POR at power up, the same synchronization reset

is also triggered when switching between configurations with

the SEL0/1 pins. This ensures that the outputs remain aligned

in every configuration. This reset causes the outputs to

suspend for a few hundred microseconds so the switchover is

not glitch-less. The reset can be disabled for applications

where glitch-less switch over is required and alignment is not

critical.

When using I2C to reprogram an output divider during

operation, alignment can be lost. Alignment can be restored

by manually triggering the reset through I2C.

When alignment is required for outputs with different

frequencies, the outputs are actually aligned on the falling

edges of each output by default. Rising edge alignment can

also be achieved by utilizing the programmable skew feature

to delay the faster clock by 180 degrees. The programmable

skew feature also allows for fine tuning of the alignment.

For details of register programming, please see VersaClock 5

Family Register Descriptions and Programming Guide for

details.

SD/OE Input

OEn OSn

Global Shutdown

OUTn

SH bit SP bi t OSn bi t OEn bi t S D/OE OUTn

0 0 0 x x Tri-state2

0 0 1 0 x Output active

0 0 1 1 0 Output active

0 0 1 1 1 Output driven High Low

0 1 0 x x Tri-state2

0 1 1 0 x Output active

0 1 1 1 0 Output driven High Low

0 1 1 1 1 Output active

1 0 0 x 0 Tri-state2

1 0 1 0 0 Output active

1 0 1 1 0 Output active

1 1 0 x 0 Tri-state2

1 1 1 0 0 Output active

1 1 1 1 0 Output driven High Low

1x x x 1

Output driven High Low

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

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Output Divides

Each of the four output divides are comprised of a 12-bit

integer counter, and a 24-bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate any

frequency with a synthesis accuracy better than 50ppb.

The Output Divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

Output Skew

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100 MHz output

and a 2800 MHz VCO, you can select how many 11.161pS

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

dependent on the VCO period and the output period.

Output Drivers

The OUT1 and OUT2 clock outputs are provided with

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

The operating voltage ranges of each output is determined by

its independent output power pin (VDDO) and thus each can

have different output voltage levels. Output voltage levels of

2.5V or 3.3V are supported for differential HCSL, LVPECL

operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS

and differential LVDS operation.

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

LVCMOS Operation

When a given output is configured to provide LVCMOS levels,

then both the OUTx and OUTxB outputs will toggle at the

selected output frequency. All the previously described

configuration and control apply equally to both outputs.

Frequency, phase alignment, voltage levels and enable /

disable status apply to both the OUTx and OUTxB pins. The

OUTx and OUTxB outputs can be selected to be

phase-aligned with each other or inverted relative to one

another by register programming bits. Selection of

phase-alignment may have negative effects on the phase

noise performance of any part of the device due to increased

simultaneous switching noise within the device.

Device Hardware Configuration

The 5P49V5913 supports an internal One-Time

Programmable (OTP) memory that can be pre-programmed

at the factory with up to 4 complete device configuration.

These configurations can be over-written using the serial

interface once reset is complete. Any configuration written via

the programming interface needs to be re-written after any

power cycle or reset. Please contact IDT if a specific

factory-programmed configuration is desired.

Device Start-up & Reset Behavior

The 5P49V5913 has an internal power-up reset (POR) circuit.

The POR circuit will remain active for a maximum of 10ms

after device power-up.

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The device will load internal registers according to Ta ble 3.

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

Power Up Ramp Sequence

VDDA and VDDD must ramp up together. VDDO0~2 must

ramp up before, or concurrently with, VDDA and VDDD. All

power supply pins must be connected to a power rail even if

the output is unused. All power supplies must ramp in a linear

fashion and ramp monotonically.

VDDO0~2

VDDA

VDDD

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I2C Mode Operation

The device acts as a slave device on the I2C bus using one of

the two I2C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

For full electrical I2C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

I2C Slave Read and Write Cycle Sequencing

CurrentRead

SDevAddr+R A Data0 A Data1 A A DatanAbar P

SequentialRead

SDevAddr+W A Data0 A Data1 A A DatanAbar P

RegstartAddr ASr DevAddr+R A

SequentialWrite

SDevAddr+W A Data0 PA Data1 A A Datan A

frommastertoslave

fromslavetomaster

RegstartAddr A

S=start

Sr=repeatedstart

A=acknowledge

Abar=noneacknowledge

P=stop

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Table 6:I2C Bus DC Characteristics

Table 7:I2C Bus AC Characteristics

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

Note 2: I2C inputs are 5V tolerant.

Symbol Parameter Conditions Min Typ Max Unit

VIH Input HIGH Level For SEL1/SDA pin and

SEL0/SCL pin.

0.7xVDDD 5.5 2V

VIL Input LOW Level For SEL1/SDA pin and

SEL0/SCL pin.

GND-0.3 0.3xVDDD V

VHYS Hysteresis of Inputs 0.05xVDDD V

IIN Input Leakage Current -1 30 µA

VOL Output LOW Voltage IOL = 3 mA 0.4 V

Symbol Parameter Min Typ Max Unit

FSCLK Serial Clock Frequency (SCL) 10 400 kHz

tBUF Bus free time between STOP and START 1.3 µs

tSU:START Setup Time, START 0.6 µs

tHD:START Hold Time, START 0.6 µs

tSU:DATA Setup Time, data input (SDA) 0.1 µs

tHD:DATA Hold Time, data input (SDA) 10µs

tOVD Output data valid from clock 0.9 µs

CBCapacitive Load for Each Bus Line 400 pF

tRRise Time, data and clock (SDA, SCL) 20 + 0.1xCB300 ns

tFFall Time, data and clock (SDA, SCL) 20 + 0.1xCB300 ns

tHIGH HIGH Time, clock (SCL) 0.6 µs

tLOW LOW Time, clock (SCL) 1.3 µs

tSU:STOP Setup Time, STOP 0.6 µs

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Table 8:Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P49V5913. These ratings, which are standard values for IDT

commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect

product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Table 9:Recommended Operation Conditions

Note: VDDO1 and VDDO2 must be powered on either before or simultaneously with VDDD, VDDA and VDDO0.

Item Rating

Supply Voltage, VDDA, VDDD, VDDO 3.465V

Inputs

XIN/REF

CLKIN, CLKINB

Other inputs

0V to 1.2V voltage swing

0V to 1.2V voltage swing single-ended

-0.5V to VDDD

Outputs, VDDO (LVCMOS) -0.5V to VDDO+ 0.5V

Outputs, IO (SDA) 10mA

Package Thermal Impedance, JA 42C/W (0 mps)

Package Thermal Impedance, JC 41.8C/W (0 mps)

Storage Temperature, TSTG -65C to 150C

ESD Human Body Model 2000V

Junction Temperature 125°C

Symbol Parameter Min Typ Max Unit

VDDOX Power supply voltage for supporting 1.8V outputs 1.71 1.8 1.89 V

VDDOX Power supply voltage for supporting 2.5V outputs 2.375 2.5 2.625 V

VDDOX Power supply voltage for supporting 3.3V outputs 3.135 3.3 3.465 V

VDDD Power supply voltage for core logic functions 1.71 3.465 V

VDDA Analog power supply voltage. Use filtered analog power

supply.

1.71 3.465 V

TAOperating temperature, ambient -40 +85 °C

CLOAD_OUT Maximum load capacitance (3.3V LVCMOS only) 15 pF

FIN External reference crystal 140MHz

External reference clock CLKIN, CLKINB 5350

tPU Power up time for all VDDs to reach minimum specified

voltage (power ramps must be monotonic)

0.05 5 ms

SEPTEMBER 12, 2018 13 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

Table 10:Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down

Resistance (TA = +25 °C)

Table 11:Crystal Characteristics

Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.

Table 12:DC Electrical Characteristics

Symbol Parameter Min Typ Max Unit

CIN Input Capacitance (CLKIN, CLKINB, CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL)

37pF

Pull-down Resistor CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB,

OUT0_SEL_I2CB

100 300 k

ROUT LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V) 17 

XIN/REF Programmable input capacitance at XIN/REF 08pF

XOUT Programmable input capacitance at XOUT 08pF

Para m eter Te st Condi tions Mi ni m um Typica l Max i m um Units

Mode of Oscillation

Frequency 8 25 40 MHz

Equivalent Series Resistance (ESR) 10 100 Ω

Shunt Capacitance 7pF

Load Capacitance (CL) @ <=25 MHz 6 8 12 pF

Load Capacitance (CL) >25M to 40M 6 8 pF

Maximum Crystal Drive Level 100 µW

Fundamental

Sym bol Para m eter Test Condi tions Mi n Typ Max Unit

Iddcore3Core Supply Current

100 MHz on all outputs, 25 MHz

REFCLK 30 34 mA

LVPECL, 350 MHz, 3.3V VDDOx 42 47 mA

LVPECL, 350 MHz, 2.5V VDDOx 37 42 mA

LVDS, 350 MHz, 3.3V VDDOx 18 21 mA

LVDS, 350 MHz, 2.5V VDDOx 17 20 mA

LVDS, 350 MHz, 1.8V VDDOx 16 19 mA

HCSL, 250 MHz, 3.3V VDDOx, 2 pF load 29 33 mA

HCSL, 250 MHz, 2.5V VDDOx, 2 pF load 28 33 mA

LVCMOS, 50 MHz, 3.3V, VDDOx

1,2

16 18 mA

LVCMOS, 50 MHz, 2.5V, VDDOx

1,2

14 16 mA

LVCMOS, 50 MHz, 1.8V, VDDOx

1,2

12 14 mA

LVCMOS, 200 MHz, 3.3V VDDOx

36 42 mA

LVCMOS, 200 MHz, 2.5V VDDOx

1,2

27 32 mA

LVCMOS, 200 MHz, 1.8V VDDOx

1,2

16 19 mA

Iddpd Power Down Current SD asserted, I2C Programming 10 14 mA

1. Single CMOS driver active.

2. Measured into a 5” 50 Ohm trace with 2 pF load.

3. Iddcore = IddA+ IddD, no loads.

Iddox Output Buffer Supply Current

PROGRAMMABLE CLOCK GENERATOR 14 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

Table 13:Electrical Characteristics – Differential Clock Input Parameters 1,2 (Supply

Voltage VDDA, VDDD, VDDO0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C)

1. Guaranteed by design and characterization, not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

Table 14:DC Electrical Characteristics for 3.3V LVCMOS (VDDO = 3.3V±5%, TA = -40°C to +85°C) 1

1. See “Recommended Operating Conditions” table.

Symbol Parameter Test Conditions Min Typ Max Unit

VIH Input HIGH Voltage–CLKIN, CLKINB Single-ended input 0.55 1.7 V

VIL Input LOW Voltage–CLKIN, CLKINB Single-ended input GND - 0.3 0.4 V

VSWING Input Amplitude - CLKIN, CLKINB Peak to Peak value, single-ended 200 1200 mV

dv/dt Input Slew Rate - CLKIN, CLKINB Measured differentially 0.4 8 V/ns

IIL Input Leakage Low Current VIN = GND -5 5 µA

IIH Input Leakage High Current VIN = 1.7V 20 µA

dTIN Input Duty Cycle Measurement from differential

waveform

45 55 %

Symbol Pa rameter Test Condi tions Mi n Typ Max Unit

VOH Output HIGH Voltage IOH = -15mA 2.4 VDDO V

VOL Output LOW Voltage IOL = 15mA 0.4 V

IOZDD Output Leakage Current (OUT1~2) Tri-state outputs, VDDO = 3.465V 5µA

IOZDD Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V 30 µA

VIH Input HIGH Voltage Single-ended inputs - CLKSEL, SD/OE 0.7xVDDD VDDD + 0.3 V

VIL Input LOW Voltage Single-ended inputs - CLKSEL, SD/OE GND - 0.3 0.3xVDDD V

VIH Input HIGH Voltage Single-ended input OUT0_SEL_I2CB 2 VDDO0 + 0.3 V

VIL Input LOW Voltage Single-ended input OUT0_SEL_I2CB GND - 0.3 0.4 V

VIH Input HIGH Voltage Single-ended input - XIN/REF 0.8 1.2 V

VIL Input LOW Voltage Single-ended input - XIN/REF GND - 0.3 0.4 V

TR/TF Input Rise/Fall Time CLKSEL, SD/OE, SEL1SDA, SEL0/SCL 300 ns

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5P49V5913 DATASHEET

Table 15:DC Electrical Characteristics for 2.5V LVCMOS (VDDO = 2.5V±5%, TA = -40°C to +85°C)

Table 16:DC Electrical Characteristics for 1.8V LVCMOS (VDDO = 1.8V±5%, TA = -40°C to +85°C)

Symbol Pa rameter Test Condi tions Mi n Typ Max Unit

VOH Output HIGH Voltage IOH = -12mA 0.7xVDDO V

VOL Output LOW Voltage IOL = 12mA 0.4 V

IOZDD Output Leakage Current OUT1~2) Tri-state outputs, VDDO = 2.625V 5µA

IOZDD Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V 30 µA

VIH Input HIGH Voltage Single-ended inputs - CLKSEL, SD/OE 0.7xVDDD VDDD + 0.3 V

VIL Input LOW Voltage Single-ended inputs - CLKSEL, SD/OE GND - 0.3 0.3xVDDD V

VIH Input HIGH Voltage Single-ended input OUT0_SEL_I2CB 1.7 VDDO0 + 0.3 V

VIL Input LOW Voltage Single-ended input OUT0_SEL_I2CB GND - 0.3 0.4 V

VIH Input HIGH Voltage Single-ended input - XIN/REF 0.8 1.2 V

VIL Input LOW Voltage Single-ended input - XIN/REF GND - 0.3 0.4 V

TR/TF Input Rise/Fall Time CLKSEL, SD/OE, SEL1SDA, SEL0/SCL 300 ns

Symbol Pa rameter Test Condi tions Mi n Typ Max Unit

VOH Output HIGH Voltage IOH = -8mA 0.7 xVDDO VDDO V

VOL Output LOW Voltage IOL = 8mA 0.25 x VDDO V

IOZDD Output Leakage Current (OUT1~2) Tri-state outputs, VDDO = 3.465V 5µA

IOZDD Output Leakage Current (OUT0) Tri-state outputs, VDDO = 3.465V 30 µA

VIH Input HIGH Voltage Single-ended inputs - CLKSEL, SD/OE 0.7 * VDDD VDDD + 0.3 V

VIL Input LOW Voltage Single-ended inputs - CLKSEL, SD/OE GND - 0.3 0.3* VDDD V

VIH Input HIGH Voltage Single-ended input OUT0_SEL_I2CB

0.65 * VDDO0

VDDO0 + 0.3 V

VIL Input LOW Voltage Single-ended input OUT0_SEL_I2CB GND - 0.3 0.4 V

VIH Input HIGH Voltage Single-ended input - XIN/REF 0.8 1.2 V

VIL Input LOW Voltage Single-ended input - XIN/REF GND - 0.3 0.4 V

TR/TF Input Rise/Fall Time CLKSEL, SD/OE, SEL1SDA, SEL0/SCL 300 ns

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5P49V5913 DATASHEET

Table 17:DC Electrical Characteristics for LVDS(VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

Table 18:DC Electrical Characteristics for LVDS (VDDO = 1.8V+5%, TA = -40°C to +85°C)

Table 19:DC Electrical Characteristics for LVPECL (VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to

+85°C)

Symbol Parameter Min Typ Max Unit

VOT (+) Differential Output Voltage for the TRUE binary state 247 454 mV

VOT (-) Differential Output Voltage for the FALSE binary state -247 -454 mV

VOT Change in VOT between Complimentary Output States 50 mV

VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.25 1.375 V

VOS Change in VOS between Complimentary Output States 50 mV

IOS Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO 924mA

IOSD Differential Outputs Short Circuit Current, VOUT+ = VOUT -612mA

Symbol Parameter Min Typ Max Unit

VOT (+) Differential Output Voltage for the TRUE binary state 247 454 mV

VOT (-) Differential Output Voltage for the FALSE binary state -247 -454 mV

VOT Change in VOT between Complimentary Output States 50 mV

VOS Output Common Mode Voltage (Offset Voltage) 0.8 0.875 0.95 V

VOS Change in VOS between Complimentary Output States 50 mV

IOS Outputs Short Circuit Current, VOUT+ or VOUT - = 0V or VDDO 924mA

IOSD Differential Outputs Short Circuit Current, VOUT+ = VOUT -612mA

Symbol Parameter Min Typ Max Unit

VOH Output Voltage HIGH, terminated through 50 tied to VDD - 2 V VDDO - 1.19 VDDO - 0.69 V

VOL Output Voltage LOW, terminated through 50 tied to VDD - 2 V VDDO - 1.94 VDDO - 1.4 V

VSWING Peak-to-Peak Output Voltage Swing 0.55 0.993 V

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5P49V5913 DATASHEET

Table 20:Electrical Characteristics – DIF 0.7V HCSL Differential Outputs (VDDO = 3.3V±5%,

2.5V±5%, TA = -40°C to +85°C)

Symbol Parameter Conditions Min Typ Max Units Notes

dV/dt Slew Rate Scope averaging on 1 4 V/ns 1,2,3

ΔdV/dt Slew Rate Scope averaging on 20 % 1,2,3

VHIGH Voltage High 660 850 mV 1,6,7

VLOW Voltage Low -150 150 mV 1,6

VMAX Maximum Voltage 1150 mV 1

VMIN Minimum Voltage -300 mV 1

VSWING Voltage Swing Scope averaging off 300 mV 1,2,6

VCROSS Crossing Voltage Value Scope averaging off 250 550 mV 1,4,6

ΔVCROSS Crossing Voltage variation Scope averaging off 140 mV 1,5

Note 7. Measured with scope averaging off, using statis tics function. Variation is difference between min. and max.

Note 4: VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.

Clock rising and Clock# falling).

Note 5: the total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute)

allowed. The intent is to limit VCROSS induced modulation by setting ΔVCROSS to be smaller than VCROSS absolute.

Note 6: Measured from single-ended waveform.

Statistical measurement on single-ended

signal using oscilloscope math function

(Scope averaging ON)

Measurement on single-ended signal using

absolute value (Scope averaging off)

Note 1: Guaranteed by design and characterization. Not 100% tested in production

Note 2: Measured from differential waveform.

Note 3: Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a +/-150mV window around differntial

0V.

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5P49V5913 DATASHEET

Table 21:AC Timing Electrical Characteristics

(VDDO = 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)

(Spread Spectrum Generation = OFF)

Symbol Para m e te r Test Conditions Min. Typ. Max. Units

Input frequency limit (XIN) 840MHz

Input frequency limit (REF) 1200MHz

Input frequency limit (CLKIN, CLKINB) 1350MHz

Single ended clock output limit (LVCMOS) 1200

Differential clock output limit (LVPECL/

LVDS/HCSL) 1350

fVCO VCO Frequency VCO operating frequency range 2600 2900 MHz

fPFD PFD Frequency PFD operating frequency range 1 1150 MHz

fBW Loop Bandwidth Input frequency = 25MHz 0.06 0.9 MHz

t2 Input Duty Cycle Duty Cycle 45 50 55 %

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX= 2.5V or

3.3V

45 50 55 %

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX=1.8V 40 50 60 %

Measured at VDD/2, Reference output

OUT0 (5MHz - 120MHz) with 50% duty

cycle input

40 50 60 %

Measured at VDD/2, Reference output

OUT0 (150.1MHz - 200MHz) with 50% duty

cycle input

30 50 70 %

Slew Rate, SLEW[1:0] = 00 1.0 2.2

Slew Rate, SLEW[1:0] = 01 1.2 2.3

Slew Rate, SLEW[1:0] = 10 1.3 2.4

Slew Rate, SLEW[1:0] = 11 1.7 2.7

Slew Rate, SLEW[1:0] = 00 0.6 1.3

Slew Rate, SLEW[1:0] = 01 0.7 1.4

Slew Rate, SLEW[1:0] = 10 0.6 1.4

Slew Rate, SLEW[1:0] = 11 1.0 1.7

Slew Rate, SLEW[1:0] = 00 0.3 0.7

Slew Rate, SLEW[1:0] = 01 0.4 0.8

Slew Rate, SLEW[1:0] = 10 0.4 0.9

Slew Rate, SLEW[1:0] = 11 0.7 1.2

Rise Times LVDS, 20% to 80% 300

Fall Times LVDS, 80% to 20% 300

Rise Times LVPECL, 20% to 80% 400

Fall Times LVPECL, 80% to 20% 400

fIN 1Input Frequency

t3 5Output Duty Cycle

t4 2

fOUT Output Frequency MHz

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=3.3V

V/ns

Single-ended 2.5V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=2.5V

Single-ended 1.8V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX=1.8V

t5 ps

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5P49V5913 DATASHEET

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

differential outputs (1.8V to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

OUT2=125MHz

46 ps

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

LVCMOS outputs (1.8 to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

OUT2=125MHz

74 ps

RMS Phase Jitter (12kHz to 5MHz

integration range) reference clock (OUT0),

25 MHz LVCMOS outputs (1.8 to 3.3V

nominal output voltage).

OUT0=25MHz

OUT1=100MHz

OUT2=125MHz

0.5 ps

RMS Phase Jitter (12kHz to 20MHz

integration range) differential output, VDDO

= 3.465V, 25MHz crystal, 156.25MHz

output frequency

OUT0=25MHz

OUT1=100MHz

OUT2=125MHz

0.75 1.5 ps

t7 Output Skew

Skew between the same frequencies, with

outputs using the same driver format and

phase delay set to 0 ns.

75 ps

t8 3Startup Time

PLL lock time from power-up, measured

after all VDD's have raised above 90% of

their target value.

10 ms

t9 4Startup Time PLL lock time from shutdown mode 34ms

1. Practical lower frequency is determined by loop filter settings.

2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.

3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.

4. Actual PLL lock time depends on the loop configuration.

t6 Clock Jitter

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5P49V5913 DATASHEET

Table 22:PCI Express Jitter Specifications (VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the

worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band)

and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the

PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Table 23:Jitter Specifications 1,2,3

Symbol Parameter Conditions Min Typ Max PCIe Industry

Specification Units Notes

(PCIe Gen1) Phase Jitter

Peak-to-Peak

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

30 86 ps 1,4

tREFCLK_HF_RMS

(PCIe Gen2) Phase Jitter RMS

ƒ = 100MHz, 25MHz Crystal Input

High Band: 1.5MHz - Nyquist (clock

frequency/2)

2.56 3.10 ps 2,4

tREFCLK_LF_RMS

(PCIe Gen2) Phase Jitter RMS ƒ = 100MHz, 25MHz Crystal Input

Low Band: 10kHz - 1.5MHz

0.27 3.0 ps 2,4

tREFCLK_RMS

(PCIe Gen3) Phase Jitter RMS

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

0.8 1.0 ps 3,4

Para m e te r Symbol Te st Condition Min Typ Max Unit

GbE Random Jitter (12 kHz–20 MHz)4JGbE Crystal in = 25 MHz, All CLKn at 125 MHz5- 0.79 0.95 ps

GbE Random Jitter (1.875–20 MHz) RJGbE Crystal in = 25 MHz, All CLKn at 125 MHz5- 0.32 0.5 ps

OC-12 Random Jitter (12 kHz–5 MHz) JOC12 CLKIN = 19.44 MHz, All CLKn at 155.52 MHz5- 0.69 0.95 ps

PCI Express 1.1 Common Clocked Total Jitter6-9.112ps

RMS Jitter6, 10 kHz to 1.5MHz - 0.1 0.3 ps

RMS Jitter6, 1.5MHz to 50MHz - 0.9 1.1 ps

PCI Express 3.0 Common Clocked RMS Jitter6-0.20.4ps

2 For best jitter performance, keep the single ended clock input slew rates at more than 1.0 V/ns and the differential clock input slew rates more than 0.3 V/ns.

3 All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase

due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact

IDT for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter.

4 DJ for PCI and GbE is < 5 ps pp.

5 Output FOD in Integer mode.

6 All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter. Jitter is measured w ith the Intel Clock Jitter Tool,

Ver. 1.6.6.

(VDDx = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

PCI Express 2.1 Common Clocked

Notes :

1 All measurements w ith Spread Spectrum Off.

SEPTEMBER 12, 2018 21 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

Table 24:Spread Spectrum Generation Specifications

Test Circuits and Loads

Test Circuits and Loads for Outputs

Symbol Parameter Description Min Typ Max Unit

fOUT Output Frequency Output Frequency Range 5300MHz

fMOD Mod Frequency Modulation Frequency 30 to 63 kHz

fSPREAD Spread Value Amount of Spread Value (programmable) - Center Spread ±0.25% to ±2.5% %fOUT

Amount of Spread Value (programmable) - Down Spread -0.5% to -5%

OUTx

VDDA CLKOUT

GND

0.1µF

VDDOx

0.1µF

VDDD

0.1µF

HCSL Output

33 5050

HCSL Differential Output Test Load

2pF 2pF

Zo=100ohm differential

PROGRAMMABLE CLOCK GENERATOR 22 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

Typical Phase Noise at 100MHz (3.3V, 25°C)

NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.

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5P49V5913 DATASHEET

5P49V5913 Applications Schematic

Layout notes.

by 3 x the trace width.

2.Do not share crystal load

components.

capacitor ground via with other

bulk capacitor pad then through

3.Route power from bead through

clock chip Vdd pad.

0.1uF capacitor pad then to

4.Do not share ground vias. One

ground pin one ground via.

1.Separate Xout and Xin traces

Revision history

0.1 9/19/2014 first publication

Manufacture Part Number Z@100MHz PkgSz DC res. Current(Ma)

Fair-Rite 2504021217Y0 120 0402 0.5 200

muRata BLM15AG221SN1 220 0402 0.35 300

muRata BLM15BB121SN1 120 0402 0.35 300

TDK MMZ1005S241A 240 0402 0.18 200

TECSTAR TB4532153121 120 0402 0.3 300

NOTE:FERRITE BEAD FB1 =

PLACE NEAR

I2C CONTROLLER

IF USED

LVDS TERMINATION

3.3V LVPECL TERMINATION

HCSL TERMINATION

CONFIGURATION

PULL-UP FOR

HARDWARE

CONTROL

REMOVE FOR I2C

LVCMOS TERMINATION

FOR LVDS, LVPECL AC COUPLE

USE TERMINATION ON RIGHT

6,7,8,9 and 24

pull-down resistors:

load capacitors

Use internal crystal

have weak internal

The following pins

C3 is for pin 5

SEE DATASHEET FOR BIAS NETWORK

0.1

Integrated Device Technology

Friday, September 19, 2014

5P49V5913A_SCH

San Jose, CA

Size

Document Number

Rev

Date: Sheet of

FG_X1 V1P8VCA

OUT_0_SEL-I2C

V1P8VC

CLKIN V1P8VC

CLKINB OUTR0

CLKSEL V1P8VC

OUTR1

SDA OUTRB1

SCL

V1P8VC

OUTR2

SD OUTRB2

SDA

SCL CLKIN

OUT_0_SEL-I2C

CLKINB

V1P8VCA OUTR2 OUT_2

FG_X2

V1P8VC

V1P8VCA

VCC1P8

V3P3

V1P8VC

RECEIVER

C12 .1uF

1 2

R12 50

1 2

R14 33

1 2

R11 50

1 2

49.9

1 2

.1uF

C11

.1uF

1uF

.1uF

RECEIVER

.1uF

C13 .1uF

1 2

6.8 pF

NO-POP

R13 33

1 2

10uF

R15 33

1 2

FB1

SIGNAL_BEAD

1 2

R10 50

1 2

49.9

1 2

5P49V5913A

XOUT

XIN/REF

CLKIN

CLKINB

CLKSEL

SEL1/SDA

SEL0/SCL

SD/OE

VDDA

VDDD

VDDO0

OUT0_SEL_I2CB

VDDO1

OUT1

OUT1B

VDDO2

OUT2

OUT2B

VDDA

EPAD

10K

1 2

R3 100

1 2

RECEIVER

.1uF

R6 33

1 2

6.8 pF

NO-POP

10K

1 2

2.2

1 2

10K

1 2

GNDGND

CRYSTAL_SMD

25.000MHz

CL=8pF

PROGRAMMABLE CLOCK GENERATOR 24 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

Overdriving the XIN/REF Interface

LVCMOS Driver

The XIN/REF input can be overdriven by an LVCMOS driver

or by one side of a differential driver through an AC coupling

capacitor. The XOUT pin can be left floating. The amplitude of

the input signal should be between 500mV and 1.2V and the

slew rate should not be less than 0.2V/ns. Figure General

Diagram for LVCMOS Driver to XTAL Input Interface shows an

example of the interface diagram for a LVCMOS driver.

This configuration has three properties; the total output

impedance of Ro and Rs matches the 50 ohm transmission

line impedance, the Vrx voltage is generated at the CLKIN

inputs which maintains the LVCMOS driver voltage level

across the transmission line for best S/N and the R1-R2

voltage divider values ensure that the clock level at XIN is less

than the maximum value of 1.2V.

General Diagram for LVCMOS Driver to XTAL Input Interface

Table 25 Nominal Voltage Divider Values vs LVCMOS VDD for

XIN shows resistor values that ensure the maximum drive

level for the XIN/REF port is not exceeded for all combinations

of 5% tolerance on the driver VDD, the VersaClock VDDA and

5% resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the voltage divider attenuation

as long as the minimum drive level is maintained over all

tolerances. To assist this assessment, the total load on the

driver is included in the table.

Table 25: Nominal Voltage Divider Values vs LVCMOS VDD for XIN



XOUT

XI N / REF

0. 1 uF

V_XIN

LV CMOS

VDD

Ro + Rs = 50 ohms

Rs Zo = 50 Ohm

LVCMOS Driver VDD Ro+Rs R1 R 2 V_XIN (peak) Ro+Rs+R1+R2

3.3 50.0 130 75 0.97 255

2.5 50.0 100 100 1.00 250

1.8 50.0 62 130 0.97 242

SEPTEMBER 12, 2018 25 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

LVPECL Driver

Figure General Diagram for LVPECL Driver to XTAL Input

Interface shows an example of the interface diagram for a

+3.3V LVPECL driver. This is a standard LVPECL termination

with one side of the driver feeding the XIN/REF input. It is

recommended that all components in the schematics be

placed in the layout; though some components might not be

used, they can be utilized for debugging purposes. The

datasheet specifications are characterized and guaranteed by

using a quartz crystal as the input. If the driver is 2.5V

LVPECL, the only change necessary is to use the appropriate

value of R3.

General Diagram for +3.3V LVPECL Driver to XTAL Input Interface

CLKIN Equivalent Schematic

Figure CLKIN Equivalent Schematic below shows the basis of

the requirements on VIH max, VIL min and the 1200 mV p-p

single ended Vswing maximum.

•The CLKIN and CLKINB Vih max spec comes from the

cathode voltage on the input ESD diodes D2 and D4, which

are referenced to the internal 1.2V supply. CLKIN or

CLKINB voltages greater than 1.2V + 0.5V =1.7V will be

clamped by these diodes. CLKIN and CLKINB input

voltages less than -0.3V will be clamped by diodes D1 and

D3.

•The 1.2V p-p maximum Vswing input requirement is

determined by the internally regulated 1.2V supply for the

actual clock receiver. This is the basis of the Vswing spec in

Table 13.



+3.3 V LV PE CL Dr iv er

Zo = 50 Ohm

XOUT

XI N / REF

0. 1 uF

PROGRAMMABLE CLOCK GENERATOR 26 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

CLKIN Equivalent Schematic

Wiring the Differential Input to Accept Single-Ended Levels

Figure Recommended Schematic for Wiring a Differential

Input to Accept Single-end ed Levels shows how a differential

input can be wired to accept single ended levels. This

configuration has three properties; the total output impedance

of Ro and Rs matches the 50 ohm transmission line

impedance, the Vrx voltage is generated at the CLKIN inputs

which maintains the LVCMOS driver voltage level across the

transmission line for best S/N and the R1-R2 voltage divider

values ensure that Vrx p-p at CLKIN is less than the maximum

value of 1.2V.

Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels



Vrx

VersaClock 5 Receiver

CLKI N

CLKI NB

LV CMOS

VDD

Zo = 50 Ohm

Ro + Rs = 50

SEPTEMBER 12, 2018 27 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

Table 26 Nominal Voltage Divider Values vs Driver VDD

shows resistor values that ensure the maximum drive level for

the CLKIN port is not exceeded for all combinations of 5%

tolerance on the driver VDD, the VersaClock Vddo_0 and 5%

resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the impedance of the R1-R2

divider. To assist this assessment, the total load on the driver

is included in the table.

Table 26: Nominal Voltage Divider Values vs Driver VDD

HCSL Differential Clock Input Interface

CLKIN/CLKINB will accept DC coupled HCSL signals.

CLKIN, CLKINB Input Driven by an HCSL Driver

3.3V Differential LVPECL Clock Input Interface

The logic levels of 3.3V LVPECL and LVDS can exceed VIH

max for the CLKIN/B pins. Therefore the LVPECL levels must

be AC coupled to the VersaClock differential input and the DC

bias restored with external voltage dividers. A single table of

bias resistor values is provided below for both for 3.3V

LVPECL and LVDS. Vbias can be VDDD, VDDOX or any other

available voltage at the VersaClock receiver that is most

conveniently accessible in layout.

CLKIN, CLKINB Input Driven by a 3.3V LVPECL Driver

LVCMOS Driver VDD Ro+Rs R1 R2 Vrx (peak) Ro+Rs+R1+R2

3.3 50.0 130 75 0.97 255

2.5 50.0 100 100 1.00 250

1.8 50.0 62 130 0.97 242

Zo=50ohm

CLKIN

CLKINB

VersaClock 5 Receiver

+3.3V LVPECL

Driver

Zo=50ohm

VersaClock 5 Receiver

R9 R10

50ohm 50ohm

Vbias

Rpu1 Rpu2

CLKIN

CLKINB

RTT

50ohm

0.01µF

R15

4.7kohm

R13

4.7kohm

PROGRAMMABLE CLOCK GENERATOR 28 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

CLKIN, CLKINB Input Driven by an LVDS Driver

Table 27: Bias Resistors for 3.3V LVPECL and LVDS Drive to CLKIN/B

2.5V Differential LVPECL Clock Input Interface

The maximum DC 2.5V LVPECL voltage meets the VIH max

CLKIN requirement. Therefore 2.5V LVPECL can be

connected directly to the CLKIN terminals without AC coupling

CLKIN, CLKINB Input Driven by a 2.5V LVPECL Driver

Vbias

(V) Rpu1/2

(kohm) CLKIN/B Bias Voltage

(V)

3.3 22 0.58

2.5 15 0.60

1.8 10 0.58

LVDS Driver

Zo=50ohm

VersaClock 5 Receiver

Rterm

100ohm

Vbias

Rpu1 Rpu2

CLKIN

CLKINB

0.1µF

4.7kohm

+2.5V LVPECL

Driver

Zo=50ohm

R1 R2

50ohm 50ohm

RTT

18ohm

Versaclock 5 Receiver

CLKIN

CLKINB

SEPTEMBER 12, 2018 29 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (ZT) is between 90. and 132. The

actual value should be selected to match the differential

impedance (Zo) of your transmission line. A typical

point-to-point LVDS design uses a 100 parallel resistor at the

receiver and a 100. differential transmission-line

environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must

be placed as close to the receiver as possible. The standard

termination schematic as shown in figure Standard

Termination or the termination of figure Optional Termination

can be used, which uses a center tap capacitance to help filter

common mode noise. The capacitor value should be

approximately 50pF. In addition, since these outputs are LVDS

compatible, the input receiver's amplitude and common-mode

input range should be verified for compatibility with the IDT

LVDS output. If using a non-standard termination, it is

recommended to contact IDT and confirm that the termination

will function as intended. For example, the LVDS outputs

cannot be AC coupled by placing capacitors between the

LVDS outputs and the 100 ohm shunt load. If AC coupling is

required, the coupling caps must be placed between the 100

ohm shunt termination and the receiver. In this manner the

termination of the LVDS output remains DC coupled.

LVDS

Driver

LVDS

Driver LVDS

Receiver

LVDS

Receiver

ZO  ZT

Standard Termination

Optional Termination

PROGRAMMABLE CLOCK GENERATOR 30 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs generate ECL/LVPECL compatible

outputs. Therefore, terminating resistors (DC current path to

ground) or current sources must be used for functionality.

These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize

operating frequency and minimize signal distortion. The figure

below show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist and

it would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

3.3V LVPECL Output Termination (1)

3.3V LVPECL Output Termination (2)

LVPECL

Zo=50ohm

3.3V

R1 R2

3.3V

50ohm 50ohm

RTT

50ohm

Input

LVPECL

Zo=50ohm

3.3V

Input

R1 R2

3.3V

84ohm 84ohm

3.3V

R3 R4

125ohm 125ohm

SEPTEMBER 12, 2018 31 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

Termination for 2.5V LVPECL Outputs

Figures 2.5V L VPECL Driver Termination Example (1) and (2)

show examples of termination for 2.5V LVPECL driver. These

terminations are equivalent to terminating 50 to VDDO – 2V.

For VDDO = 2.5V, the VDDO – 2V is very close to ground level.

The R3 in Figure 2.5V LVPECL Driver Termination Example

(3) can be eliminated and the termination is shown in example

(2).

2.5V LVPECL Driver Termination Example (1)

2.5V LVPECL Driver Termination Example (2)

2.5V LVPECL Driver Termination Example (3)

2.5V LVPECL

Driver

Zo=50ohm

2.5V

R2 R4

VDDO = 2.5V

62.5ohm 62.5ohm

2.5V

R1 R3

250ohm 250ohm

2.5V LVPECL

Driver

Zo=50ohm

2.5V

R1 R2

VDDO = 2.5V

50ohm 50ohm

2.5V LVPECL

Driver

Zo=50ohm

2.5V

R1 R2

VDDO = 2.5V

50ohm 50ohm

18ohm

PROGRAMMABLE CLOCK GENERATOR 32 SEPTEMBER 12, 2018

5P49V5913 DATASHEET

PCI Express Application Note

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below

shows the most frequently used Common Clock Architecture

in which a copy of the reference clock is provided to both ends

of the PCI Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes

PLLs are modeled as well as the phase interpolator in the

receiver. These transfer functions are called H1, H2, and H3

respectively. The overall system transfer function at the

receiver is:

The jitter spectrum seen by the receiver is the result of

applying this system transfer function to the clock spectrum

X(s) and is:

In order to generate time domain jitter numbers, an inverse

Fourier Transform is performed on X(s)*H3(s) * [H1(s) -

H2(s)].

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen1 Magnitude of Transfer Function

For PCI Express Gen2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in RMS. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCIe Gen2A Magnitude of Transfer Function

PCIe Gen2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

Ht s H3 s H1 s H2 s–=

Ys Xs H3 sH1 s H2 s–=

SEPTEMBER 12, 2018 33 PROGRAMMABLE CLOCK GENERATOR

5P49V5913 DATASHEET

PCIe Gen3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI Express

Reference Clock Requirements.

Marking Diagram

1. Line 1 is the truncated part number.

2. “ddd” denotes dash code.

3. “YWW” is the last digit of the year and week that the part was assembled.

4. “**” denotes lot number.

5. “$” denotes mark code.

5913B

ddd

YWW**$

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-

lectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

Tech Support

www.idt.com/go/support

Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is

the most current data available.

www.idt.com/document/psc/nlnlg24-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-280-x-280-mm

Ordering Information

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

Revision History

Part / Order Number Shipping Packaging Package Temperature

5P49V5913BdddNLGI Trays 24-pin VFQFPN -40° to +85C

5P49V5913BdddNLGI8 Tape and Reel 24-pin VFQFPN -40° to +85C

Date Description of Change

September 12, 2018 Corrected typo in Power Down Current units from µA to mA.

March 3, 2017 Updated package outline drawings.

February 24, 2017 1. Added “Output Alignment” section.

2. Update “Output Divides” section

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.80 x 2.80 mm

NLG24P2, PSC-4192-02, Rev 02, Page 1

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.80 x 2.80 mm

NLG24P2, PSC-4192-02, Rev 02, Page 2

Package Revision History

Rev No.Date Created Description

Rev 01 Add Chamfer

Oct 12, 2016

Rev 02 New Format, Recalculate Land Pattern

Nov 2, 2018