© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 10
1Publication Order Number:
MC14511B/D
MC14511B
BCD-To-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD−to−seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4−bit storage latch, an 8421
BCD−to−seven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn−off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven−segment
light−emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
Features
•Low Logic Circuit Power Dissipation
•High−Current Sourcing Outputs (Up to 25 mA)
•Latch Storage of Code
•Blanking Input
•Lamp Test Provision
•Readout Blanking on all Illegal Input Combinations
•Lamp Intensity Modulation Capability
•Time Share (Multiplexing) Facility
•Supply Voltage Range = 3.0 V to 18 V
•Capable of Driving Two Low−power TTL Loads, One Low−power
Schottky TTL Load, or Two HTL Loads Over the Rated Temperature
Range
•Chip Complexity: 216 FETs or 54 Equivalent Gates
•Triple Diode Protection on all Inputs
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin Input Voltage Range, All Inputs −0.5 to VDD + 0.5 V
IDC Current Drain per Input Pin 10 mA
PDPower Dissipation,
per Package (Note 2)
500 mW
TAOperating Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
IOHmax Maximum Output Drive Current
(Source) per Output
25 mA
POHmax Maximum Continuous Output Power
(Source) per Output (Note 3)
50 mA
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C to 125°C
3. POHmax = IOH (VDD − VOH)
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SO−16
DW SUFFIX
CASE 751G 1
16
14511B
AWLYYWWG
SOEIAJ−16
F SUFFIX
CASE 966 1
16
MC14511B
ALYWG
SOIC−16
D SUFFIX
CASE 751B
1
16
14511BG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
16
1
MC14511BCP
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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MC14511B
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2
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages
to this high−impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range
VSS v (Vin or Vout) v VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted
to VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
b
a
g
f
VDD
e
d
c
BI
LT
C
B
VSS
A
D
LE
0123456789
DISPLAY
a
b
c
d
e
fg
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
XX0XXXX1111111 8
X 0 1 X X X X 0 0 0 0 0 0 0 Blank
01100001111110 0
01100010110000 1
01100101101101 2
01100111111001 3
01101000110011 4
01101011011011 5
01101100011111 6
01101111110000 7
01110001111111 8
01110011110011 9
0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
111XXXX * *
X = Don’t Care
* Depends upon the BCD code previously applied when LE = 0
TRUTH TABLE
MC14511B
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55°C 25°C 125°C
Unit
Min Max Min
Typ
(Note 4) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.1
9.1
14.1
−
−
−
4.1
9.1
14.1
4.57
9.58
14.59
−
−
−
4.1
9.1
14.1
−
−
−
Vdc
Input Voltage # “0” Level
(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Voltage
(IOH = 0 mA) Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)
VOH 5.0 4.1
−
3.9
−
3.4
−
−
−
−
−
−
−
4.1
−
3.9
−
3.4
−
4.57
4.24
4.12
3.94
3.70
3.54
−
−
−
−
−
−
4.1
−
3.5
−
3.0
−
−
−
−
−
−
−
Vdc
10 9.1
−
9.0
−
8.6
−
−
−
−
−
−
−
9.1
−
9.0
−
8.6
−
9.58
9.26
9.17
9.04
8.90
8.70
−
−
−
−
−
−
9.1
−
8.6
−
8.2
−
−
−
−
−
−
−
Vdc
15 14.1
−
14
−
13.6
−
−
−
−
−
−
−
14.1
−
14
−
13.6
−
14.59
14.27
14.18
14.07
13.95
13.70
−
−
−
−
−
−
14.1
−
13.6
−
13.2
−
−
−
−
−
−
−
Vdc
Output Drive Current
(VOL = 0.4 V) Sink
(VOL = 0.5 V)
(VOL = 1.5 V)
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current Iin 15 −± 0.1 −±0.00001 ± 0.1 −± 1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package) Vin = 0 or VDD,
Iout = 0 mA
IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Notes 5 & 6)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.9 mA/kHz) f + IDD
IT = (3.8 mA/kHz) f + IDD
IT = (5.7 mA/kHz) f + IDD
mAdc
4. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
5. The formulas given are for the typical characteristics only at 25°C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in mA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 7) (CL = 50 pF, TA = 25°C)
Characteristic Symbol
VDD
Vdc Min Typ Max Unit
Output Rise Time
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns
tTLH 5.0
10
15
−
−
−
40
30
25
80
60
50
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
tTHL 5.0
10
15
−
−
−
125
75
65
250
150
130
ns
Data Propagation Delay Time
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPLH 5.0
10
15
−
−
−
640
250
175
1280
500
350
ns
tPHL 5.0
10
15
−
−
−
720
290
200
1440
580
400
Blank Propagation Delay Time
tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPLH 5.0
10
15
−
−
−
600
200
150
750
300
220
ns
tPHL 5.0
10
15
−
−
−
485
200
160
970
400
320
Lamp Test Propagation Delay Time
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPLH 5.0
10
15
−
−
−
313
125
90
625
250
180
ns
tPHL 5.0
10
15
−
−
−
313
125
90
625
250
180
Setup Time tsu 5.0
10
15
100
40
30
−
−
−
−
−
−
ns
Hold Time th5.0
10
15
60
40
30
−
−
−
−
−
−
ns
Latch Enable Pulse Width tWL 5.0
10
15
520
220
130
260
110
65
−
−
−
ns
7. The formulas given are for the typical characteristics only.
MC14511B
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Figure 1. Dynamic Power Dissipation Signal Waveforms
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
VSS
VOH
VOL
90%
50%
10%
50%
A, B, AND C
ANY OUTPUT
50% DUTY CYCLE
1
2f
Figure 2. Dynamic Signal Waveforms
20 ns 20 ns
VDD
90%
INPUT C
(a) Inputs D and LE low, and
Inputs A, B, BI and LT high.
VSS
VOH
VOL
50%
10%
OUTPUT g
tPLH tPHL
90%
10%
50%
tTLH tTHL
(b) Input D low,
Inputs A, B, BI and LT high.
20 ns
10%
90%
50%
VDD
VSS
VDD
VSS
VOH
VOL
th
tsu
50%
INPUT C
OUTPUT g
LE
(c) Data DCBA strobed into latches.
20 ns 20 ns
VDD
VSS
LE
90%
50%
10%
tWL
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6
CONNECTIONS TO VARIOUS DISPLAY READOUTS
COMMON
CATHODE LED
≈ 1.7 V
VDD
VSS
VDD
COMMON
ANODE LED
VSS
≈ 1.7 V
LIGHT EMITTING DIODE (LED) READOUT
INCANDESCENT READOUT FLUORESCENT READOUT
GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT
VDD VDD
**
VSS
VDD
VSS
FILAMENT
SUPPLY
DIRECT
(LOW BRIGHTNESS)
VSS OR APPROPRIATE
VOLTAGE BELOW VSS.
(CAUTION: Maximum working voltage = 18.0 V)
VDD
APPROPRIATE
VOLTAGE
VSS VSS
VDD
EXCITATION
(SQUARE WAVE,
VSS TO VDD)
1/4 OF MC14070B
** A filament pre−warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.
Direct DC drive of LCD’s not recommended for life of
LCD readouts.
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7
Figure 3. Logic Diagram
LE5
D6
C2
B1
A7
VDD = PIN 16
VSS = PIN 8
BI4
LT3
14g
15f
9e
10d
11c
12b
13a
ORDERING INFORMATION
Device Package Shipping†
MC14511BCPG PDIP−16
(Pb−Free)
500 / Tape & Ammo Box
MC14511BDG SOIC−16
(Pb−Free)
48 Units / Rail
MC14511BDR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14511BDWR2G SO−16 WB
(Pb−Free)
1000 / Tape & Reel
MC14511BFG SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC14511BFELG SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14511B
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8
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
SO−16 WB
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
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9
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
MC14511B/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
