PIC16LF18313-I/P - Microchip Technology

 2015-2017 Microchip Technology Inc. DS40001799C-page 1

PIC16(L)F18313/18323

Description

PIC16(L)F18313/18323 microcontrollers feature Analog, Core Independent Peripherals and Communication

Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.

The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,

PWM and communications) to add flexibility to the application design.

Core Features

• C Compiler Optimized RISC Architecture

• Only 48 Instructions

• Operating Speed:

- DC – 32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• 16-Level Deep Hardware Stack

• Up to Four 8-bit Timers

• Up to Three 16-bit Timers

• Low-Current Power-on Reset (POR)

• Power-up Timer (PWRT)

• Brown-out Reset (BOR)

• Low-Power BOR (LPBOR) Option

• Extended Watchdog Timer (WDT) with Dedicated

On-Chip Oscillator for Reliable Operation

• Programmable Code Protection

Memory

• 3.5 Kbytes Program Flash Memory

• 256B Data SRAM Memory

• 256B of EEPROM

• Direct, Indirect and Relative Addressing Modes

Operating Characteristics

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF18313/18323)

- 2.3V to 5.5V (PIC16F18313/18323)

• Temperature Range:

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

eXtreme Low-Power (XLP) Features

• Sleep mode: 40 nA @ 1.8V, typical

• Watchdog Timer: 250 nA @ 1.8V, typical

• Secondary Oscillator: 300 nA @ 32 kHz

• Operating Current:

-8 A @ 32 kHz, 1.8V, typical

-37 A/MHz @ 1.8V, typical

Power-Saving Functionality

• IDLE mode: ability to put the CPU core to Sleep

while internal peripherals continue operating from

the system clock

• DOZE mode: ability to run the CPU core slower

than the system clock used by the internal periph-

erals

• SLEEP mode: Lowest Power Consumption

• Peripheral Module Disable (PMD): peripheral

power disable hardware module to minimize

power consumption of unused peripherals

Digital Peripherals

• Configurable Logic Cell (CLC):

- Two CLCs

- Integrated combinational and sequential logic

• Complementary Waveform Generator (CWG):

- Rising and falling edge dead-band control

- Full-bridge, half-bridge, 1-channel drive

- Multiple signal sources

• Capture/Compare/PWM (CCP) modules:

- Two CCPs

- 16-bit resolution for Capture/Compare modes

- 10-bit resolution for PWM mode

• Pulse-Width Modulators (PWM)

-Two 10-bit PWMs

• Numerically Controlled Oscillator (NCO):

- Precision linear frequency generator (@50%

duty cycle) with 0.0001% step size of source

input clock

- Input Clock: 0 Hz < FNCO < 32 MHz

- Resolution: FNCO/220

• Serial Communications:

- EUSART

- RS-232, RS-485, LIN compatible

- Auto-Baud Detect, auto-wake-up on start

- Master Synchronous Serial Port (MSSP)

- SPI

-I

2C, SMBus, PMBus™ compatible

• Data Signal Modulator (DSM):

- Modulates a carrier signal with digital data to

create custom carrier synchronized output

waveforms

Full-Featured, Low Pin Count Microcontrollers with XLP

PIC16(L)F18313/18323

DS40001799C-page 2  2015-2017 Microchip Technology Inc.

• Up to 12 I/O Pins:

- Individually programmable pull-ups

- Slew rate control

- Interrupt-on-change with edge-select

- Input level selection control (ST or TTL)

- Digital open-drain enable

• Peripheral Pin Select (PPS):

- I/O pin remapping of digital peripherals

• Timer modules:

-Timer0:

- 8/16-bit timer/counter

- Synchronous or asynchronous operation

- Programmable prescaler/postscaler

- Time base for capture/compare function

- Timer1 with gate control:

- 16-bit timer/counter

- Programmable internal or external clock

sources

- Multiple gate sources

- Multiple gate modes

- Time base for capture/compare function

-Timer2:

- 8-bit timers

- Programmable prescaler/postscaler

- Time base for PWM function

Analog Peripherals

• 10-bit Analog-to-Digital Converter (ADC):

- Up to 11 external channels

- Conversion available during Sleep

• Comparator:

- Up to two comparators

- Fixed Voltage Reference at non-inverting

input(s)

- Comparator outputs externally accessible

• 5-bit Digital-to-Analog Converter (DAC):

- 5-bit resolution, rail-to-rail

- Positive Reference Selection

- Unbuffered I/O pin output

- Internal connections to ADCs and

comparators

• Voltage Reference:

- Fixed Voltage Reference with 1.024V, 2.048V

and 4.096V output levels

Flexible Oscil lator Structure

• High-Precision Internal Oscillator:

- Software-selectable frequency range up to 32

MHz

- ±2% at nominal 4 MHz calibration point

• 4x PLL with External Sources

• Low-Power Internal 31 kHz Oscillator

(LFINTOSC)

• External Low-Power 32 kHz Crystal Oscillator

(SOSC)

• External Oscillator Block with:

- Three Crystal/Resonator modes up to

20 MHz

- Three External Clock modes up to 32 MHz

- Fail-Safe Clock Monitor

- Detects clock source failure

- Oscillator Start-up Timer (OST)

- Ensures stability of crystal oscillator

sources

 2015-2017 Microchip Technology Inc. DS40001799C-page 3

PIC16(L)F18313/18323

PIC16(L)F183XX Family Types

Device

Data Sheet Index

Program Flash

Memory (Words)

Program Flash

Memory (Kbytes)

Data Memor y

(bytes)

Data SRAM

(bytes)

I/Os(2)

10-bit ADC (ch)

5-bit DAC

High-Speed/

Comparators

CWG

Clock Ref

Timers

(8/16-bit)

CCP

10-bit PWM

NCO

EUSART

I2C/SPI

CLC

DSM

PPS

XLP

PMD

Idle and Doze

Debug(1)

PIC16(L)F18313 (1) 2048 3.5 256 256 6 5 1 1 1 1 2/1 2 2 1 1 1/1 2 1 Y Y Y Y I

PIC16(L)F18323 (1) 2048 3.5 256 256 12 11 1 2 1 1 2/1 2 2 1 1 1/1 2 1 Y Y Y Y I

PIC16(L)F18324 (2) 4096 7256 512 12 11 1 2 2 1 4/3 4 2 1 1 1/1 4 1 Y Y Y Y I

PIC16(L)F18325 (3) 8192 14 256 1024 12 11 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I

PIC16(L)F18326 (4) 16384 28 256 2048 12 15 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I

PIC16(L)F18344 (2) 4096 7256 512 18 17 1 2 2 1 4/3 4 2 1 1 1/1 4 1 Y Y Y Y I

PIC16(L)F18345 (3) 8192 14 256 1024 18 17 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I

PIC16(L)F18346 (4) 16384 28 256 2048 18 21 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I

Note 1: Debugging Methods: (I) – Integrated on Chip;

2: One pin is input-only.

Data Sheet Index: (Unshaded devices are described in this document.)

1: DS40001799 PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP

2: DS40001800 PIC16(L)F18324/18344 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP

3: DS40001795 PIC16(L)F18325/18345 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP

4: DS40001839 PIC16(L)F18326/18346 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP

Note: For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

PIC16(L)F18313/18323

DS40001799C-page 4  2015-2017 Microchip Technology Inc.

Pin Diagrams

FIGURE 1: 8-PIN PDIP, SOIC, UDFN

FIGURE 2: 14-PIN PDIP, SOIC , TSSOP

FIGURE 3: 16-PIN UQFN

VDD

RA5

RA4

VPP/MCLR/RA3

RA0/ICSPDAT

RA1/ICSPCLK

RA2

VSS

PIC16(L)F18313

VDD

RA5

RA4

VPP/MCLR/RA3

RC5

RC4

RC3

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

RC1

RC2

VSS

PIC16(L)F18323

RC4

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

VDD

RA5

RA4

RA3/MCLR/VPP

RC5

RC3

RC2

RC1

PIC16(L)F18323

Note 1: It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS

connection to the device.

 2015-2017 Microchip Technology Inc. DS40001799C-page 5

PIC16(L)F18313/18323

TABLE 1: 8-PIN ALLOCATION TABLE (PIC16 (L)F 18 313 )

I/O(2)

PDIP/SOIC/UDFN

ADC

Reference

Comparator

NCO

DAC

DSM

Timers

CCP

PWM

CWG

MSSP

EUSART

CLC

CLKR

Interrupt

Pull-up

Basic

RA0 7ANA0 —C1IN0+ —DAC1OUT MDCIN1(1) — — — — — — CLCIN3(1) —IOC YICDDAT/

ICSPDAT

RA1 ANA1 VREF+C1IN0- —DAC1REF+MDMIN

(1) ————

SCK1(1)

SCL1(1,3,4) RX(1) CLCIN2(1) —IOC YICDCLK/

ICSPCLK

RA2 5ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1IN(1) SDA1(1,3,4)

SDI1(1) — — — INT(1)

IOC

Y —

RA3 4—— — — — — — — — — SS1(1) —CLCIN0(1) —IOC Y MCLR

VPP

RA4 3ANA4 —C1IN1- — — — T1G(1)

SOSCO

— — — — — — — IOC YCLKOUT

OSC2

RA5 2 ANA5 —— — —MDCIN2(1) T1CKI(1)

SOSCIN

SOSCI

CCP1(1)

CCP2(1) —— ——

CLCIN1(1) —IOC Y CLKIN

OSC1

VDD 1— — — — — — — — — — — — — —— — VDD

VSS 8—— — — — — — — — — — — — ——— VSS

OUT(2)

— — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A SDA1(3) CK CLC1OUT CLKR — — —

—— — — — — — — CCP2 PWM6 CWG1B SCL1(3) DT CLC2OUT ——— —

— — — — — — — — — — CWG1C SDO1 TX — — — — —

—— — — — — — — — — CWG1D SCK1 ——————

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: These pins are configured for I2C logic levels as described in Section 13.3 “Bidirect ion al Pins ”; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g.,

RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.

PIC16(L)F18313/18323

DS40001799C-page 6  2015-2017 Microchip Technology Inc.

TABLE 2: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323)

I/O(2)

PDIP/SOIC/TSSOP

UQFN

ADC

Reference

Comparator

NCO

DAC

DSM

Timers

CCP

PWM

CWG

MSSP

EUSART

CLC

CLKR

Interrupt

Pull-up

Basic

RA0 13 12 ANA0 —C1IN0+ —DAC1OUT — — — — — — — — —IOC YICDDAT/

ICSPDAT

RA1 12 11 ANA1 VREF+C1IN0-

C2IN0-

—DAC1REF+———— — ————

IOC Y ICDCLK/

ICSPCLK

RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1IN(1) — — — — INT(1)

IOC

Y —

RA3 4 3 —— — — — — — — — — — — — —

IOC Y MCLR

VPP

RA4 3 2 ANA4 — — — — — T1G(1)

SOSCO

— — — — — — — IOC YCLKOUT

OSC2

RA5 2 1 ANA5 ——— — —

T1CKI(1)

SOSCIN

SOSCI

—— — ——

CLCIN3(1) —IOC Y CLKIN

OSC1

RC0 10 9ANC0 —C2IN0+ — — — — — — — SCK1(1)

SCL1(1,3,4) — — — IOC Y —

RC1 9 8 ANC1 —C1IN1-

C2IN1-

—— — —— — —SDI1(1)

SDA1(1,3,4) —CLCIN2(1) —IOC Y —

RC2 8 7 ANC2 —C1IN2-

C2IN2-

— — MDCIN1(1) — — — — — — — — IOC Y—

RC3 7 6 ANC3 —C1IN3-

C2IN3-

——

MDMIN(1) —CCP2(1) ——

SS1(1) —CLCIN0(1) —IOC Y —

RC4 6 5 ANC4 — — — — — — — — — — — CLCIN1(1) —IOC Y—

RC5 5 4 ANC5 ——— —MDCIN2(1) —CCP1(1) ———

RX(1) ——

IOC Y —

VDD 116 — — — — — — — — — — — — — — — — VDD

VSS 14 13 —— — — — — — — — — — — — — ——VSS

OUT(2)

— — — — C1OUT NCO —DSM TMR0 CCP1 PWM5 CWG1A SDA1(3) CK CLC1OUT CLKR — — —

——— —

C2OUT —— — —

CCP2 PWM6 CWG1B SCL1(3) DT CLC2OUT ——— —

— — — — — — — — — — — CWG1C SDO1 TX — — — —

——— — — — — — — — — CWG1D SCK1 ——————

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-3.

3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

4: These pins are configured for I2C logic levels as described in Section 13.3 “Bidirectional Pins”; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5)

will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.

 2015-2017 Microchip Technology Inc. DS40001799C-page 7

PIC16(L)F18313/18323

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers ..................................................................................... 16

3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19

4.0 Memory Organization ................................................................................................................................................................. 21

5.0 Device Configuration.................................................................................................................................................................. 51

6.0 Resets ........................................................................................................................................................................................ 58

7.0 Oscillator Module........................................................................................................................................................................ 66

8.0 Interrupts .................................................................................................................................................................................... 85

9.0 Power-Saving Operation Modes .............................................................................................................................................. 101

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 107

11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 111

12.0 I/O Ports ................................................................................................................................................................................... 128

13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 142

14.0 Peripheral Module Disable ....................................................................................................................................................... 148

15.0 Interrupt-on-Change ................................................................................................................................................................. 154

16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 160

17.0 Temperature Indicator Module ................................................................................................................................................. 163

18.0 Comparator Module.................................................................................................................................................................. 165

19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 174

20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 180

21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 202

22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 217

23.0 Numerically Controlled Oscillator (NCO1) Module ................................................................................................................... 231

24.0 5-bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 242

25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 246

26.0 Timer0 Module ......................................................................................................................................................................... 257

27.0 Timer1 Module with Gate Control............................................................................................................................................. 264

28.0 Timer2 Module ......................................................................................................................................................................... 277

29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 282

30.0 Master Synchronous Serial Port (MSSP1) Module .................................................................................................................. 293

31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) ............................................................. 346

32.0 Reference Clock Output Module .............................................................................................................................................. 371

33.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 374

34.0 Instruction Set Summary.......................................................................................................................................................... 376

35.0 Electrical Specifications............................................................................................................................................................ 390

36.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 420

37.0 Development Support............................................................................................................................................................... 441

38.0 Packaging Information.............................................................................................................................................................. 445

The Microchip Website ...................................................................................................................................................................... 468

Customer Change Notification Service .............................................................................................................................................. 468

Customer Support .............................................................................................................................................................................. 468

Product Identification System ............................................................................................................................................................ 469

PIC16(L)F18313/18323

DS40001799C-page 8  2015-2017 Microchip Technology Inc.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer No tific atio n Syst em

 2015-2017 Microchip Technology Inc. DS40001799C-page 9

PIC16(L)F18313/18323

1.0 DEVICE OVERVIEW

The PIC16(L)F18313/18323 are described within this

data sheet. The PIC16(L)F18313 is available in 8-pin

PDIP, SOIC and UDFN packages, and the

PIC16(L)F18323 is available in 14-pin PDIP, SOIC and

TSSOP packages and 16-pin UQFN packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F18313/18323 devices. Tabl e 1-2 shows the

pinout descriptions.

Reference Table 1-1 for peripherals available per device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16(L)F18313

PIC16(L)F18323

Analog-to-Digital Converter (ADC) ●●

Temperature Indicator ●●

Digital-to-Analog Converter (DAC)

DAC1 ●●

Fixed Voltage Reference (FVR)

ADCFVR ●●

CDAFVR ●●

Digital Signal Modulator (DSM)

DSM1 ●●

Numerically Controlled Oscillator (NCO)

NCO1 ●●

Capture/Compare/PWM Modules (CCP)

CCP1 ●●

CCP2 ●●

Comparators

C1 ●●

C2 ●

Complementary Waveform Generator (CWG)

CWG1 ●●

Configurable Logic Cell (CLC)

CLC1 ●●

CLC2 ●●

Enhanced Universal Synchronous/Asynchronous Receiver/

Transmitter (EUSART)

EUSART1 ●●

Master Synchronous Serial Port (MSSP)

MSSP1 ●●

Pulse-Width Modulator (PWM)

PWM5 ●●

PWM6 ●●

Timers (TMR)

TMR0 ●●

TMR1 ●●

TMR2 ●●

 2015-2017 Microchip Technology Inc. DS40001799C-page 10

PIC16(L)F18313/18323

FIGURE 1-1: PIC16(L)F18313/18323 BLOCK DIAGRAM

Rev. 10-000039Z

5/25/2017

CLKIN/OSC1

RAM

CPU

(Note 3)

Timing

Generation

EXTOSC

Oscillator

MCLR

Program

Flash Memory

FVR

ADC

10-bit

C1Timer1Timer2

CCP1CCP2WD T

DAC1C2(2)

Timer0

PORTC(2)

CLC1CLC2 MSSP1

CLKOUT/OSC2

EUSART1

PWM5

Second ar y

Oscillator

(SOSC)

SOSCI

SOSCO

PORTA

Temp

Indicator

PWM6

CWG1NCO1 CWG2

Note 1: See available chapters for more information on peripherals.

2: Available on PIC16(L)F18323 only.

3: See Figure 4-1.

 2015-2017 Microchip Technology Inc. DS40001799C-page 11

PIC16(L)F18313/18323

TABLE 1-2: PIC16(L)F18313 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/ANA0/C1IN0+/

DAC1OUT/CLCIN3(1)/MDCIN1(1)/

ICSPDAT/ICDDAT

RA0 TTL/ST CMOS General purpose I/O.

ANA0 AN — ADC Channel A0 input.

C1IN0+ AN — Comparator C1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

MDCIN1 TTL/ST — Modular Carrier input 1.

ICSPDAT TTL/ST — ICSP™ Data I/O.

ICDDAT TTL/ST — In-Circuit Debug Data I/O.

RA1/ANA1/VREF+/C1IN0-/

MDMIN(1)/CLCIN2(1)/SCK1(3)/

SCL1(3)/RX(1)/DAC1REF+/

ICSPCLK/ICDCLK

RA1 TTL/ST CMOS General purpose I/O.

ANA1 AN — ADC Channel A1 input.

VREF+ AN — ADC Voltage Reference Positive input.

C1IN0- AN — Comparator C1 negative input.

MDMIN TTL/ST — Modulator Source Input.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

SCK1 TTL/ST — SPI clock.

SCL1 I2CODI

2C clock input/output.

RX TTL/ST — EUSART asynchronous input.

DAC1REF+ AN — Digital-to-Analog Converter positive reference voltage

input.

ICSPCLK — CMOS Serial Programming Clock.

ICDCLK — CMOS In-Circuit Debug Clock.

RA2/ANA2/VREF-/DAC1REF-/

SDI1(1,3)/SDA1(1,3)/T0CKI(1)/

CWG1IN(1)/INT(1)

RA2 TTL/ST CMOS General purpose I/O.

ANA2 AN — ADC Channel A3 input.

VREF- AN — ADC Voltage Reference Negative input.

DAC1REF- AN — Digital-to-Analog Converter negative reference voltage

input.

SDI1 TTL/ST — SPI Data Input.

SDA1 I2CODI

2C clock input/output.

T0CKI TTL/ST — TMR0 clock input.

CWG1IN TTL/ST — Complementary Waveform Generator input.

INT TTL/ST — External interrupt.

RA3/MCLR/VPP/SS1(1)/CLCIN0(1) RA3 TTL/ST CMOS General purpose I/O.

MCLR TTL/ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

SS1TTL/ST — Slave Select input.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output

selection registers. See Register 13-2.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F18313/18323

DS40001799C-page 12  2015-2017 Microchip Technology Inc.

RA4/ANA4/C1IN1-/T1G(1)/

SOSCO/OSC2/CLKOUT

RA4 TTL/ST CMOS General purpose I/O.

ANA4 AN — ADC Channel A4 input.

C1IN1- AN — Comparator C1 negative input.

T1G TTL/ST — TMR1 gate input.

SOSCO — XTAL Secondary Oscillator Connection.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA5/ANA5/MDCIN2(1)/T1CKI(1)/

SOSCIN/SOSCI/CLCIN1(1)/

CCP1(1)/CCP2(2)/OSC1/CLKIN

RA5 TTL/ST CMOS General purpose I/O.

ANA5 AN — ADC Channel A5 input.

MDCIN2 TTL/ST — Modular Carrier input 2.

T1CKI TTL/ST — TMR1 clock input.

SOSCIN TTL/ST — Secondary Oscillator Input Connection.

SOSCI XTAL — Secondary Oscillator Connection.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

CCP1 TTL/ST — Capture/Compare/PWM1 input.

CCP2 TTL/ST — Capture/Compare/PWM2 input.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN TTL/ST — External clock input.

OUT(2) C1OUT — CMOS Comparator output.

NCO1 — CMOS NCO output.

CCP1 — CMOS Capture/Compare/PWM1 output.

CCP2 — CMOS Capture/Compare/PWM2 output.

PWM5 — CMOS PWM5 output.

PWM6 — CMOS PWM6 output.

CWG1A — CMOS Complementary Waveform Generator Output A.

CWG1B — CMOS Complementary Waveform Generator Output B.

CWG1C — CMOS Complementary Waveform Generator Output C.

CWG1D — CMOS Complementary Waveform Generator Output D.

SDA1(3) —ODI

2C data input/output.

SDO1 — CMOS SPI data output.

SCK1 — CMOS SPI clock output.

SCL1(3) —ODI

2C clock output.

TX/CK — CMOS EUSART asynchronous TX data/synchronous clock

output.

DT — CMOS EUSART synchronous data output.

CLC1OUT — CMOS Configurable Logic Cell 1 source output.

CLC2OUT — CMOS Configurable Logic Cell 2 source output.

DSM — CMOS Modulator output.

TMR0 — CMOS TMR0 output.

CLKR — CMOS Clock reference output.

TABLE 1-2: PIC16(L)F18313 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output

selection registers. See Register 13-2.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

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PIC16(L)F18313/18323

TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/ANA0/C1IN0+/

DAC1OUT/ICSPDAT/ICDDAT

RA0 TTL/ST CMOS General purpose I/O.

ANA0 AN — ADC Channel A0 input.

C1IN0+ AN — Comparator C1 positive input.

DAC1OUT — AN Digital-to-Analog Converter output.

ICSPDAT TTL/ST — ICSP™ Data I/O.

ICDDAT TTL/ST — In-Circuit Debug Data I/O.

RA1/ANA1/VREF+/C1IN0-/

C2IN0-/DAC1REF+/ICSPCLK/

ICDCLK

RA1 TTL/ST CMOS General purpose I/O.

ANA1 AN — ADC Channel A1 input.

VREF+ AN — ADC Voltage Reference input.

C1IN0- AN — Comparator C1 negative input.

C2IN0- AN — Comparator C2 negative input.

DAC1REF+ AN — Digital-to-Analog Converter positive reference voltage input.

ICSPCLK TTL/ST — Serial Programming Clock.

ICDCLK TTL/ST — In-Circuit Debug Clock.

RA2/ANA2/VREF-/DAC1REF-/

T0CKI(1)/CWG1IN(1)/INT(1) RA2 TTL/ST CMOS General purpose I/O.

ANA2 AN — ADC Channel A2 input.

VREF- AN — ADC Negative Voltage Reference input.

DAC1REF- AN — Digital-to-Analog Converter negative reference voltage

input.

T0CKI TTL/ST — TMR0 clock input.

CWG1IN TTL/ST — Complementary Waveform Generator input.

INT TTL/ST — External interrupt.

RA3/MCLR/VPP RA3 TTL/ST CMOS General purpose I/O.

MCLR TTL/ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

RA4/ANA4/T1G(1)/SOSCO/

OSC2/CLKOUT

RA4 TTL/ST CMOS General purpose I/O.

ANA4 AN — ADC Channel A4 input.

T1G TTL/ST — TMR1 gate input.

SOSCO — XTAL Secondary Oscillator Connection.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

RA5/ANA5/T1CKI(1)/CLCIN3(1)/

SOSCI/SOSCIN/OSC1/CLKIN

RA5 TTL/ST CMOS General purpose I/O.

ANA5 AN — ADC Channel A5 input.

T1CKI TTL/ST — TMR1 clock input.

CLCIN3 TTL/ST — Configurable Logic Cell source input.

SOSCI XTAL — Secondary Oscillator Connection.

SOSCIN TTL/ST — Secondary Oscillator Input Connection.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN TTL/ST — External clock input.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output

selection registers. See Register 13-2.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F18313/18323

DS40001799C-page 14  2015-2017 Microchip Technology Inc.

RC0/ANC0/C2IN0+/SCL1(1)/

SCK1(1) RC0 TTL/ST CMOS General purpose I/O.

ANC0 AN — ADC Channel C0 input.

C2IN0+ AN — Comparator positive input.

SCL1 I2CODI

2C clock.

SCK1 TTL/ST — SPI clock.

RC1/ANC1/C1IN1-/C2IN1-/

SDA1(1)/SDI1(1)/CLCIN2(1) RC1 TTL/ST CMOS General purpose I/O.

ANC1 AN — ADC Channel C1 input.

C1IN1- AN — Comparator C1 negative input.

C2IN1- AN — Comparator C2 negative input.

SDA1 I2CODI

2C data.

SDI1 TTL/ST — SPI data input.

CLCIN2 TTL/ST — Configurable Logic Cell source input.

RC2/ANC2/C1IN2-/C2IN2-/

MDCIN1(1) RC2 TTL/ST CMOS General purpose I/O.

ANC2 AN — ADC Channel C2 input.

C1IN2- AN — Comparator C1 negative input.

C2IN2- AN — Comparator C2 negative input.

MDCIN1 TTL/ST — Modular Carrier input 1.

RC3/ANC3/C1IN3-/C2IN3-/

MDMIN(1)/CCP2(1)/CLCIN0(1)/

SS1(1)

RC3 TTL/ST CMOS General purpose I/O.

ANC3 AN — ADC Channel C3 input.

C1IN3- AN — Comparator C1 negative input.

C2IN3- AN — Comparator C2 negative input.

MDMIN TTL/ST — Modular Source input.

CCP2 TTL/ST — Capture/Compare/PWM2.

CLCIN0 TTL/ST — Configurable Logic Cell source input.

SS1TTL/ST — Slave Select input.

RC4/ANC4/CLCIN1(1) RC4 TTL/ST CMOS General purpose I/O.

ANC4 AN — ADC Channel C4 input.

CLCIN1 TTL/ST — Configurable Logic Cell source input.

RC5/ANC5/MDCIN2(1)/CCP1(1)/

RX(1) RC5 TTL/ST CMOS General purpose I/O.

ANC5 AN — ADC Channel C5 input.

MDCIN2 TTL/ST — Modular Carrier input 2.

CCP1 TTL/ST — Capture/Compare/PWM1.

RX TTL/ST — EUSART asynchronous input.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output

selection registers. See Register 13-2.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

 2015-2017 Microchip Technology Inc. DS40001799C-page 15

PIC16(L)F18313/18323

OUT(2) C1OUT — CMOS Comparator output.

C2OUT — CMOS Comparator output.

CCP1 — CMOS Capture/Compare/PWM1 output.

CCP2 — CMOS Capture/Compare/PWM2 output.

PWM5 — CMOS PWM5 output.

PWM6 — CMOS PWM6 output.

CWG1A — CMOS Complementary Waveform Generator Output A.

CWG1B — CMOS Complementary Waveform Generator Output B.

CWG1C — CMOS Complementary Waveform Generator Output C.

CWG1D — CMOS Complementary Waveform Generator Output D.

SDA1(3) —ODI

2C data input/output.

SDO1 — CMOS SPI data output.

SCK1 — CMOS SPI clock output.

SCL1(3) —ODI

2C clock output.

TX/CK — CMOS EUSART asynchronous TX data/synchronous clock output.

DT — CMOS EUSART synchronous data output.

CLC1OUT — CMOS Configurable Logic Cell 1 source output.

CLC2OUT — CMOS Configurable Logic Cell 2 source output.

NCO1 — CMOS Numerically controlled oscillator output.

DSM — CMOS Data Signal Modulator output.

TMR0 — CMOS TMR0 clock output.

TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.

2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output

selection registers. See Register 13-2.

3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.

PIC16(L)F18313/18323

DS40001799C-page 16  2015-2017 Microchip Technology Inc.

2.0 GUIDELINES FOR GETTING

STARTED WITH

PIC16(L)F183XX

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC16(L)F183XX family of 8-bit

microcontrollers requires attention to a minimal set of

device pin connections before proceeding with

development.

The following pins must always be connected:

•All V

DD and VSS pins

(see Section 2.2 “Power Supply Pins”)

•MCLR pin (when configured for external

operation)

(see Section 2.3 “Master Clear (MCLR) Pin”)

These pins must also be connected if they are being

used in the end application:

• ICSPCLK/ICSPDAT pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging

purposes (see Section 2.4 “ICSP™ Pins”)

• OSC1 and OSC2 pins when an external oscillator

source is used

(see Section 2.5 “External Oscillator Pins”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins are used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

FIGURE 2-1: RECOM MENDE D

MINIMUM CONNECTIONS

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins (VDD and VSS) is required. All VDD

and VSS pins must be connected. None can be left

floating.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A 0.1 µF (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device, with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

•Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type

capacitor in parallel to the above described

decoupling capacitor. The value of the second

capacitor can be in the range of 0.01 µF to

0.001 µF. Place this second capacitor next to

each primary decoupling capacitor. In high-speed

circuit designs, consider implementing a decade

pair of capacitances as close to the power and

ground pins as possible (e.g., 0.1 µF in parallel

with 0.001 µF).

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

inductance.

2.2.2 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits, including microcontrollers, to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 µF to 47 µF.

VDD

VSS

VDD

MCLR/VPP

Key (all values are recommendations):

C1 and C2: 0.1 PF, 20V ceramic

R1: 10 kȍ

R2: 100ȍ to 470ȍ

Note1: Only when MCLRE configuration bit is 1 and the

MCLR pin does not have a weak pull-up.

PIC16(L)F1xxx

(Note 1)

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PIC16(L)F18313/18323

2.3 Master Clear (MCLR) Pin

The MCLR pin provides three specific device functions:

• Device Reset (when MCLRE = 1)

• Digital input pin (when MCLRE = 0)

• Device Programming and Debugging

If programming and debugging are not required in the

end application then either set the MCLRE

configuration bit to ‘1’ and use the pin as a digital input

or clear the MCLRE Configuration bit and leave the pin

open to use the internal weak pull-up. The addition of

other components, to help increase the application’s

resistance to spurious Resets from voltage sags, may

be beneficial. A typical configuration is shown in

Figure 2-1. Other circuit designs may be implemented,

depending on the application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must be

considered. Device programmers and debuggers drive

the MCLR pin. Consequently, specific voltage levels

(VIH and VIL) and fast signal transitions must not be

adversely affected. Therefore, the programmer

MCLR/VPP output should be connected directly to the

pin so that R1 isolates the capacitor, C1 from the MCLR

pin during programming and debugging operations.

Any components associated with the MCLR pin should

be placed within 0.25 inch (6 mm) of the pin.

2.4 ICSP™ Pins

The ICSPCLK and ICSPDAT pins are used for

In-Circuit Serial Programming™ (ICSP™) and

debugging purposes. It is recommended to keep the

trace length between the ICSP connector and the ICSP

pins on the device as short as possible. If the ICSP

connector is expected to experience an ESD event, a

series resistor is recommended, with the value in the

range of a few tens of ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

ICSPCLK and ICSPDAT pins are not recommended as

they will interfere with the programmer/debugger

communications to the device. If such discrete

components are an application requirement, they

should be isolated from the programmer by resistors

between the application and the device pins or

removed from the circuit during programming.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits, and pin input voltage high

(VIH) and input low (VIL) requirements.

For device emulation, ensure that the “Communication

Channel Select” (i.e., ICSPCLK/ICSPDAT pins),

programmed into the device, matches the physical

connections for the ICSP to the Microchip debugger/

emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 37.0 “Development Support”.

PIC16(L)F18313/18323

DS40001799C-page 18  2015-2017 Microchip Technology Inc.

2.5 External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency secondary oscillator (refer to

Section 7.0 “Oscillator Module” for details).

The oscillator circuit should be placed on the same side

of the board as the device. Place the oscillator circuit

close to the respective oscillator pins with no more than

0.5 inch (12 mm) between the circuit components and

the pins. The load capacitors should be placed next to

the oscillator itself, on the same side of the board.

Use a grounded copper pour around the oscillator

circuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

Layout suggestions are shown in Figure 2-2. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to

completely surround the pins and components. A

suitable solution is to tie the broken guard sections to a

mirrored ground layer. In all cases, the guard trace(s)

must be returned to ground.

In planning the application’s routing and I/O

assignments, ensure that adjacent port pins, and other

signals in close proximity to the oscillator, are benign

(i.e., free of high frequencies, short rise and fall times,

and other similar noise).

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate website

(www.microchip.com):

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro® Devices”

• AN849, “Basic PICmicro® Oscillator Design”

• AN943, “Practical PICmicro® Oscillator Analysis

and Design”

• AN949, “Ma ki ng Your Oscillator Work ”

2.6 Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output logic low.

FIGURE 2-2: SUGGESTED

PLACEMENT OF THE

OSCILLATOR CIRCUIT

GND

OSC1

OSC2

SOSCO

SOSCI

Copper Pour Primary Oscillator

Crystal

Secondary Oscillator

Crystal

DEVICE PINS

Primary

Oscillator

SOSC: C1 SOSC: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

DEVICE PINS

(tied to ground)

(SOSC)

 2015-2017 Microchip Technology Inc. DS40001799C-page 19

PIC16(L)F18313/18323

3.0 ENHANCED MID-RANGE CPU

This family of devices contains an enhanced mid-range

8-bit CPU core. The CPU has 48 instructions. Interrupt

capability includes automatic context saving.

The hardware stack is 16-levels deep and has

Overflow and Underflow Reset capability. Direct,

Indirect, and Relative addressing modes are available.

Two File Select Registers (FSRs) provide the ability to

read program and data memory.

FIGURE 3-1: CORE DATA PATH BLOCK DIAGRAM

Rev. 10-000055B

8/23/2016

Program Counter

MUX

Addr MUX

16-Level Stack

(15-bit)

Program Memory

Read (PMR)

Instruction Reg

Configuration

FSR0 Reg

FSR1 Reg

BSR Reg

STATUS Reg

RAM

W Reg

Power-up

Timer

Power-on

Reset

Wat chdog

Timer

Brown-out

Reset

Instruction

Decode and

Control

Timing

Generation

Internal

Oscillator

Block

ALU

Flash

Program

Memory

MUX

Data Bus

Program

Bus

Direct Addr

Indirect

Addr

RAM Addr

OSC1/CLKIN

OSC2/CLKOUT

VDD VSS

SOSCI

SOSCO

PIC16(L)F18313/18323

DS40001799C-page 20  2015-2017 Microchip Technology Inc.

3.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 8.5 “Automatic Context Saving”

for more information.

3.2 16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or

Underflow will set the appropriate bit (STKOVF or

STKUNF) in the PCON0 register, and if enabled, will

cause a software Reset. See Section 4.4 “Stack” for

more details.

3.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers, program memory, and data

EEPROM, which allows one Data Pointer for all

memory. When an FSR points to program memory,

there is one additional instruction cycle in instructions

using INDF to allow the data to be fetched. General

purpose memory can now also be addressed linearly,

providing the ability to access contiguous data larger

than 80 bytes. See Section 4.5 “Indirect

Addressing” for more details.

3.4 Instruction Set

There are 48 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 34.0 “Instruction Set Summary” for more

details.

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PIC16(L)F18313/18323

4.0 MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

- Revision ID

-User ID

- Program Flash Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

• Data EEPROM

4.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing 32K x 14 program

memory space. Table 4-1 shows the memory sizes

implemented. Accessing a location above these

boundaries will cause a wrap-around within the

implemented memory space. The Reset vector is at

0000h and the interrupt vector is at 0004h (see

Figure 4-1).

TABLE 4-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Size (Words) Last Program Memory Address

PIC16(L)F18313/18323 2048 07FFh

PIC16(L)F18313/18323

DS40001799C-page 22  2015-2017 Microchip Technology Inc.

FIGURE 4-1: PROGRAM MEMORY MAP

AND ST ACK FOR

PIC16(L)F18313/18323

4.1.1 READING PROGRAM MEMORY AS

DATA

There are three methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory. The third method

is to use the NVMCON registers to access the program

memory.

4.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 4-1.

EXAMPL E 4-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very

simple to implement. If your code must remain portable

with previous generations of microcontrollers,

computed GOTO method must be used because the

BRW instruction is not available in some devices, such

as the PIC16F6XX, PIC16F7XX, PIC16F8XX, and

PIC16F9XX devices.

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory Page 0-3

07FFh

Wraps to Page 0

0800h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

Rollover to Page 0

Rollover to Page 0 7FFFh

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

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PIC16(L)F18313/18323

4.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by

setting bit 7 of an FSRxH register and reading the

matching INDFx register. The MOVIW instruction will

place the lower eight bits of the addressed word in the

W register. Writes to the program memory cannot be

performed via the INDF registers. Instructions that read

the program memory via the FSR require one extra

instruction cycle to complete. Example 4-2

demonstrates reading the program memory via an

FSR.

The HIGH directive will set bit 7 if a label points to a

location in the program memory.

EXAMPLE 4-2: ACCESSING PROGRAM

MEMORY VIA FSR

4.1.1.3 NVMREG Access

The NVMREG interface allows read/write access to all

locations accessible by the FSRs, User ID locations,

and EEPROM. The NVMREG interface also provides

read-only access to Device ID, Revision ID, and

Configuration data. See Section 11.4 “NVMREG

Access” for more information.

4.2 Data Memory Organization

The data memory is partitioned into 32 memory banks

with 128 bytes in each bank. Each bank consists of

(Figure 4-2):

• 12 core registers

• Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

4.2.1 BANK SELECTION

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 4.5 “Indirect

Addressing”” for more information.

Data memory uses a 12-bit address. The upper five bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

FIGURE 4-2: BANKED MEMORY

PARTITIONING

4.2.2 CORE REGISTERS

The core registers contain the registers that directly

affect basic operation. The core registers occupy the

first 12 addresses of every data memory bank

(addresses x00h/x80h through x0Bh/x8Bh). These

registers are listed below in Tabl e 4 -2. For detailed

information, see Tab le 4-4 .

TABLE 4-2: CORE REGISTERS

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

Memory Region

7-bit Bank Offset

Addresses BANKx

x00h or x80h INDF0

x01h or x81h INDF1

x02h or x82h PCL

x03h or x83h STATUS

x04h or x84h FSR0L

x05h or x85h FSR0H

x06h or x86h FSR1L

x07h or x87h FSR1H

x08h or x88h BSR

x09h or x89h WREG

x0Ah or x8Ah PCLATH

x0Bh or x8Bh INTCON

PIC16(L)F18313/18323

DS40001799C-page 24  2015-2017 Microchip Technology Inc.

4.2.2.1 STATUS Register

The STATUS register, shown in Register 4-1, contains:

• The arithmetic status of the ALU

• The Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 34.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT Time-out occurred

bit 3 PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2015-2017 Microchip Technology Inc. DS40001799C-page 25

PIC16(L)F18313/18323

4.2.3 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes after the core registers of

every data memory bank (addresses x0Ch/x8Ch

through x1Fh/x9Fh), with the exception of banks 27, 28,

and 29 (PPS and CLC registers). The registers

associated with the operation of the peripherals are

described in the appropriate peripheral chapter of this

data sheet.

4.2.4 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank. The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 4.5.2

“Linear Data Memory” for more information.

4.2.5 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

4.2.6 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F18313/18323 are as

shown in Table 4-4.

TABLE 4-3: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (ALL BANKS)

Bank

Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on all

other

Resets

All Banks

000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx

001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register) xxxx xxxx xxxx xxxx

002h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

003h STATUS — — —TOPD ZDCC---1 1000 ---q quuu

004h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

005h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

006h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

007h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

008h BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

009h WREG Working Register 0000 0000 uuuu uuuu

00Ah PCLATH —————Write Buffer for the upper three bits

of the Program Counter

---- -000 ---- -000

00Bh INTCON GIE PEIE —————INTEDG00-- ---1 00-- ---1

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimple-

mented, read as ‘0’.

Note 1: These Registers can be accessed from any bank

 2015-2017 Microchip Technology Inc. DS40001799C-page 26

PIC16(L)F18313/18323

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Bank 0

CPU CORE REGISTERS; see Table 4-2 for specifics

00Ch PORTA ― ― RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

00Dh ― ― Unimplemented ― ―

00Eh PORTC X ―Unimplemented ――

―X― ― RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

00Fh ― ― Unimplemented ― ―

010h PIR0 ― ― TMR0IF IOCIF ― ― ― INTF --00 ---0 --00 ---0

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 0000 0000 0000 0000

012h PIR2 X ― ― ― C1IF NVMIF ― ― ― NCO1IF 0000 0000 0000 0000

―X―C2IF C1IF NVMIF ― ― ― NCO1IF 0000 0000 0000 0000

013h PIR3 OSFIF CSWIF ― ― ― ― CLC2IF CLC1IF 0000 0000 0000 0000

014h PIR4 ―CWG1IF ― ― ― ― CCP2IF CCP1IF 0000 0000 0000 0000

015h TMR0L TMR0<7:0> 0000 0000 0000 0000

016h TMR0H TMR0<15:8> 1111 1111 1111 1111

017h T0CON0 T0EN ―T0OUT T016BIT T0OUTPS<3:0> 0-00 0000 0-00 0000

018h T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 0000 0000 0000 0000

019h TMR1L TMR1L<7:0> xxxx xxxx uuuu uuuu

01Ah TMR1H TMR1H<7:0> xxxx xxxx uuuu uuuu

01Bh T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSC T1SYNC ―TMR1ON 0000 00-0 uuuu uu-u

01Ch T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu

01Dh TMR2 TMR2<7:0> 0000 0000 0000 0000

01Eh PR2 PR2<7:0> 1111 1111 1111 1111

01Fh T2CON ―T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 27  2015-2017 Microchip Technology Inc.

Bank 1

CPU CORE REGISTERS; see Table 4-2 for specifics

08Ch TRISA ― ― TRISA5 TRISA4 ―TRISA2 TRISA1 TRISA0 --11 -111 --11 -111

08Dh ― ― Unimplemented ― ―

08Eh TRISC X ―Unimplemented ― ―

―X― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

08Fh ― ― Unimplemented ― ―

090h PIE0 ― ― TMR0IE IOCIE ― ― ― INTE --00 ---0 --00 ---0

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 0000 0000 0000 0000

092h PIE2 X ― ― ― C1IE NVMIE ― ― ― NCO1IE 0000 0000 0000 0000

―X―C2IE C1IE NVMIE ― ― ― NCO1IE 0000 0000 0000 0000

093h PIE3 OSFIE CSWIE ― ― ― ― CLC2IE CLC1IE 0000 0000 0000 0000

094h PIE4 ―CWG1IE ― ― ― ― CCP2IE CCP1IE 0000 0000 0000 0000

095h ― ― Unimplemented ― ―

096h ― ― Unimplemented ― ―

097h WDTCON ― ― WDTPS<4:0> SWDTEN --01 0110 --01 0110

098h ― ― Unimplemented ― ―

099h ― ― Unimplemented ― ―

09Ah ― ― Unimplemented ― ―

09Bh ADRESL ADRESL<7:0> xxxx xxxx uuuu uuuu

09Ch ADRESH ADRESH<7:0> xxxx xxxx uuuu uuuu

09Dh ADCON0 CHS<5:0> GO/DONE ADON 0000 0000 0000 0000

09Eh ADCON1 ADFM ADCS<2:0> ―ADNREF ADPREF<1:0> 0000 -000 0000 -000

09Fh ADACT ― ― ― ― ADACT<3:0> ---- 0000 ---- 0000

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 28

PIC16(L)F18313/18323

Bank 2

CPU CORE REGISTERS; see Table 4-2 for specifics

10Ch LATA ― ― LATA5 LATA4 ―LATA2 LATA1 LATA0 --xx -xxx --uu -uuu

10Dh ― ― Unimplemented ― ―

10Eh LATC X ―Unimplemented ― ―

―X― ― LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu

10Fh ― ― Unimplemented ― ―

110h ― ― Unimplemented ― ―

111h CM1CON0 C1ON C1OUT ―C1POL ―C1SP C1HYS C1SYNC 00-0 -100 00-0 -100

112h CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> 0000 0000 0000 0000

113h CM2CON0 X ―Unimplemented ― ―

―X C2ON C2OUT ―C2POL ―C2SP C2HYS C2SYNC 00-0 -100 00-0 -100

114h CM2CON1 X ―Unimplemented ― ―

―X C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> 0000 0000 0000 0000

115h CMOUT X ― ― ― ― ― ― ― ― MC1OUT ---- ---0 ---- ---0

―X― ― ― ― ― ― MC2OUT MC1OUT ---- --00 ---- --00

116h BORCON SBOREN Reserved ― ― ― ― ― BORRDY 1--- ---q u--- ---u

117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000

118h DACCON0 DAC1EN ―DAC1OE ―DAC1PSS<1:0> ―DAC1NSS 0-0- 00-0 0-0- 00-0

119h DACCON1 ― ― ― DAC1R<4:0> ---0 0000 ---0 0000

11Ah-11Fh ― ― Unimplemented ― ―

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 29  2015-2017 Microchip Technology Inc.

Bank 3

CPU CORE REGISTERS; see Table 4-2 for specifics

18Ch ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 --11 -111 --11 -111

18Dh ― ― Unimplemented ― ―

18Eh ANSELC X ―Unimplemented ― ―

―X― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 --11 1111 --11 1111

18Fh ― ― Unimplemented ― ―

190h ― ― Unimplemented ― ―

191h ― ― Unimplemented ― ―

192h ― ― Unimplemented ― ―

193h ― ― Unimplemented ― ―

194h ― ― Unimplemented ― ―

195h ― ― Unimplemented ― ―

196h ― ― Unimplemented ― ―

197h VREGCON(1) ― ― ― ― ― ― VREGPM Reserved ---- --01 ---- --01

198h ― ― Unimplemented ― ―

199h RC1REG RC1REG<7:0> 0000 0000 0000 0000

19Ah TX1REG TX1REG<7:0> 0000 0000 0000 0000

19Bh SP1BRGL SP1BRG<7:0> 0000 0000 0000 0000

19Ch SP1BRGH SP1BRG<15:8> 0000 0000 0000 0000

19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

19Fh BAUD1CON ABDOVF RCIDL ―SCKP BRG16 ―WUE ABDEN 01-0 0-00 01-0 0-00

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 30

PIC16(L)F18313/18323

Bank 4

CPU CORE REGISTERS; see Table 4-2 for specifics

20Ch WPUA ― ― WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000

20Dh ― ― Unimplemented ― ―

20Eh WPUC X ―Unimplemented ― ―

―X― ― WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --00 0000 --00 0000

20Fh ― ― Unimplemented ― ―

210h ― ― Unimplemented ― ―

211h SSP1BUF SSP1BUF<7:0> xxxx xxxx uuuu uuuu

212h SSP1ADD SSP1ADD<7:0> 0000 0000 0000 0000

213h SSP1MSK SSP1MSK<7:0> 1111 1111 1111 1111

214h SSP1STAT SMP CKE D/A PS R/WUA BF 0000 0000 0000 0000

215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000

216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000

217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000

218h-21Fh ― ― Unimplemented ― ―

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 31  2015-2017 Microchip Technology Inc.

Bank 5

CPU CORE REGISTERS; see Table 4-2 for specifics

28Ch ODCONA ― ― ODCA5 ODCA4 ―ODCA2 ODCA1 ODCA0 --00 -000 --00 -000

28Dh ― ― Unimplemented ― ―

28Eh ODCONC X ―Unimplemented ― ―

―X― ― ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 --00 0000 --00 0000

28Fh ― ― Unimplemented ― ―

290h ― ― Unimplemented ― ―

291h CCPR1L CCPR1<7:0> xxxx xxxx xxxx xxxx

292h CCPR1H CCPR1<15:8> xxxx xxxx xxxx xxxx

293h CCP1CON CCP1EN ―CCP1OUT CCP1FMT CCP1MODE<3:0> 0-x0 0000 0-x0 0000

294h CCP1CAP ― ― ― ― ― CCP1CTS<2:0> ---- 0000 ---- xxxx

295h CCPR2L CCPR2<7:0> xxxx xxxx xxxx xxxx

296h CCPR2H CCPR2<15:8> xxxx xxxx xxxx xxxx

297h CCP2CON CCP2EN ―CCP2OUT CCP2FMT CCP2MODE<3:0> 0-x0 0000 0-x0 0000

298h CCP2CAP ― ― ― ― ― CCP2CTS<2:0> ---- -000 ---- -xxx

299h ― ― Unimplemented ― ―

29Ah ― ― Unimplemented ― ―

29Bh ― ― Unimplemented ― ―

29Ch ― ― Unimplemented ― ―

29Dh ― ― Unimplemented ― ―

29Eh ― ― Unimplemented ― ―

29Fh ― ― Unimplemented ― ―

Bank 6

30Ch SLRCONA —— SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --11 -111 --11 -111

30Dh — — Unimplemented — —

30Eh SLRCONC X —Unimplemented — —

—X —— SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 --11 1111 --11 1111

30Fh-31Fh — — Unimplemented — —

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 32

PIC16(L)F18313/18323

Bank 7

CPU CORE REGISTERS; see Table 4-2 for specifics

38Ch INLVLA ― ― INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111

38Dh ― ― Unimplemented ― ―

38Eh INLVLC X ―Unimplemented ― ―

―X― ― INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 --11 1111 --11 1111

38Fh ― ― Unimplemented ― ―

390h ― ― Unimplemented ― ―

391h IOCAP ― ― IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000

392h IOCAN ― ― IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000

393h IOCAF ― ― IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000

394h ― ― Unimplemented ― ―

395h ― ― Unimplemented ― ―

396h ― ― Unimplemented ― ―

397h IOCCP X ―Unimplemented ― ―

―X― ― IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 --00 0000 --00 0000

398h IOCCN X ―Unimplemented ― ―

―X― ― IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 --00 0000 --00 0000

399h IOCCF X ―Unimplemented ― ―

―X― ― IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 --00 0000 --00 0000

39Ah CLKRCON CLKREN ― ― CLKRDC<1:0> CLKRDIV<2:0> 0--1 0000 0--1 0000

39Bh ― ― Unimplemented ― ―

39Ch MDCON MDEN ― ― MDOPOL MDOUT ― ― MDBIT 0--0 0--0 0--0 0--0

39Dh MDSRC ― ― ― ― MDMS<3:0> ---- xxxx ---- uuuu

39Eh MDCARH ―MDCHPOL MDCHSYNC ―MDCH<3:0> -xx- xxxx -uu- uuuu

39Fh MDCARL ―MDCLPOL MDCLSYNC ―MDCL<3:0> -xx- xxxx -uu- uuuu

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 33  2015-2017 Microchip Technology Inc.

Bank 8

CPU CORE REGISTERS; see Table 4-2 for specifics

40Ch-41Fh — — Unimplemented — —

Bank 9

48Ch-497h — — Unimplemented — —

498h NCO1ACCL NCO1ACC<7:0> 0000 0000 0000 0000

499h NCO1ACCH NCO1ACC<15:8> 0000 0000 0000 0000

49Ah NCO1ACCU ― ― ― ― NCO1ACC<19:16> ---- 0000 ---- 0000

49Bh NCO1INCL NCO1INC<7:0> 0000 0001 0000 0001

49Ch NCO1INCH NCO1INC<15:8> 0000 0000 0000 0000

49Dh NCO1INCU ― ― ― ― NCO1INC<19:16> ---- 0000 ---- 0000

49Eh NCO1CON N1EN ―N1OUT N1POL ― ― ― N1PFM 0-00 ---0 0-00 ---0

49Fh NCO1CLK N1PWS<2:0> ― ― ― N1CKS<1:0> 000- --00 000- --00

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 34

PIC16(L)F18313/18323

Bank 10-11

CPU CORE REGISTERS; see Table 4-2 for specifics

50Ch-51Fh — — Unimplemented — —

58Ch-59Fh — — Unimplemented — —

Bank 12

60Ch ― ― Unimplemented ― ―

60Dh ― ― Unimplemented ― ―

60Eh ― ― Unimplemented ― ―

60Fh ― ― Unimplemented ― ―

610h ― ― Unimplemented ― ―

611h ― ― Unimplemented ― ―

612h ― ― Unimplemented ― ―

613h ― ― Unimplemented ― ―

614h ― ― Unimplemented ― ―

615h ― ― Unimplemented ― ―

616h ― ― Unimplemented ― ―

617h PWM5DCL PWM5DC<1:0> ― ― ― ― ― ― xx-- ---- uu-- ----

618h PWM5DCH PWM5DC<9:2> xxxx xxxx uuuu uuuu

619h PWM5CON PWM5EN ―PWM5OUT PWM5POL ― ― ― ― 0-00 ---- 0-00 ----

61Ah PWM6DCL PWM6DC<1:0> ― ― ― ― ― ― xx-- ---- uu-- ----

61Bh PWM6DCH PWM6DC<9:2> xxxx xxxx uuuu uuuu

61Ch PWM6CON PWM6EN ―PWM6OUT PWM6POL ― ― ― ― 0-00 ---- 0-00 ----

61Dh-61Fh ― ― Unimplemented ― ―

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 35  2015-2017 Microchip Technology Inc.

Bank 13

CPU CORE REGISTERS; see Table 4-2 for specifics

68Ch ― ― Unimplemented ― ―

68Dh ― ― Unimplemented ― ―

68Eh ― ― Unimplemented ― ―

68Fh ― ― Unimplemented ― ―

690h ― ― Unimplemented ― ―

691h CWG1CLKCON ― ― ― ― ― ― ― CS ---- ---0 ---- ---0

692h CWG1DAT ― ― ― ― DAT<3:0> ---- 0000 ---- 0000

693h CWG1DBR ― ― DBR<5:0> --00 0000 --00 0000

694h CWG1DBF ― ― DBF<5:0> --00 0000 --00 0000

695h CWG1CON0 EN LD ――― MODE<2:0> 00-- -000 00-- -000

696h CWG1CON1 ― ― IN ―POLD POLC POLB POLA --x- 0000 --x- 0000

697h CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> ― ― 0001 01-- 0001 01--

698h CWG1AS1 ― ― ― ― AS3E AS2E(1) AS1E AS0E ---0 0000 ---0 0000

699h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000

69Ah-69Fh ― ― Unimplemented ― ―

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 36

PIC16(L)F18313/18323

Banks 14-16

CPU CORE REGISTERS; see Table 4-2 for specifics

70Ch-71Fh — — Unimplemented — —

78Ch-79Fh — — Unimplemented — —

80Ch-81Fh — — Unimplemented — —

Bank 17

88Ch ― ― Unimplemented ― ―

88Dh ― ― Unimplemented ― ―

88Eh ― ― Unimplemented ― ―

88Fh ― ― Unimplemented ― ―

890h ― ― Unimplemented ― ―

891h NVMADRL NVMADR<7:0> 0000 0000 0000 0000

892h NVMADRH ―NVMADR<14:8> 1000 0000 1000 0000

893h NVMDATL NVMDAT<7:0> 0000 0000 0000 0000

894h NVMDATH ― ― NVMDAT<13:8> --00 0000 --00 0000

895h NVMCON1 ―NVMREGS LWLO FREE WRERR WREN WR RD -000 x000 -000 q000

896h NVMCON2 NVMCON2<7:0> 0000 0000 0000 0000

897h ― ― Unimplemented ― ―

898h ― ― Unimplemented ― ―

899h ― ― Unimplemented ― ―

89Ah ― ― Unimplemented ― ―

89Bh PCON0 STKOVF STKUNF ―RWDT RMCLR RI POR BOR 00-1 110q qq-q qquu

89Ch-89Fh ― ― Unimplemented ― ―

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 37  2015-2017 Microchip Technology Inc.

Bank 18

CPU CORE REGISTERS; see Table 4-2 for specifics

90Ch ― ― Unimplemented ― ―

90Dh ― ― Unimplemented ― ―

90Eh ― ― Unimplemented ― ―

90Fh ― ― Unimplemented ― ―

910h ― ― Unimplemented ― ―

911h PMD0 SYSCMD FVRMD ―――NVMMD CLKRMD IOCMD 00-- -000 00-- -000

912h PMD1 NCOMD ― ― ― ― TMR2MD TMR1MD TMR0MD 0--- -000 0--- -000

913h PMD2 X ― ― DACMD ADCMD ― ― ― CMP1MD ―-00- --0- -00- --0-

―X―DACMD ADCMD ― ― CMP2MD CMP1MD ―-00- -00- -00- -00-

914h PMD3 ―CWG1MD PWM6MD PWM5MD ― ― CCP2MD CCP1MD -000 --00 -000 --00

915h PMD4 ― ― UART1MD ― ― ― MSSP1MD ―--0- --0- --0- --0-

916h PMD5 ― ― ― ― ― CLC2MD CLC1MD DSMMD ---- -000 ---- -000

917h ― ― Unimplemented ― ―

918h CPUDOZE IDLEN DOZEN ROI DOE ―DOZE<2:0> 000- -000 000- -000

919h OSCCON1 ―NOSC<2:0> NDIV<3:0> -qqq 0000 -qqq 0000

91Ah OSCCON2 ―COSC<2:0> CDIV<3:0> -qqq 0000 -qqq 0000

91Bh OSCCON3 CSWHOLD SOSCPWR SOSCBE ORDY NOSCR ― ― ― 0000 0--- 0000 0---

91Ch OSCSTAT1 EXTOR HFOR ―LFOR SOR ADOR ―PLLR qq-q qq-q qq-q qq-q

91Dh OSCEN EXTOEN HFOEN ―LFOEN SOSCEN ADOEN ― ― 00-0 00-- 00-0 00--

91Eh OSCTUNE ― ― HFTUN<5:0> --10 0000 --10 0000

91Fh OSCFRQ ― ― ― ― HFFRQ<3:0> ---- 0110 ---- 0110

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 38

PIC16(L)F18313/18323

Banks 19-27

CPU CORE REGISTERS; see Table 4-2 for specifics

98Ch-9EFh — — Unimplemented — —

A0Ch-A6Fh — — Unimplemented — —

A8Ch-AEFh — — Unimplemented — —

B0Ch-B6Fh — — Unimplemented — —

B8Ch-BEFh — — Unimplemented — —

C0Ch-C1Fh — — Unimplemented — —

C8Ch-CEFh — — Unimplemented — —

D0Ch-D6Fh — — Unimplemented — —

D8Ch-D6Fh — — Unimplemented — —

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 39  2015-2017 Microchip Technology Inc.

Banks 28

CPU CORE REGISTERS; see Table 4-2 for specifics

E0Ch — — Unimplemented — —

E0Dh — — Unimplemented — —

E0Eh — — Unimplemented — —

E0Fh PPSLOCK — — — — — — — PPSLOCKED ---- ---0 ---- ---0

E10h INTPPS — — — INTPPS<4:0> ---0 0010 ---u uuuu

E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0010 ---u uuuu

E12h T1CKIPPS — — — T1CKIPPS<4:0> ---0 0101 ---u uuuu

E13h T1GPPS — — — T1GPPS<4:0> ---0 0100 ---u uuuu

E14h CCP1PPS X— — — — CCP1PPS<4:0> ---0 0101 ---u uuuu

—X — — — CCP1PPS<4:0> ---1 0101 ---u uuuu

E15h CCP2PPS X— — — — CCP2PPS<4:0> ---0 0101 ---u uuuu

—X — — — CCP2PPS<4:0> ---1 0011 ---u uuuu

E16h — — Unimplemented — —

E17h — — Unimplemented — —

E18h CWG1PPS — — — CWG1PPS<4:0> ---0 0010 ---u uuuu

E19h — — Unimplemented — —

E1Ah MDCIN1PPS X— — — — MDCIN1PPS<4:0> ---0 0000 ---u uuuu

—X — — — MDCIN1PPS<4:0> ---1 0010 ---u uuuu

E1Bh MDCIN2PPS X— — — — MDCIN2PPS<4:0> ---0 0101 ---u uuuu

—X — — — MDCIN2PPS<4:0> ---1 0101 ---u uuuu

E1Ch MDMINPPS X— — — — MDMINPPS<4:0> ---0 0001 ---u uuuu

—X — — — MDMINPPS<4:0> ---1 0011 ---u uuuu

E1Dh — — Unimplemented — —

E1Eh — — Unimplemented — —

E1Fh — — Unimplemented — —

E20h SSP1CLKPPS X—— — — SSP1CLKPPS<4:0> ---0 0001 ---u uuuu

—X — — — SSP1CLKPPS<4:0> ---1 0000 ---u uuuu

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 40

PIC16(L)F18313/18323

E21h SSP1DATPPS X — — — — SSP1DATPPS<4:0> ---0 0010 ---u uuuu

—X — — — SSP1DATPPS<4:0> ---1 0001 ---u uuuu

E22h SSP1SSPPS X— — — — SSP1SSPPS<4:0> ---0 0011 ---u uuuu

—X — — — SSP1SSPPS<4:0> ---1 0011 ---u uuuu

E23h — — Unimplemented — —

E24h RXPPS X— — — — RXPPS<4:0> ---0 0001 ---u uuuu

—X — — — RXPPS<4:0> ---0 0101 ---u uuuu

E25h TXPPS X— — — — TXPPS<4:0> ---0 0000 ---u uuuu

—X — — — TXPPS<4:0> ---1 0100 ---u uuuu

E26h — — Unimplemented — —

E27h — — Unimplemented — —

E28h CLCIN0PPS X— — — — CLCIN0PPS<4:0> ---0 0011 ---u uuuu

—X — — — CLCIN0PPS<4:0> ---1 0011 ---u uuuu

E29h CLCIN1PPS X— — — — CLCIN1PPS<4:0> ---0 0101 ---u uuuu

—X — — — CLCIN1PPS<4:0> ---1 0100 ---u uuuu

E2Ah-E6Fh — — Unimplemented — —

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 41  2015-2017 Microchip Technology Inc.

Bank 29

CPU CORE REGISTERS; see Table 4-2 for specifics

E8Ch-E8Fh — — Unimplemented — —

E90h RA0PPS — — — RA0PPS<4:0> ---0 0000 ---u uuuu

E91h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---u uuuu

E92h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---u uuuu

E93h — — Unimplemented — —

E94h RA4PPS — — — RA4PPS<4:0> ---0 0000 ---u uuuu

E95h RA5PPS — — — RA5PPS<4:0> ---0 0000 ---u uuuu

E96h-E9Fh — — Unimplemented ---0 0000 ---u uuuu

EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---u uuuu

EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---u uuuu

EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---u uuuu

EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---u uuuu

EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---u uuuu

EA5h RC5PPS — — — RC5PPS<4:0> ---0 0000 ---u uuuu

E97h — — Unimplemented ---0 0000 ---u uuuu

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

 2015-2017 Microchip Technology Inc. DS40001799C-page 42

PIC16(L)F18313/18323

Bank 30

CPU CORE REGISTERS; see Table 4-2 for specifics

F0Ch — — Unimplemented — —

F0Dh — — Unimplemented — —

F0Eh — — Unimplemented — —

F0Fh CLCDATA — — — — — — MLC2OUT MLC1OUT ---- --00 ---- --00

F10h CLC1CON LC1EN — LC1OUT LC1INPT LC1INTN LC1MODE<2:0> 0-00 0000 0-00 0000

F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu

F12h CLC1SEL0 — — — LC1D1S<4:0> ---x xxxx ---u uuuu

F13h CLC1SEL1 — — — LC1D2S<4:0> ---x xxxx ---u uuuu

F14h CLC1SEL2 — — — LC1D3S<4:0> ---x xxxx ---u uuuu

F15h CLC1SEL3 — — — LC1D4S<4:0> ---x xxxx ---u uuuu

F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu

F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu

F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu

F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu

F1Ah CLC2CON LC2EN — LC2OUT LC2INPT LC2INTN LC2MODE<2:0> 0-00 0000 0-00 0000

F1Bh CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu

F1Ch CLC2SEL0 — — — LC2D1S<4:0> ---x xxxx ---u uuuu

F1Dh CLC2SEL1 — — — LC2D2S<4:0> ---x xxxx ---u uuuu

F1Eh CLC2SEL2 — — — LC2D3S<4:0> ---x xxxx ---u uuuu

F1Fh CLC2SEL3 — — — LC2D4S<4:0> ---x xxxx ---u uuuu

F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu

F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu

F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu

F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 43  2015-2017 Microchip Technology Inc.

Bank 31 — only accessible from Debug Executive, unless otherwise specified

CPU CORE REGISTERS; see Table 4-2 for specifics

F8Ch-FE3h — — Unimplemented — —

FE4h(2) STATUS_SHAD — — — — —ZDCC---- -xxx ---- -uuu

FE5h(2) WREG_SHAD Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FE6h(2) BSR_SHAD — — — Bank Select Register Normal (Non-ICD) Shadow ---x -xxx ---- -uuu

FE7h(2) PCLATH_SHAD — Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx -uuu uuuu

FE8h(2) FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FE9h(2) FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FEAh(2) FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FEBh(2) FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu

FECh — — Unimplemented — —

FEDh(2) STKPTR — — — Current Stack Pointer ---x xxxx ---1 1111

FEEh(2) TOSL Top of Stack Low Byte xxxx xxxx xxxx xxxx

FEFh(2) TOSH — Top of Stack Low Byte xxxx xxxx xxxx xxxx

TABLE 4-4: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)

Address Name

PIC16(L)F18313

PIC16(L)F18323

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Value on all

other Resets

Legend: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.

Note 1: Only on PIC16F18313/18323.

PIC16(L)F18313/18323

DS40001799C-page 44  2015-2017 Microchip Technology Inc.

4.3 PCL and PCLATH

The Program Counter (PC) is 15-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 4-3 shows the five

situations for the loading of the PC.

FIGURE 4-3: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper seven bits to the PCLATH

PCL register, all 15 bits of the program counter will

change to the values contained in the PCLATH register

and those being written to the PCL register.

4.3.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTO method, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

4.3.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The CALLW instruction enables computed calls by

combining PCLATH and W to form the destination

address. A computed CALLW is accomplished by

loading the W register with the desired address and

executing CALLW. The PCL register is loaded with the

value of W and PCH is loaded with PCLATH.

4.3.4 BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

If using BRA, the signed 9-bit literal value ('k') of the

operand of the BRA instruction is added to the PC.

Since the PC will have incremented to fetch the next

instruction, the new address will be PC + 1 + k.

PCL

PCH 0

PCL

PCH 0

ALU Result

PCLATH

Instruction with

PCL as

Destination

GOTO, CALL

OPCODE <10:0>

PCLATH

PCL

PCH 0

PCLATH

CALLW

PCL

PCH 0

PC + W

BRW

PCLPCH 0

PC + OPCODE <8:0>

BRA

 2015-2017 Microchip Technology Inc. DS40001799C-page 45

PIC16(L)F18313/18323

4.4 Stack

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figure 4-4 through Figure 4-7). The

stack space is not part of either program or data space.

The PC is PUSHed onto the stack when CALL or

CALLW instructions are executed or an interrupt causes

a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer and does not

cause a Reset when either a Stack Overflow or

Underflow occur if the STVREN bit is programmed to

‘0‘ (Configuration Words). This means that after the

stack has been PUSHed sixteen times, the

seventeenth PUSH overwrites the value that was

stored from the first PUSH. The eighteenth PUSH

overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an

Overflow/Underflow, regardless of whether the Reset is

enabled.

If the STVREN bit in Configuration Words is

programmed to ‘1’, the device will be Reset if the stack

is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

4.4.1 ACCESSING THE STACK

The stack is accessible through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is five bits to allow detection of

overflow and underflow.

During normal program operation, CALL, CALLW and

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIE will decrement STKPTR. At any

time, STKPTR can be read to see how many levels

remain available on the stack. The STKPTR always

points at the currently used place on the stack.

Therefore, a CALL or CALLW will increment the

STKPTR and then write the PC, and a return will write

the PC and then decrement the STKPTR.

Reference Figure 4-4 through Figure 4-7 for examples

of accessing the stack.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Note: Care should be taken when modifying the

STKPTR while interrupts are enabled.

PIC16(L)F18313/18323

DS40001799C-page 46  2015-2017 Microchip Technology Inc.

FIGURE 4-4: ACCESSING THE STACK EXAMPLE 1

FIGURE 4-5: ACCESSING THE STACK EXAMPLE 2

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x0000

STKPTR = 0x1F

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F - 1. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘0’. If

the Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL registers will

return the contents of stack address 0x0F.

0x1F STKPTR = 0x1F

Stack Reset Disabled

(STVREN = 0)

Stack Reset Enabled

(STVREN = 1)

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x00

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURN instruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

TOSH:TOSL

 2015-2017 Microchip Technology Inc. DS40001799C-page 47

PIC16(L)F18313/18323

FIGURE 4-6: ACCESSING THE STACK EXAMPLE 3

FIGURE 4-7: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

Return Address0x06

Return Address0x05

Return Address0x04

Return Address0x03

Return Address0x02

Return Address0x01

Return Address0x00

STKPTR = 0x06

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure

on the left. A series of RETURN instructions

will repeatedly place the return addresses

into the Program Counter and pop the stack.

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

Return Address0x00 STKPTR = 0x10

When the stack is full, the next CALL or

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

Return Address

TOSH:TOSL

PIC16(L)F18313/18323

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4.5 Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into four memory regions:

• Traditional/Banked Data Memory

• Linear Data Memory

• Program Flash Memory

• EEPROM

4.5.1 TRADITIONAL/BANKED DATA

MEMORY

The banked data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

FIGURE 4-8: INDIRECT ADDRES SING

0x0000

PC value = 0x000

PC value = 0x7FF0x87FF

0x0000

0x1FFF

0x2000

0X2FEF

0X2FF0

0x7FFF

0x8000

Reserved

Traditional

Data Memory

Linear

Data Memory

Program

Flash Memory

FSR

Address

Range

Rev. 10-000044F

1/13/2017

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PIC16(L)F18313/18323

FIGURE 4-9: TRADITIONAL/BANKED DATA MEMORY MAP

Indirect AddressingDirect Addressing

Bank Select Location Select

4BSR 6 0

From Opcode FSRxL70

Bank Select Location Select

00000 00001 00010 11111

0x00

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

0FSRxH70

0000

PIC16(L)F18313/18323

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4.5.2 LINEAR DATA MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 4-10: LINEAR DATA MEMORY

MAP

4.5.3 PROGRAM FLASH MEMORY

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower eight bits of each memory location is accessible

via INDF. Writing to the program Flash memory cannot

be accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

FIGURE 4-11: PROGRAM FLASH

MEMORY MAP

4.5.4 DATA EEPROM MEMORY

The EEPROM memory can be read or written through

the NVMCON register interface (see Section 11.2

“Data EEPROM”). However, to make access to the

EEPROM easier, read-only access to the EEPROM

contents are also available through indirect addressing

via an FSR. When the MSB of the FSR (ex: FSRxH) is

set to 0x70, the lower 8-bit address value (in FSRxL)

determines the EEPROM location that may be read

(via the INDF register).

In other words, the EEPROM address range

0x00-0xFF is mapped into the FSR address space

between 0x7000 and 0x70FF. Writing to the EEPROM

cannot be accomplished via the FSR/INDF interface.

Reads from the EEPROM through the FSR/INDF inter-

face will require one additional instruction cycle to com-

plete.

Location Select 0x2000

FSRnH FSRnL

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0xF20

Bank 30

0xF6F

0x29AF

Location Select 0x8000

FSRnH FSRnL

0x0000

0x7FFF

0xFFFF

Program

Flash

Memory

(low 8

bits)

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PIC16(L)F18313/18323

5.0 DEVICE CONFIGURATION

Device configuration consists of Configuration Words,

Code Protection and Device ID.

5.1 Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h, Configuration Word 2 at 8008h, Configuration

Word 3 at 8009h, and Configuration Word 4 at 800Ah.

Note: The DEBUG bit in Configuration Words is

managed automatically by device

development tools including debuggers

and programmers. For normal device

operation, this bit should be maintained as

a ‘1’.

PIC16(L)F18313/18323

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5.2 Register Definitions: Configuration Words

R/P-1 U-1 R/P-1 U-1 U-1 R/P-1

FCMEN — CSWEN ——CLKOUTEN

bit 13 bit 8

U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1

— RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank

bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = ON FSCM timer enabled

0 = OFF FSCM timer disabled

bit 12 Unimplemented: Read as ‘1’

bit 11 CSWEN: Clock Switch Enable bit

1 = ON Writing to NOSC and NDIV is allowed

0 = OFF The NOSC and NDIV bits cannot be changed by user software

bit 10-9 Unimplemented: Read as ‘1’

bit 8 CLKOUTEN: Clock Out Enable bit

If FEXTOSC = EC, HS, HT or LP, then this bit is ignored; otherwise:

1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2

0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2

bit 7 Unimplemented: Read as ‘1’

bit 6-4 RSTOSC<2:0>: Power-up Default Value for COSC bits

This value is the Reset default value for COSC, and selects the oscillator first used by user software

111 = EXT1X EXTOSC operating per FEXTOSC<2:0> bits

110 = HFINT1 HFINTOSC (1 MHz)

101 = Reserved

100 = LFINT LFINTOSC

011 = SOSC SOSC (32.768 kHz)

010 = Reserved

001 = EXT4X EXTOSC with 4x PLL; EXTOSC operating per FEXTOSC<2:0> bits

000 = HFINT32 HFINTOSC (32 MHz)

bit 3 Unimplemented: Read as ‘1’

bit 2-0 FEXTOSC<2:0>: FEXTOSC External Oscillator Mode Selection bits

111 = ECH EC(External Clock) above 8 MHz

110 = ECM EC(External Clock) for 100 kHz to 8 MHz

101 = ECL EC(External Clock) below 100 kHz

100 = OFF Oscillator not enabled

011 = Unimplemented

010 = HS HS(Crystal oscillator) above 4 MHz

001 = XT HT(Crystal oscillator) above 100 kHz, below 4 MHz

000 = LP LP(Crystal oscillator) optimized for 32.768 kHz

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PIC16(L)F18313/18323

R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1

DEBUG STVREN PPS1WAY —BORV—

bit 13 bit 8

R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1

BOREN1 BOREN0 LPBOREN(3) — WDTE1 WDTE0 PWRTE MCLRE

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank

bit 13 DEBUG: Debugger Enable bit(1)

1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins

0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger

bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = ON Stack Overflow or Underflow will cause a Reset

0 = OFF Stack Overflow or Underflow will not cause a Reset

bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit

1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set

cycle

0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)

bit 10 Unimplemented: Read as ‘1’

bit 9 BORV: Brown-out Reset Voltage Selection bit(2)

1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices

0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V

The higher voltage setting is recommended for operation at or above 16 MHz.

bit 8 Unimplemented: Read as ‘1’

bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits

When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit

11 = ON Brown-out Reset is enabled; SBOREN bit is ignored

10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored

01 = SBOREN Brown-out Reset is enabled according to SBOREN

00 = OFF Brown-out Reset is disabled

bit 5 LPBOREN: Low-Power BOR Enable bit(3)

1 = OFF ULPBOR is disabled

0 = ON ULPBOR is enabled

bit 4 Unimplemented: Read as ‘1’

bit 3-2 WDTE<1:0>: Watchdog Timer Enable bit

11 = ON WDT is enabled; SWDTEN is ignored

10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored

01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register

00 = OFF WDT is disabled; SWDTEN is ignored

bit 1 PWRTE: Power-up Timer Enable bit

1 = OFF PWRT is disabled

0 = ON PWRT is enabled

bit 0 MCLRE: Master Clear (MCLR) Enable bit

If LVP = 1:

RA3 pin function is MCLR.

If LVP = 0:

1 = ON MCLR pin is MCLR.

0 = OFF MCLR pin function is port-defined function.

Note 1: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers

and programmers. For normal device operation, this bit should be maintained as a ‘1’.

2: See VBOR parameter for specific trip point voltages.

3: PIC16LF18313/18323 devices only.

PIC16(L)F18313/18323

DS40001799C-page 54  2015-2017 Microchip Technology Inc.

R/P-1 U-1 U-1 U-1 U-1 U-1

LVP(1) —————

bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1

—————— WRT1 WRT0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase

bit 13 LVP: Low-Voltage Programming Enable bit(1)

1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE

Configuration bit is ignored.

0 = OFF HV on MCLR/VPP must be used for programming.

bit 12-2 Unimplemented: Read as ‘1’

bit 1-0 WRT<1:0>: User NVM Self-Write Protection bits

11 = OFF Write protection off

10 = BOOT 0000h to 01FFh write-protected, 0200h to 07FFh may be modified

01 = HALF 0000h to 03FFh write-protected, 0400h to 07FFh may be modified

00 = ALL 0000h to 07FFh write-protected, no addresses may be modified

WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected.

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

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PIC16(L)F18313/18323

U-1 U-1 U-1 U-1 U-1 U-1

——————

bit 13 bit 8

U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1

——————CPDCP

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase

bit 13-2 Unimplemented: Read as ‘1’

bit 1 CPD: Data EEPROM Memory Code Protection bit

1 = OFF Data EEPROM code protection disabled

0 = ON Data EEPROM code protection enabled

bit 0 CP: Program Memory Code Protection bit

1 = OFF Program Memory code protection disabled

0 = ON Program Memory code protection enabled

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5.3 Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection and

data memory are controlled independently. Internal

access to the program memory is unaffected by any

code protection setting.

5.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Words. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Self-write

writing the program memory is dependent upon the

write protection setting. See Section 5.4 “Write

Protection” for more information.

5.3.2 DATA MEMORY PROTECTION

The entire data EEPROM is protected from external

reads and writes by the CPD bit in the Configuration

Words. When CPD = 0, external reads and writes of

EEPROM memory are inhibited and a read will return

all ‘0’s. The CPU can continue to read and write

EEPROM memory, regardless of the protection bit

settings.

5.4 Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as boot

loader software, can be protected while allowing other

regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Words define the

size of the program memory block that is protected.

5.5 User ID

Four memory locations (8000h-8003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

readable and writable during normal execution. See

Section 1 1.4.7 “NVM REG EEPROM, User ID, Device

ID and Configuration Word Access” for more

information on accessing these memory locations. For

more information on checksum calculation, see the

“PIC16(L)F183XX Memory Programming

Specification” (DS40001738).

5.6 Device ID and Revision ID

The 14-bit device ID word is located at 8006h and the

14-bit revision ID is located at 8005h. These locations

are read-only and cannot be erased or modified. See

Section 1 1.4.7 “NVM REG EEPROM, User ID, Device

ID and Configuration Word Access” for more

information on accessing these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

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PIC16(L)F18313/18323

5.7 Register Definitions: Device and Revision

RRRRRR

DEV<13:8>

bit 13 bit 8

RRRRRRRR

DEV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 DEV<13:0>: Device ID bits

R-1R-0RRRR

REV<13:8>

bit 13 bit 8

RRRRRRRR

REV<7:0>

bit 7 bit 0

Legend:

R = Readable bit

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 13-0 REV<13:0>: Revision ID bits

Note: The upper two bits of the Revision ID Register will always read ‘10’.

Device DEVID<13:0> Values

PIC16F18313 11 0000 0011 0100 (3034h)

PIC16LF18313 11 0000 0011 0110 (3036h)

PIC16F18323 11 0000 0011 0101 (3035h)

PIC16LF18323 11 0000 0011 0111 (3037h)

PIC16(L)F18313/18323

DS40001799C-page 58  2015-2017 Microchip Technology Inc.

6.0 RESETS

There are multiple ways to reset this device:

• Power-On Reset (POR)

• Brown-Out Reset (BOR)

• Low-Power Brown-Out Reset (LPBOR)

•MCLR Reset

•WDT Reset

•RESET instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

or POR event.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 6-1.

FIGURE 6-1: SI MPLIFI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Note 1: See Table 6-1 for BOR active conditions.

Device

Reset

Power-on

Reset

WDT

Time-out

Brown-out

Reset

LPBOR

Reset

RESET Instruction

MCLRE

Sleep

BOR

Active(1)

PWRTE

LFINTOSC

VDD

ICSP™ Programming Mode Exit

Stack Underflow

Stack Overlfow

VPP/MCLR

RPower-up

Timer

Rev. 10-000006A

8/14/2013

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6.1 Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

6.2 Brown-out Reset (BOR)

The BOR circuit holds the device in Reset while VDD is

below a selectable minimum level. Between the POR

and BOR, complete voltage range coverage for execu-

tion protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in

Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Table 6-1 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Words.

A VDD noise rejection filter prevents the BOR from

triggering on small events. If VDD falls below VBOR for

a duration greater than parameter TBORDC, the device

will reset, and the BOR bit of the PCON0 register will

be cleared, indicating that a Brown-out Reset condition

occurred. See Figure 6-2 for more information.

TABLE 6-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode Instruction Exec ution upon:

Release of POR or Wake-up from Sleep

11 X X Active In these specific cases, “Release of POR” and

“Wake-up from Sleep”, there is no delay in start-up.

The BOR ready flag, (BORRDY = 1), will be set

before the CPU is ready to execute instructions

because the BOR circuit is forced on by the

BOREN<1:0> bits.

10 XAwake Active Waits for release of BOR (BORRDY = 1)

Sleep Disabled BOR ignored when asleep

Active In these specific cases, “Release of POR” and

“Wake-up from Sleep”, there is no delay in start-up.

The BOR ready flag, (BORRDY = 1), will be set

before the CPU is ready to execute instructions

because the BOR circuit is forced on by the

BOREN<1:0> bits.

0X Disabled Begins immediately (BORRDY = x)

00 XXDisabled

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6.2.1 BOR IS ALWAYS ON

When the BOREN bits of Configuration Words are

programmed to ‘11’, the BOR is always on. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

6.2.2 BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are

programmed to ‘10’, the BOR is on, except in Sleep.

The device start-up will be delayed until the BOR is

ready and VDD is higher than the BOR threshold.

BOR protection is not active during Sleep, but device

wake-up will be delayed until the BOR can determine

that VDD is higher than the BOR threshold. The device

wake-up will be delayed until the BOR is ready.

6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are

programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device

wake from Sleep is not delayed by the BOR Ready

condition or the VDD level only when the SBOREN bit

is cleared in software and the device is starting up from

a non POR/BOR Reset event.

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

FIGURE 6-2: BROWN-OUT SITUATIONS

6.2.4 BOR ALWAYS OFF

When the BOREN bits of Configuration Word 2 are

programmed to ‘00’, the BOR is always disable. In the

configuration, setting the SWBOREN bit will have no

affect on BOR operation.

TPWRT(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset TPWRT(1)

< TPWRT

TPWRT(1)

VBOR

VDD

Internal

Reset

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

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PIC16(L)F18313/18323

6.3 Low-Power Brown-out Reset

(LPBOR)(PIC16LF18313/18323

Devices Only)

The Low-Power Brown-Out Reset (LPBOR) circuit

provides alternative protection against Brown-out

conditions for the PIC16LF18313/18323 devices only.

When VDD falls below the LPBOR threshold, the device

is held in Reset. When this occurs, the BOR bit of the

PCON0 register is cleared to indicate that a Brown-out

Reset occurred. The BOR bit will be cleared when

either the BOR or the LPBOR circuitry detects a BOR

condition. The LPBOR feature can be used with or

without BOR enabled.

When used while BOR is enabled, the LPBOR can be

used as a secondary protection circuit in case the BOR

circuit fails to detect the BOR condition. Additionally,

when BOR is enabled except while in Sleep

(BOREN<1:0> = 10), the LPBOR circuit will hold the

device in Reset while VDD is lower than the LPBOR

threshold, and will also re-arm the POR. (See

Table 35-11 for LPBOR Reset voltage levels).

When used without BOR enabled, the LPBOR circuit

provides a single Reset trip point with the benefit of

reduced current consumption.

6.3.1 ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the

LPBOR module defaults to disabled.

6.3.1.1 LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

OR’d together with the Reset signal of the BOR

module to provide the generic BOR signal, which goes

to the PCON0 register and to the power control block.

6.4 MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 6-2).

6.4.1 MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

6.4.2 MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 12.2 “PORTA

Registers” for more information.

6.5 Watchdog Time r (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out

period. The TO and PD bits in the STATUS register as

well as the RWDT bit in the PCON0 register, are

changed to indicate the WDT Reset. See Section 10.0

“Watchdog Timer (WDT)” for more information.

6.6 RESET Instruction

A RESET instruction will cause a device Reset. The RI

bit in the PCON0 register will be set to ‘0’. See Tabl e 6-4

for default conditions after a RESET instruction has

occurred.

6.7 Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the

PCON0 register indicate the Reset condition. These

Resets are enabled by setting the STVREN bit in

Configuration Words. See Sec tion 4.4 “S t ack” for more

information.

6.8 Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a device Reset had just occurred.

6.9 Power-up Timer

The Power-up Timer provides a nominal 64 ms

time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Words.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting ” (DS00607).

TABLE 6-2: MCLR CONFIGURATION

MCLRE LVP MCLR

00Disabled

10Enabled

x1Enabled

Note: A Reset does not drive the MCLR pin low.

PIC16(L)F18313/18323

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6.10 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. MCLR must be released (if enabled).

3. Oscillator start-up timer runs to completion (if

required for oscillator source).

The total time-out will vary based on oscillator

configuration and Power-up Timer Configuration. See

Section 7.0 “Oscillator Module” for more

information.

The Power-up Timer and oscillator start-up timer run

independently of MCLR Reset. If MCLR is kept low

long enough, the Power-up Timer will expire. Upon

bringing MCLR high, the device will begin execution

after 10 FOSC cycles (see Figure 6-3). This is useful for

testing purposes or to synchronize more than one

device operating in parallel.

FIGURE 6-3: RESE T START-UP SEQUENCE

TOST

TMCLR

TPWRT

VDD

Internal POR

Power-up Timer

MCLR

Internal RESET

Oscillator Modes

Oscillator Start-up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

External Cryst al

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6.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON0 register are updated to indicate the cause of

the Reset. Tabl e 6-3 and Tab le 6-4 show the Reset

conditions of these registers.

TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition

001110x11Power-on Reset

001110x0xIllegal, TO is set on POR

001110xx0Illegal, PD is set on POR

00u11u011Brown-out Reset

uu0uuuu0uWDT Reset

uuuuuuu00WDT Wake-up from Sleep

uuuuuuu10Interrupt Wake-up from Sleep

uuu0uuuuuMCLR Reset during Normal Operation

uuu0uuu10MCLR Reset during Sleep

u u u u 0 u u u u RESET Instruction Executed

1uuuuuuuuStack Overflow Reset (STVREN = 1)

u1uuuuuuuStack Underflow Reset (STVREN = 1)

TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Condition Program

Counter STATUS

Power-on Reset 0000h ---1 1000 00-- 110x

MCLR Reset during Normal Operation 0000h ---u uuuu uu-- 0uuu

MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu

WDT Reset 0000h ---0 uuuu uu-0 uuuu

WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu

Brown-out Reset 0000h ---1 1000 00-1 11u0

Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-u uuuu

RESET Instruction Executed 0000h ---u uuuu uu-u u0uu

Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu

Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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6.12 Power Control (PCON0) Register

The Power Control (PCON0) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

•MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON0 register bits are shown in Register 6-2.

Hardware will change the corresponding register bit

during the Reset process; if the Reset was not caused

by the condition, the bit remains unchanged

(Tabl e 6 -4).

Software should reset the bit to the inactive state after

the restart (hardware will not reset the bit).

Software may also set any PCON0 bit to the active

state, so that user code may be tested, but no Reset

action will be generated.

R/W-1/u R/W-0-0 U-0 U-0 U-0 U-0 U-0 R-q/u

SBOREN(1) Reserved — — — — — BORRDY

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SBOREN: Software Brown-out Reset Enable bit(1)

If BOREN <1:0> in Configuration Words  01:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words = 01:

1 =BOR Enabled

0 =BOR Disabled

bit 6 Reserved. Bit must be maintained as ‘0’.

bit 5-1 Unimplemented: Read as ‘0’

bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active

0 = The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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6.13 Register Definitions: Power Control

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF —RWDT RMCLR RI POR BOR

bit 7 bit 0

Legend:

HC = Bit is cleared by hardware HS = Bit is set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred

0 = A Stack Overflow has not occurred or has been cleared by firmware

bit 6 STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred

0 = A Stack Underflow has not occurred or has been cleared by firmware

bit 5 Unimplemented: Read as ‘0’

bit 4 RWDT: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware

0 = A Watchdog Timer Reset has occurred (cleared by hardware)

bit 3 RMCLR: MCLR Reset Flag bit

1 =A MCLR

Reset has not occurred or set to ‘1’ by firmware

0 =A MCLR

Reset has occurred (cleared by hardware)

bit 2 RI: RESET Instruction Flag bit

1 =A RESET instruction has not been executed or set to ‘1’ by firmware

0 =A RESET instruction has been executed (cleared by hardware)

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

BORCON SBOREN —————— BORRDY 64

PCON0 STKOVF STKUNF —RWDTRMCLR RI POR BOR 65

STATUS — — —TOPD ZDC C24

WDTCON —— WDTPS<4:0> SWDTEN 109

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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7.0 O SCILLAT OR M ODULE

7.1 Overview

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing

performance and minimizing power consumption.

Figure 7-1 illustrates a block diagram of the oscillator

module.

Clock sources can be supplied from external oscillators,

quartz-crystal resonators and ceramic resonators. In

addition, the system clock source can be supplied from

one of two internal oscillators and PLL circuits, with a

choice of speeds selectable via software. Additional

clock features include:

• Selectable system clock source between external

or internal sources via software.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, ECH, ECM, ECL) and switch

automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources.

The RSTOSC bits of Configuration Word 1 determine

the type of oscillator that will be used when the device

is reset, including when it is first powered-up.

The internal clock modes, LFINTOSC, HFINTOSC (set

at 1 MHz), or HFINTOSC (set at 32 MHz) can be set

through the RSTOSC bits.

If an external clock source is selected, the FEXTOSC

bits of Configuration Word 1 must be used in

conjunction with the RSTOSC bits to select the

External Clock mode.

The external oscillator module can be configured in one

of the following clock modes by setting the

FEXTOSC<2:0> bits of Configuration Word 1:

1. ECL – External Clock Low-Power mode

(100 kHz)

2. ECM – External Clock Medium-Power mode

( 8MHz)

3. ECH – External Clock High-Power mode

( 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (between 100 kHz and 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator

mode (above 4 MHz)

The ECH, ECM, and ECL Clock modes rely on an

external logic level signal as the device clock source.

The LP, XT, and HS Clock modes require an external

crystal or resonator to be connected to the device.

Each mode is optimized for a different frequency range.

The INTOSC internal oscillator block produces low and

high-frequency clock sources, designated LFINTOSC

and HFINTOSC. (see Internal Oscillator Block,

Figure 7-1).

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FIGURE 7-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

Rev. 10-000208L

3/13/2017

PLL Block

HFFRQ<3:0>

HFINTOSC

Secondary

Oscillator

(SOSC)

External

Oscillator

(EXTOSC)

CLKIN/ OSC1

CLKOUT/ OSC2

SOSCIN/SOSCI

SOSCO

31kHz

Oscillator

4x PLL Mode

101

100

110

010

011

000

001

111

COSC<2:0>

LFINTOSC

1 – 32 MHz

Oscillator

9-bit Postscaler Divider

1000

1001

0000

0011

0010

0001

0100

0101

0110

0111

512

256

128

CDIV<4:0>

Sleep

Idle

Sleep

SYSCMD

System Clock

Peripheral Clock

FSCM

To Peripherals

2x PLL Mode

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7.2 Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator

modules (ECH, ECM, ECL mode), quartz crystal

resonators or ceramic resonators (LP, XT and HS

modes).

There is also a secondary oscillator block which is

optimized for a 32.768 kHz external clock source,

which can be used as an alternate clock source.

There are two internal oscillator blocks:

-HFINTOSC

-LFINTOSC

The HFINTOSC can produce clock frequencies from

1-16 MHz. The LFINTOSC generates a 31 kHz clock

frequency.

There is a PLL that can be used by the external oscilla-

tor. See 7.2.1.4 “4x PL L” for more details. Additionally,

there is a PLL that can be used by the HFINTOSC at

certain frequencies. See Section 7.2.2.2 “2x PLL” for

more details.

7.2.1 EXTERNAL CLOCK SOURCES

An external clock source can be used as the device

system clock by performing one of the following

actions:

• Program the RSTOSC<2:0> bits in the

Configuration Words to select an external clock

source that will be used as the default system

clock upon a device Reset.

• Write the NOSC<2:0> and NDIV<3:0> bits in the

OSCCON1 register to switch the system clock

source.

See Section 7.3 “Clock Switching” for more

information.

7.2.1.1 EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the CLKIN input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 7-2 shows the pin connections for EC

mode.

EC mode has three power modes to select from through

Configuration Words:

• ECH – High power,  32 MHz

• ECM – Medium power,  8MHz

• ECL – Low power,  0.1 MHz

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 7-2: EXTERNAL CLOCK (EC)

MODE OPERATION

OSC1/CLKIN

OSC2/CLKOUT

Clock from

Ext. System PIC® MCU

FOSC/4 or I/O(1)

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

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7.2.1.2 LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 7-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive 32.768 kHz tuning-fork type crystals (watch

crystals), but can operate up to 100 kHz.

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive crystals and

resonators with a frequency range up to 4 MHz.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require operating frequencies

up to 20 MHz.

Figure 7-3 and Figure 7-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 7-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 7-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PIC® Oscillator Design”

(DS00849)

• AN943, “Practical PIC® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

RP(3)

Resonator

OSC2/CLKOUT

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7.2.1.3 Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR), Brown-out Reset (BOR), or a

wake-up from Sleep. The OST ensures that the

oscillator circuit, using a quartz crystal resonator or

ceramic resonator, has started and is providing a stable

system clock to the oscillator module.

7.2.1.4 4x PLL

The oscillator module contains a PLL that can be used

with external clock sources to provide a system clock

source. The input frequency for the PLL must fall within

specifications. See the PLL Clock Timing

Specifications in Table 3 5- 9.

The PLL may be enabled for use by one of two

methods:

1. Program the RSTOSC bits in the Configuration

Word 1 to enable the EXTOSC with 4x PLL.

2. Write the NOSC<2:0> bits in the OSCCON1

7.2.1.5 Secondary Oscillator

The secondary oscillator is a separate oscillator block

that can be used as an alternate system clock source.

The secondary oscillator is optimized for 32.768 kHz,

and can be used with an external crystal oscillator

connected to the SOSCI and SOSCO device pins, or

an external clock source connected to the SOSCIN pin.

The secondary oscillator can be selected during

run-time using clock switching. Refer to Section 7.3

“Clock Switching” for more information.

FIGURE 7-5: QUARTZ CRYSTAL

OPERATION

(SECONDARY

OSCILLATOR)

32.768 kHz

SOSCI

To Internal

Logic

PIC® MCU

Crystal

SOSCO

Quartz

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices” (DS00826)

• AN849, “Basic PICmicro® Oscillator

Design” (DS00849)

• AN943, “Practical PICmicro® Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V -T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

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7.2.2 INTERNAL CLOCK SOURCES

The device may be configured to use the internal

oscillator block as the system clock by performing one

of the following actions:

• Program the RSTOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

• Write the NOSC<2:0> bits in the OSCCON1

internal oscillator during run-time. See

Section 7.3 “Clock Switching” for more

information.

The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.

The internal oscillator block has two independent

oscillators that can produce two internal system clock

sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates up

to 32 MHz.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is factory calibrated and operates at

31 kHz.

7.2.2.1 HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a precision digitally-controlled internal clock source

that produces a stable clock up to 32 MHz. The

HFINTOSC can be enabled through one of the

following methods:

• Programming the RSTOSC<2:0> bits in

Configuration Word 1 to ‘110’ (1 MHz) or ‘000’

(32 MHz) to set the oscillator upon device

Power-up or Reset

• Write to the NOSC<2:0> bits of the OSCCON1

The HFINTOSC frequency can be selected by setting

the HFFRQ<2:0> bits of the OSCFRQ register.

The NDIV<3:0> bits of the OSCCON1 register allow for

division of the output of the selected clock source by a

range between 1:1 and 1:512.

7.2.2.2 2x PLL

The oscillator module contains a PLL that can be used

with the HFINTOSC clock source to provide a system

clock source. The input frequency to the PLL is limited

to 8, 12, or 16 MHz, which will yield a system clock

source of 16, 24, or 32 MHz, respectively.

The PLL may be enabled for use by one of two

methods:

1. Program the RSTOSC bits in the Configuration

Word 1 to ‘000’ to enable the HFINTOSC (32

MHz). This setting configures the HFFRQ<2:0>

bits to ‘110’ (16 MHz) and activates the 2x PLL.

2. Write ‘000’ the NOSC<2:0> bits in the

OSCCON1 register to enable the 2x PLL, and

write the correct value into the HFFRQ<3:0> bits

of the OSCFRQ register to select the desired

system clock frequency. See Register 6-6 for

more information.

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7.2.2.3 Internal Oscillator Frequency

Adjustment

The HFINTOSC and LFINTOSC internal oscillators are

both factory-calibrated. The HFINTOSC oscillator can

be adjusted in software by writing to the OSCTUNE

LFINTOSC frequency.

The default value of the OSCTUNE register is 00h. The

value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum

frequency. A value of 20h will provide an adjustment to

the minimum frequency.

When the OSCTUNE register is modified, the

HFINTOSC oscillator frequency will begin shifting to the

new frequency. Code execution continues during this

shift. There is no indication that the shift has occurred.

7.2.2.4 LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

a factory calibrated 31 kHz internal clock source.

The LFINTOSC is the clock source for the Power-up

Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe

Clock Monitor (FSCM). The LFINTOSC can also be

used as the system clock, or as a clock or input source

to certain peripherals.

The LFINTOSC is selected as the clock source through

one of the following methods:

• Programming the RSTOSC<2:0> bits of

Configuration Word 1 to enable LFINTOSC.

• Write to the NOSC<2:0> bits of the OSCCON1

7.2.2.5 Oscillator Status and Manual Enable

The ‘ready’ status of each oscillator is displayed in the

OSCSTAT1 register (Register 7-4). The oscillators can

also be manually enabled through the OSCEN register

(Register 7-5). Manual enables make it possible to

verify the operation of the EXTOSC or SOSC crystal

oscillators. This can be achieved by enabling the

selected oscillator, then watching the corresponding

‘ready’ state of the oscillator in the OSCSTAT1 register.

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7.3 Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the New Oscillator Source (NOSC) and New Divider

Selection Request (NDIV) bits of the OSCCON1

• External Oscillator (EXTOSC)

• High-Frequency Internal Oscillator (HFINTOSC)

• Low-Frequency Internal Oscillator (LFINTOSC)

• Secondary Oscillator (SOSC)

• EXTOSC with 4x PLL

• HFINTOSC with 2x PLL

7.3.1 NEW OSCILLATOR SOURCE

(NOSC) AND NEW DIVIDER

SELECTION REQUEST (NDIV) BITS

The New Oscillator Source (NOSC) and New Divider

Selection Request (NDIV) bits of the OSCCON1

that are used for the CPU and peripherals.

When the new values of NOSC<2:0> and NDIV<3:0>

are written to OSCCON1, the current oscillator

selection will continue to operate as the system clock

while waiting for the new source to indicate that it is

stable and ready. In some cases, the newly requested

source may already be in use, and is ready

immediately. In the case of a divider-only change, the

new and old sources are the same and are ready

immediately. The device may enter Sleep while waiting

for the switch as described in Section 7.3.3 “Clock

Switch and Sleep”.

When the new oscillator is ready, the New Oscillator is

Ready (NOSCR) bit of OSCCON3 and the Clock

Switch Interrupt Flag (CSWIF) bit of PIR3 become set

(CSWIF = 1). If Clock Switch Interrupts are enabled

(CSWIE = 1), an interrupt will be generated at that time.

The Oscillator Ready (ORDY) bit of OSCCON3 can

also be polled to determine when the oscillator is ready

in lieu of an interrupt.

If the Clock Switch Hold (CSWHOLD) bit of OSCCON3

is clear, the oscillator switch will occur when the New

Oscillator Ready bit (NOSCR) is set and the interrupt (if

enabled) will be serviced at the new oscillator setting.

If CSWHOLD is set, the oscillator switch is suspended,

while execution continues using the current (old) clock

source. When the NOSCR bit is set, software should:

• set CSWHOLD = 0 so the switch can complete, or

• copy COSC into NOSC<2:0> to abandon the

switch.

If DOZE is in effect, the switch occurs on the next clock

cycle, whether or not the CPU is operating during that

cycle.

Changing the clock post-divider without changing the

clock source (i.e., changing FOSC from 1 MHz to 2

MHz) is handled in the same manner as a clock source

change, as described previously. The clock source will

already be active, so the switch is relatively quick.

CSWHOLD must be clear (CSWHOLD = 0) for the

switch to complete.

The current COSC and CDIV are indicated in the

OSCCON2 register up to the moment when the switch

actually occurs, at which time OSCCON2 is updated

and ORDY is set. NOSCR is cleared by hardware to

indicate that the switch is complete.

7.3.2 PLL INPUT SWITCH

Switching between the PLL and any non-PLL source is

managed as described above. The input to the PLL is

established when NOSC<2:0> selects the PLL, and

maintained by the COSC setting.

When NOSC<2:0> and COSC select the PLL with

different input sources, the system continues to run

using the COSC setting, and the new source is enabled

per NOSC<2:0>. When the new oscillator is ready (and

CSWHOLD = 0), system operation is suspended while

the PLL input is switched and the PLL acquires lock.

7.3.3 CLOCK SWITCH AND SLEEP

If OSCCON1 is written with a new value and the device

is put to Sleep before the switch completes, the switch

will not take place and the device will enter Sleep

mode.

When the device wakes from Sleep and the

CSWHOLD bit is clear, the device will wake with the

‘new’ clock active, and the Clock Switch Interrupt Flag

bit (CSWIF) will be set.

When the device wakes from Sleep and the

CSWHOLD bit is set, the device will wake with the ‘old’

clock active and the new clock will be requested again.

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FIGURE 7-6: CLOCK SWITCH (CSWHOLD = 0)

FIGURE 7-7: CLOCK SWITCH (CSWHOLD = 1)

Note1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.

2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.

CSWHOLD

NOSCR

OSC #2

CSWIF

OSCCON1

WRITTEN

Note 1

USER

CLEAR

OSC #1

Note 2

ORDY

Note1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

CSWHOLD

NOSCR

OSC #1 OSC #2

CSWIF

OSCCON1

WRITTEN

Note 1

ORDY

USER

CLEAR

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FIGURE 7-8: CLOCK SWITCH ABANDONED

Note1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.

2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.

CSWHOLD

NOSCR

OSC #1

CSWIF

OSCCON1

WRITTEN OSCCON1

WRITTEN

Note 2

ORDY

Note 1

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7.4 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM is enabled by setting the FCMEN bit in the

Configuration Words. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, ECL, ECM,

ECH, and Secondary Oscillator).

FIGURE 7-9: FSCM BLOCK DIAGRAM

7.4.1 FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 7-9. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

external clock goes low.

7.4.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to the HFINTOSC at 1 MHz clock

frequency and sets the bit flag OSFIF of the PIR3

OSFIE bit of the PIE3 register is also set. The device

firmware can then take steps to mitigate the problems

that may arise from a failed clock. The system clock will

continue to be sourced from the internal clock source

until the device firmware successfully restarts the

external oscillator and switches back to external

operation, by writing to the NOSC<2:0> and

NDIV<3:0>bits of the OSCCON1 register.

7.4.3 FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or changing the

NOSC<2:0> and NDIV<3:0> bits of the OSCCON1

external oscillator with PLL, the OST is restarted. While

the OST is running, the device continues to operate

from the INTOSC selected in OSCCON1. When the

OST times out, the Fail-Safe condition is cleared after

successfully switching to the external clock source. The

OSFIF bit should be cleared prior to switching to the

external clock source. If the Fail-Safe condition still

exists, the OSFIF flag will again be set by hardware.

External

LFINTOSC ÷ 64

31 kHz

(~32 s)

488 Hz

(~2 ms)

Clock Monitor

Latch

Clock

Failure

Detected

Oscillator

Clock

Sample Clock

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7.4.4 RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC

Clock modes so that the external clock signal can be

stopped if required. Therefore, the device will always

be executing code while the OST is operating when

using one of the EC modes.

FIGURE 7-10: FSCM TI MING DIAGRAM

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Te s t Test Test

Clock Monitor Output

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7.5 Register Definitions: Oscillator Control

U-0 R/W-f/f(1) R/W-f/f(1) R/W-f/f(1) R/W-q/q(4) R/W-q/q(4) R/W-q/q(4) R/W-q/q(4)

—NOSC<2:0>

(2,3) NDIV<3:0>(2,3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

q = Reset value is determined by hardware

bit 7 Unimplemented: Read as ‘0’

bit 6-4 NOSC<2:0>: New Oscillator Source Request bits

The setting requests a source oscillator and PLL combination per Table 7- 1 .

POR value = RSTOSC (Register 5.2).

bit 3-0 NDIV<3:0>: New Divider Selection Request bits

The setting determines the new postscaler division ratio per Table 7 -2.

Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.

2: If NOSC is written with a reserved value (Table 7-1), the HFINTOSC will be automatically selected as the

clock source.

3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.

4: When RSTOSC = 110 (HFINTOSC 1 MHz) the NDIV bits will default to '0010' upon Reset; for all other

NOSC settings the NVID bits will default to '0000' upon Reset.

U-0 R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1)

— COSC<2:0> CDIV<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

q = Reset value is determined by hardware

bit 7 Unimplemented: Read as ‘0’

bit 6-4 COSC<2:0>: Current Oscillator Source Select bits (read-only)

Indicates the current source oscillator and PLL combination per Tabl e 7-1.

bit 3-0 CDIV<3:0>: Current Divider Select bits (read-only)

Indicates the current postscaler division ratio per Table 7 -2.

Note1: The Reset value (q/q) will match the NOSC<2:0>/NDIV<3:0> bits.

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TABLE 7-1: NOSC/COSC BIT SETTINGS

NOSC<2:0>

COSC<2:0> Clock Source

111 EXTOSC(1)

110 HFINTOSC (1 MHz)

101 Reserved

100 LFINTOSC

011 SOSC

010 Reserved

001 EXTOSC with 4xPLL(1)

000 HFINTOSC with 2x PLL

(32 MHz)

Note 1: EXTOSC configured by the FEXTOSC

bits of Configuration Word 1

(Register 5-1).

TABLE 7-2: NDIV/CDIV BIT SETTINGS

NDIV<3:0>

CDIV<3:0> Cl ock Di vid er

1111–1010 Reserved

1001 512

1000 256

0111 128

0110 64

0101 32

0100 16

0011 8

0010 4

0001 2

0000 1

R/W/HC-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 U-0 U-0 U-0

CSWHOLD SOSCPWR SOSCBE ORDY NOSCR — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

q = Reset value is determined by hardware HC = Hardware clear

bit 7 CSWHOLD: Clock Switch Hold bit

1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready

0 = Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit

is set at the time that NOSCR becomes ‘1’, the switch and interrupt will occur.

bit 6 SOSCPWR: Secondary Oscillator Power Mode Select bit

If SOSCBE = 0

1 = Secondary oscillator operating in High-Power mode

0 = Secondary oscillator operating in Low-Power mode

If SOSCBE = 1

x = Bit is ignored

bit 5 SOSCBE: Secondary Oscillator Bypass Enable bit

1 = Secondary oscillator SOSCI is configured as an external clock input (ST-buffer); SOSCO is not

used.

0 = Secondary oscillator is configured as a crystal oscillator using SOSCO and SOSCI pins.

bit 4 ORDY: Oscillator Ready bit (read-only)

1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC

0 = A clock switch is in progress

bit 3 NOSCR: New Oscillator is Ready bit (read-only)

1 = A clock switch is in progress and the oscillator selected by NOSC indicates a Ready condition

0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready

bit 2-0 Unimplemented: Read as ‘0’.

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R-q/q R-q/q U-0 R-q/q R-q/q R-q/q U-0 R-q/q

EXTOR HFOR —LFORSORADOR—PLLR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

q = Reset value is determined by hardware

bit 7 EXTOR: EXTOSC (external) Oscillator Ready

1 = The oscillator is ready to be used

0 = The oscillator is not enabled, or is not yet ready to be used.

bit 6 HFOR: HFINTOSC Oscillator Ready

1 = The oscillator is ready to be used

0 = The oscillator is not enabled, or is not yet ready to be used.

bit 5 Unimplemented: Read as ‘0’

bit 4 LFOR: LFINTOSC Oscillator Ready

1 = The oscillator is ready to be used

0 = The oscillator is not enabled, or is not yet ready to be used.

bit 3 SOR: Secondary Oscillator Ready

1 = The oscillator is ready to be used

0 = The oscillator is not enabled, or is not yet ready to be used.

bit 2 ADOR: ADCRC Oscillator Ready

1 = The oscillator is ready to be used

0 = The oscillator is not enabled, or is not yet ready to be used

bit 1 Unimplemented: Read as ‘0’

bit 0 PLLR: PLL is ready

1 = The PLL is ready to be used

0 = The PLL is not enabled, the required input source is not ready, or the PLL is not ready.

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R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0

EXTOEN HFOEN — LFOEN SOSCEN ADOEN — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 EXTOEN: External Oscillator Manual Request Enable bit

1 = EXTOSC is explicitly enabled, operating as specified by FEXTOSC

0 = EXTOSC could be enabled by another module

bit 6 HFOEN: HFINTOSC Oscillator Manual Request Enable bit

1 = HFINTOSC is explicitly enabled, operating as specified by OSCFRQ (Register 7-6)

0 = HFINTOSC could be enabled by another module

bit 5 Unimplemented: Read as ‘0’

bit 4 LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit

1 = LFINTOSC is explicitly enabled

0 = LFINTOSC could be enabled by another module

bit 3 SOSCEN: Secondary Oscillator Manual Request Enable bit

1 = Secondary Oscillator is explicitly enabled

0 = Secondary Oscillator could be enabled by another module

bit 2 ADOEN: ADOSC (600 kHz) Oscillator Manual Request Enable bit

1 = ADOSC is explicitly enabled

0 = ADOSC could be enabled by another module

bit 1 Unimplemented: Read as ‘0’

bit 0 Unimplemented: Read as ‘0’

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U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

— — — — HFFRQ<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’.

bit 3-0 HFFRQ<3:0>: HFINTOSC Frequency Selection bits

HFFRQ<3:0> Nominal Freq. (MHz)

(NOSC = 110)2xPLL Freq. (MHz)

(NOSC = 000)

0000 1

Reserved

0001 2

0010 Reserved

0011 4

0100 816

0101 12 24

0110 16 32

0111 32 Reserved

1xxx 32

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U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— HFTUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting

q = Reset value is determined by hardware

bit 7-6 Unimplemented: Read as ‘0’.

bit 5-0 HFTUN<5:0>: HFINTOSC Frequency Tuning bits

01 1111 = Maximum frequency

01 1110

•

00 0001

00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value).

11 1111

•

10 0000 = Minimum frequency.

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TABLE 7-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

OSCCON1 — NOSC<2:0> NDIV<3:0> 78

OSCCON2 — COSC<2:0> CDIV<3:0> 78

OSCCON3 CWSHOLD SOSCPWR SOSCBE ORDY NOSCR — — — 79

OSCSTAT1 EXTOR HFOR —LFOR

SOR ADOR —PLLR 80

OSCEN EXTOEN HFOEN —LFOEN

SOSCEN ADOEN — — 81

OSCFRQ — — — — HFFRQ<3:0> 82

OSCTUNE ——HFTUN<5:0>83

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 7-4: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG1 13:8 — — FCMEN — CSWEN ——CLKOUTEN

7:0 — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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8.0 INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

Many peripherals produce interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1.

FIGURE 8-1: INTERRUPT LOGIC

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE Interrupt

to CPU

Wake-up

(If in Sleep mode)

GIE

(TMR1IF) PIR1<0>

PIRn<7>

PEIE

(TMR1IE) PIE1<0>

Peripheral Interrupts

PIEn<7>

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8.1 Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) (PIEx bits) for the specific

interrupt event(s)

• PEIE bit of the INTCON register

The PIR1, PIR2, PIR3 and PIR4 registers record

individual interrupts via interrupt flag bits. Interrupt flag

bits will be set, regardless of the status of the GIE, PEIE

and individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See “Sec tion 8.5 “Automati c

Context Savi ng”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

8.2 Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The interrupt is sampled during

Q1 of the instruction cycle. The actual interrupt latency

then depends on the instruction that is executing at the

time the interrupt is detected. See Figure 8-2 and

Figure 8-3 for more details.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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FIGURE 8-2: INTERRUP T LATENCY

FIGURE 8-3: INT PIN INTERRUPT TIMING

Rev. 10-000269E

8/31/2016

Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q2Q2Q2Q2Q2Q2 Q2Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q4Q4Q4Q4Q4Q4Q4

OSC1

CLKOUT

INT

PC - 1 PC

Fetch

Execute PC - 2 PC - 1 PC

PC + 1

123 123

PC = 0x0004

PC = 0x0005

PC = 0x0006

1 Cycle Instruction at PC

Latency

Valid Interrupt

window(1)

Indeterminate

Latency(2)

Note 1: An interrupt may occur at any time during the interrupt window.

2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Forced NOP

Inst (PC) Inst (PC + 1)

Inst (PC – 1) Inst (0004h)

Forced NOP

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 35.0 “Electrical Specifications””.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

(1) (2)

(3) (4)

(5)

(1)

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8.3 Interrupts During Sleep

All interrupts can be used to wake from Sleep. To wake

from Sleep, the peripheral must be able to operate

without the system clock. The interrupt source must

have the appropriate Interrupt Enable bit(s) set prior to

entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 9.0

“Power-Sav ing Operatio n Mode s” for more details.

8.4 INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the PIE0 register. The INTEDG bit

of the INTCON register determines on which edge the

interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the PIR0 register will be set when a valid

edge appears on the INT pin. If the GIE and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector.

8.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these

registers are automatically restored. Any modifications

to these registers during the ISR will be lost. If

modifications to any of these registers are desired, the

corresponding shadow register should be modified and

the value will be restored when exiting the ISR. The

shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s

application, other registers may also need to be saved.

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8.6 Re gist er Defini tions : In te rru pt C on t rol

R/W/HS/HC-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R-1/1

GIE PEIE — — — — —INTEDG

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

HS = hardware set HC = Hardware clear

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts

0 = Disables all peripheral interrupts

bit 5-1 Unimplemented: Read as ‘0’.

bit 0 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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U-0 U-0 R/W/HS-0/0 R/W-0/0 U-0 U-0 U-0 R/W/HS-0/0

——TMR0IEIOCIE — — —INTE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7-6 Unimplemented: Read as ‘0’.

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 IOCIE: Interrupt-on-Change Interrupt Enable bit

1 = Enables the IOC change interrupt

0 = Disables the IOC change interrupt

bit 3-1 Unimplemented: Read as ‘0’.

bit 0 INTE: INT External Interrupt Flag bit(1)

1 = Enables the INT external interrupt

0 = Disables the INT external interrupt

Note 1: The external interrupt INT pin is selected by INTPPS (Register 13-1).

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt

0 = Disables the Timer1 gate acquisition interrupt

bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSART transmit interrupt

bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit

1 = MSSP bus collision interrupt enabled

0 = MSSP bus collision interrupt not enabled

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

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U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0

—C2IE(1) C1IE NVMIE — — — NCO1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’.

bit 6 C2IE: Comparator C2 Interrupt Enable bit(1)

1 = Enables the Comparator C2 interrupt

0 = Disables the Comparator C2 interrupt

bit 5 C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt

0 = Disables the Comparator C1 interrupt

bit 4 NVMIE: NVM Interrupt Enable Bit

1 = NVM task complete interrupt enabled

0 = NVM interrupt not enabled

bit 3-1 Unimplemented: Read as ‘0’.

bit 0 NCO1IE: NCO Interrupt Enable bit

1 = NCO rollover interrupt enabled

0 = NCO rollover interrupt not enabled

Note 1: Comparator C2 not available on PIC16(L)F18313 devices.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2015-2017 Microchip Technology Inc. DS40001799C-page 93

PIC16(L)F18313/18323

R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0

OSFIE CSWIE — — — — CLC2IE CLC1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit.

1 = Enables the Oscillator Fail interrupt

0 = Disables the Oscillator Fail interrupt

bit 6 CSWIE: Clock Switch Complete Interrupt Enable bit

1 = The clock switch module interrupt is enabled

0 = The clock switch module interrupt is not enabled

bit 5-2 Unimplemented: Read as ‘0’.

bit 1 CLC2IE: CLC2 Interrupt Enable bit

1 = CLC2 interrupt enabled

0 = CLC2 interrupt disabled

bit 0 CLC1IE: CLC1 Interrupt Enable bit

1 = CLC1 interrupt enabled

0 = CLC1 interrupt disabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIC16(L)F18313/18323

DS40001799C-page 94  2015-2017 Microchip Technology Inc.

U-0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0

—CWG1IE— — — — CCP2IE CCP1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 Unimplemented: Read as ‘0’.

bit 6 CWG1IE: CWG 1 Interrupt Enable bit

1 = CWG1 interrupt enabled

0 = CWG1 interrupt not enabled

bit 5-2 Unimplemented: Read as ‘0’.

bit 1 CCP2IE: CCP2 Interrupt Enable bit

1 = CCP2 interrupt is enabled

0 = CCP2 interrupt is not enabled

bit 0 CCP1IE: CCP1 Interrupt Enable bit

1 = CCP1 interrupt is enabled

0 = CCP1 interrupt is not enabled

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

 2015-2017 Microchip Technology Inc. DS40001799C-page 95

PIC16(L)F18313/18323

U-0 U-0 R/W/HS-0/0 R-0 U-0 U-0 U-0 R/W/HS-0/0

——TMR0IFIOCIF

(1) — — —INTF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS= Hardware Set

bit 7-6 Unimplemented: Read as ‘0’

bit 5 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 4 IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)

1 = An enabled edge was detected by the IOC module. One of the IOCF bits is set.

0 = No enabled edge is was detected by the IOC module. None of the IOCF bits is set.

Pins are individually masked via IOCxP and IOCxN.

bit 3-1 Unimplemented: Read as ‘0’

bit 0 INTF: INT External Interrupt Flag bit(1)

1 = The INT external interrupt occurred (must be cleared in software)

0 = The INT external interrupt did not occur

Note 1: The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag,

application firmware must clear all of the IOCAF-IOCCF register bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

PIC16(L)F18313/18323

DS40001799C-page 96  2015-2017 Microchip Technology Inc.

R/W/HS-0/0 R/W/HS-0/0 R-0 R-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = The Timer1 gate has gone inactive (the gate is closed).

0 = The Timer1 gate has not gone inactive.

bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit

1 = The A/D conversion completed

0 = The A/D conversion is not completed

bit 5 RCIF: EUSART Receive Interrupt Flag bit (read-only)

1 = The EUSART1 receive buffer is not empty

0 = The EUSART1 receive buffer is empty

bit 4 TXIF: EUSART Transmit Interrupt Flag bit (read-only)

1 = The EUSART1 transmit buffer is empty

0 = The EUSART1 transmit buffer is not empty

bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0 = Waiting for the Transmission/Reception/Bus Condition in progress

bit 2 BCL1IF: MSSP Bus Collision Interrupt Flag bit

1 = A bus collision was detected (must be cleared in software)

0 = No bus collision was detected

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = TMR1 overflow occurred (must be cleared in software)

0 = No TMR1 overflow occurred

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

 2015-2017 Microchip Technology Inc. DS40001799C-page 97

PIC16(L)F18313/18323

U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 R/W/HS-0/0

—C2IF(1) C1IF NVMIF — — — NCO1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 Unimplemented: Read as ‘0’

bit 6 C2IF: Comparator C2 Interrupt Flag bit(1)

1 = Comparator 2 interrupt asserted

0 = Comparator 2 interrupt not asserted

bit 5 C1IF: Comparator C1 Interrupt Flag bit

1 = Comparator 1 interrupt asserted

0 = Comparator 1 interrupt not asserted

bit 4 NVMIF: NVM Interrupt Flag bit

1 = The NVM has completed a programming task

0 = NVM interrupt not asserted

bit 3-1 Unimplemented: Read as ‘0’

bit 0 NCO1IF: NCO Interrupt Flag bit

1 = The NCO has rolled over.

0 = No NCO interrupt is asserted.

Note 1: Comparator C2 not available on PIC16(L)F18313 devices.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

PIC16(L)F18313/18323

DS40001799C-page 98  2015-2017 Microchip Technology Inc.

R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0

OSFIF CSWIF — — — — CLC2IF CLC1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 OSFIF: Oscillator Fail-Safe Interrupt Flag bit

1 = Fail-Safe Clock Monitor module has detected a failed oscillator

0 = External oscillator operating normally.

bit 6 CSWIF: Clock Switch Complete Interrupt Flag bit

1 = The clock switch module has completed the clock switch; new oscillator is ready

0 = The clock switch module has not completed clock switch.

bit 5-2 Unimplemented: Read as ‘0’

bit 1 CLC2IF: CLC2 Interrupt Flag bit

1 = The CLC2OUT interrupt condition has been met

0 = No CLC2 interrupt

bit 0 CLC1IF: CLC1 Interrupt Flag bit

1 = The CLC1OUT interrupt condition has been met

0 = No CLC1 interrupt

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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PIC16(L)F18313/18323

U-0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0

—CWG1IF — — — — CCP2IF CCP1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set

bit 7 Unimplemented: Read as ‘0’

bit 6 CWG1IF: CWG1 Interrupt Flag bit

1 = CWG1 has gone into shutdown

0 = CWG1 is operating normally, or interrupt cleared

bit 5-2 Unimplemented: Read as ‘0’

bit 1 CCP2IF: CCP2 Interrupt Flag bit

bit 0 CCP1IF: CCP1 Interrupt Flag bit

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

Value CCPM Mod e

Capture Compare PWM

1Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

0Capture did not occur Compare match did not

occur

Output trailing edge did not

occur

Value CCPM Mode

Capture Compare PWM

1Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

0Capture did not occur Compare match did not

occur

Output trailing edge did not

occur

PIC16(L)F18313/18323

DS40001799C-page 100  2015-2017 Microchip Technology Inc.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE — — — — —INTEDG89

PIE0 ——TMR0IEIOCIE — — —INTE90

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIE2 —C2IE

(1) C1IE NVMIE — — — NCO1IE 92

PIE3 OSFIE CSWIE — — — — CLC2IE CLC1IE 93

PIE4 —CWG1IE — — — — CCP2IE CCP1IE 94

PIR0 ——TMR0IFIOCIF — — —INTF95

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIR2 —C2IF

(1) C1IF NVMIF — — — NCO1IF 97

PIR3 OSFIF CSWIF — — — — CLC2IF CLC1IF 98

PIR4 —CWG1IF — — — — CCP2IF CCP1IF 99

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

Note 1: Comparator C2 not available on PIC16(L)F18313 devices.

 2015-2017 Microchip Technology Inc. DS40001799C-page 101

PIC16(L)F18313/18323

9.0 POWER-SAVING OPERATION

MODES

The purpose of the Power-Down modes is to reduce

power consumption. There are three Power-Down

modes: DOZE mode, IDLE mode, and Sleep mode.

9.1 DOZE Mode

Doze mode allows for power savings by reducing CPU

operation and program memory access, without

affecting peripheral operation. Doze mode differs from

Sleep mode because the system oscillators continue to

operate, while only the CPU and program memory are

affected. The reduced execution saves power by

eliminating unnecessary operations within the CPU

and memory.

When the Doze Enable (DOZEN) bit is set

(DOZEN = 1), the CPU executes only one instruction

cycle out of every N cycles as defined by the

DOZE<2:0> bits of the CPUDOZE register. For

example, if DOZE<2:0> = 100, the instruction cycle

ratio is 1:32. The CPU and memory execute for one

instruction cycle and then lay idle for 31 instruction

cycles. During the unused cycles, the peripherals

continue to operate at the system clock speed.

9.1.1 DOZE OPERATION

The Doze operation is illustrated in Figure 9-1. For this

example:

• Doze enable (DOZEN) bit set (DOZEN = 1)

•DOZE<2:0>=001 (1:4) ratio

• Recover-on-Interrupt (ROI) bit set (ROI = 1)

As with normal operation, the program memory fetches

for the next instruction cycle. The instruction clocks to

the peripherals continue throughout.

9.1.2 INTERRUPTS DURING DOZE

If an interrupt occurs and the Recover-on-Interrupt

(ROI) bit is clear (ROI = 0) at the time of the interrupt,

the Interrupt Service Routine (ISR) continues to exe-

cute at the rate selected by DOZE<2:0>. Interrupt

latency is extended by the DOZE<2:0> ratio.

If an interrupt occurs and the ROI bit is set (ROI = 1) at

the time of the interrupt, the DOZEN bit is cleared and

the CPU executes at full speed. The prefetched

instruction is executed and then the interrupt vector

sequence is executed. In Figure 9-1, the interrupt

occurs during the 2nd instruction cycle of the Doze

period, and immediately brings the CPU out of Doze. If

the Doze-on-Exit (DOE) bit is set (DOE = 1) when the

RETFIE operation is executed, DOZEN is set, and the

CPU executes at the reduced rate based on the

DOZE<2:0> ratio.

FIGURE 9-1: DOZE MODE OPERATION EXAMPLE

System

Clock

/ŶƐƚƌƵĐƚŝŽŶ

WĞƌŝŽĚƐ

CPU Clock

PFM Op’s

CPU Op’s

1111111111111

1234 2 22222

22222222222 2

1 111113 333334 44444

3333333333333

4444444444444

Fetch Fetch FetchFetch

Exec Exec Exec(1,2) Exec Exec Exec

Push

NOP

0004h

Interrup t

Here

(ROI = 1)

PIC16(L)F18313/18323

DS40001799C-page 102  2015-2017 Microchip Technology Inc.

9.2 IDLE Mode

When the IDLE Enable (IDLEN) bit is clear

(IDLEN = 0), the SLEEP instruction will put the device

into full Sleep mode (see Section 9.3 “Sleep Mode”).

When IDLEN is set (IDLEN = 1), the SLEEP instruction

will put the device into IDLE mode. In IDLE mode, the

CPU and memory operations are halted, but the

peripheral clocks continue to run. This mode is similar

to DOZE mode, except that in IDLE both the CPU and

program memory are shut off.

9.2.1 IDLE AND INTERRUPTS

IDLE mode ends when an interrupt occurs (even if

GIE = 0), but IDLEN is not changed. The device can

re-enter IDLE by executing the SLEEP instruction.

If Recover-on-Interrupt is enabled (ROI = 1), the

interrupt that brings the device out of IDLE also

restores full-speed CPU execution when DOZE is also

enabled.

9.2.2 IDLE AND WDT

When in IDLE, the WDT Reset is blocked and will

instead wake the device. The WDT wake-up is not an

interrupt, therefore ROI does not apply.

9.3 Sleep Mode

Sleep mode is entered by executing the SLEEP

instruction, while the Idle Enable (IDLEN) bit of the

CPUDOZE register is clear (IDLEN = 0). If the SLEEP

instruction is executed while the IDLEN bit is set

(IDLEN = 1), the CPU will enter the Idle mode

(Section 9.3.3 “Low-Power Sleep Mode”).

Upon entering Sleep mode, the following conditions

exist:

1. Resets other than WDT are not affected by

Sleep mode; WDT will be cleared but keeps

running if enabled for operation during Sleep.

2. The PD bit of the STATUS register is cleared.

3. The TO bit of the STATUS register is set.

4. The CPU and System clocks are disabled.

5. 31 kHz LFINTOSC, HFINTOSC and SOSC will

remain enabled if any peripheral has requested

them as a clock source or if the HFOEN,

LFOEN, or SOSCEN bits of the OSCEN register

are set.

6. ADC is unaffected if the dedicated ADCRC

oscillator is selected. When the ADC clock

source is something other than ADCRC, a

SLEEP instruction causes the present

conversion to be aborted and the ADC module

is turned off, although the ADON bit remains set.

7. I/O ports maintain the status they had before

Sleep was executed (driving high, low, or

high-impedance) only if no peripheral connected

to the I/O port is active.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

- I/O pins should not be floating

- External circuitry sinking current from I/O pins

- Internal circuitry sourcing current from I/O

pins

- Current draw from pins with internal weak

pull-ups

- Modules using any oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules. See Section 24.0 “5-bit Digital-to-Analog

Converter (DAC1) Module” and Section 16.0 “Fixed

Voltage Reference (FVR)” for more information on

these modules.

Note: Peripherals using FOSC will continue

running while in IDLE (but not in Sleep).

Peripherals using HFINTOSC,

LFINTOSC, or SOSC will continue

operation in both IDLE and SLEEP.

Note: If CLKOUT is enabled (CLKOUT = 0,

Configuration Word 1), the output will

continue operating while in IDLE.

Note: The WDT can bring the device out of

IDLE, in the same way it brings the device

out of Sleep. The DOZEN bit is not

affected.

 2015-2017 Microchip Technology Inc. DS40001799C-page 103

PIC16(L)F18313/18323

9.3.1 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled.

3. POR Reset.

4. Watchdog Timer, if enabled

5. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information).

The first three events will cause a device Reset. The

last two events are considered a continuation of

program execution. To determine whether a device

Reset or wake-up event occurred, refer to Section 6.11

“Determining the Cause of a Reset”.

The WDT is cleared when the device wakes-up from

Sleep, regardless of the source of wake-up.

9.3.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

-SLEEP instruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

-TO

bit of the STATUS register will not be set

-PD bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the

execution of a SLEEP instruction

-SLEEP instruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

PIC16(L)F18313/18323

DS40001799C-page 104  2015-2017 Microchip Technology Inc.

FIGURE 9-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT

9.3.3 LOW-POWER SLEEP MODE

The PIC16F18313/18323 device contains an internal

Low Dropout (LDO) voltage regulator, which allows the

device I/O pins to operate at voltages up to 5.5V while

the internal device logic operates at a lower voltage.

The LDO and its associated reference circuitry must

remain active when the device is in Sleep mode.

The PIC16F18313/18323 allows the user to optimize

the operating current in Sleep, depending on the

application requirements.

Low-Power Sleep mode can be selected by setting the

VREGPM bit of the VREGCON register. Depending on

the configuration of this bit, the LDO and reference

circuitry are placed in a low-power state when the

device is in Sleep.

9.3.3.1 Sleep Current vs. Wake-up Time

In the default operating mode, the LDO and reference

circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly

since all circuits remain active. In Low-Power Sleep

mode, when waking-up from Sleep, an extra delay time

is required for these circuits to return to the normal

configuration and stabilize.

The Low-Power Sleep mode is beneficial for

applications that stay in Sleep mode for long periods of

time. The Normal mode is beneficial for applications

that need to wake from Sleep quickly and frequently.

9.3.3.2 Peripheral Usage in Sleep

Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode

selected. The Low-Power Sleep mode is intended for

use with these peripherals:

• Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/Interrupt-on-change pins

• Timer 1 (with external clock source)

It is the responsibility of the end user to determine what

is acceptable for their application when setting the

VREGPM settings in order to ensure operation in

Sleep.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Forced NOP

PC + 2 0004h 0005h

Forced NOP

TOST(3)

PC + 2

Note 1: External clock. High, Medium, Low mode assumed.

2: CLKOUT is shown here for timing reference.

3: TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.

4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

Note: The PIC16LF18313/18323 does not have

a configurable Low-Power Sleep mode.

PIC16LF18313/18323 is an unregulated

device and is always in the lowest power

state when in Sleep, with no wake-up time

penalty. This device has a lower maximum

VDD and I/O voltage than the

PIC16F18313/18323. See Section 35.0

“Electrical Specifications” for more

information.

 2015-2017 Microchip Technology Inc. DS40001799C-page 105

PIC16(L)F18313/18323

9.4 Register Definitions: Voltage Regulator Control

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1

— — — — — —VREGPMReserved

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep(2); Draws lowest current in Sleep, slower wake-up

0 = Normal-Power Sleep mode enabled in Sleep(2); Draws higher current in Sleep, faster wake-up

bit 0 Reserved: Read as ‘1’. Maintain this bit set.

Note 1: PIC16F18313/18323 only.

2: See Section 35.0 “Electrical Specifications”.

R/W-0/u R/W/HC/HS-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

IDLEN DOZEN(1,2) ROI DOE — DOZE<2:0>

bit 7 bit 0

Legend: HS = Hardware Set

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Hardware clear

bit 7 IDLEN: Idle Enable bit

1 =A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s)

0 =A SLEEP instruction places the device into Full-Sleep mode

bit 6 DOZEN: Doze Enable bit(1,2)

1 = The CPU executes instruction cycles according to DOZE setting.

0 = The CPU executes all instruction cycles (fastest, highest power operation).

bit 5 ROI: Recover-on-Interrupt bit

1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation.

0 = Interrupt entry does not change DOZEN

bit 4 DOE: Doze-on-Exit bit

1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.

0 = RETFIE does not change DOZEN

bit 3 Unimplemented: Read as ‘0’.

bit 2-0 DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

111 = 1:256

110 =1:128

101 =1:64

100 =1:32

011 =1:16

010 =1:8

001 =1:4

000 =1:2

Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.

2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.

PIC16(L)F18313/18323

DS40001799C-page 106  2015-2017 Microchip Technology Inc.

TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE — — — — —INTEDG89

PIE0 ——TMR0IEIOCIE— — —INTE

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIE2 —C2IE(1) C1IE NVMIE — — — NCO1IE 92

PIE3 OSFIE CSWIE — — — — CLC2IE CLC1IE 93

PIE4 —CWG1IE — — — — CCP2IE CCP1IE 94

PIR0 ——TMR0IFIOCIF

— — — INTF 95

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIR2 —C2IF(1) C1IF NVMIF — — — NCO1IF 97

PIR3 OSFIF CSWIF — — — — CLC2IF CLC1IF 98

PIR4 —CWG1IF — — — — CCP2IF CCP1IF 99

IOCAP —— IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 156

IOCAN —— IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 156

IOCAF —— IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 157

IOCCP(1) —— IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 158

IOCCN(1) —— IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 158

IOCCF(1) —— IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 159

STATUS — — —TOPD ZDC C 24

VREGCON(2) — — — — — —VREGPM —105

CPUDOZE IDLEN DOZEN ROI DOE — DOZE<2:0> 105

WDTCON ——WDTPS<4:0>SWDTEN109

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

Note 1: PIC16(L)F18323 only.

2: PIC16F18313/18323 only.

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PIC16(L)F18313/18323

10.0 W ATCHDOG T IME R (WDT)

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Multiple WDT clearing conditions

• Operation during Sleep

FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM

LFINTOSC 23-bit Programmable

Prescaler WDT WDT Time-out

WDTPS<4:0>

SWDTEN

Sleep

WDTE<1:0> = 11

WDTE<1:0> = 01

WDTE<1:0> = 10

PIC16(L)F18313/18323

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10.1 Independent Clock Source

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this

chapter are based on a nominal interval of 1 ms. See

Table 35-8 for the LFINTOSC specification.

10.2 WDT Operating Modes

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Words. See Table 10-1.

10.2.1 WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to

‘11’, the WDT is always on.

WDT protection is active during Sleep.

10.2.2 WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.2.3 WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

10.2.4 WDT IS ALWAYS OFF

When the WDTE bits are set to '00', the WDT is

disabled, and the SWDTEN bit of the WDTCON is

ignored.

10.3 Time-out Peri od

The WDTPS<4:0> bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

10.4 Clearing the WDT

The WDT is cleared when any of the following

conditions occur:

•Any Reset

•CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep due to an interrupt

• Oscillator fail

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

See Table 10-2 for more information.

10.5 Operation During Sleep

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting.

When the device exits Sleep, the WDT is cleared

again. The WDT remains clear until the OST, if

enabled, completes. See Section 7.0 “Oscillator

Module” for more information on the OST.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. See STATUS Register (Register 4-1) for more

information.

TABLE 10-1: WDT OPERATING MODES

WDTE<1:0> SWDTEN Device

Mode WDT Mode

11 XXActive

10 XAwake Active

Sleep Disabled

01 1XActive

0Disabled

00 X X Disabled

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions WDT

WDTE = 00 Cleared and Disabled

WDTE = 01 and SWDTEN = 0

Exit Sleep due to a Reset + System Clock = XT, HS, LP Cleared until the end of OST

Exit Sleep due to a Reset + System Clock = HFINTOSC, LFINTOSC, EC, SOSC

Exit Sleep due to an interrupt

Cleared

Enter Sleep

CLRWDT Command

Oscillator Failure (see Section 7.4 “Fail-Safe Clock Monitor”)

System Reset

Any clock switch or divider change (see Section 7.3 “Clock Switching”) Unaffected

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10.6 Register Definitions: Watchdog Control

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0

—— WDTPS<4:0>(1) SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)

Bit Value = Prescale Rate

11111 = Reserved. Results in minimum interval (1:32)

•

10011 = Reserved. Results in minimum interval (1:32)

10010 = 1:8388608 (223) (Interval 256s nominal)

10001 = 1:4194304 (222) (Interval 128s nominal)

10000 = 1:2097152 (221) (Interval 64s nominal)

01111 = 1:1048576 (220) (Interval 32s nominal)

01110 = 1:524288 (219) (Interval 16s nominal)

01101 = 1:262144 (218) (Interval 8s nominal)

01100 = 1:131072 (217) (Interval 4s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)

01010 = 1:32768 (Interval 1s nominal)

01001 = 1:16384 (Interval 512 ms nominal)

01000 = 1:8192 (Interval 256 ms nominal)

00111 = 1:4096 (Interval 128 ms nominal)

00110 = 1:2048 (Interval 64 ms nominal)

00101 = 1:1024 (Interval 32 ms nominal)

00100 = 1:512 (Interval 16 ms nominal)

00011 = 1:256 (Interval 8 ms nominal)

00010 = 1:128 (Interval 4 ms nominal)

00001 = 1:64 (Interval 2 ms nominal)

00000 = 1:32 (Interval 1 ms nominal)

bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 1x:

This bit is ignored.

If WDTE<1:0> = 01:

1 = WDT is turned on

0 = WDT is turned off

If WDTE<1:0> = 00:

This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

PIC16(L)F18313/18323

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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

STATUS ———TO

PD ZDCC24

WDTCON —— WDTPS<4:0> SWDTEN 109

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

Watchdog Timer.

TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG2 13:8 — — DEBUG STVREN PPS1WAY —BORV —

7:0 BOREN1 BOREN0 LPBOREN —WDTE1WDTE0PWRTE MCLRE

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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11.0 NONVOLATILE MEMORY

(NVM) CONTROL

NVM is separated into two types: Program Flash

Memory and Data EEPROM.

NVM is accessible by using both the FSR and INDF

registers, or through the NVMREG register interface.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the operating

voltage range of the device.

NVM can be protected in two ways; by either code

protection or write protection.

Code protection (CP and CPD bits in Configuration

Word 4) disables access, reading and writing, to both

the program Flash memory and EEPROM via external

device programmers. Code protection does not affect

the self-write and erase functionality. Code protection

can only be Reset by a device programmer performing

a Bulk Erase to the device, clearing all nonvolatile

memory, Configuration bits, and user IDs.

Write protection prohibits self-write and erase to a

portion or all of the program Flash memory, as defined

by the WRT<1:0> bits of Configuration Word 3. Write

protection does not affect a device programmer’s ability

to read, write, or erase the device.

11.1 Program Flash Memory

Program Flash memory consists of 8192 14-bit words

as user memory, with additional words for user ID

information, Configuration Words, and interrupt

vectors. Program Flash memory provides storage

locations for:

• User program instructions

• User defined data

Program Flash memory data can be read and/or written

to through:

• CPU instruction fetch (read-only)

• FSR/INDF indirect access (read-only)

(Section 11.3 “FSR and INDF Access”)

• NVMREG access (Section 11.4 “NVMREG

Access”

• External device programmer

Read operations return a single word of memory. When

write and erase operations are done on a row basis, the

row size is defined in Table 11-1. Program Flash

memory will erase to a logic ‘1’ and program to a logic

‘0’.

It is important to understand the program Flash

memory structure for erase and programming

operations. Program Flash memory is arranged in

rows. A row consists of 32 14-bit program memory

words. A row is the minimum size that can be erased

by user software.

All or a portion of a row can be programmed. Data to be

written into the program memory row is written to 14-bit

wide data write latches. These latches are not directly

accessible to the user, but may be loaded via

sequential writes to the NVMDATH:NVMDATL register

pair.

11.1.1 PROGRAM MEMORY VOLTAGES

The program Flash memory is readable and writable

during normal operation over the full VDD range.

11.1.1.1 Programming Externally

The program memory cell and control logic support

write and Bulk Erase operations down to the minimum

device operating voltage.

11.1.1.2 Self-Programming

The program memory cell and control logic will support

write and row erase operations across the entire VDD

range. Bulk Erase is not available when

self-programming.

TABLE 11-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Device Row Erase

(words)

Write

Latches

(words)

PIC16(L)F18313 32 32

PIC16(L)F18323

Note: To modify only a portion of a previously

programmed row, the contents of the

entire row must be read and saved in

either RAM or the row’s write latches prior

to the erase. Then, the new data and

retained data can be written into the write

latches to reprogram the row of program

Flash memory. Any unprogrammed

locations can be written without first

erasing the row. In this case, it is not

necessary to save and rewrite the other

previously programmed locations

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11.2 Data EEPROM

Data EEPROM consists of 256 bytes of user data

memory. The EEPROM provides storage locations for

8-bit user defined data.

EEPROM can be read and/or written through:

• FSR/INDF indirect access (Section 11.3 “FSR

and INDF Access”)

• NVMREG access (Section 11.4 “NVMREG

Access”)

• External device programmer

Unlike program Flash memory, which must be written

to by row, EEPROM can be written to byte by byte.

11.3 FSR and INDF Access

The FSR and INDF registers allow indirect access to

the program Flash memory or EEPROM.

11.3.1 FSR READ

With the intended address loaded into an FSR register,

a MOVIW instruction or read of INDF will read data from

the Program Flash Memory or EEPROM. The CPU

operation is suspended during the read, and resumes

immediately after. Read operations return a single word

of memory. When the MSB of the FSR (ex: FSRxH) is

set to 0x70, the lower 8-bit address value (in FSRxL)

determines the EEPROM location that may be read

from (through the INDF register). In other words, the

EEPROM address range 0x00-0xFF is mapped into the

FSR address space between 0x7000-0x70FF. Writing

to the EEPROM cannot be accomplished via the

FSR/INDF interface.

11.3.2 FSR WRITE

Writing/erasing the NVM through the FSR registers (ex.

MOVWI instruction) is not supported in the

PIC16(L)F18313/18323 devices.

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11.4 NVMREG Access

The NVMREG interface allows read/write access to all

the locations accessible by FSRs, and also read/write

access to the user ID locations and EEPROM, and

read-only access to the device identification, revision,

and Configuration data.

Reading, writing, or erasing of NVM via the NVMREG

interface is prevented when the device is

code-protected.

11.4.1 NVMREG READ OPERATION

To read a NVM location using the NVMREG interface,

the user must:

1. Clear the NVMREGS bit of the NVMCON1

Flash memory locations, or set NVMREGS if the

user intends to access user ID, Configuration, or

EEPROM locations.

2. Write the desired address into the

NVMADRH:NVMADRL register pair

(Table 11-2).

3. Set the RD bit of the NVMCON1 register to

initiate the read.

Once the read control bit is set, the CPU operation is

suspended during the read, and resumes immediately

after. The data is available in the very next cycle, in the

NVMDATH:NVMDATL register pair; therefore, it can be

read as two bytes in the following instructions.

NVMDATH:NVMDATL register pair will hold this value

until another read or until it is written to by the user.

Upon completion, the RD bit is cleared by hardware.

FIGURE 11-1: PROGRAM FLASH

MEMORY READ

FLOWCHART

EXAMPLE 11-1: PROGRAM FLASH MEMORY READ

End Read Operation

Select Memory:

Program Flash Memory, EEPROM,

Config. Words, User ID (NVMREGS)

Select Word Address

(NVMADRH:NVMADRL)

Start Read Operation

Initiate Read Operation

(RD = 1)

Data read now in

NVMDATH:NVMDATL

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

* data will be returned in the variables;

* PROG_DATA_HI, PROG_DATA_LO

BANKSEL NVMADRL ; Select Bank for NVMCON registers

MOVLW PROG_ADDR_LO ;

MOVWF NVMADRL ; Store LSB of address

MOVLW PROG_ADDR_HI ;

MOVWF NVMADRH ; Store MSB of address

BCF NVMCON1,NVMREGS ; Do not select Configuration Space

BSF NVMCON1,RD ; Initiate read

MOVF NVMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location

MOVF NVMDATH,W ; Get MSB of word

MOVWF PROG_DATA_HI ; Store in user location

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11.4.2 NVM UNLOCK SEQUENCE

The unlock sequence is a mechanism that protects the

NVM from unintended self-write programming or eras-

ing. The sequence must be executed and completed

without interruption to successfully complete any of the

following operations:

• Program Flash Memory Row Erase

• Load of Program Flash Memory write latches

• Write of Program Flash Memory write latches to

Program Flash Memory memory

• Write of Program Flash Memory write latches to

user IDs

• Write to EEPROM

The unlock sequence consists of the following steps

and must be completed in order:

• Write 55h to NVMCON2

• Write AAh to NMVCON2

• Set the WR bit of NVMCON1

Once the WR bit is set, the processor will stall internal

operations until the operation is complete and then

resume with the next instruction.

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

FIGURE 11-2: NVM UNLOCK

SEQUENCE FLOWCHART

EXAMPLE 11-2: NVM UNLOCK SEQUENCE

Note: The two NOP instructions after setting the

WR bit, which were required in previous

devices, are not required for

PIC16(L)F18313/18323 devices. See

Figure 11-2.

End Unlock Operation

Write 55h to NVMCON2

Write AAh to NVMCON2

Initiate Write or Erase Operation

(WR = 1)

NOP Instruction

(not required for

PIC16(L)F18313/18323 devices)

NOP Instruction

(not required for

PIC16(L)F18313/18323 devices)

Start Unlock Sequence

Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.

2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

BANKSEL NVMCON1

BSF NVMCON1,WREN ; Enable write/erase

MOVLW 55h ; Load 55h

BCF INTCON,GIE ; Recommended so sequence is not interrupted

MOVWF NVMCON2 ; Step 1: Load 55h into NVMCON2

MOVLW AAh ; Step 2: Load W with AAh

MOVWF NVMCON2 ; Step 3: Load AAh into NVMCON2

BSF NVMC ON 1, WR ; Step 4: Se t WR bit to be gi n wr it e/ er as e

BSF INTC ON ,G IE ; Re-e na bl e in te rr up ts

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11.4.3 NVMREG WRITE TO EEPROM

Writing to the EEPROM is accomplished by the

following steps:

1. Set the NVMREGS and WREN bits of the

NVMCON1 register.

2. Write the desired address (address +7000h) into

the NVMADRH:NVMADRL register pair

(Table 11-2).

3. Perform the unlock sequence as described in

Section 11.4.2 “NVM Unlock Sequence”.

A single EEPROM byte is written with NVMDATA. The

operation includes an implicit erase cycle for that byte

(it is not necessary to set the FREE bit), and requires

many instruction cycles to finish. CPU execution

continues in parallel and, when complete, WR is

cleared by hardware, NVMIF is set, and an interrupt will

occur if NVMIE is also set. Software must poll the WR

bit to determine when writing is complete, or wait for the

interrupt to occur. WREN will remain unchanged.

Once the EEPROM write operation begins, clearing the

WR bit will have no effect; the operation will run to

completion.

11.4.4 NVMREG ERASE OF PROGRAM

FLASH MEMORY

Program Flash memory can only be erased one row at

a time. No automatic erase occurs upon the initiation of

the write to program Flash memory.

To erase a program Flash memory row:

1. Clear the NVMREGS bit of the NVMCON1

locations, or set the NVMREGS bit to erase user

ID locations.

2. Write the desired address into the

NVMADRH:NVMADRL register pair

(Table 11-2).

3. Set the FREE and WREN bits of the NVMCON1

4. Perform the unlock sequence as described in

Section 11.4.2 “NVM Unlock Sequence”.

If the program Flash memory address is write-pro-

tected, the WR bit will be cleared and the erase opera-

tion will not take place.

While erasing program Flash memory, CPU operation

is suspended, and resumes when the operation is

complete. Upon completion, the NVMIF is set, and an

interrupt will occur if the NVMIE bit is also set.

Write latch data is not affected by erase operations,

and WREN will remain unchanged.

FIGURE 11-3: NVM ERASE

FLOWCHART

Unlock Sequence

(Figure 11-2)

End Erase Operation

Select Memory:

Program Flash Memory, Config.

Words, User ID (NVMREGS)

Disable Write/Erase Operation

(WREN = 0)

Select Word Address

(NVMADRH:NVMADRL)

Start Erase Operation

CPU stalls while Erase operation

completes (2 ms typical)

Select Erase Operation

(FREE = 1)

Disable Interrupts

(GIE = 0)

Enable Interrupts

(GIE = 1)

Enable Write/Erase Operation

(WREN = 1)

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EXAMPLE 11-3: ERASING ONE ROW OF PROGRAM FLASH MEMORY

; This sam pl e ro w er as e ro ut in e as su me s th e fo ll ow in g:

; 1.A vali d ad dr es s wi th in the era se row is lo ad ed in va ri ab le s AD DR H: AD DR L

; 2.ADDR H an d AD DR L ar e lo ca te d in com mo n RA M (l oc at io ns 0x7 0 - 0x 7F )

BANKSEL NVMADRL

MOVF ADDRL,W

MOVWF NVMADR L ; L oa d lo we r 8 bi ts of er as e ad dr es s bo un da ry

MOVF ADDRH,W

MOVWF NVMADR H ; L oa d up pe r 6 bi ts of er as e ad dr es s bo un da ry

BCF NVMCON 1, NV MR EG S ; Cho os e Pr og ra m Fl as h Me mo ry are a

BSF NVMCON1,FREE ; Specify an erase operation

BSF NVMCON1,WREN ; Enable writes

BCF INTCON,GIE ; Disable interrupts during unlock sequence

; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------

MOVLW 55h ; Load 55h to get read y for unlock sequence

MOVWF NVMCON2 ; First step is to load 55h into NVMCON2

MOVLW AAh ; S ec on d st ep is to loa d AA h in to W

MOVWF NVMCON2 ; Third step is to load AAh into NVMCON2

BSF NVMCON1,WR ; Final step is to set WR bit

; --------------------------------------------------------------------------------------

BSF INTCON,GIE ; Re-enable interrupts, erase is complete

BCF NVMCON1,WREN ; Disable writes

TABLE 11-2: NVM ORGANIZATION AND ACCESS INFORMATION

Master Values NVMREG A cce ss F SR Access

Memory

Function

Program

Counter (PC),

ICSP™ Address

Memory

Type

NVMREGS

bit

(NVMCON1)

NVMADR

<14:0> Allowed

Operations FSR

Address

FSR

Programming

Address

Reset Vector 0000h

Program

Flash

Memory

0 0000h

READ

WRITE

8000h

READ-ONLY

User Memory 0001h 0 0001h 8001h

0003h 0003h 8003h

INT Vector 0004h 0 0004h 8004h

User Memory 0005h 0 0005h 8005h

17FFh 17FFh FFFFh

User ID

No PC Address

Program

Flash

Memory

1 0000h

READ

No Access

0003h

Reserved — — 0004h —

Rev ID

Program

Flash

Memory

1 0005h

READ

Device ID 1 0006h

CONFIG1 1 0007h

CONFIG2 1 0008h

CONFIG3 1 0009h

CONFIG4 000Ah

User Memory EEPROM 1 7000h READ 7000h READ-ONLY

70FFh WRITE 70FFh

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11.4.5 NVMREG WRITE TO PROGRAM

FLASH MEMORY

Program memory is programmed using the following

steps:

1. Load the address of the row to be programmed

into NVMADRH:NVMADRL.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten.

Program memory can only be erased one row at a time.

No automatic erase occurs upon the initiation of the

write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 11-4 (row writes to program memory with 32

write latches) for more details.

The write latches are aligned to the Flash row address

boundary defined by the upper ten bits of

NVMADRH:NVMADRL,

(NVMADRH<6:0>:NVMADRL<7:5>)

with the lower five bits of NVMADRL, (NVMADRL<4:0>)

determining the write latch being loaded. Write opera-

tions do not cross these boundaries. At the completion

of a program memory write operation, the data in the

write latches is reset to contain 0x3FFF.

The following steps should be completed to load the

write latches and program a row of program memory.

These steps are divided into two parts. First, each write

latch is loaded with data from the

NVMDATH:NVMDATL using the unlock sequence with

LWLO = 1. When the last word to be loaded into the

write latch is ready, the LWLO bit is cleared and the

unlock sequence executed. This initiates the

programming operation, writing all the latches into

Flash program memory.

1. Set the WREN bit of the NVMCON1 register.

2. Clear the NVMREGS bit of the NVMCON1

3. Set the LWLO bit of the NVMCON1 register.

When the LWLO bit of the NVMCON1 register is

‘1’, the write sequence will only load the write

latches and will not initiate the write to Flash

program memory.

4. Load the NVMADRH:NVMADRL register pair

with the address of the location to be written.

5. Load the NVMDATH:NVMDATL register pair

with the program memory data to be written.

6. Execute the unlock sequence (Section 11.4.2

“NVM Unlock Sequence”). The write latch is

now loaded.

7. Increment the NVMADRH:NVMADRL register

pair to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the NVMCON1 register.

When the LWLO bit of the NVMCON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the NVMDATH:NVMDATL register pair

with the program memory data to be written.

11. Execute the unlock sequence (Section 11.4.2

“NVM Unlock Sequence”). The entire program

memory latch content is now written to Flash

program memory.

An example of the complete write sequence is shown in

Example 11-4. The initial address is loaded into the

NVMADRH:NVMADRL register pair; the data is loaded

using indirect addressing.

Note: The special unlock sequence is required

to load a write latch with data or initiate a

Flash programming operation. If the

unlock sequence is interrupted, writing to

the latches or program memory will not be

initiated.

Note: The program memory write latches are

reset to the blank state (0x3FFF) at the

completion of every write or erase

operation. As a result, it is not necessary

to load all the program memory write

latches. Unloaded latches will remain in

the blank state.

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FIGURE 11-4: BLOCK WR ITES TO PROGRAM FLASH MEMORY WITH 32 WRITE LATCHES

6 8

1414

Write Latch #31

1Fh

1414

Program Memory Write Latches

14 14 14

NVMADRH<6:0>

NVMADRL<7:5>

Program Flash Memory

Row

Address

Decode

Addr

Write Latch #30

1Eh

Write Latch #1

01h

Write Latch #0

00h

Addr Addr Addr

000h 001Fh

001Eh

0000h 0001h

001h 003Fh

003Eh

0020h 0021h

002h 005Fh005Eh0040h 0041h

3FEh 7FDFh7FDEh7FC0h 7FC1h

3FFh 7FFFh7FFEh7FE0h 7FE1h

NVMADRL<4:0>

400h 800Bh - 801Fh8000h - 8003h

Configuration

Words

USER ID 0 - 3

8007h – 800Ah8005h -8006h

DEVICE ID

Dev / Rev

reserved reserved

Configuration Memory

NVMREGS = 0

NVMREGS = 1

NVMADRH NVMADRL

7 6 0 7 5 4 0

c4 c3 c2 c1 c0r9 r8 r7 r6 r5 r4 r3-r1 r0r2

NVMDATH NVMDATL

7 5 0 7 0

8004h

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FIGURE 11-5: PROGRAM FLASH MEMORY WRITE FLOWCHART

Start Write Operation

Determine number of

words to be written into

PFM or Configuration

Memory. The number of

words cannot exceed the

number of words per row

(word_cnt)

Select

PFM or Config. Memory

(NVMREGS)

Select Row Address

(NVMADRH:NVMADRL)

Select Write Operation

(FREE = 0)

Load Write Latches Only

(LWLO = 1)

Disable Interrupts

(GIE = 0)

Enable Write/Erase

Operation (WREN = 1)

Load the value to write

(NVMDATH:NVMDATL)

Update the word counter

(word_cnt--)

Last word to write?

Unlock Sequence

No delay when writing to

PFM Latches

Re-enable Interrupts

(GIE = 1)

Write Latches to PFM

(LWLO = 0)

Disable Interrupts

(GIE = 0)

CPU stalls while Write

operation completes

(2 ms typical)

Disable Write/Erase

Operation (WREN = 0)

End Write Operation

Increment Address

(NVMADRH:NVMADRL++)

Unlock Sequence

Re-enable Interrupts

(GIE = 1)

Yes

(Figure 11-2)

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EXAMPLE 11-4: WRITING TO PROGRAM FLASH MEMORY

; This write routine assumes the following:

; 1. 32 words of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

; 5. NVM interrupts are not taken into account

BANKSEL NVMADRH

MOVF ADDRH,W

MOVWF NVMADRH ; Load initial address

MOVF ADDRL,W

MOVWF NVMADRL

MOVLW LOW DATA_ADDR ; Load initial data address

MOVWF FSR0L

MOVLW HIGH DATA_ADDR

MOVWF FSR0H

BCF NVMCON1,NVMREGS ; Set Program Flash Memory as write location

BSF NVMCON1,WREN ; Enable writes

BSF NVMCON1,LWLO ; Load only write latches

LOOP MOVIW FSR0++

MOVWF NVMDATL ; Load first data byte

MOVIW FSR0++

MOVWF NVMDATH ; Load second data byte

MOVF NVMADRL,W

XORLW 0x1F ; Check if lower bits of address are 00000

ANDLW 0x1F ; and if on last of 32 addresses

BTFSC STATUS,Z ; Last of 32 words?

GOTO START_WRITE ; If so, go write latches into memory

CALL UNLOCK_SEQ ; If not, go load latch

INCF NVMADRL,F ; Increment address

GOTO LOOP

START_WRITE

BCF NVMCON1,LWLO ; Latch writes complete, now write memory

CALL UNLOCK_SEQ ; Perform required unlock sequence

BCF NVMCON1,LWLO ; Disable writes

UNLOCK_SEQ

MOVLW 55h

BCF INTCON,GIE ; Disable interrupts

MOVWF NVMCON2 ; Begin unlock sequence

MOVLW AAh

MOVWF NVMCON2

BSF NVMCON1,WR

BSF INTCON,GIE ; Unlock sequence complete, re-enable interrupts

return

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11.4.6 MODIFYING PROGRAM FLASH

MEMORY

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

1. Load the starting address of the row to be

modified.

2. Read the existing data from the row into a RAM

image.

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be

rewritten.

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

FIGURE 11-6: PROGRAM FLASH

MEMORY MODIFY

FLOWCHART

Start

Modify Operation

Read Operation

(Figure x.x)

Erase Operation

(Figure x.x)

Modify Image

The words to be modified are

changed in the RAM image

End

Modify Operation

Write Operation

use RAM image

(Figure x.x)

An image of the entire row read

must be stored in RAM

Figure 11-1

Figure 11-3

Figure 11-5

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11.4.7 NVMREG EEPROM, USER ID,

DEVICE ID AND CONFIGURATION

WORD ACCESS

Instead of accessing program Flash memory, the

EEPROM, the user ID’s, Device ID/Revision ID and

Configuration Words can be accessed when

NVMREGS = 1 in the NVMCON1 register. This is the

region that would be pointed to by PC<15> = 1, but not

all addresses are accessible. Different access may

exist for reads and writes. Refer to Table 11-3.

When read access is initiated on an address outside

the parameters listed in Table 11-3, the NVMDATH:

NVMDATL register pair is cleared, reading back ‘0’s.

TABLE 11-3: EEPROM, USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS

(NVMREGS = 1)

Address Function Read Access Write Access

8000h-8003h User IDs Yes Yes

8005h-8006h Device ID/Revision ID Yes No

8007h-800Ah Configuration Words 1-4 Yes No

F000h-F0FFh EEPROM Yes Yes

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11.4.8 WRITE VERIFY

It is considered good programming practice to verify that

program memory writes agree with the intended value.

Since program memory is stored as a full row, then the

stored program memory contents are compared with the

intended data stored in RAM after the last write is

complete.

FIGURE 11 -7: PROGRAM FLASH

MEMORY VERIFY

FLOWCHART

Start

Verify Operation

Read Operation

End

Verify Operation

This routine assumes that the last row

of data written was from an image

saved in RAM. This image will be used

to verify the data currently stored in

Flash Program Memory.

NVMDAT =

RAM image?

Last Word?

Fail

Verify Operation

Yes

Figure 11-1

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11.4.9 WRERR BIT

The WRERR bit can be used to determine if a write

error occurred.

WRERR will be set if one of the following conditions

occurs:

• If WR is set while the NVMADRH:NMVADRL

points to a write-protected address

• A Reset occurs while a self-write operation was in

progress

• An unlock sequence was interrupted

The WRERR bit is normally set by hardware, but can

be set by the user for test purposes. Once set, WRERR

must be cleared in software.

TABLE 11-4: ACTIONS FOR PROGRAM FLASH MEMORY WHEN WR = 1

Free L WLO Action s for Program Flash M emory when WR = 1Comments

00Write the write latch data to program Flash memory

row. See Section 11.4.4 “NVMREG Erase of Pro-

gram Flash Memory”

• If WP is enabled, WR is cleared

and WRERR is set

• Write latches are reset to 3FFh

• NVMDATH:NVMDATL is ignored

01Copy NVMDATH:NVMDATL to the write latch corre-

sponding to NVMADR LSBs. See Section 11.4.4

“NVMREG Erase of Program Flash Memory”

• Write protection is ignored

• No memory access occurs

1xErase the 32-word row of NVMADRH:NVMADRL

location. See Sec tion 11.4.3 “NVM REG Write to

EEPROM”

• If WP is enabled, WR is cleared

and WRERR is set

• All 32 words are erased

• NVMDATH:NVMDATL is ignored

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11.5 Register Definitions: Program Flash Memory Control

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

NVMDAT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMDAT<7:0>: Read/write value for Least Significant bits of program memory

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— NVMDAT<13:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 NVMDAT<13:8>: Read/write value for Most Significant bits of program memory(1)

Note 1: This byte is ignored when writing to EEPROM.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

NVMADR<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMADR<7:0>: Specifies the Least Significant bits for program memory address

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— NVMADR<14:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘1’

bit 6-0 NVMADR<14:8>: Specifies the Most Significant bits for program memory address

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U-0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HS-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0

— NVMREGS LWLO FREE WRERR WREN WR RD

bit 7 bit 0

Legend: q = Reset value is determined by hardware HS = Hardware set

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 Unimplemented: Read as ‘0’

bit 6 NVMREGS: Configuration Select bit

1 = Access EEPROM, Configuration, user ID and device ID registers

0 = Access program Flash memory

bit 5 LWLO: Load Write Latches Only bit

When FREE = 0:

1 = The next WR command updates the write latch for this word within the row; no memory operation

is initiated.

0 = The next WR command writes data or erases.

Otherwise: The bit is ignored.

bit 4 FREE: Program Flash Memory Erase Enable bit

When NVMREGS:NVMADR points to a program Flash memory location:

1 = Performs an erase operation with the next WR command; the row containing the indicated address

is erased (to all 1s) to prepare for writing.

0 = All erase operations have completed normally

bit 3 WRERR: Program/Erase Error Flag bit (1,2,3)

1 = A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to

one while NVMADR points to a write-protected address.

0 = The program or erase operation completed normally

bit 2 WREN: Program/Erase Enable bit

1 = Allows program/erase cycles

0 = Inhibits programming/erasing of program Flash

bit 1 WR: Write Control bit(4,5,6)

When NVMREG:NVMADR points to a EEPROM location:

1 = Initiates an erase/program cycle at the corresponding EEPROM location

0 = NVM program/erase operation is complete and inactive

When NVMREG:NVMADR points to a program Flash memory location:

1 = Initiates the operation indicated by Tab le 11 -5

0 = NVM program/erase operation is complete and inactive

bit 0 RD: Read Control bit(7)

1 = Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction

cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared)

in software.

0 = NVM read operation is complete and inactive.

Note 1: Bit may change while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).

2: Bit must be cleared by software; hardware will not clear this bit.

3: Bit may be written to ‘1’ by software in order to implement test sequences.

4: This bit can only be set by following the unlock sequence of Sect i on 11. 4.2 “NVM Unlock Seq uence”.

5: Operations are self-timed, and the WR bit is cleared by hardware when complete.

6: Once a write operation is initiated, setting this bit to zero will have no effect.

7: Reading from EEPROM loads only NVMDATL<7:0> (Register 11-1).

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W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0

NVMCON2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NVMCON2<7:0>: Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

NVMCON1 register. The value written to this register is used to unlock the writes.

TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE —————INTEDG 89

PIR2 —C2IF(2) C1IF NVMIF — — — NCO1IF 97

PIE2 —C2IE(2) C1IE NVMIE — — — NCO1IE 92

NVMCON1 —NVMREGS LWLO FREE WRERR WREN WR RD 126

NVMCON2 NVMCON2 127

NVMADRL NVMADR<7:0> 125

NVMADRH —(1) NVMADR<14:8> 125

NVMDATL NVMDAT<7:0> 125

NVMDATH —— NVMDAT<13:8> 125

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.

Note 1: Unimplemented, read as ‘1’.

2: PIC16(L)F18323 only.

TABLE 11-6: SUMMARY OF CONFIGURATION WORD WITH NONVOLATILE MEMORY (NVM)

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11 /3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG3 13:8 — — LVP — — — — — 54

7:0 ——————WRT<1:0>

CONFIG4 13:8 — — — — — — — — 55

7:0 ——————CPDCP

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.

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12.0 I/O PORTS

Each port has ten standard registers for its operation.

These registers are:

• PORTx registers (reads the levels on the pins of

the device)

• LATx registers (output latch)

• TRISx registers (data direction)

• ANSELx registers (analog select)

• WPUx registers (weak pull-up)

• INLVLx (input level control)

• SLRCONx registers (slew rate)

• ODCONx registers (open-drain)

Most port pins share functions with device peripherals,

both analog and digital. In general, when a peripheral

is enabled on a port pin, that pin cannot be used as a

general purpose output; however, the pin can still be

read.

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A write operation to the LATx register has the same

effect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital

input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels

on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A

simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 12-1.

FIGURE 12-1: GENERIC I/O PORT

OPERATION

12.1 I/O Priorities

Each pin defaults to the PORT data latch after Reset.

Other functions are selected with the peripheral pin

select logic. See Sectio n 13.0 “Perip hera l Pin Sele ct

(PPS) Module” for more information.

Analog input functions, such as ADC and comparator

inputs, are not shown in the peripheral pin select lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx register. Digital output

functions may continue to control the pin when it is in

Analog mode.

Analog outputs, when enabled, take priority over the

digital outputs and force the digital output driver to the

high-impedance state.

TABLE 12-1: PORT AVAILABILITY PER

DEVICE

Device

PORTA

PORTC

PIC16(L)F18313 ●

PIC16(L)F18323 ●●

Write LATx

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Read LATx

Data Bus

To digital peripherals

ANSELx

VDD

VSS

To analog peripherals

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12.2 PORTA Registers

12.2.1 DATA REGISTER

PORTA is a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 12-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA3, which is

input-only and its TRIS bit will always read as ‘1’.

Example 12-1 shows how to initialize PORTA.

Reading the PORTA register (Register 12-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

The PORT data latch LATA (Register 12-3) holds the

output port data, and contains the latest value of a

LATA or PORTA write.

EXAMPLE 12-1: INITIALIZI NG PORTA

12.2.2 DIRECTION CONTROL

The TRISA register (Register 12-2) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

inputs always read ‘0’.

12.2.3 OPEN-DRAIN CONTROL

The ODCONA register (Register 12-6) controls the

open-drain feature of the port. Open-drain operation is

independently selected for each pin. When an

ODCONA bit is set, the corresponding port output

becomes an open-drain driver capable of sinking

current only. When an ODCONA bit is cleared, the

corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

12.2.4 SLEW RATE CONTROL

The SLRCONA register (Register 12-7) controls the

slew rate option for each port pin. Slew rate control is

independently selectable for each port pin. When an

SLRCONA bit is set, the corresponding port pin drive is

slew rate limited. When an SLRCONA bit is cleared,

The corresponding port pin drive slews at the maximum

rate available.

12.2.5 INPUT THRESHOLD CONTROL

The INLVLA register (Register 12-8) controls the input

voltage threshold for each of the available PORTA input

pins. A selection between the Schmitt Trigger CMOS or

the TTL Compatible thresholds is available. The input

threshold is important in determining the value of a read

of the PORTA register and also the level at which an

interrupt-on-change occurs, if that feature is enabled.

See Table 35-4 for more information on threshold

levels.

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

BANKSEL PORTA ;

CLRF PORTA ;Clear PORTA

BANKSEL LATA ;Data Latch

CLRF LATA ;

BANKSEL ANSELA ;

CLRF ANSELA ;digital I/O

BANKSEL TRISA ;

MOVLW B'00111000' ;Set RA<5:3> as inputs

MOVWF TRISA ;and set RA<2:0> as

;outputs

Note: It is not necessary to set open-drain

control when using the pin for I2C; the I2C

module controls the pin and makes the pin

open-drain.

Note: Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate a

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

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12.2.6 ANALOG CONTROL

The ANSELA register (Register 12-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

12.2.7 WEAK PULL-UP CONTROL

The WPUA register (Register 12-5) controls the

individual weak pull-ups for each PORT pin.

PORTA pin RA3 includes the MCLR/VPP input. The

MCLR input allows the device to be reset, and can be

disabled by the MCLRE bit of Configuration Word 2. A

weak pull-up is present on the RA3 port pin. This weak

pull-up is enabled when MCLR is enabled (MCLRE = 1)

or the WPUA3 bit is set. The weak pull-up is disabled

when is disabled and the WPUA3 bit is clear.

12.2.8 PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions.

Each pin defaults to the PORT latch data after Reset.

Other output functions are selected with the peripheral

pin select logic. See Section 13.0 “Peripheral Pin

Select (PPS) Module” for more information.

Analog input functions, such as ADC and comparator

inputs are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

Note: The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

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12.3 Re g is ter De finiti o n s : P O R TA

U-0 U-0 R/W-x/u R/W-x/u R-x/u R/W-x/u R/W-x/u R/W-x/u

——RA5RA4RA3

(2) RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

2: Bit RA3 is read-only, and will read ‘1’ when MCLRE = 1 (master clear enabled).

U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1

—— TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

bit 3 Unimplemented: Read as ‘1’

bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

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U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u

——LATA5LATA4— LATA2 LATA1 LATA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)

bit 3 Unimplemented: Read as ‘0’

bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return

of actual I/O pin values.

U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1

—— ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ANSA<5:4>: Analog Select between Analog or Digital Function on pins RA<5:4>, respectively

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

0 = Digital I/O. Pin is assigned to port or digital special function.

bit 3 Unimplemented: Read as ‘0’

bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

0 = Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

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U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— WPUA5 WPUA4 WPUA3(1) WPUA2 WPUA1 WPUA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(2)

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: If MCLRE = 1, the weak pull-up in RA3 is always enabled; bit WPUA3 is not affected.

2: The weak pull-up device is disabled if the pin is configured as an output except when the pin is also config-

ured as open-drain. When configured as open-drain, the pull-up is enabled when the output value is high,

and disabled when the output value is low.

U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

—— ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 ODCA<5:4>: PORTA Open-Drain Enable bits

For RA<5:4> pins, respectively

1 = Port pin operates as open-drain drive (sink current only)

0 = Port pin operates as standard push-pull drive (source and sink current)

bit 3 Unimplemented: Read as ‘0’

bit 2-0 ODCA<2:0>: PORTA Open-Drain Enable bits

For RA<2:0> pins, respectively

1 = Port pin operates as open-drain drive (sink current only)

0 = Port pin operates as standard push-pull drive (source and sink current)

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U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1

—— SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits

For RA<5:4> pins, respectively

1 = Port pin slew rate is limited

0 = Port pin slews at maximum rate

bit 3 Unimplemented: Read as ‘0’

bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits

For RA<2:0> pins, respectively

1 = Port pin slew rate is limited

0 = Port pin slews at maximum rate

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits

For RA<5:0> pins, respectively

1 = ST input used for PORT reads and interrupt-on-change

0 = TTL input used for PORT reads and interrupt-on-change

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TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA

TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 131

TRISA —— TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 131

LATA ——LATA5LATA4— LATA2 LATA1 LATA0 132

ANSELA —— ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 132

WPUA —— WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 133

ODCONA —— ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0 133

SLRCONA —— SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 134

INLVLA —— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 134

Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register

on Page

CONFIG2 13:8 — — DEBUG STVREN PPS1WAY —BORV —53

7:0 BOREN1 BOREN0 LPBOREN — WDTE1 WDTE0 PWRTE MCLRE

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

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12.4 PORTC Registers

12.4.1 DATA REGISTER

PORTC is a bidirectional port that is 6-bits wide. The

corresponding data direction register is TRISC

(Register 12-10). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 12-1 shows how to initialize an I/O port.

Reading the PORTC register (Register 12-9) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

The PORT data latch LATC (Register 12-11) holds the

output port data, and contains the latest value of a LATC

or PORTC write.

12.4.2 DIRECTION CONTROL

The TRISC register (Register 12-10) controls the

PORTC pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISC register are maintained set when using them

as analog inputs. I/O pins configured as analog inputs

always read ‘0’.

12.4.3 INPUT THRESHOLD CONTROL

The INLVLC register (Register 12-16) controls the input

voltage threshold for each of the available PORTC

input pins. A selection between the Schmitt Trigger

CMOS or the TTL Compatible thresholds is available.

The input threshold is important in determining the

value of a read of the PORTC register and also the

level at which an interrupt-on-change occurs, if that

feature is enabled. See Table 35-4 for more information

on threshold levels.

12.4.4 OPEN-DRAIN CONTROL

The ODCONC register (Register 12-14) controls the

open-drain feature of the port. Open-drain operation is

independently selected for each pin. When an

ODCONC bit is set, the corresponding port output

becomes an open-drain driver capable of sinking

current only. When an ODCONC bit is cleared, the

corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

12.4.5 SLEW RATE CONTROL

The SLRCONC register (Register 12-15) controls the

slew rate option for each port pin. Slew rate control is

independently selectable for each port pin. When an

SLRCONC bit is set, the corresponding port pin drive is

slew rate limited. When an SLRCONC bit is cleared,

The corresponding port pin drive slews at the maximum

rate available.

12.4.6 ANALOG CONTROL

The ANSELC register (Register 12-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELC bits has no effect on digital out-

put functions. A pin with TRIS clear and ANSELC set will

still operate as a digital output, but the Input mode will be

analog. This can cause unexpected behavior when exe-

cuting read-modify-write instructions on the affected

port.

12.4.7 WEAK PULL-UP CONTROL

The WPUC register (Register 12-13) controls the

individual weak pull-ups for each PORT pin.

12.4.8 PORTC FUNCTIONS AND OUTPUT

PRIORITIES

Each pin defaults to the PORT latch data after Reset.

Other functions are selected with the peripheral pin

select logic. See Sectio n 13.0 “Perip hera l Pin Sele ct

(PPS) Module” for more information.

Analog output functions, such as ADC and comparator

inputs, are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

Note: Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate a

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

Note: It is not necessary to set open-drain

control when using the pin for I2C; the I2C

module controls the pin and makes the pin

open-drain.

Note: The ANSELC bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

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12.5 Re g is ter De finiti o n s : P O R T C

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

—— RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RC<5:0>: PORTC General Purpose I/O Pin bits(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

return of actual I/O pin values.

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U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISC<5:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

—— LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 LATC<5:0>: PORTC Output Latch Value bits

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U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANSC<5:0>: Analog Select between Analog or Digital Function on pins RC<5:0>, respectively

0 = Digital I/O. Pin is assigned to port or digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 WPUC<5:0>: Weak Pull-up Register bits(1)

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: The weak pull-up is disabled if the pin is configured as an output except when the pin is also configured as

open-drain. When configured as open-drain, the pull-up is enabled when the output value is high, and

disabled when the output value is low.

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U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ODCC<5:0>: PORTC Open-Drain Enable bits

For RC<5:0> pins, respectively

1 = Port pin operates as open-drain drive (sink current only)

0 = Port pin operates as standard push-pull drive (source and sink current)

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 SLRC<5:0>: PORTC Slew Rate Enable bits

For RC<5:0> pins, respectively

1 = Port pin slew rate is limited

0 = Port pin slews at maximum rate

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U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

—— INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 INLVLC<5:0>: PORTC Input Level Select bits

For RC<5:0> pins, respectively

1 = ST input used for PORT reads and interrupt-on-change

0 = TTL input used for PORT reads and interrupt-on-change

TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 137

TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 138

ANSELC — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 139

ODCONC — — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 140

SLRCONC — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 140

INLVLC — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 141

Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

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13.0 PERIPHERAL PIN SELECT

(PPS) MODULE

The Peripheral Pin Select (PPS) module connects

peripheral inputs and outputs to the device I/O pins.

Only digital signals are included in the selections. All

analog inputs and outputs remain fixed to their

assigned pins. Input and output selections are

independent as shown in the simplified block diagram

Figure 13-1.

13.1 PPS Inputs

Each peripheral has a PPS register with which the

inputs to the peripheral are selected. Inputs include the

device pins.

Although every peripheral has its own PPS input selec-

tion register, the selections are identical for every

peripheral as shown in Register 13-1.

13.2 PPS Outputs

Each I/O pin has a PPS register with which the pin

output source is selected. With few exceptions, the port

TRIS control associated with that pin retains control

over the pin output driver. Peripherals that control the

pin output driver as part of the peripheral operation will

override the TRIS control as needed. These

peripherals are:

• EUSART1 (synchronous operation)

• MSSP (I2C)

Although every pin has its own PPS peripheral

selection register, the selections are identical for every

pin as shown in Register 13-2.

FIGURE 13-1: SIMPLIFIED PPS BLOCK DIAGRAM

Note: The notation “xxx” in the register name is

a place holder for the peripheral identifier.

For example, CLC1PPS.

Note: The notation “Rxy” is a place holder for the

pin identifier. For example, RA0PPS.

RA0

Rxy

RA0PPS

RxyPPS

RC7(1)

RC7PPS(1)

PPS Outputs

PPS Inputs

Peripheral abc

Peripheral xyz

abcPPS

xyzPPS

RA0

RC7(1)

Note 1: RB<7:4> and RC<7:6> are available on PIC16(L)F18323 only.

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13.3 Bidirectional Pins

PPS selections for peripherals with bidirectional

signals on a single pin must be made so that the PPS

input and PPS output select the same pin. Peripherals

that have bidirectional signals are:

• EUSART1 (synchronous operation)

• MSSP (I2C)

13.4 PPSLOCKED Bit

The PPS includes a mode in which all input and output

selections can be locked to prevent inadvertent

changes. PPS selections are locked by setting the

PPSLOCKED bit of the PPSLOCK register. Setting and

clearing this bit requires a special sequence as an extra

precaution against inadvertent changes. Examples of

setting and clearing the PPSLOCKED bit are shown in

Example 13-1.

EXAMPLE 13-1: PP S LOCK/UNLOCK

SEQUENCE

13.5 PPS1WAY Bit

The PPS can be locked by setting the PPS1WAY bit of

Configuration Word 2.

When the PPS1WAY bit is set, the PPSLOCKED bit of

the PPSLOCK register can be cleared and set only

one time after a device Reset. Once the PPS registers

are configured, user software sets the PPSLOCKED

bit, preventing any further writes to the PPS registers.

The PPS registers can be read at any time, regardless

of the PPS1WAY or PPSLOCKED settings.

When the PPS1WAY bit is clear, the PPSLOCKED bit

of the PPSLOCK register can be cleared and set

multiple times during code execution, but requires the

PPS lock/unlock sequence to be performed each time

modifications to the PPS registers are made.

13.6 Operation During Sleep

PPS input and output selections are unaffected by

Sleep.

13.7 Effects of a Reset

A device Power-On-Reset (POR) clears all PPS input

and output selections to their default values, and clears

the PPSLOCKED bit of the PPSLOCK register. All other

Resets leave the selections unchanged. Default input

selections are shown in pin allocation Table 1 and

Table 2 .

Note: The I2C default input pins are I2C and

SMBus compatible and are the only pins

on the PIC16(L)F18313/18323 with this

compatibility. Clock and data signals can

be routed to any pin, however pins without

I2C compatibility will operate at standard

TTL/ST logic levels as selected by the

INVLV register.

; suspend interrupts

bcf INTCON,GIE

; BANKSEL PPSLOCK ; set bank

; required sequence, next 5 instructions

movlw 0x55

movwf PPSLOCK

movlw 0xAA

movwf PPSLOCK

; Set PPSLOCKED bit to disable writes or

; Clear PPSLOCKED bit to enable writes

bsf PPSLOCK,PPSLOCKED

; restore interrupts

bsf INTCON,GIE

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13.8 Register Definitions: PPS Input Selection

U-0 U-0 U-0 R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u

— — — xxxPPS<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits

11xxx = Reserved. Do not use.

10111 = Reserved. Do not use.

10110 = Reserved. Do not use.

10101 = Peripheral input is RC5(1)

10100 = Peripheral input is RC4(1)

10011 = Peripheral input is RC3(1)

10010 = Peripheral input is RC2(1)

10001 = Peripheral input is RC1(1)

10000 = Peripheral input is RC0(1)

...

01xxx = Reserved. Do not use.

...

0011x = Reserved. Do not use.

00101 = Peripheral input is RA5

00100 = Peripheral input is RA4

00011 = Peripheral input is RA3

00010 = Peripheral input is RA2

00001 = Peripheral input is RA1

00000 = Peripheral input is RA0

Note 1: PIC16(L)F18323 only.

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U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u

— — — RxyPPS<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits

11111 = Rxy source is DSM

11110 = Rxy source is CLKR

11101 = Rxy source is NCO1

11100 = Rxy source is TMR0

11011 = Reserved

11010 = Reserved

11001 = Rxy source is SDO1/SDA1

11000 = Rxy source is SCK1/SCL1(1)

10111 = Rxy source is C2(2)

10110 = Rxy source is C1

10101 = Rxy source is DT(1)

10100 = Reserved

10011 = Reserved

10010 = Reserved

10001 = Reserved

10000 = Reserved

01111 = Rxy source is CCP4

01110 = Rxy source is CCP3

01101 = Rxy source is CCP2

01100 = Rxy source is CCP1

01011 = Rxy source is CWG1D(1)

01010 = Rxy source is CWG1C(1)

01001 = Rxy source is CWG1B(1)

01000 = Rxy source is CWG1A(1)

00111 = Reserved

00110 = Reserved

00101 = Rxy source is CLC2OUT

00100 = Rxy source is CLC1OUT

00011 = Rxy source is PWM6

00010 = Rxy source is PWM5

00001 = Reserved

00000 = Reserved

Note 1: TRIS control is overridden by the peripheral as required.

2: PIC16(L)F18323 only.

PIC16(L)F18313/18323

DS40001799C-page 146  2015-2017 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0

——————— PPSLOCKED

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 Unimplemented: Read as ‘0’

bit 0 PPSLOCKED: PPS Locked bit

1= PPS is locked. PPS selections can not be changed.

0= PPS is not locked. PPS selections can be changed.

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

PPSLOCK — — — — — — — PPSLOCKED 146

INTPPS — — — INTPPS<4:0> 144

T0CKIPPS — — — T0CKIPPS<4:0> 144

T1CKIPPS — — — T1CKIPPS<4:0> 144

T1GPPS — — — T1GPPS<4:0> 144

CCP1PPS — — — CCP1PPS<4:0> 144

CCP2PPS — — — CCP2PPS<4:0> 144

CWG1PPS — — — CWG1PPS<4:0> 144

MDCIN1PPS — — — MDCIN1PPS<4:0> 144

MDCIN2PPS — — — MDCIN2PPS<4:0> 144

MDMINPPS — — — MDMINPPS<4:0> 144

SSP1CLKPPS — — — SSP1CLKPPS<4:0> 144

SSP1DATPPS — — — SSP1DATPPS<4:0> 144

SSP1SSPPS — — — SSP1SSPPS<4:0> 144

RXPPS — — — RXPPS<4:0> 144

CLCIN0PPS — — — CLCIN0PPS<4:0> 144

CLCIN1PPS — — — CLCIN1PPS<4:0> 144

CLCIN2PPS — — — CLCIN2PPS<4:0> 144

CLCIN3PPS — — — CLCIN3PPS<4:0> 144

RA0PPS — — — RA0PPS<4:0> 145

RA1PPS — — — RA1PPS<4:0> 145

RA2PPS — — — RA2PPS<4:0> 145

RA4PPS — — — RA4PPS<4:0> 145

RA5PPS — — — RA5PPS<4:0> 145

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.

Note 1: PIC16(L)F18323 only.

 2015-2017 Microchip Technology Inc. DS40001799C-page 147

PIC16(L)F18313/18323

RC0PPS(1) — — — RC0PPS<4:0> 145

RC1PPS(1) — — — RC1PPS<4:0> 145

RC2PPS(1) — — — RC2PPS<4:0> 145

RC3PPS(1) — — — RC3PPS<4:0> 145

RC4PPS(1) — — — RC4PPS<4:0> 145

RC5PPS(1) — — — RC5PPS<4:0> 145

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.

Note 1: PIC16(L)F18323 only.

PIC16(L)F18313/18323

DS40001799C-page 148  2015-2017 Microchip Technology Inc.

14.0 PERIPHERAL MODULE

DISABLE

The PIC16(L)F18313/18323 provides the ability to

disable selected modules, placing them into the lowest

possible power mode.

For legacy reasons, all modules are ON by default

following any Reset.

14.1 Disabling a Module

Disabling a module has the following effects:

• All clock and control inputs to the module are

suspended; there are no logic transitions, and the

module will not function.

• The module is held in Reset.

- Writing to the SFRs is disabled

- Reads return 00h

• Analog outputs are disabled; Digital outputs read

‘0’

14.2 Enabling a Module

When the register bit is cleared, the module is re-

enabled and will be in its Reset state; SFR data will

reflect the POR Reset values.

Depending on the module, it may take up to one full

instruction cycle for the module to become active.

There should be no interaction with the module (e.g.,

writing to registers) for at least one instruction after it

has been re-enabled.

14.3 System Clock Disable

Setting SYSCMD (PMD0, Register 14-1) disables the

system clock (FOSC) distribution network to the

peripherals. Not all peripherals make use of SYSCLK,

so not all peripherals are affected. Refer to the specific

peripheral description to see if it will be affected by this

bit.

R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

SYSCMD FVRMD ——— NVMMD CLKRMD IOCMD

7 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SYSCMD: Disable Peripheral System Clock Network bit

See description in Section 14.3 “System Clock Disable”.

1 = System Clock network disabled (a.k.a. FOSC)

0 = System Clock network enabled

bit 6 FVRMD: Disable Fixed Voltage Reference FVR bit

1 = FVR module disabled

0 = FVR module enabled

bit 5-3 Unimplemented: Read as ‘0’

bit 2 NVMMD: NVM Module Disable bit(1)

1 = Data EEPROM reading and writing is disabled; NVMCON registers cannot be written; FSR access

to EEPROM returns zero.

0 = NVM module enabled

bit 1 CLKRMD: Disable Clock Reference CLKR bit

1 = CLKR module disabled

0 = CLKR module enabled

bit 0 IOCMD: Disable Interrupt-on-Change bit, All Ports

1 = IOC module(s) disabled

0 = IOC module(s) enabled

Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.

 2015-2017 Microchip Technology Inc. DS40001799C-page 149

PIC16(L)F18313/18323

R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

NCOMD ———— TMR2MD TMR1MD TMR0MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 NCOMD: Disable Numerically Control Oscillator bit

1 = NCO1 module disabled

0 = NCO1 module enabled

bit 6-3 Unimplemented: Read as ‘0’

bit 2 TMR2MD: Disable Timer TMR2 bit

1 = TMR2 module disabled

0 = TMR2 module enabled

bit 1 TMR1MD: Disable Timer TMR1 bit

1 = TMR1 module disabled

0 = TMR1 module enabled

bit 0 TMR0MD: Disable Timer TMR0 bit

1 = TMR0 module disabled

0 = TMR0 module enabled

PIC16(L)F18313/18323

DS40001799C-page 150  2015-2017 Microchip Technology Inc.

U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 U-0

— DACMD ADCMD — — CMP2MD(1) CMP1MD —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 DACMD: Disable DAC bit

1 = DAC module disabled

0 = DAC module enabled

bit 5 ADCMD: Disable ADC bit

1 = ADC module disabled

0 = ADC module enabled

bit 4-3 Unimplemented: Read as ‘0’

bit 2 CMP2MD: Disable Comparator C2 bit(1)

1 = Comparator C2 module disabled

0 = Comparator C2 module enabled

bit 1 CMP1MD: Disable Comparator C1 bit

1 = Comparator C1 module disabled

0 = Comparator C1 module enabled

bit 0 Unimplemented: Read as ‘0’

Note 1: PIC16(L)F18323 only.

 2015-2017 Microchip Technology Inc. DS40001799C-page 151

PIC16(L)F18313/18323

U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0

— CWG1MD PWM6MD PWM5MD —— CCP2MD CCP1MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 Unimplemented: Read as ‘0’

bit 6 CWG1MD: Disable CWG1 bit

1 = CWG1 module disabled

0 = CWG1 module enabled

bit 5 PWM6MD: Disable PWM6 bit

1 = PWM6 module disabled

0 = PWM6 module enabled

bit 4 PWM5MD: Disable PWM5 bit

1 = PWM5 module disabled

0 = PWM5 module enabled

bit 3-2 Unimplemented: Read as ‘0’

bit 1 CCP2MD: Disable CCP2 bit

1 = CCP2 module disabled

0 = CCP2 module enabled

bit 0 CCP1MD: Disable CCP1 bit

1 = CCP1 module disabled

0 = CCP1 module enabled

PIC16(L)F18313/18323

DS40001799C-page 152  2015-2017 Microchip Technology Inc.

U-0 U-0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0

——UART1MD— — — MSSP1MD —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5 UART1MD: Disable EUSART1 bit

1 = EUSART1 module disabled

0 = EUSART1 module enabled

bit 4-2 Unimplemented: Read as ‘0’

bit 1 MSSP1MD: Disable MSSP1 bit

1 = MSSP1 module disabled

0 = MSSP1 module enabled

bit 0 Unimplemented: Read as ‘0’

 2015-2017 Microchip Technology Inc. DS40001799C-page 153

PIC16(L)F18313/18323

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — — CLC2MD CLC1MD DSMMD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-3 Unimplemented: Read as ‘0’

bit 2 CLC2MD: Disable CLC2 bit

1 = CLC2 module disabled

0 = CLC2 module enabled

bit 1 CLC1MD: Disable CLC1 bit

1 = CLC1 module disabled

0 = CLC1 module enabled

bit 0 DSMMD: Disable Data Signal Modulator bit

1 = DSM module disabled

0 = DSM module enabled

PIC16(L)F18313/18323

DS40001799C-page 154  2015-2017 Microchip Technology Inc.

15.0 INTERRUPT-ON-CHANGE

All pins on all ports can be configured to operate as

Interrupt-On-Change (IOC) pins. An interrupt can be

generated by detecting a signal that has either a rising

edge or a falling edge. Any individual pin, or combination

of pins, can be configured to generate an interrupt. The

interrupt-on-change module has the following features:

• Interrupt-on-Change enable

- Rising and falling edge detection

• Individual pin configuration

• Individual pin interrupt flags

Figure 15-1 is a block diagram of the IOC module.

15.1 Enabling the Module

To allow individual pins to generate an interrupt, the

IOCIE bit of the PIE0 register must be set. If the IOCIE

bit is disabled, the edge detection on the pin will still

occur, but an interrupt will not be generated.

15.2 Individual Pin Configuration

For each pin, a rising edge detector and a falling edge

detector are present. To enable a pin to detect a rising

edge, the associated bit of the IOCxP register is set. To

enable a pin to detect a falling edge, the associated bit

of the IOCxN register is set.

A pin can be configured to detect rising and falling

edges simultaneously by setting the associated bits in

both of the IOCxP and IOCxN registers.

15.3 Interrupt Flags

The bits located in the IOCxF registers are status flags

that correspond to the interrupt-on-change pins of each

port. If an expected edge is detected on an appropriately

enabled pin, then the status flag for that pin will be set,

and an interrupt will be generated if the IOCIE bit is set.

The IOCIF bit of the PIR0 register reflects the status of

all IOCxF bits.

15.3.1 CLEARING INTERRUPT FLAGS

The individual status flags, (IOCxF register bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 15-1: CLEA RING INTERRUPT

FLAGS

(PORTA EXAMPLE)

15.4 Operation in Sleep

The interrupt-on-change interrupt event will wake the

device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the affected

IOCxF register will be updated prior to the first instruction

executed out of Sleep.

MOVLW 0xff

XORWF IOCAF, W

ANDWF IOCAF, F

 2015-2017 Microchip Technology Inc. DS40001799C-page 155

PIC16(L)F18313/18323

FIGURE 15-1: INTERRUP T-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)

IOCANx

IOCAPx

Q4Q1

data bus =

0 or 1

write IOCAFx

IOCIE

to data bus

IOCAFx

edge

detect

IOC interrupt

to CPU core

from all other

IOCnFx individual

pin detectors

RAx

Rev . 10-000 037A

6/2/201 4

PIC16(L)F18313/18323

DS40001799C-page 156  2015-2017 Microchip Technology Inc.

15.5 Register Definitions: Interrupt-on-Change Control

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin

 2015-2017 Microchip Technology Inc. DS40001799C-page 157

PIC16(L)F18313/18323

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

—— IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits

1 = An enabled change was detected on the associated pin

Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling

edge was detected on RAx.

0 = No change was detected, or the user cleared the detected change.

PIC16(L)F18313/18323

DS40001799C-page 158  2015-2017 Microchip Technology Inc.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCCP<5:0>: Interrupt-on-Change PORTC Positive Edge Enable bits(1)

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag

will be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin

Note 1: PIC16(L)F18323 only.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

—— IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCCN<5:0>: Interrupt-on-Change PORTC Negative Edge Enable bits(1)

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will

be set upon detecting an edge.

0 = Interrupt-on-Change disabled for the associated pin

Note 1: PIC16(L)F18323 only.

 2015-2017 Microchip Technology Inc. DS40001799C-page 159

PIC16(L)F18313/18323

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

—— IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCCF<5:0>: Interrupt-on-Change PORTC Flag bits(1)

1 = An enabled change was detected on the associated pin.

Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a

falling edge was detected on RCx.

0 = No change was detected, or the user cleared the detected change.

Note 1: PIC16(L)F18323 only.

TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA —— ANSA4 ANSA4 — ANSA2 ANSA1 ANSA0 132

ANSELC(1) — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

TRISA —— TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 131

TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

INTCON GIE PEIE —————INTEDG89

PIE0 — — TMR0IE IOCIE ———INTE 90

IOCAP —— IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 156

IOCAN —— IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 156

IOCAF —— IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 157

IOCCP(1) —— IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 158

IOCCN(1) —— IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 158

IOCCF(1) —— IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 159

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

PIC16(L)F18313/18323

DS40001799C-page 160  2015-2017 Microchip Technology Inc.

16.0 FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR subsystem can be configured to supply a

reference voltage to the following:

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

16.1 Independent Gain Amplifiers

The output of the FVR, which is supplied to the ADC,

Comparators and DAC, is routed through two

independent programmable gain amplifiers. Each

amplifier can be programmed for a gain of 1x, 2x or 4x,

to produce the three possible voltage levels.

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module.

Reference Section 22.0 “Analog-to-Digital Con-

verter (ADC) Module” for additional information.

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the DAC and comparator

module. Reference Section 24.0 “5-bit Digi-

tal-to-Analog Converter (DAC1) Module” and

Section 18.0 “Comparator Module” for additional

information.

16.2 FVR St abilization Peri od

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. See Table 35-16 for FVR start-up times.

FIGURE 16-1: VOLTAGE REFERENCE BLOCK DIAGRAM

Note: Fixed Voltage Reference output cannot

exceed VDD.

ADFVR<1:0>

CDAFVR<1:0>

FVR_buffer1

(To ADC Module)

FVR_buffer2

(To Comparators

and DAC)

FVREN FVRRDY

Note 1

Rev . 10-000 053C

12/9 /201 3

Note: Any peripheral requiring the fixed reference (see Tab le 16-1).

 2015-2017 Microchip Technology Inc. DS40001799C-page 161

PIC16(L)F18313/18323

16.3 Register Definitions: FVR Control

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

FVREN FVRRDY(1) TSEN(3) TSRNG(3) CDAFVR<1:0> ADFVR<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled

0 = Fixed Voltage Reference is disabled

bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)

1 = Fixed Voltage Reference output is ready for use

0 = Fixed Voltage Reference output is not ready or not enabled

bit 5 TSEN: Temperature Indicator Enable bit(3)

1 = Temperature Indicator is enabled

0 = Temperature Indicator is disabled

bit 4 TSRNG: Temperature Indicator Range Selection bit(3)

1 =VOUT = VDD - 4VT (High Range)

0 =V

OUT = VDD - 2VT (Low Range)

bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits

11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2)

10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2)

01 = Comparator FVR Buffer Gain is 1x, (1.024V)

00 = Comparator FVR Buffer is off

bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit

11 = ADC FVR Buffer Gain is 4x, (4.096V)(2)

10 = ADC FVR Buffer Gain is 2x, (2.048V)(2)

01 = ADC FVR Buffer Gain is 1x, (1.024V)

00 = ADC FVR Buffer is off

Note 1: FVRRDY is always ‘1’.

2: Fixed Voltage Reference output cannot exceed VDD.

3: See Section 17.0 “Temperature Indicator Module” for additional information.

PIC16(L)F18313/18323

DS40001799C-page 162  2015-2017 Microchip Technology Inc.

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 161

ADCON0 CHS<5:0> GO/DONE ADON 225

ADCON1 ADFM ADCS<2:0> —ADNREF ADPREF<1:0> 226

CMxCON1 CxINTP CxINTN CxPCH<2:0> CxNCH<2:0> 172

DAC1CON0 DAC1EN —DAC1OE — DAC1PPS<1:0> —DAC1NSS 244

Legend: Shaded cells are not used with the Fixed Voltage Reference.

 2015-2017 Microchip Technology Inc. DS40001799C-page 163

PIC16(L)F18313/18323

17.0 TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die. The circuit’s range of operating

temperature falls between -40°C and +85°C. The

output is a voltage that is proportional to the device

temperature. The output of the temperature indicator is

internally connected to the device ADC.

The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,

depending on the level of calibration performed. A one-

point calibration allows the circuit to indicate a

temperature closely surrounding that point. A two-point

calibration allows the circuit to sense the entire range

of temperature more accurately. Reference Application

Note AN2092, “Using the Temperature Indicator

Module” (DS00002092) for more details regarding the

calibration process.

17.1 Circuit Operation

Figure 17-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is

achieved by measuring the forward voltage drop across

multiple silicon junctions.

Equation 17-1 describes the output characteristics of

the temperature indicator.

EQUATION 17-1: VOUT RANGES

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 16.0 “Fixed Voltage Reference (FVR)” for

more information.

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no

current.

The circuit operates in either high or low range. The high

range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This

provides more resolution over the temperature range.

This range requires a higher bias voltage to operate and

thus, a higher VDD is needed.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

voltage drop and thus, a lower VDD voltage is needed to

operate the circuit. The low range is provided for low

voltage operation.

FIGURE 17-1: TEMPERATURE CIRCUIT

DIAGRAM

17.2 Minimum Operating VDD

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications.

When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high

enough to ensure that the temperature circuit is

correctly biased.

Table 17-1 shows the recommended minimum VDD vs.

range setting.

17.3 Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is provided for

the temperature circuit output. Refer to Section 22.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

High Range: VOUT = VDD - 4VT

Low R ange: VOUT = VDD - 2VT

TABLE 17-1: RECOMMENDED VDD VS.

RANGE

Min. VDD, TSRNG = 1Min. VDD, TSRNG = 0

3.6V 1.8V

TSEN

TSRNG

VDD

VOUT To A DC

Temp. Indicator

PIC16(L)F18313/18323

DS40001799C-page 164  2015-2017 Microchip Technology Inc.

17.4 ADC Acquisition Time

To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input

multiplexer is connected to the temperature indicator

output before the conversion is performed.

TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 161

Legend: Shaded cells are unused by the temperature indicator module.

 2015-2017 Microchip Technology Inc. DS40001799C-page 165

PIC16(L)F18313/18323

18.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

• Programmable input selection

- Selectable voltage reference

• Programmable output polarity

• Rising/falling output edge interrupts

• Wake-up from Sleep

• CWG Auto-shutdown source

18.1 Comparator Overview

A single comparator is shown in Figure 18-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

The comparators available for this device are located in

Table 18-1.

FIGURE 18-1: SI NGLE COMPARATOR

TABLE 18-1: AVAILABLE COMP ARATORS

Device C1 C2

PIC16(L)F18313 ●

PIC16(L)F18323 ●●

–

VIN+

VIN-Output

Output

VIN+

VIN-

Note: The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

PIC16(L)F18313/18323

DS40001799C-page 166  2015-2017 Microchip Technology Inc.

FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000027M

9/20/2016

CxIN0-

CxIN1-

CxIN0+

FVR_buffer2

DAC_output

CxVN

CxVP

CxPCH<2:0>

CxNCH<2:0>

CxON(1)

CxSP CxHYS

Interrupt

Rising

Edge

CxINTP

CxINTN

CxOUT

MCxOUT

CxSYNC

set bit

CxIF

TRIS bit

CxOUT

CxOUT_sync

Interrupt

Falling

Edge

FVR_buffer2

CxPOL

(From Timer1 Module) T1CLK

peripherals

Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

000

011

010

001

100

101

110

111

Reserved

CxIN2-

CxIN3-

PPS

RxyPPS

000

011

010

001

100

101

110

111

Reserved

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PIC16(L)F18313/18323

18.2 Comparator Control

Each comparator has two control registers: CMxCON0

and CMxCON1.

The CMxCON0 register (see Register 18-1) contains

Control and Status bits for the following:

• Enable

•Output

• Output polarity

• Hysteresis enable

• Timer1 output synchronization

The CMxCON1 register (see Register 18-2) contains

Control bits for the following:

• Interrupt on positive/negative edge enables

• Positive input channel selection

• Negative input channel selection

18.2.1 COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

18.2.2 COMPARATOR OUTPUT

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register.

The comparator output can also be routed to an

external pin through the RxyPPS register

(Register 13-2). The corresponding TRIS bit must be

clear to enable the pin as an output.

18.2.3 COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Table 18-2 shows the output state versus input

conditions, including polarity control.

18.3 Comparator Hysteresis

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

See Comparator Specifications in Table 35-14 for more

information.

18.4 Timer1 Gate Operation

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 27.5 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

It is recommended that the comparator output be

synchronized to Timer1. This ensures that Timer1 does

not increment while a change in the comparator is

occurring.

18.4.1 COMPARATOR OUTPUT

SYNCHRONIZATION

The output from a comparator can be synchronized

with Timer1 by setting the CxSYNC bit of the

CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. This allows the

timer/counter to synchronize with the CxOUT bit so that

the software sees no ambiguity due to timing. See the

Comparator Block Diagram (Figure 18-2) and the

Timer1 Block Diagram (Figure 27-1) for more

information.

Note 1: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 18-2: COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition CxPOL CxOUT

CxVN > CxVP00

CxVN < CxVP01

CxVN > CxVP11

CxVN < CxVP10

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DS40001799C-page 168  2015-2017 Microchip Technology Inc.

18.5 Comparator Interrupt

An interrupt can be generated when either the rising

edge or falling edge detector detects a change in the

output value of each comparator.

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, you must set the following bits:

• CxON bit of the CMxCON0 register

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

18.6 Comparator Positive Input

Selection

Configuring the CxPCH<2:0> bits of the CMxCON1

analog pin to the non-inverting input of the comparator:

• CxIN0+ analog pin

• DAC output

• FVR (Fixed Voltage Reference)

•V

SS (Ground)

See Section 16.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Se ction 24.0 “ 5-bi t Digital-to-Analog Conv erter

(DAC1) Module” for more information on the DAC

input signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

18.7 Comparator Negative Input

Selection

The CxNCH<2:0> bits of the CMxCON1 register direct

an analog input pin and internal reference voltage or

analog ground to the inverting input of the comparator:

•CxIN- pin

• FVR (Fixed Voltage Reference)

• Analog Ground

18.8 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage

Reference Specifications in Table 35-14 for more

details.

Note: Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching

the comparator on or off with the CxON bit

of the CMxCON0 register.

Note: To use CxINy+ and CxINy- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

 2015-2017 Microchip Technology Inc. DS40001799C-page 169

PIC16(L)F18313/18323

18.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 18-3. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is

forward biased and a latch-up may occur.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

FIGURE 18-3: ANALOG INPUT MODEL

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

provide an input based on their level as

either a TTL or ST input buffer.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

Rs < 10K

CPIN

5 pF

VDD

VT  0.6V

RIC

ILEAKAGE(1)

Vss

Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA= Analog Voltage

VT= Threshold Voltage

To Comparator

Note 1: See I/O Ports in Table 35-4.

Analog

Input

PIC16(L)F18313/18323

DS40001799C-page 170  2015-2017 Microchip Technology Inc.

18.10 CWG Auto-shutdown Source

The output of the comparator module can be used as

an auto-shutdown source for the CWG module. When

the output of the comparator is active and the

corresponding ASxE is enabled, the CWG operation

will be suspended immediately (Section 20.7.1.2

“External Input Source Shutdown”).

18.11 Operation in Sleep Mode

The comparator module can operate during Sleep. The

comparator clock source is based on the Timer1 clock

source. If the Timer1 clock source is either the system

clock (FOSC) or the instruction clock (FOSC/4), Timer1

will not operate during Sleep, and synchronized

comparator outputs will not operate.

A comparator interrupt will wake the device from Sleep.

The CxIE bits of the PIE2 register must be set to enable

comparator interrupts.

 2015-2017 Microchip Technology Inc. DS40001799C-page 171

PIC16(L)F18313/18323

18.12 Register Definitions: Comparator Control

R/W-0/0 R-0/0 U-0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0

CxON CxOUT —CxPOL —CxSP CxHYS CxSYNC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled

0 = Comparator is disabled and consumes no active power

bit 6 CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):

1 = CxVP < CxVN

0 = CxVP > CxVN

If CxPOL = 0 (non-inverted polarity):

1 = CxVP > CxVN

0 = CxVP < CxVN

bit 5 Unimplemented: Read as ‘0’

bit 4 CxPOL: Comparator Output Polarity Select bit

1 = Comparator output is inverted

0 = Comparator output is not inverted

bit 3 Unimplemented: Read as ‘0’

bit 2 CxSP: Comparator Speed/Power Select bit

1 = Comparator operates in Normal-Power, High-Speed mode

0 = Reserved. (do not use)

bit 1 CxHYS: Comparator Hysteresis Enable bit

1 = Comparator hysteresis enabled

0 = Comparator hysteresis disabled

bit 0 CxSYNC: Comparator Output Synchronous Mode bit

1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0 = Comparator output to Timer1 and I/O pin is asynchronous

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CxINTP CxINTN CxPCH<2:0> CxNCH<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0 = No interrupt flag will be set on a positive going edge of the CxOUT bit

bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0 = No interrupt flag will be set on a negative going edge of the CxOUT bit

bit 5-3 CxPCH<2:0>: Comparator Positive Input Channel Select bits

111 = CxVP connects to VSS

110 = CxVP connects to FVR Buffer 2

101 = CxVP connects to DAC output

100 = CxVP unconnected

011 = CxVP unconnected

010 = CxVP unconnected

001 = CxVN unconnected

000 = CxVP connects to CxIN0+ pin

bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits

111 = CxVN connects to VSS

110 = CxVN connects to FVR Buffer 2

101 = CxVN unconnected

100 = CxVN unconnected

011 = CxVN connects to CxIN3- pin(1)

010 = CxVN connects to CxIN2- pin(1)

001 = CxVN connects to CxIN1- pin

000 = CxVN connects to CxIN0- pin

Note 1: PIC16(L)F18323 only.

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PIC16(L)F18313/18323

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0

— — — — — — MC2OUT(1) MC1OUT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MC2OUT: Mirror Copy of C2OUT bit(1)

bit 0 MC1OUT: Mirror Copy of C1OUT bit

Note 1: PIC16(L)F18323 only.

TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

TRISA ― ― TRISA5 TRISA4 ―TRISA2 TRISA1 TRISA0 131

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

CMxCON0 CxON CxOUT ―CxPOL ―CxSP CxHYS CxSYNC 171

CMxCON1 CxINTP CxINTN CxPCH<2:0> CxNCH<2:0> 172

CMOUT ― ― ― ― ― ― MC2OUT(1) MC1OUT 173

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 161

DACCON0 DAC1EN ―DAC1OE ―DAC1PSS<1:0> ―DAC1NSS 244

DACCON1 ― ― ― DAC1R<4:0> 245

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIE2 ―C2IE(1) C1IE NVMIE ― ― ― NCO1IE 92

PIR2 ―C2IF(1) C1IF NVMIF ― ― ― NCO1IF 97

CLCINxPPS ― ― ― CLCINxPPS<4:0> 144

MDMINPPS ― ― ― MDMINPPS<4:0> 144

T1GPPS ― ― ― T1GPPS<4:0> 144

CWG1AS1 ― ― ― ― AS3E AS2E AS1E AS0E 199

Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: PIC16(L)F18323 only.

PIC16(L)F18313/18323

DS40001799C-page 174  2015-2017 Microchip Technology Inc.

19.0 PULSE-WIDTH MODULATION

(PWM)

The PWMx modules generate Pulse Width Modulated

(PWM) signals of varying frequency and duty cycle.

In addition to the CCP modules, the

PIC16(L)F18313/18323 devices contain two PWM

modules.

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the ‘on’ state (pulse width), and the low

portion of the signal is considered the ‘off’ state. The

term duty cycle describes the proportion of the ‘on’ time

to the ‘off’ time and is expressed in percentages, where

0% is fully off and 100% is fully on. A lower duty cycle

corresponds to less power applied and a higher duty

cycle corresponds to more power applied. The PWM

period is defined as the duration of one complete cycle

or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and in turn the power that is applied to the

load.

Figure 19-1 shows a typical waveform of the PWM

signal.

FIGURE 19-1: PWM OUTP UT

19.1 Standard PWM Mode

The standard PWM mode generates a Pulse-Width

Modulation (PWM) signal on the PWMx pin with up to

ten bits of resolution. The period, duty cycle, and

resolution are controlled by the following registers:

• TMR2 register

• PR2 register

•PWMxCON registers

• PWMxDCH registers

• PWMxDCL registers

Figure 29-2, "Compare Mode Operation Block Diagram"

shows a simplified block diagram of the PWM operation.

If PWMPOL = 0, the default state of the output is ‘0‘. If

PWMPOL = 1, the default state is ‘1’. If PWMEN = ‘0’,

the output will be the default state.

Period

Pulse

Width

TMR2 = 0

TMR2 = PWMDC

TMR2 = PR2

Note: The corresponding TRIS bit must be

cleared to enable the PWM output on the

PWMx pin

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PIC16(L)F18313/18323

FIGURE 19-2: SIMPL I FI ED PWM BLOCK DIAGRAM

19.1.1 PWM PERIOD

Referring to Figure 19-1, the PWM output has a period

and a pulse width. The frequency of the PWM is the

inverse of the period (1/period).

The PWM period is specified by writing to the PR2

following formula:

EQUATION 19-1: PWM PERIOD

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

• The PWMx pin is set (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM pulse width is latched from PWMxDC.

19.1.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDC register. The PWMxDCH

contains the eight MSbs and bits <7:6> of the

PWMxDCL register contain the two LSbs.

The PWMDC register is double-buffered and can be

updated at any time. This double buffering is essential

for glitch-free PWM operation. New values take effect

when TMR2 = PR2. Note that PWMDC is left-justified.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two

bits of the prescaler, to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to

1:1.

Equation 19-2 is used to calculate the PWM pulse

width.

Equation 19-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 19-2: PULSE WIDTH

EQUATION 19-3: DUTY CYCLE RATIO

Duty Cycle reg isters

PWMDCH PWMDCL<7:6>

Comparator

TMR2

PR2

Output Polarity

(PWMPOL)

PWMx

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

PWM Pe riod PR21+4TOSC =

(TM R2 Prescale Valu e)

Note: TOSC = 1/FOSC

Pulse Width PWMxDC T

OSC



(TMR2 Prescale Value)

Duty Cycle Ratio PWMxDC

4PR21+

-------------------------------=

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DS40001799C-page 176  2015-2017 Microchip Technology Inc.

19.1.3 PWM RESOLUTION

PWM resolution, expressed in number of bits, defines

the maximum number of discrete steps that can be

present in a single PWM period. For example, a 10-bit

resolution will result in 1024 discrete steps, whereas an

8-bit resolution will result in 256 discrete steps.

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 19-4.

EQUATION 19-4:

19.1.4 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the

PWMx pin is driving a value, it will continue to drive that

value. When the device wakes up, TMR2 will continue

from its previous state.

19.1.5 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 7.0, Oscillator Module for additional details.

19.1.6 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

PWMx registers to their Reset states.

19.1.7 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the module for using the PWMx outputs:

1. Disable the PWMx pin output driver(s) by setting

the associated TRIS bit(s).

2. Configure the PWM output polarity by

configuring the PWMxPOL bit of the PWMxCON

3. Load the PR2 register with the PWM period

value, as determined by Equation 19-1.

4. Load the PWMxDCH register and bits <7:6> of

the PWMxDCL register with the PWM duty cycle

value, as determined by Equation 19-2.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register.

• Select the Timer2 prescale value by

configuring the T2CKPS bit of the T2CON

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Wait until the TMR2IF is set.

7. When the TMR2IF flag bit is set:

• Clear the associated TRIS bit(s) to enable

the output driver.

• Route the signal to the desired pin by

configuring the RxyPPS register.

• Enable the PWMx module by setting the

PWMxEN bit of the PWMxCON register.

In order to send a complete duty cycle and period on

the first PWM output, the above steps must be followed

in the order given. If it is not critical to start with a

complete PWM signal, then the PWM module can be

enabled during Step 2 by setting the PWMxEN bit of the

PWMxCON register.

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

Resolution 4PR21+log 2log

----------------------------------------- bits=

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19.2 Re g is ter De finiti o n s : P W M C o n tr o l

R/W-0/0 U-0 R-0 R/W-0/0 U-0 U-0 U-0 U-0

PWMxEN — PWMxOUT PWMxPOL — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PWMxEN: PWM Module Enable bit

1 = PWM module is enabled

0 = PWM module is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 PWMxOUT: PWM Module Output Level when bit is read.

bit 4 PWMxPOL: PWMx Output Polarity Select bit

1 = PWM output is active-low.

0 = PWM output is active-high.

bit 3-0 Unimplemented: Read as ‘0’

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

PWMxDC<9:2>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PWMxDC<9:2>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.

R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0

PWMxDC<1:0> — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 PWMxDC<1:0>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.

bit 5-0 Unimplemented: Read as ‘0’

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TABLE 19-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 19-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale 1641111

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

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TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWMx

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA —— TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 131

ANSELA — — ANSA5 ANSA4 —ANSA2 ANSA1 ANSA0 132

TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) —— ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

PWM5CON PWM5EN —PWM5OUTPWM5POL— — — — 177

PWM5DCH PWM5DC<9:2> 177

PWM5DCL PWM5DC<1:0> — — — — — — 177

PWM6CON PWM6EN —PWM6OUTPWM6POL— — — — 177

PWM6DCH PWM6DC<9:2> 177

PWM6DCL PWM6DC<1:0> — — — — — — 177

INTCON GIE PEIE — — — — —INTEDG89

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIR2 — C2IF(1) C1IF NVMIF — — — NCO1IF 97

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIE2 — C2IE(1) C1IE NVMIE ———NCO1IE 92

T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 279

TMR2 TMR2<7:0> 280

PR2 PR2<7:0> 280

CWG1DAT ————DAT<3:0>

196

CLCxSELy ——LCxDyS<5:0>210

MDSRC ————MDMS<3:0> 253

MDCARH — MDCHPOL MDCHSYN

—MDCH<3:0> 254

MDCARL — MDCLPOL MDCLSYNC —MDCL<3:0> 255

Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

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20.0 COMPLEMENTARY WAVEFORM

GENERATOR (CWG) MODULE

The Complementary Waveform Generator (CWG1)

produces complementary waveforms with dead-band

delay from a selection of input sources.

The CWG1 module has the following features:

• Selectable dead-band clock source control

• Selectable input sources

• Output enable control

• Output polarity control

• Dead-band control with independent 6-bit rising

and falling edge dead-band counters

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

- Auto-shutdown pin override control

20.1 Fundamental Operation

The CWG generates two output waveforms from the

selected input source.

The off-to-on transition of each output can be delayed

from the on-to-off transition of the other output, thereby,

creating a time delay immediately where neither output

is driven. This is referred to as dead time and is covered

in Section 20.6 “Dead-Band Control”.

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. This is

referred to as auto-shutdown and is covered in

Section 20.7 “Auto-Shutdown Control”.

20.2 Operating Modes

The CWG1 module can operate in six different modes,

as specified by the MODE<2:0> bits of the

CWG1CON0 register:

• Half-Bridge mode

• Push-Pull mode

• Asynchronous Steering mode

• Synchronous Steering mode

• Full-Bridge mode, Forward

• Full-Bridge mode, Reverse

All modes accept a single pulse data input, and

provide up to four outputs as described in the following

sections.

All modes include auto-shutdown control as described

in Section 20.11 “Register Definitions: CWG

Control”

20.2.1 HALF-BRIDGE MODE

In Half-Bridge mode, two output signals are generated

as true and inverted versions of the input as illustrated

in Figure 20-1. A non-overlap (dead-band) time is

inserted between the two outputs as described in

Section 20.6 “Dead-Band Control”. Steering modes

are not used in Half-Bridge mode.

The unused outputs, CWG1C and CWG1D, drive

similar signals with polarity independently controlled by

POLC and POLD, respectively.

FIGURE 20-1: CWG1 HALF-BRIDGE MODE OPERATION

Note: Except as noted for Full-bridge mode

(Section 20.2.4 “Full-Bridge Modes”),

mode changes should only be performed

while EN = 0 (Register 20-1).

CWG[

clock

Input

source

CWG[A

CWG[B

Falling Event

Dead Band

Rising Event

Dead Band

Rising Event

Dead Band

Falling Event

Dead Band

Falling Event

Dead Band

Rising Event

Dead Band

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20.2.2 PUSH-PULL MODE

In Push-Pull mode, two output signals are generated,

alternating copies of the input as illustrated in

Figure 20-2. This alternation creates the push-pull

effect required for driving some transformer based

power supply designs. Dead-band control is not used in

Push-Pull mode. Steering modes are not used in

Push-Pull mode.

The push-pull sequencer is reset whenever EN = 0 or

if an auto-shutdown event occurs. The sequencer is

clocked by the first input pulse, and the first output

appears on CWG1A.

The unused outputs CWG1C and CWG1D drive copies

of CWG1A and CWG1B, respectively, but with polarity

controlled by POLC and POLD.

FIGURE 20-2: CWG1 PU SH -PULL MODE OPERATION

20.2.3 STEERING MODES

In both Synchronous and Asynchronous Steering

modes, the modulated input signal can be steered to

any combination of four CWG outputs and a fixed-value

will be presented on all the outputs not used for the

PWM output. Each output has independent polarity,

steering, and shutdown options. Dead-band control is

not used in either Steering mode.

When STRy = 0 (Register 20-5), the corresponding pin

is held at the level defined by SDATy (Register 20-5).

When STRy = 1, the pin is driven by the modulated

input signal.

The POLy bits (Register 20-2) control the signal

polarity only when STRy = 1.

The CWG auto-shutdown operation also applies to

Steering modes as described in Section 20.11

“Register Definitio ns: CWG Control”.

CWG[

clock

CWG[A

CWG[B

Input

source

Note: Only the STRy bits are synchronized; the

DATy (data) bits are not synchronized.

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20.2.3.1 Synchronous Steering Mode

In Synchronous Steering mode (MODE<2:0> bits

=001, Register 20-1), changes to steering selection

registers take effect on the next rising edge of the

modulated data input (Figure 20-3). In Synchronous

Steering mode, the output will always produce a

complete waveform.

FIGURE 20-3: EXAMP LE OF SYNCHRONOUS STEERING (MODE<2:0> = 001)

20.2.3.2 Asynchronous Steering Mode

In Asynchronous mode (MODE<2:0> bits = 000,

instruction cycle that writes to CWG1STR. In

Asynchronous Steering mode, the output signal may

be an incomplete waveform (Register 20-4). This

operation may be useful when the user firmware needs

to immediately remove a signal from the output pin.

FIGURE 20-4: EXAMP LE OF ASY NCHRO NOUS STEERING (MODE<2:0> = 000)

20.2.3.3 Start-up Considerations

The application hardware must use the proper external

pull-up and/or pull-down resistors on the CWG output

pins. This is required because all I/O pins are forced to

high-impedance at Reset.

The POLy bits (Register 20-2) allow the user to choose

whether the output signals are active-high or active-

low.

Rising edge

of input

Rising edge

of input

CWG[A follows CWG[input

CWG[

INPUT

CWG[A

WGSTRA

CWG[

INPUT

CWG[A

WGSTRA

End of Instruction Cycle End of Instruction Cycle

CWG[A follows CWG[input

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20.2.4 FULL-BRIDGE MODES

In Forward and Reverse Full-Bridge modes, three out-

puts drive static values while the fourth is modulated by

the data input. Dead-band control is described in

Section 20.2.3 “Steering Modes” and Section 20.6

“Dead-Band Control”. Steering modes are not used

with either of the Full-Bridge modes.

The mode selection may be toggled between forward

and reverse (changing MODE<2:0>) without clearing

EN.

When connected as shown in Figure 20-5, the outputs

are appropriate for a full-bridge motor driver. Each

CWG output signal has independent polarity control, so

the circuit can be adapted to high-active and low-active

drivers.

FIGURE 20-5: EXAMP LE OF FULL-BRIDGE APPLICA TION

V+

V-

FET

Driver

FET

Driver

FET

Driver

FET

Driver

CWG[A

CWG[B

CWG[C

CWG[D

Load

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20.2.4.1 Full-Bridge Forward Mode

In Full-Bridge Forward mode (MODE<2:0> = 010),

CWG1A is driven to its active state and CWG1D is

modulated while CWG1B and CWG1C are driven to

their inactive state, as illustrated at the top

of Figure 20-6.

20.2.4.2 Full-Bridge Reverse Mode

In Full-Bridge Reverse mode (MODE<2:0> = 011),

CWG1C is driven to its active state and CWG1B is

modulated while CWG1A and CWG1D are driven to

their inactive state, as illustrated at the bottom of

Figure 20-6.

FIGURE 20-6: EXAMPLE OF FULL-BRIDGE OUTPUT

20.2.4.3 Direction Change in Full-Bridge

Mode

In Full-Bridge mode, changing MODE<2:0> controls

the forward/reverse direction. Changes to MODE<2:0>

change to the new direction on the next rising edge of

the modulated input.

A direction change is initiated in software by changing

the MODE<2:0> bits of the CWG1CON0 register. The

sequence is illustrated in Figure 20-7.

• The associated active output CWG1A and the

inactive output CWG1C are switched to drive in

the opposite direction.

• The previously modulated output CWG1D is

switched to the inactive state, and the previously

inactive output CWG1B begins to modulate.

• CWG modulation resumes after the

direction-switch dead band has elapsed.

CWG[A(2)

CWG[B(2)

CWG[C(2)

CWG[D(2)

Period

Pulse Width

(1) (1)

Forward

Mode

Pulse Width

Period

Reverse

Mode

CWG[A(2)

CWG[B(2)

CWG[C(2)

CWG[D(2)

(1) (1)

Note 1: A rising CWG data input creates a rising event on the modulated output.

2: Output signals shown as active-high; all POLy bits are clear.

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20.2.4.4 Dead-Band Delay in Full-Bridge

Mode

Dead-band delay is important when either of the

following conditions is true:

1. The direction of the CWG output changes when

the duty cycle of the data input is at or near

100%, or

2. The turn-off time of the power switch, including

the power device and driver circuit, is greater

than the turn-on time.

The dead-band delay is inserted only when changing

directions, and only the modulated output is affected.

The statically-configured outputs (CWG1A and

CWG1C) are not afforded dead band, and switch

essentially simultaneously.

Figure 20-7 shows an example of the CWG outputs

changing directions from forward to reverse, at near

100% duty cycle. In this example, at time t1, the output

of CWG1A and CWG1D become inactive, while output

CWG1C becomes active. Since the turn-off time of the

power devices is longer than the turn-on time, a shoot-

through current will flow through power devices QC and

QD for the duration of ‘t’. The same phenomenon will

occur to power devices QA and QB for the CWG

direction change from reverse to forward.

If changing the CWG direction at high duty cycle is

required for an application, two possible solutions for

eliminating the shoot-through current are:

1. Reduce the CWG duty cycle for one period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

FIGURE 20-7: EXAMP LE OF PW M DIRECT ION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period Reverse Period

Pulse Width

TON

TOFF

T = TOFF - TON

CWG[A

CWG[B

CWG[C

CWG[D

External Switch C

External Switch D

Potential Shoot-

Through Current

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FIGURE 20-8:

SIMPLIFIED

CWG1

BLOCK DIAGRAM (HALF-BRIDG E MODE, MODE<2:0> =

100

)

Rev. 10-000209A

10/16/2014

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

clock

data in

data out

clock

data in

data out

AS0E

C1OUT

AS1E

AS2E

C2OUT

CLC2

AS3E

SHUTDOWN = 1

REN

SHUTDOWN = 0

POLA

POLB

POLC

POLD

cwg data

FREEZE DQ

cwg data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

Rising Dead-Band Block

Falling Dead-Band Block

cwg data A

cwg data B

Auto-

shutdown

source

SHUTDOWN

CWGxPPS

CLC4

AS4E

CWG DATA

INPUT

CWG CLOCK

cwg data

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FIGURE 20-9:

SIMPLIF IED CWG BLOCK DIAGRAM (PUSH-PULL MODE, MODE <2:0> =

101

)

Rev. 10-000210A

10/16/2014

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

cwg data

CWG DATA

INPUT

SHUTDOWN = 1

REN

SHUTDOWN = 0

POLA

POLB

POLC

POLD

cwg data

FREEZE DQ

cwg data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

cwg data A

cwg data B

Auto-

shutdown

source

SHUTDOWN

AS0E

C1OUT

AS1E

AS2E

C2OUT

CLC2

AS3E

CWGxPPS

CLC4

AS4E

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FIGURE 20-10: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)

Rev. 10-000211A

10/16/2014

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

CWG DATA

INPUT

SHUTDOWN = 1

REN

SHUTDOWN = 0

POLA

POLB

POLC

POLD

cwg data

FREEZE DQ

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

DATD

STRD

DATC

STRC

DATB

STRB

DATA

STRA

cwg data

SHUTDOWN

Auto-

shutdown

source

cwg data D

cwg data C

cwg data B

cwg data A

MODE<2:0> = 000: Asynchronous

MODE<2:0> = 001: Synchronous

AS0E

C1OUT

AS1E

AS2E

C2OUT

CLC2

AS3E

CWGxPPS

CLC4

AS4E

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FIGURE 20-11: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE

MODES)

Rev. 10-000212A

10/16/2014

LSAC<1:0>

LSBD<1:0>

LSAC<1:0>

LSBD<1:0>

cwg data

CWG CLOCK clock

signal in

signal out

clock

signal in

signal out

CWGx DATA

INPUT

SHUTDOWN = 1

REN

SHUTDOWN = 0

POLA

POLB

POLC

POLD

cwg data

FREEZE DQ

cwg data

CWGxD

CWGxC

CWGxB

CWGxA

‘1’

‘0’

‘1’

‘0’

High-Z

Rising Dead-Band Block

Falling Dead-Band Block

cwg data A

cwg data B

Auto-

shutdown

source

SHUTDOWN

MODE<2:0> = 010: Forward

MODE<2:0> = 011: Reverse

CWG CLOCK

MODE<2:0>

cwg data

cwg data C

cwg data D

AS0E

C1OUT

AS1E

AS2E

C2OUT

CLC2

AS3E

CWGxPPS

CLC4

AS4E

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20.3 Clock Source

The clock source is used to drive the dead-band timing

circuits. The CWG1 module allows the following clock

sources to be selected:

•F

OSC (system clock)

• HFINTOSC (16 MHz only)

When the HFINTOSC is selected the HFINTOSC will

be kept running during Sleep. Therefore, CWG modes

requiring dead band can operate in Sleep provided that

the CWG data input is also active during Sleep. The

clock sources are selected using the CS bit of the

CWG1CLKCON register (Register 20-3).

20.4 Selectable Input Sources

The CWG generates the output waveforms from the

input sources in Table 20-1 .

The input sources are selected using the DAT<3:0>

bits in the CWG1DAT register (Register 20-4).

20.5 Output Control

Immediately after the CWG module is enabled, the

complementary drive is configured with all output

drives cleared.

20.5.1 CWG1 OUTPUTS

Each CWG output can be routed to a Peripheral Pin

Select (PPS) output via the RxyPPS register (see

Section 13.0 “Peripheral Pin Select (PPS)

Module”).

20.5.2 POLARITY CONTROL

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active-low. Clearing the output

polarity bit configures the corresponding output as

active-high. However, polarity does not affect the

override levels. Output polarity is selected with the

POLy bits of the CWG1CON1 register.

20.6 Dead-Band Control

Dead-band control provides for non-overlapping output

signals to prevent current shoot-through in power

switches. The CWG1 modules contain two 6-bit

dead-band counters. These counters can be loaded

with values that will determine the length of the dead

band initiated on either the rising or falling edges of the

input source. Dead-band control is used in either Half-

Bridge or Full-Bridge modes.

The rising-edge dead-band delay is determined by the

rising dead-band count register (Register 20-8,

CWG1DBR) and the falling-edge dead-band delay is

determined by the falling dead-band count register

(Register 20-9, CWG1DBF). Dead-band duration is

established by counting the CWG clock periods from

zero up to the value loaded into either the rising or fall-

ing dead-band counter registers. The dead-band

counters are incremented on every rising edge of the

CWG clock source.

20.6.1 RISING EDGE AND REVERSE

DEAD BAND

In Half-Bridge mode, the rising edge dead band delays

the turn-on of the CWG1A output after the rising edge

of the CWG data input. In Full-Bridge mode, the

reverse dead-band delay is only inserted when

changing directions from Forward mode to Reverse

mode, and only the modulated output CWG1B is

affected.

The CWG1DBR register determines the duration of the

dead-band interval on the rising edge of the input

source signal. This duration is from 0 to 64 periods of

the CWG clock.

Dead band is always initiated on the edge of the input

source signal. A count of zero indicates that no dead

band is present.

If the input source signal reverses polarity before the

dead-band count is completed then no output will be

seen on the respective output.

The CWG1DBR register value is double-buffered. If

EN = 0 (Register 20-1), the buffer is loaded when

CWG1DBR is written. If EN = 1, then the buffer will be

loaded at the rising edge, following the first falling edge

of the data input after the LD bit (Register 20-1) is set.

TABLE 20-1: SELECTABLE INPUT

SOURCES

Source

Peripheral Signal Name

CWG1PPS CWG PPS input connection

C1OUT Comparator 1 output

C2OUT Comparator 2 output

CCP1 Capture/Compare/PWM output

CCP2 Capture/Compare/PWM output

PWM5 PWM5 output

PWM6 PWM6 output

NCO1 Numerically Controlled Oscillator (NCO)

output

CLC1 Configurable Logic Cell 1 output

CLC2 Configurable Logic Cell 2 output

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20.6.2 FALLING EDGE AND FORWARD

DEAD BAND

In Half-Bridge mode, the falling edge dead band delays

the turn-on of the CWG1B output at the falling edge of

the CWG1 data input. In Full-Bridge mode, the forward

dead-band delay is only inserted when changing direc-

tions from Reverse mode to Forward mode, and only

the modulated output CWG1D is affected.

The CWG1DBF register determines the duration of the

dead-band interval on the falling edge of the input

source signal. This duration is from zero to 64 periods

of the CWG clock.

Dead band is always initiated on the edge of the input

source signal. A count of zero indicates that no dead

band is present.

If the input source signal reverses polarity before the

dead-band count is completed, then no output will be

seen on the respective output.

The CWG1DBF register value is double-buffered.

When EN = 0 (Register 20-1), the buffer is loaded when

CWG1DBF is written. If EN = 1, then the buffer will be

loaded at the rising edge following the first falling edge

of the data input after the LD (Register 20-1) is set.

20.6.3 DEAD-BAND JITTER

The CWG input data signal may be asynchronous to

the CWG input clock, so some jitter may occur in the

observed dead band in each cycle. The maximum jitter

is equal to one CWG clock period. See Equation 20-1

for details and an example.

EQUATION 20-1: DEAD-BAND DELAY TIME

CALCULATION

TDEAD BAND_MIN–1

FCWG_CLOCK

--------------------------------- D B x 4 :0>=

TDEAD BAND_MAX–1

FCWG_CLOCK

--------------------------------- D B x 4 :0 > 1+=

TJITTER TDEAD BAND_MAX–TDEAD BAND_MIN–

–=

TJITTER 1

FCWG_CLOCK

---------------------------------=

TDEAD BAND_MAX–TDEAD BAND_MIN–TJITTER

Example:

DBR 4:0> 0x0A 10==

FCWG_CLOCK 8 MHz=

TJITTER 1

8 MHz

------------------=

TDEAD BAND_MIN–125 ns 10 1.25 s==

TDEAD BAND_MAX–1.25 s0.125 s1.37 s=+=

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20.7 Auto-Shutdown Control

Auto-shutdown is a method to immediately override the

CWG output levels with specific overrides that allow for

safe shutdown of the circuit. The shutdown state can

be either cleared automatically or held until cleared by

software.

20.7.1 SHUTDOWN

The shutdown state can be entered by either of the

following two methods:

• Software generated

• External input

The SHUTDOWN bit indicates when a Shutdown con-

dition exists. The bit may be set or cleared in software

or by hardware.

20.7.1.1 Software-Generated Shutdown

Setting the SHUTDOWN bit of the CWG1AS0 register

will force the CWG into the shutdown state.

When auto-restart is disabled, the shutdown state will

persist as long as the SHUTDOWN bit is set.

When auto-restart is enabled, the SHUTDOWN bit will

clear automatically and resume operation on the next

rising edge event.

20.7.1.2 External Input Source Shutdown

Any of the auto-shutdown external inputs can be

selected to suspend the CWG operation. These

sources are individually enabled by the ASxE bits of the

CWG1AS1 register (Register 20-7). When any of the

selected inputs goes active (pins are active-low), the

CWG outputs will immediately switch to the override

levels selected by the LSBD<1:0> and LSAC<1:0> bits

without any software delay (Section 20.7.1.3 “Pin

Override Levels”). Any of the following external input

sources can be selected to cause a Shutdown

condition:

• Comparator C1

• Comparator C2(PIC16(L)F18323 only)

•CLC2

•CWG1PPS

20.7.1.3 Pin Override Levels

The levels driven to the CWG outputs during an auto-

shutdown event are controlled by the LSBD<1:0> and

LSAC<1:0> bits of the CWG1AS0 register (Register 20-

6). The LSBD<1:0> bits control CWG1B/D output

levels, while the LSAC<1:0> bits control the CWG1A/C

output levels.

20.7.1.4 Auto-Shutdown Interrupts

When an auto-shutdown event occurs, either by

software or hardware setting SHUTDOWN, the

CWG1IF flag bit of the PIR4 register is set (Register 8-

11).

20.8 Auto-Shutdown Restart

After an auto-shutdown event has occurred, there are

two ways to resume operation:

• Software controlled

• Auto-restart

In either case, the shut-down source must be cleared

before the restart can take place. That is, either the

Shutdown condition must be removed, or the

corresponding WGASxE bit must be cleared.

20.8.1 SOFTWARE-CONTROLLED

RESTART

If the REN bit of the CWG1ASD0 register is clear

(REN = 0), the CWG1 module must be restarted after

an auto-shutdown event through software.

Once all auto-shutdown conditions are removed, the

software must clear SHUTDOWN. Once SHUTDOWN

is cleared, the CWG module will resume operation

upon the first rising edge of the CWG data input.

20.8.2 AUTO-RESTART

If the REN bit of the CWG1ASD0 register is set

(REN = 1), the CWG1 module will restart from the

shutdown state automatically.

Once all auto-shutdown conditions are removed, the

hardware will automatically clear SHUTDOWN. Once

SHUTDOWN is cleared, the CWG module will resume

operation upon the first rising edge of the CWG data

input.

Note: Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state

cannot be cleared, except by disabling

auto-shutdown, as long as the shutdown

input level persists.

Note: SHUTDOWN bit cannot be cleared in

software if the auto-shutdown condition is

still present.

Note: SHUTDOWN bit cannot be cleared in

software if the auto-shutdown condition is

still present.

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20.9 Operation During Sleep

The CWG1 module will operate during Sleep, provided

that the input sources remain active.

If the HFINTOSC is selected as the module clock

source, dead-band generation will remain active. This

will have a direct effect on the Sleep mode current.

20.10 Configuring the CWG

1. Ensure that the TRIS control bits corresponding

to CWG outputs are set so that all are

configured as inputs, ensuring that the outputs

are inactive during setup. External hardware

should ensure that pin levels are held to safe

levels.

2. Clear the EN bit, if not already cleared.

3. Configure the MODE<2:0> bits of the

CWG1CON0 register to set the output operating

mode.

4. Configure the POLy bits of the CWG1CON1

5. Configure the DAT<3:0> bits of the CWG1DAT

6. If a Steering mode is selected, configure the

STRy bits to select the desired output on the

CWG outputs.

7. Configure the LSBD<1:0> and LSAC<1:0> bits

of the CWG1AS0 register to select the auto-

shutdown output override states (this is

necessary even if not using auto-shutdown

because start-up will be from a shutdown state).

8. If auto-restart is desired, set the REN bit of

CWG1AS0.

9. If auto-shutdown is desired, configure the ASxE

bits of the CWG1AS1 register to select the

shutdown source.

10. Set the desired rising and falling dead-band

times with the CWG1DBR and CWG1DBF

registers.

11. Select the clock source in the CWG1CLKCON

12. Set the EN bit to enable the module.

13. Clear the TRIS bits that correspond to the CWG

outputs to set them as outputs.

14. If auto-restart is to be used, set the REN bit and

the SHUTDOWN bit will be cleared

automatically. Otherwise, clear the

SHUTDOWN bit in software to start the CWG.

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20.11 Register Definitions: CWG Control

R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

EN LD(1) — — —MODE<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Bit is set/cleared by hardware

bit 7 EN: CWG1 Enable bit

1 = CWG1 is enabled

0 = CWG1 is disabled

bit 6 LD: CWG Load Buffers bit(1)

1 = Dead-band count buffers to be loaded on CWG data rising edge following first falling edge after

this bit is set.

0 = Buffers remain unchanged

bit 5-3 Unimplemented: Read as ‘0’

bit 2-0 MODE<2:0>: CWG1 Mode bits

111 = Reserved

110 = Reserved

101 = CWG outputs operate in Push-Pull mode

100 = CWG outputs operate in Half-Bridge mode

011 = CWG outputs operate in Reverse Full-Bridge mode

010 = CWG outputs operate in Forward Full-Bridge mode

001 = CWG outputs operate in Synchronous Steering mode

000 = CWG outputs operate in Asynchronous Steering mode

Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.

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U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — IN —POLD POLC POLB POLA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5 IN: CWG1 Data Input Signal (read-only)

bit 4 Unimplemented: Read as ‘0’

bit 3 POLD: CWG1D Output Polarity bit

1 = Signal output is inverted polarity

0 = Signal output is normal polarity

bit 2 POLC: CWG1C Output Polarity bit

1 = Signal output is inverted polarity

0 = Signal output is normal polarity

bit 1 POLB: CWG1B Output Polarity bit

1 = Signal output is inverted polarity

0 = Signal output is normal polarity

bit 0 POLA: CWG1A Output Polarity bit

1 = Signal output is inverted polarity

0 = Signal output is normal polarity

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0

— — — — — — — CS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-1 Unimplemented: Read as ‘0’

bit 0 CS: CWG Clock Source Selection Select bits

CS Clock Source

0FOSC

1HFINTOSC (remains operating during Sleep)

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U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — DAT<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 DAT<3:0>: CWG Data Input Selection bits

Note 1: PIC16(L)F18323 only; otherwise selection is Reserved.

DAT Data Source

0000 CWG1PPS

0001 C1OUT

0010 C2OUT(1)

0011 CCP1

0100 CCP2

0101 Reserved

0110 Reserved

0111 PWM5

1000 PWM6

1001 NCO1

1010 CLC1

1011 CLC2

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 OVRD: Steering Data D bit

bit 6 OVRC: Steering Data C bit

bit 5 OVRB: Steering Data B bit

bit 4 OVRA: Steering Data A bit

bit 3 STRD: Steering Enable bit D(2)

1 = CWG1D output has the CWG1 data input waveform with polarity control from POLD bit

0 = CWG1D output is assigned to value of OVRD bit

bit 2 STRC: Steering Enable bit C(2)

1 = CWG1C output has the CWG1 data input waveform with polarity control from POLC bit

0 = CWG1C output is assigned to value of OVRC bit

bit 1 STRB: Steering Enable bit B(2)

1 = CWG1B output has the CWG1 data input waveform with polarity control from POLB bit

0 = CWG1B output is assigned to value of OVRB bit

bit 0 STRA: Steering Enable bit A(2)

1 = CWG1A output has the CWG1 data input waveform with polarity control from POLA bit

0 = CWG1A output is assigned to value of OVRA bit

Note 1: The bits in this register apply only when MODE<2:0> = 00x (Register 20-1, steering modes).

2: This bit is double-buffered when MODE<2:0> = 001.

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R/W/HS/SC-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 U-0 U-0

SHUTDOWN REN LSBD<1:0> LSAC<1:0> — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1,2)

1 = An auto-shutdown state is in effect

0 = No auto-shutdown event has occurred

bit 6 REN: Auto-Restart Enable bit

1 = Auto-restart is enabled

0 = Auto-restart is disabled

bit 5-4 LSBD<1:0>: CWG1B and CWG1D Auto-Shutdown State Control bits

11 =A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event occurs.

10 =A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event occurs.

01 = Pin is tri-stated on CWG1B/D when an auto-shutdown event occurs.

00 = The inactive state of the pin, including polarity, is placed on CWG1B/D after the required

dead-band interval when an auto-shutdown event occurs.

bit 3-2 LSAC<1:0>: CWG1A and CWG1C Auto-Shutdown State Control bits

11 =A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event occurs.

10 =A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event occurs.

01 = Pin is tri-stated on CWG1A/C when an auto-shutdown event occurs.

00 = The inactive state of the pin, including polarity, is placed on CWG1A/C after the required

dead-band interval when an auto-shutdown event occurs.

bit 1-0 Unimplemented: Read as ‘0’

Note 1: This bit may be written while EN = 0 (Register 20-1), to place the outputs into the shutdown configuration.

2: The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this

bit is cleared.

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U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— ——— AS3E AS2E(1) AS1E AS0E

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-4 Unimplemented: Read as ‘0’

bit 3 AS3E: CWG Auto-Shutdown Source 3 (CLC2) Enable bit

1 = Auto-shutdown from CLC2 is enabled

0 = Auto-shutdown from CLC2 is disabled

bit 2 AS2E: CWG Auto-Shutdown Source 2 (C2) Enable bit(1)

1 = Auto-shutdown from Comparator 2 is enabled

0 = Auto-shutdown from Comparator 2 is disabled

bit 1 AS1E: CWG Auto-Shutdown Source 1 (C1) Enable bit

1 = Auto-shutdown from Comparator 1 is enabled

0 = Auto-shutdown from Comparator 1 is disabled

bit 0 AS0E: CWG Auto-Shutdown Source 0 (CWG1PPS) Enable bit

1 = Auto-shutdown from CWG1PPS is enabled

0 = Auto-shutdown from CWG1PPS is disabled

Note 1: PIC16(L)F18323 only; otherwise read as ‘0’.

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

——DBR<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 DBR<5:0>: CWG Rising Edge Triggered Dead-Band Count bits

11 1111 = 63-64 CWG clock periods

11 1110 = 62-63 CWG clock periods

00 0010 = 2-3 CWG clock periods

00 0001 = 1-2 CWG clock periods

00 0000 = 0 CWG clock periods. Dead-band generation is bypassed.

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U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

——DBF<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 DBF<5:0>: CWG Falling Edge Triggered Dead-Band Count bits

11 1111 = 63-64 CWG clock periods

11 1110 = 62-63 CWG clock periods

00 0010 = 2-3 CWG clock periods

00 0001 = 1-2 CWG clock periods

00 0000 = 0 CWG clock periods. Dead-band generation is bypassed.

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TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

PIR4 ―CWG1IF ― ― ― ― CCP2IF CCP1IF 99

PIE4 ―CWG1IE ― ― ― ― CCP2IE CCP1IE 94

CWG1CON0 EN LD ― ― ― MODE<2:0> 194

CWG1CON1 ― ― IN ―POLD POLC POLB POLA 195

CWG1CLKCON ― ― ― ― ― ― ― CS 195

CWG1DAT ― ― ― ― DAT<3:0> 196

CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 197

CWG1AS0 SHUTDOWN REN LSBD<1:0> LSAC<1:0> ― ― 198

CWG1AS1 ― ― ― ― AS3E AS2E AS1E AS0E 199

CWG1DBR ― ― DBR<5:0> 199

CWG1DBF ― ― DBF<5:0> 200

CWG1PPS ― ― ― CWG1PPS<4:0> 144

Legend: – = unimplemented location, read as ‘0’. Shaded cells are not used by the CWG1 module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘0’.

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21.0 CONFIGURABLE LOGIC CELL

(CLC)

The Configurable Logic Cell (CLCx) provides

programmable logic that operates outside the speed

limitations of software execution. The logic cell takes up

to 36 input signals and, through the use of configurable

gates, reduces the 32 inputs to four logic lines that drive

one of eight selectable single-output logic functions.

Input sources are a combination of the following:

• I/O pins

• Internal clocks

• Peripherals

•Register bits

The output can be directed internally to peripherals and

to an output pin.

Refer to Figure 21-1 for a simplified diagram showing

signal flow through the CLCx.

Possible configurations include:

• Combinatorial Logic

-AND

-NAND

- AND-OR

- AND-OR-INVERT

-OR-XOR

-OR-XNOR

• Latches

-S-R

- Clocked D with Set and Reset

- Transparent D with Set and Reset

- Clocked J-K with Reset

FIGURE 21-1: CLCx SIMPLIFIED BLOCK DIAGRAM

Input Data Selection Gates(1)

Logic

Function

(2)

lcxg2

lcxg1

lcxg3

lcxg4

LCxMODE<2:0>

lcxq

LCxEN

LCxPOL

det

Interrupt

det

Interrupt

set bit

CLCxIF

LCXINTN

LCXINTP

CLCx

to Peripherals

LCx_out

LCxOUT

MLCxOUT

PPS

Module

LCx_in[0]

LCx_in[1]

LCx_in[2]

LCx_in[29]

LCx_in[30]

LCx_in[3]

Rev. 10-000025,

//201

Note 1: See Figure 21-2.

2: See Figure 21-3.

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21.1 CLCx Setup

Programming the CLCx module is performed by config-

uring the four stages in the logic signal flow. The four

stages are:

• Data selection

• Data gating

• Logic function selection

• Output polarity

Each stage is setup at run time by writing to the

corresponding CLCx Special Function Registers. This

has the added advantage of permitting logic

reconfiguration on-the-fly during program execution.

21.1.1 DATA SELECTION

There are 32 signals available as inputs to the

configurable logic.

Data selection is through four multiplexers as indicated

on the left side of Figure 21-2. Data inputs in the figure

are identified by the ‘LCx_in’ signal name.

Table 21-1 correlates the input number to the actual

signal for each CLC module. The column labeled

‘LCxDyS<4:0> Value’ indicates the MUX selection code

for the selected data input. LCxDyS is an abbreviation to

identify the specific input multiplexer: LCxD1S<4:0>

through LCxD4S<4:0>.

Data inputs are selected with CLCxSEL0 through

CLCxSEL3 registers (Register 21-3 through

TABLE 21-1: CLCx DATA INPUT

SELECTION

CLCxSELy<4:0>

VALUE CLCx INPUT SOURCE

11111 [31] FOSC

11110 [30] HFINTOSC

11101 [29] LFINTOSC

11100 [28] ADCRC

11011 [27] IOCIF int flag bit

11010 [26] TMR2/PR2 match

11001 [25] TMR1 overflow

11000 [24] TMR0 overflow

10111 [23] EUSART (DT) output

10110 [22] EUSART (TX/CK) output

10101 [21] Reserved

10100 [20] Reserved

10011 [19] SDA1

10010 [18] SCL1

10001 [17] PWM6 output

10000 [16] PWM5 output

01111 [15] Reserved

01110 [14] Reserved

01101 [13] CCP2 output

01100 [12] CCP1 output

01011 [11] CLKR output

01010 [10] DSM output

01001 [9] C2(1) output

01000 [8] C1 output

00111 [7] Reserved

00110 [6] Reserved

00101 [5] CLC2 output

00100 [4] CLC1 output

00011 [3] CLCIN3PPS

00010 [2] CLCIN2PPS

00001 [1] CLCIN1PPS

00000 [0] CLCIN0PPS

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21.1.2 INPUT DATA SELECTION GATES

Outputs from the input multiplexers are directed to the

desired logic function input through the data gating

stage. Each data gate can direct any combination of the

four selected inputs.

The gate can be configured to direct each input signal

as inverted or non-inverted data. The output of each

gate can be inverted before going on to the logic

function stage.

The gating is in essence a 1-to-4 input

AND/NAND/OR/NOR gate. When every input is

inverted and the output is inverted, the gate is an OR of

all enabled data inputs. When the inputs and output are

not inverted, the gate is an AND of all enabled inputs.

Table 21-2 summarizes the basic logic that can be

obtained in gate 1 by using the gate logic select bits

and gate polarity bits. The table shows the logic of four

input variables, but each gate can be configured to

use less than four. If no inputs are selected, the output

will be zero or one, depending on the gate output

polarity bit.

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,

the gate output is zero, regardless of the other inputs,

but may emit logic glitches (transient-induced pulses).

If the output of the channel must be zero or one, the

recommended method is to set all gate bits to zero and

use the gate polarity bit to set the desired level.

Data gating is configured with the gate logic select

registers as follows:

• Gate 1: CLCxGLS0 (Register 21-7)

• Gate 2: CLCxGLS1 (Register 21-8)

• Gate 3: CLCxGLS2 (Register 21-9)

• Gate 4: CLCxGLS3 (Register 21-10)

numbers because other variations of this module have

multiple gate selections in the same register.

Data gating is indicated in the right side of Figure 21-2.

Only one gate is shown in detail. The remaining three

gates are configured identically with the exception that

the data enables correspond to the enables for that

gate.

21.1.3 LOGIC FUNCTION

There are eight available logic functions including:

• AND-OR

•OR-XOR

•AND

• S-R Latch

• D Flip-Flop with Set and Reset

• D Flip-Flop with Reset

• J-K Flip-Flop with Reset

• Transparent Latch with Set and Reset

Logic functions are shown in Figure 21-3. Each logic

function has four inputs and one output. The four inputs

are the four data gate outputs of the previous stage.

The output is fed to the inversion stage and from there

to other peripherals, an output pin, and back to the

CLCx itself.

21.1.4 OUTPUT POLARITY

The last stage in the configurable logic cell is the output

polarity. Setting the LCxPOL bit of the CLCxPOL

Changing the polarity while the interrupts are enabled

will cause an interrupt for the resulting output transition.

TABLE 21-2: DATA GATING LOGIC

CLCxGLSy LCxGyPOL Gate Logic

0x55 14-input AND

0x55 04-input NAND

0xAA 14-input NOR

0xAA 04-input OR

0x00 0Logic 0

0x00 1Logic 1

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21.2 CLCx Interrupts

An interrupt will be generated upon a change in the

output value of the CLCx when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in each CLC for this purpose.

The CLCxIF bit of the associated PIR3 register will be

set when either edge detector is triggered and its

associated enable bit is set. The LCxINTP bit enables

rising edge interrupts and the LCxINTN bit enables fall-

ing edge interrupts. Both are located in the CLCxCON

To fully enable the interrupt, set the following bits:

• CLCxIE bit of the PIE3 register

• LCxINTP bit of the CLCxCON register (for a rising

edge detection)

• LCxINTN bit of the CLCxCON register (for a

falling edge detection)

• PEIE and GIE bits of the INTCON register

The CLCxIF bit of the PIR3 register, must be cleared in

software as part of the interrupt service. If another edge

is detected while this flag is being cleared, the flag will

still be set at the end of the sequence.

21.3 Output Mirror Copies

Mirror copies of all LCxCON output bits are contained

in the CLCDATA register. Reading this register

samples the outputs of all CLCs simultaneously. This

prevents any timing skew introduced by testing or

reading the LCxOUT bits in the individual CLCxCON

registers.

21.4 Effects of a Reset

The CLCxCON register is cleared to zero as the result

of a Reset. All other selection and gating values remain

unchanged.

21.5 Operation During Sleep

The CLC module operates independently from the

system clock and will continue to run during Sleep,

provided that the input sources selected remain active.

The HFINTOSC remains active during Sleep when the

CLC module is enabled and the HFINTOSC is

selected as an input source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and as a CLC input

source, when the CLC is enabled, the CPU will go idle

during Sleep, but the CLC will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

21.6 CLCx Setup Steps

The following steps should be followed when setting up

the CLCx:

• Disable CLCx by clearing the LCxEN bit.

• Select desired inputs using CLCxSEL0 through

CLCxSEL3 registers (See Table 21-1).

• Clear any associated ANSEL bits.

• Set all TRIS bits associated with external CLC

inputs.

• Enable the chosen inputs through the four gates

using CLCxGLS0, CLCxGLS1, CLCxGLS2, and

CLCxGLS3 registers.

• Select the gate output polarities with the

LCxGyPOL bits of the CLCxPOL register.

• Select the desired logic function with the

LCxMODE<2:0> bits of the CLCxCON register.

• Select the desired polarity of the logic output with

the LCxPOL bit of the CLCxPOL register. (This

step may be combined with the previous gate out-

put polarity step).

• If driving a device pin, set the desired pin PPS

control register and also clear the TRIS bit

corresponding to that output.

• If interrupts are desired, configure the following

bits:

- Set the LCxINTP bit in the CLCxCON register

for rising event.

- Set the LCxINTN bit in the CLCxCON

- Set the CLCxIE bit of the PIE3 register.

- Set the GIE and PEIE bits of the INTCON

• Enable the CLCx by setting the LCxEN bit of the

CLCxCON register.

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FIGURE 21-2: INPUT DATA SELECTION AND GATING

lcxg1

LCxG1POL

Data GATE 1

LCxD1G1T

lcxg2

lcxg3

lcxg4

Data GATE 2

Data GATE 3

Data GATE 4

LCxD1G1N

LCxD2G1T

LCxD2G1N

LCxD3G1T

LCxD3G1N

LCxD4G1T

LCxD4G1N

LCxD1S<4:0>

LCxD2S<4:0>

LCxD3S<4:0>

LCxD4S<4:0>

LCx_in[0]

LCx_in[31]

00000

11111

Data Selection

lcxd1T

lcxd1N

lcxd2T

lcxd2N

lcxd3T

lcxd3N

lcxd4T

lcxd4N

(Same as Data GATE 1)

LCx_in[0]

LCx_in[31]

00000

11111

LCx_in[0]

LCx_in[31]

00000

11111

LCx_in[0]

LCx_in[35]

00000

11111

Data GATE 3

(Same as Data GATE 1)

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FIGURE 21-3: PROGRAMM ABLE LOGIC FUNCTIONS

lcxg1

lcxg2

lcxg3

lcxg4

lcxq

AND-OR OR-XOR

LCxMODE<2:0> = 000 LCxMODE<2:0> = 001

4-input AND S-R Latch

LCxMODE<2:0> = 010 LCxMODE<2:0> = 011

lcxg1

lcxg2

lcxg3

lcxg4

lcxq

Qlcxq

lcxg1

lcxg2

lcxg3

lcxg4

lcxg1

lcxg2

lcxg3

lcxg4

lcxq

1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R

J-K Flip-Flop with R 1-Input Transparent Latch with S and R

LCxMODE<2:0> = 100 LCxMODE<2:0> = 101

LCxMODE<2:0> = 110 LCxMODE<2:0> = 111

Qlcxq

lcxg1

lcxg2

lcxg3

lcxg4

lcxg1

lcxg2

lcxg3

lcxg4

lcxq

lcxg1

lcxg2

lcxg3

lcxg4

lcxq

lcxg1

lcxg2

lcxg3

lcxg4

Rev. 10-000122A

7/30/2013

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21.7 Register Definitions: CLC Control

R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

LCxEN — LCxOUT LCxINTP LCxINTN LCxMODE<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals

0 = Configurable logic cell is disabled and has logic zero output

bit 6 Unimplemented: Read as ‘0’

bit 5 LCxOUT: Configurable Logic Cell Data Output bit

Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT.

bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit

1 = CLCxIF will be set when a rising edge occurs on CLCxOUT

0 = CLCxIF will not be set

bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit

1 = CLCxIF will be set when a falling edge occurs on CLCxOUT

0 = CLCxIF will not be set

bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits

111 = Cell is 1-input transparent latch with S and R

110 = Cell is J-K flip-flop with R

101 = Cell is 2-input D flip-flop with R

100 = Cell is 1-input D flip-flop with S and R

011 = Cell is S-R latch

010 = Cell is 4-input AND

001 = Cell is OR-XOR

000 = Cell is AND-OR

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R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxPOL: CLCxOUT Output Polarity Control bit

1 = The output of the logic cell is inverted

0 = The output of the logic cell is not inverted

bit 6-4 Unimplemented: Read as ‘0’

bit 3 LCxG4POL: Gate 3 Output Polarity Control bit

1 = The output of gate 3 is inverted when applied to the logic cell

0 = The output of gate 3 is not inverted

bit 2 LCxG3POL: Gate 2 Output Polarity Control bit

1 = The output of gate 2 is inverted when applied to the logic cell

0 = The output of gate 2 is not inverted

bit 1 LCxG2POL: Gate 1 Output Polarity Control bit

1 = The output of gate 1 is inverted when applied to the logic cell

0 = The output of gate 1 is not inverted

bit 0 LCxG1POL: Gate 0 Output Polarity Control bit

1 = The output of gate 0 is inverted when applied to the logic cell

0 = The output of gate 0 is not inverted

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U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — LCxD1S<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD1S<4:0>: CLCx Data1 Input Selection bits

See Table 21-1.

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — LCxD2S<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD2S<4:0>: CLCx Data 2 Input Selection bits

See Table 21-1.

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — LCxD3S<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD3S<4:0>: CLCx Data 3 Input Selection bits

See Table 21-1.

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U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — LCxD4S<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 LCxD4S<4:0>: CLCx Data 4 Input Selection bits

See Table 21-1.

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 0

0 = CLCIN3 (true) is not gated into CLCx Gate 0

bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit

1 = CLCIN3 (inverted) is gated into CLCx Gate 0

0 = CLCIN3 (inverted) is not gated into CLCx Gate 0

bit 5 LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit

1 = CLCIN2 (true) is gated into CLCx Gate 0

0 = CLCIN2 (true) is not gated into CLCx Gate 0

bit 4 LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit

1 = CLCIN2 (inverted) is gated into CLCx Gate 0

0 = CLCIN2 (inverted) is not gated into CLCx Gate 0

bit 3 LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit

1 = CLCIN1 (true) is gated into CLCx Gate 0

0 = CLCIN1 (true) is not gated into CLCx Gate 0

bit 2 LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit

1 = CLCIN1 (inverted) is gated into CLCx Gate 0

0 = CLCIN1 (inverted) is not gated into CLCx Gate 0

bit 1 LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit

1 = CLCIN0 (true) is gated into CLCx Gate 0

0 = CLCIN0 (true) is not gated into CLCx Gate 0

bit 0 LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit

1 = CLCIN0 (inverted) is gated into CLCx Gate 0

0 = CLCIN0 (inverted) is not gated into CLCx Gate 0

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 1

0 = CLCIN3 (true) is not gated into CLCx Gate 1

bit 6 LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit

1 = CLCIN3 (inverted) is gated into CLCx Gate 1

0 = CLCIN3 (inverted) is not gated into CLCx Gate 1

bit 5 LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit

1 = CLCIN2 (true) is gated into CLCx Gate 1

0 = CLCIN2 (true) is not gated into CLCx Gate 1

bit 4 LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit

1 = CLCIN2 (inverted) is gated into CLCx Gate 1

0 = CLCIN2 (inverted) is not gated into CLCx Gate 1

bit 3 LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit

1 = CLCIN1 (true) is gated into CLCx Gate 1

0 = CLCIN1 (true) is not gated into CLCx Gate 1

bit 2 LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit

1 = CLCIN1 (inverted) is gated into CLCx Gate 1

0 = CLCIN1 (inverted) is not gated into CLCx Gate 1

bit 1 LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit

1 = CLCIN0 (true) is gated into CLCx Gate 1

0 = CLCIN0 (true) is not gated into CLCx Gate 1

bit 0 LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit

1 = CLCIN0 (inverted) is gated into CLCx Gate 1

0 = CLCIN0 (inverted) is not gated into CLCx Gate 1

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PIC16(L)F18313/18323

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 2

0 = CLCIN3 (true) is not gated into CLCx Gate 2

bit 6 LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit

1 = CLCIN3 (inverted) is gated into CLCx Gate 2

0 = CLCIN3 (inverted) is not gated into CLCx Gate 2

bit 5 LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit

1 = CLCIN2 (true) is gated into CLCx Gate 2

0 = CLCIN2 (true) is not gated into CLCx Gate 2

bit 4 LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit

1 = CLCIN2 (inverted) is gated into CLCx Gate 2

0 = CLCIN2 (inverted) is not gated into CLCx Gate 2

bit 3 LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit

1 = CLCIN1 (true) is gated into CLCx Gate 2

0 = CLCIN1 (true) is not gated into CLCx Gate 2

bit 2 LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit

1 = CLCIN1 (inverted) is gated into CLCx Gate 2

0 = CLCIN1 (inverted) is not gated into CLCx Gate 2

bit 1 LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit

1 = CLCIN0 (true) is gated into CLCx Gate 2

0 = CLCIN0 (true) is not gated into CLCx Gate 2

bit 0 LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit

1 = CLCIN0 (inverted) is gated into CLCx Gate 2

0 = CLCIN0 (inverted) is not gated into CLCx Gate 2

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit

1 = CLCIN3 (true) is gated into CLCx Gate 3

0 = CLCIN3 (true) is not gated into CLCx Gate 3

bit 6 LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit

1 = CLCIN3 (inverted) is gated into CLCx Gate 3

0 = CLCIN3 (inverted) is not gated into CLCx Gate 3

bit 5 LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit

1 = CLCIN2 (true) is gated into CLCx Gate 3

0 = CLCIN2 (true) is not gated into CLCx Gate 3

bit 4 LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit

1 = CLCIN2 (inverted) is gated into CLCx Gate 3

0 = CLCIN2 (inverted) is not gated into CLCx Gate 3

bit 3 LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit

1 = CLCIN1 (true) is gated into CLCx Gate 3

0 = CLCIN1 (true) is not gated into CLCx Gate 3

bit 2 LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit

1 = CLCIN1 (inverted) is gated into CLCx Gate 3

0 = CLCIN1 (inverted) is not gated into CLCx Gate 3

bit 1 LCxG4D1T: Gate 3 Data 1 True (non-inverted) bit

1 = CLCIN0 (true) is gated into CLCx Gate 3

0 = CLCIN0 (true) is not gated into CLCx Gate 3

bit 0 LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit

1 = CLCIN0 (inverted) is gated into CLCx Gate 3

0 = CLCIN0 (inverted) is not gated into CLCx Gate 3

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PIC16(L)F18313/18323

U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0

— — — — — — MLC2OUT MLC1OUT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 MLC2OUT: Mirror copy of LC2OUT bit

bit 0 MLC1OUT: Mirror copy of LC1OUT bit

TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register

on Page

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR3 OSFIF CSWIF ― ― ― ― CLC2IF CLC1IF 98

PIE3 OSFIE CSWIE ― ― ― ― CLC2IE CLC1IE 93

CLC1CON LC1EN ―LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 208

CLC1POL LC1POL ― ― ― LC1G4POL LC1G3POL LC1G2POL LC1G1POL 209

CLC1SEL0 ― ― ― LC1D1S<4:0> 210

CLC1SEL1 ― ― ― LC1D2S<4:0> 210

CLC1SEL2 ― ― ― LC1D3S<4:0> 210

CLC1SEL3 ― ― ― LC1D4S<4:0> 211

CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 211

CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 212

CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 213

CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 214

CLC2CON LC2EN ―LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 208

CLC2POL LC2POL ― ― ― LC2G4POL LC2G3POL LC2G2POL LC2G1POL 209

CLC2SEL0 ― ― ― LC2D1S<4:0> 210

CLC2SEL1 ― ― ― LC2D2S<4:0> 210

CLC2SEL2 ― ― ― LC2D3S<4:0> 210

CLC2SEL3 ― ― ― LC2D4S<4:0> 211

Legend: — = Unimplemented, read as ‘0’. Shaded cells are unused by the CLC module.

Note 1: PIC16(L)F18323 only.

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CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 211

CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 212

CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 213

CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 214

CLCDATA ― ― ― ― ― ― MLC2OUT MLC1OUT 215

CLCIN0PPS ― ― ― CLCIN0PPS<4:0> 144

CLCIN1PPS ― ― ― CLCIN1PPS<4:0> 144

CLC1OUTPPS ― ― ― CLC1OUTPPS<4:0> 144

CLC2OUTPPS ― ― ― CLC2OUTPPS<4:0> 144

Legend: — = Unimplemented, read as ‘0’. Shaded cells are unused by the CLC module.

Note 1: PIC16(L)F18323 only.

TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (CONTINUED)

Name Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register

on Page

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22.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 22-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 22-1: ADC B LOCK DIAGRAM

VRPOSVRNEG

Enable

DACx_output

FVR_buffer1

Temp Indicator

CHS<4:0>

External

Channel

Inputs

GO/DONE

complete

start

ADC

Sample Circuit

Write to bit

GO/DONE

VSS

VDD

VREF+pin

VDD

ADPREF<1:0>

10-bit Result

ADRESH ADRESL

ADFM

Internal

Channel

Inputs

AN0

ANa

ANz

set bit ADIF

VSS

ADON

sampled

input

Fosc

Divider FOSC

FOSC/n

FRC

ADC

Clock

Select

ADC_clk

ADCS<2:0>

FRC

ADC CLOCK SOURCE

AUTO CONVERSION

TRIGGER

Positive

Reference

Select

Rev. 10-000033E

6/11/2015

ANb

VREF-pin

ADNREF

Negative

Reference

Select

Trigger Select

Trigger Sources

. . .

TRIGSEL<5:0>

FVR BUFFER

RESERVED

PIC16(L)F18313/18323

DS40001799C-page 218  2015-2017 Microchip Technology Inc.

22.1 ADC Configuration

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Result formatting

22.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 12.0 “I/O Ports” for more information.

22.1.2 CHANNEL SELECTION

There are several channel selections available:

• Five PORTA pins (RA0-RA2, RA4-RA5)

• Six PORTC pins (RC0-RC5, PIC16(L)F18323

only)

• Temperature Indicator

• DAC output

• Fixed Voltage Reference (FVR)

•V

SS (ground)

The CHS<5:0> bits of the ADCON0 register

(Register 22-1) determine which channel is connected

to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 22.2

“ADC Operation” for more information.

22.1.3 ADC VOLTAGE REFERENCE

The ADPREF<1:0> bits of the ADCON1 register

provides control of the positive voltage reference. The

positive voltage reference can be:

•V

REF+ pin

•VDD

• FVR 2.048V

• FVR 4.096V (Not available on LF devices)

The ADNREF bit of the ADCON1 register provides

control of the negative voltage reference. The negative

voltage reference can be:

•V

REF- pin

•VSS

See Section 16.0 “Fixed Voltage Reference (FVR)”

for more details on the Fixed Voltage Reference.

22.1.4 CONVERSION CLOCK

The source of the conversion clock is software

selectable via the ADCS<2:0> bits of the ADCON1

•F

OSC/2

•F

OSC/4

•FOSC/8

•FOSC/16

•F

OSC/32

•FOSC/64

• ADCRC (dedicated RC oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 12 TAD periods

as shown in Figure 22-2.

For correct conversion, the appropriate TAD specification

must be met. Refer to Table 35-13 for more information.

Table 22-1 gives examples of appropriate ADC clock

selections.

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

Note: It is recommended that when switching

from an ADC channel of a higher voltage

to a channel of a lower voltage, the

software selects the VSS channel before

switching to the channel of the lower

voltage. If the ADC does not have a

dedicated VSS input channel, the VSS

selection (DAC1R<4:0> = b’00000’)

through the DAC output channel can be

used. If the DAC is in use, a free input

channel can be connected to VSS, and

can be used in place of the DAC.

Note: Unless using the ADCRC, any changes in

the system clock frequency will change

the ADC clock frequency, which may

adversely affect the ADC result.

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FIGURE 22-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TABLE 22-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD) Device Fr equency (FOSC)

ADC

Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s

FOSC/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s4.0 s

FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s2.0 s8.0 s(3)

FOSC/16 101 800 ns 800 ns 1.0 s2.0 s4.0 s16.0 s(3)

FOSC/32 010 1.0 s1.6 s2.0 s4.0 s8.0 s(3) 32.0 s(2)

FOSC/64 110 2.0 s3.2 s4.0 s8.0 s(3) 16.0 s(2) 64.0 s(2)

ADCRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: See TAD parameter for ADCRC source typical TAD value.

2: These values violate the required T

AD time.

3: Outside the recommended TAD time.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived

from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be

performed with the device in Sleep mode.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

Set GO bit

Conversion Starts

Holding capacitor disconnected

from analog input (THCD).

On the following cycle:

ADRESH:ADRESL is loaded,

GO bit is cleared,

ADIF bit is set,

holding capacitor is reconnected to analog input.

b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Enable ADC (ADON bit)

and

Select channel (ACS bits)

THCD

TACQ

PIC16(L)F18313/18323

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22.1.5 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the ADIE bit of the PIE1 register and the

PEIE bit of the INTCON register must both be set and

the GIE bit of the INTCON register must be cleared. If

all three of these bits are set, the execution will switch

to the Interrupt Service Routine.

22.1.6 RESULT FORMATTING

The 10-bit ADC conversion result can be supplied in

two formats, left justified or right justified. The ADFM bit

of the ADCON1 register controls the output format.

Figure 22-3 shows the two output formats.

FIGURE 22-3: 10-BIT ADC CONVERSION RESULT FORMAT

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the ADCRC oscillator is selected.

ADRESH ADRESL

(ADFM = 0)MSB LSB

bit 7 bit 0 bit 7 bit 0

10-bit ADC Result Unimplemented: Read as ‘0’

(ADFM = 1)MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit ADC Result

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22.2 ADC Operation

22.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the

GO/DONE bit of the ADCON0 register to a ‘1’ will start

the Analog-to-Digital conversion.

22.2.2 COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with

new conversion result

22.2.3 TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

22.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the ADCRC

option. When the ADCRC oscillator source is selected,

the ADC waits one additional instruction before starting

the conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

ADCRC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

22.2.5 AUTO-CONVERSION TRIGGER

The Auto-conversion Trigger allows periodic ADC

measurements without software intervention. When a

rising edge of the selected source occurs, the

GO/DONE bit is set by hardware.

The Auto-conversion Trigger source is selected with

the ADACT<4:0> bits of the ADACT register.

See Table 22-2 for auto-conversion sources.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 22.2.6 “ADC Conver-

sion Procedure”.

Note: A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

TABLE 22-2: ADC AUTO-CONVERSION

SOURCES

Source

Peripheral Description

TMR0 Timer0 Overflow condition

TMR1 Timer1 Overflow condition

TMR2 Match between Timer2 and PR2

C1 Comparator C1 output

C2(1) Comparator C2 output

CLC1 CLC1 output

CLC2 CLC2 output

CCP1 CCP1 output

CCP2 CCP2 output

Note 1: PIC16(L)F18323 only.

Note: The ADC auto-conversion feature is not

available while the device is in Sleep

mode

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22.2.6 ADC CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

• Configure pin as analog (Refer to the ANSEL

2. Configure the ADC module:

• Select ADC conversion clock

• Select voltage reference

• Select ADC input channel

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

EXAMPLE 22-1: ADC CONVE RSION

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 22.3 “ADC Acquisi-

tion Requir ements”.

;This code block configures the ADC

;for polling, Vdd and Vss references, ADCRC

;oscillator and AN0 input.

;

;Conversion start & polling for completion ;

are included.

;

BANKSEL ADCON1 ;

MOVLW B’11110000’ ;Right justify, ADCRC

;oscillator

MOVWF ADCON1 ;Vdd and Vss Vref

BANKSEL TRISA ;

BSF TRISA,0 ;Set RA0 to input

BANKSEL ANSEL ;

BSF ANSEL,0 ;Set RA0 to analog

BANKSEL ADCON0 ;

MOVLW B’00000001’ ;Select channel AN0

MOVWF ADCON0 ;Turn ADC On

CALL SampleTime ;Acquisiton delay

BSF ADCON0,ADGO ;Start conversion

BTFSC ADCON0,ADGO ;Is conversion done?

GOTO $-1 ;No, test again

BANKSEL ADRESH ;

MOVF ADRESH,W ;Read upper 2 bits

MOVWF RESULTHI ;store in GPR space

BANKSEL ADRESL ;

MOVF ADRESL,W ;Read lower 8 bits

MOVWF RESULTLO ;Store in GPR space

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22.3 ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 22-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 22-4. The maximum recommended

impedance for analog sources is 10 k. As the

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an ADC acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 22-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

EQUATION 22-1: ACQUISITION TIME EXAMPLE

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

TACQ Amplifier Settling Time Hold Ca pacitor Charging Time Temp erature Coefficient++=

TAMP TCTCOFF++=

2µs TCTemperature - 25°C0.05µs/°C++=

TCCHOLD RIC RSS RS++ ln(1/2047)–=

10pF 1k



10k



++– ln(0.0004885)=

1.37=µs

VAPPLIED 1e

Tc–

---------

–







VAPPLIED 11

2n1+

1–

--------------------------–





VAPPLIED 11

2n1+

1–

--------------------------–





VCHOLD=

VAPPLIED 1e

TC–

----------

–







VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] VCHOLD char ge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following equations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k



5.0V V DD=

Assumptions:

Note: Where n = number of bits of the ADC.

TACQ 2µs 892ns 50°C- 25°C0.05µs/°C++=

4.62µs=

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DS40001799C-page 224  2015-2017 Microchip Technology Inc.

FIGURE 22-4: ANALOG INPUT MODEL

FIGURE 22-5: ADC TRANSFER FUN CTION

CPIN

Analog

5 pF

VDD

VT  0.6V

VT  0.6V I LEAKAGE(1)

RIC  1k

Sampling

Switch

SS Rss

CHOLD = 10 pF

Ref-

Sampling Switch

567891011

(k)

VDD

Legend:

CPIN

I LEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

Note 1: Refer to Table 35-4 (parameter D060).

RSS = Resistance of Sampling Switch

Input

= External series resistanceRs

3FFh

3FEh

ADC Output Code

3FDh

3FCh

03h

02h

01h

00h

Full-Scale

3FBh

0.5 LSB

Ref- Zero-Scale

Transition Ref+

Transition

1.5 LSB

Full-Scale Range

Analog Input Voltage

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22.4 Register Definitions: ADC Control

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CHS<5:0> GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 CHS<5:0>: Analog Channel Select bits

111111 = FVR (Fixed Voltage Reference)(2)

111110 = DAC1 output(1)

111101 = Temperature Indicator(3)

111100 =VSS

111011 = Reserved. No channel connected.

•

010101 = ANC5(4)

010100 = ANC4(4)

010011 = ANC3(4)

010010 = ANC2(4)

010001 = ANC1(4)

010000 = ANC0(4)

001011 = Reserved. No channel connected.

•

000101 =ANA5

000100 =ANA4

000011 = Reserved. No channel connected.

000010 =ANA2

000001 =ANA1

000000 =ANA0

bit 1 GO/DONE: ADC Conversion Status bit

1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.

This bit is automatically cleared by hardware when the ADC conversion has completed.

0 = ADC conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

Note 1: See Section 24.0 “5-bit Digital-to-Analog Converter (DAC1) Module” for more information.

2: See Section 16.0 “Fixed Voltage Reference (FVR)” for more information.

3: See Section 17.0 “Temperature Indicator Module” for more information.

4: PIC16(L)F18323 only.

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0

ADFM ADCS<2:0> — ADNREF ADPREF<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits

111 = ADCRC (dedicated RC oscillator)

110 =F

OSC/64

101 =F

OSC/16

100 =F

OSC/4

011 = ADCRC (dedicated RC oscillator)

010 =FOSC/32

001 =F

OSC/8

000 =F

OSC/2

bit 3 Unimplemented: Read as ‘0’

bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit

When ADON = 0, all multiplexer inputs are disconnected.

0 =V

REF- is connected to VSS

1 =VREF- is connected to external VREF-

bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits

11 =V

REF+ is connected to internal Fixed Voltage Reference (FVR) module(1)

10 =VREF+ is connected to external VREF+ pin(1)

01 = Reserved

00 =V

REF+ is connected to VDD

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage

specification exists. See Table 35-13 for details.

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PIC16(L)F18313/18323

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — ADACT<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 ADACT<3:0>: Auto-Conversion Trigger Selection bits(1)

1111-1110=Reserved

1101 = CCP2

1100 = CCP1

1011 = Reserved

1010 = Reserved

1001 =CLC2

1000 =CLC1

0111 = Comparator C2(3)

0110 = Comparator C1

0101 = Timer2-PR2 match

0100 = Timer1 overflow(2)

0011 = Timer0 overflow(2)

0010 = Reserved

0001 = Reserved

0000 = No auto-conversion trigger selected

Note 1: This is a rising edge sensitive input for all sources.

2: Trigger corresponds to when the peripheral’s interrupt flag is set.

3: PIC16(L)F18323 only.

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<9:2>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<1:0> — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

bit 5-0 Reserved: Do not use.

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — — — — ADRES<9:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

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TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE — — — — —INTEDG

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

TRISA — — TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 131

TRISC(1) —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELA —— ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 132

ANSELC(1) —— ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

ADCON0 CHS<5:0> GO/DONE ADON 225

ADCON1 ADFM ADCS<2:0> — ADNREF ADPREF<1:0> 226

ADACT — — — — ADACT<3:0> 227

ADRESH ADRESH<7:0> 228

ADRESL ADRESL<7:0> 228

FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 161

DAC1CON1 — — —DAC1R<4:0>245

OSCSTAT1 EXTOR HFOR —LFOR SOR ADOR —PLLR 80

Legend: — = unimplemented read as ‘0’. Shaded cells are not used for the ADC module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

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PIC16(L)F18313/18323

23.0 NUMERICALLY CONTROLLED

OSCILLATOR (NCO1) M ODU LE

The Numerically Controlled Oscillator (NCO1) module

is a timer that uses the overflow from the addition of an

increment value to divide the input frequency. The

advantage of the addition method over simple

counter-driven timer is that the output frequency

resolution does not vary with the divider value. The

NCO1 is most useful for applications that require

frequency accuracy and fine resolution at a fixed duty

cycle.

Features of the NCO1 include:

• 20-bit increment function

• Fixed Duty Cycle (FDC) mode

• Pulse Frequency (PF) mode

• Output pulse width control

• Multiple clock input sources

• Output polarity control

• Interrupt capability

Figure 23-1 is a simplified block diagram of the NCO1

module.

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PIC16(L)F18313/18323

FIGURE 23-1: NUMERICA LLY CONTROLLED OSCILLATOR MODULE SIMPLIFIED BLOCK DIAGRAM

000

011

010

001

100

101

110

111

1&2INCU 1&2INCH 1&2INCL

INCBUFU(1) INCBUFH(1) INCBUFL(1)

1&2ACCU 1&2ACCH 1&2ACCL

HFINTOSC

FOSC

LC1BRXW

5HVHUYHG

1CKS<1:0>

1PWS<2:0>

Ripple Counter

1&2BFON

Overflow

Reset

1EN

13)0

1&2POL

1&2PPS

Adder

1&2BLnterrupt 1&2IF

1&2BRXW bit

Peripherals

Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO1 module. They are shown for

reference only and are not user accessible.

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23.1 NCO1 Operation

The NCO1 operates by repeatedly adding a fixed value

to an accumulator. Additions occur at the input clock

rate. The accumulator will overflow with a carry

periodically, which is the raw NCO1 output

(NCO_overflow). This effectively reduces the input

clock by the ratio of the addition value to the maximum

accumulator value. See Equation 23-1.

The NCO1 output can be further modified by stretching

the pulse or toggling a flip-flop. The modified NCO1

output is then distributed internally to other peripherals

and can optionally be output to a pin. The accumulator

overflow also generates an interrupt (NCO_interrupt).

The NCO1 period changes in discrete steps to create

an average frequency.

EQUATION 23-1: NC01 OVERFLOW FREQUENCY

23.1.1 NCO1 CLOCK SOURCES

Clock sources available to the NCO1 include:

•HFINTOSC

•FOSC

• LC1_out

The NCO1 clock source is selected by configuring the

N1CKS<2:0> bits in the NCO1CLK register.

23.1.2 ACCUMULATOR

The accumulator is a 20-bit register. Read and write

access to the accumulator is available through three

registers:

• NCO1ACCL

• NCO1ACCH

• NCO1ACCU

23.1.3 ADDER

The NCO1 adder is a full adder, which operates

independently from the system clock. The addition of

the previous result and the increment value replaces

the accumulator value on the rising edge of each input

clock.

23.1.4 INCREMENT REGISTERS

The increment value is stored in three registers making

up a 20-bit increment. In order of LSB to MSB they are:

• NCO1INCL

• NCO1INCH

• NCO1INCU

When the NCO1 module is enabled, the NCO1INCU

and NCO1INCH registers should be written first, then

the NCO1INCL register. Writing to the NCO1INCL

loaded simultaneously on the second rising edge of the

NCO_clk signal.

The registers are readable and writable. The increment

registers are double-buffered to allow value changes to

be made without first disabling the NCO1 module.

When the NCO1 module is disabled, the increment

buffers are loaded immediately after a write to the

increment registers.

FOVERFLOW NCO1 Clock Frequency Increment Value



220

-------------------------------------------------------------------------------------------------------------------=

Note: The increment buffer registers are not

user-accessible.

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23.2 Fixed Duty Cycle (FDC) Mode

In Fixed Duty Cycle (FDC) mode, every time the

accumulator overflows (NCO_overflow), the output is

toggled. This provides a 50% duty cycle with a constant

frequency, provided that the increment value remains

constant. The FDC frequency can be calculated using

Equation 23-2. The FDC frequency is half of the

overflow frequency since it takes two overflow events

to generate one FDC clock period. For more

information, see Figure 23-2.

EQUATION 23-2: FDC FREQUENCY

The FDC mode is selected by clearing the N1PFM bit

in the NCO1CON register.

23.3 Pulse Frequency (PF) Mode

In Pulse Frequency (PF) mode, every time the

accumulator overflows (NCO_overflow), the output

becomes active for one or more clock periods. Once

the clock period expires, the output returns to an

inactive state. This provides a pulsed output. The

output becomes active on the rising clock edge

immediately following the overflow event. For more

information, see Figure 23-2.

The value of the active and inactive states depends on

the polarity bit, N1POL, in the NCO1CON register.

The PF mode is selected by setting the N1PFM bit in

the NCO1CON register.

23.3.1 OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the

output can vary in width by multiple clock periods.

Various pulse widths are selected with the

N1PWS<2:0> bits in the NCO1CLK register.

When the selected pulse width is greater than the

accumulator overflow time frame, the output of the

NCO1 does not toggle.

23.4 Output Polarity Control

The last stage in the NCO1 module is the output

polarity. The N1POL bit in the NCO1CON register

selects the output polarity. Changing the polarity while

the interrupts are enabled will cause an interrupt for the

resulting output transition.

The NCO1 output can be used internally by source

code or other peripherals. Accomplish this by reading

the N1OUT (read-only) bit of the NCO1CON register.

The NCO1 output signal is available to the following

peripherals:

•CWG

Ffdc Foverflow 2=

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FIGURE 23-2: FDC OUTPUT MODE OPERATION DIAGRAM

Rev. 10-000029A

11/7/2013

00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h

4000h 4000h 4000h

NCO_interrupt

NCOx Output

FDC Mode

NCOx Output

PF Mode

NCOxPWS =

NCOx Output

PF Mode

NCOxPWS =

NCOx

Accumulator

Value

NCOx

Increment

Value

NCOx

Clock

Source

000

001

NCO_overflow

PIC16(L)F18313/18323

DS40001799C-page 236  2015-2017 Microchip Technology Inc.

23.5 Interrupts

When the accumulator overflows (NCO_overflow), the

NCO1 Interrupt Flag bit, NCO1IF, of the PIR2 register

is set. To enable the interrupt event (NCO_interrupt),

the following bits must be set:

• N1EN bit of the NCO1CON register

• NCO1IE bit of the PIE2 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt must be cleared by software by clearing

the NCO1IF bit in the Interrupt Service Routine.

23.6 Effects of a Reset

All of the NCO1 registers are cleared to zero as the

result of a Reset.

23.7 Operation in Sleep

The NCO1 module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock source selected remains active.

The HFINTOSC remains active during Sleep when the

NCO1 module is enabled and the HFINTOSC is

selected as the clock source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the NCO1 clock

source, when the NCO1 is enabled, the CPU will go

idle during Sleep, but the NCO1 will continue to operate

and the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

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23.8 NCO1 Control Registers

R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0

N1EN — N1OUT N1POL — — —N1PFM

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 N1EN: NCO1 Enable bit

1 = NCO1 module is enabled

0 = NCO1 module is disabled

bit 6 Unimplemented: Read as ‘0’.

bit 5 N1OUT: NCO1 Output bit

Displays the current output value of the NCO1 module

bit 4 N1POL: NCO1 Polarity

1 = NCO1 output signal is inverted

0 = NCO1 output signal is not inverted

bit 3-1 Unimplemented: Read as ‘0’.

bit 0 N1PFM: NCO1 Output Divider mode

1 = NCO1 operates in Pulse Frequency mode

0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2

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R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0

N1PWS<2:0> ——— N1CKS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 N1PWS<2:0>: NCO1 Output Pulse Width Select(1, 2)

000 = NCO1 output is active for 1 input clock period

001 = NCO1 output is active for 2 input clock periods

010 = NCO1 output is active for 4 input clock periods

011 = NCO1 output is active for 8 input clock periods

100 = NCO1 output is active for 16 input clock periods

101 = NCO1 output is active for 32 input clock periods

110 = NCO1 output is active for 64 input clock periods

111 = NCO1 output is active for 128 input clock periods

bit 4-2 Unimplemented: Read as ‘0’

bit 1-0 N1CKS<1:0>: NCO1 Clock Source Select bits

00 = HFINTOSC (16 MHz)

01 = FOSC

10 = CLC1OUT

11 =Reserved

Note 1: N1PWS applies only when operating in Pulse Frequency mode.

2: If NCO1 pulse width is greater than NCO1 overflow period, the NCO1 output does not toggle.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

NCO1ACC<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1ACC<7:0>: NCO1 Accumulator, low byte

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PIC16(L)F18313/18323

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

NCO1ACC<15:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1ACC<15:8>: NCO1 Accumulator, high byte

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

———— NCO1ACC<19:16>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 NCO1ACC<19:16>: NCO1 Accumulator, upper byte

Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH:NCO1ACCL. The 24 bits are reserved but not all

are used.This register updates in real-time, asynchronously to the CPU; there is no provision to guarantee

atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will

produce undefined results.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1

NCO1INC<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1INC<7:0>: NCO1 Increment, low byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

2: NCO1INC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after

writing to NCO1INCL;NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.

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DS40001799C-page 240  2015-2017 Microchip Technology Inc.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

NCO1INC<15:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 NCO1INC<15:8>: NCO1 Increment, high byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — — — NCO1INC<19:16>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 NCO1INC<19:16>: NCO1 Increment, upper byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

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TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCO1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Register

on Page

TRISA —— TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 131

ANSELA —— ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 132

TRISC(1) —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) —— ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

PIR2 —C2IF(1) C1IF NVMIF ———NCO1IF 97

PIE2 —C2IE(1) C1IE NVMIE ———NCO1IE 92

INTCON GIE PEIE — — — — — INTEDG 89

NCO1CON N1EN — N1OUT N1POL ———N1PFM237

NCO1CLK N1PWS<2:0> — — — N1CKS<1:0> 238

NCO1ACCL NCO1ACC <7:0> 238

NCO1ACCH NCO1ACC <15:8> 239

NCO1ACCU — — — — NCO1ACC <19:16> 239

NCO1INCL NCO1INC<7:0> 239

NCO1INCH NCO1INC<15:8> 240

NCO1INCU — — — — NCO1INC<19:16> 240

CWG1DAT — — — —DAT<3:0>196

MDSRC — — — — MDMS<3:0> 253

MDCARH —MDCHPOL MDCHSYNC —MDCH<3:0> 254

MDCARL —MDCLPOL MDCLSYNC —MDCL<3:0> 255

CCPxCAP — — — — CCPxCTS<3:0> 290

Legend: — = unimplemented read as ‘0’. Shaded cells are not used for NCO1 module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

PIC16(L)F18313/18323

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24.0 5-BIT DIGIT AL-TO-ANALOG

CONVERTER (DAC1) MODULE

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The input of the DAC can be connected to:

•External V

REF pins

•VDD supply voltage

• FVR (Fixed Voltage Reference)

The output of the DAC can be configured to supply a

reference voltage to the following:

• Comparator positive input

• ADC input channel

• DAC1OUT pin

The Digital-to-Analog Converter (DAC) is enabled by

setting the DAC1EN bit of the DAC1CON0 register.

24.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels

are set with the DAC1R<4:0> bits of the DAC1CON1

The DAC output voltage is determined by Equation 24-1:

EQUATION 24-1: DAC OUTPUT VOLT AGE

24.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Table 35-15.

24.3 DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT pin by

setting the DAC1OE bit of the DAC1CON0 register.

Selecting the DAC reference voltage for output on the

DAC1OUT pin automatically overrides the digital

output buffer and digital input threshold detector

functions, it disables the weak pull-up and the

constant-current drive function of that pin. Reading the

DAC1OUT pin when it has been configured for DAC

reference voltage output will always return a ‘0’.

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to the DAC1OUT pin. Figure 24-2

shows an example buffering technique.

VOUT VSOURCE+VSOURCE-

–

DAC1R4:0

----------------------------------







VSOURCE-

+=

VSOURCE+VDD or=

VSOURCE-VSS or=

VREF+ or FVR

VREF-

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PIC16(L)F18313/18323

FIGURE 24-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

FIGURE 24-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

Note 1: The unbuffered DAC1_output is provided on the DAC1OUT pin(s).

VREF+

VDD

VSOURCE+

VSOURCE-

VSS

Steps

32-to-1 MUX

To Peripherals

DAC1OUT (1)

DAC1OE

DAC1_output

DAC1EN

DAC1R<4:0>

FVR_buffer2

Reserved

DAC1PSS

VREF-

DAC1NSS

DAC1OUT Buffered DAC Output

–

DAC

Module

Voltage

Reference

Output

Impedance

PIC® MCU

PIC16(L)F18313/18323

DS40001799C-page 244  2015-2017 Microchip Technology Inc.

24.4 Operation During Sleep

The DAC continues to function during Sleep. When the

device wakes up from Sleep through an interrupt or a

Watchdog Timer time-out, the contents of the

DAC1CON0 register are not affected.

24.5 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DAC1OUT pin.

• The DAC1R<4:0> range select bits are cleared.

24.6 Register Definitions: DAC Control

R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0

DAC1EN —DAC1OE— DAC1PSS<1:0> — DAC1NSS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DAC1EN: DAC1 Enable bit

1 = DAC is enabled

0 = DAC is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 DAC1OE: DAC1 Voltage Output 1 Enable bit

1 = DAC voltage level is output on the DAC1OUT pin

0 = DAC voltage level is disconnected from the DAC1OUT pin

bit 4 Unimplemented: Read as ‘0’

bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits

11 = Reserved, do not use

10 = FVR output

01 =V

REF+ pin

00 =V

bit 1 Unimplemented: Read as ‘0’

bit 0 DAC1NSS: DAC1 Negative Source Select bits

1 =V

REF- pin

0 =V

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U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— — —DAC1R<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 DAC1R<4:0>: DAC1 Voltage Output Select bits

VOUT = (VSRC+ - VSRC-)*(DAC1R<4:0>/32) + VSRC

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on pag e

DACCON0 DAC1EN —DAC1OE— DAC1PSS<1:0> — DAC1NSS 244

DACCON1 — — —DAC1R<4:0>245

CMxCON1 CxINTP CxINTN CxPCH<2:0> CxNCH<2:0> 172

ADCON0 CHS<5:0> GO/DONE ADON 225

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

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25.0 DATA SIGNAL MODULATOR

(DSM) MODULE

The Data Signal Modulator (DSM) is a peripheral which

allows the user to mix a data stream, also known as a

modulator signal, with a carrier signal to produce a

modulated output.

Both the carrier and the modulator signals are supplied

to the DSM module either internally from the output of

a peripheral, or externally through an input pin.

The modulated output signal is generated by

performing a logical “AND” operation of both the carrier

and modulator signals and then provided to the MDOUT

pin.

The carrier signal is comprised of two distinct and

separate signals. A carrier high (CARH) signal and a

carrier low (CARL) signal. During the time in which the

modulator (MOD) signal is in a logic high state, the

DSM mixes the carrier high signal with the modulator

signal. When the modulator signal is in a logic low

state, the DSM mixes the carrier low signal with the

modulator signal.

Using this method, the DSM can generate the following

types of key modulation schemes:

• Frequency-Shift Keying (FSK)

• Phase-Shift Keying (PSK)

• On-Off Keying (OOK)

Additionally, the following features are provided within

the DSM module:

• Carrier Synchronization

• Carrier Source Polarity Select

• Carrier Source Pin Disable

• Programmable Modulator Data

• Modulator Source Pin Disable

• Modulated Output Polarity Select

• Slew Rate Control

Figure 25-1 shows a simplified block diagram of the

Data Signal Modulator peripheral.

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PIC16(L)F18313/18323

FIGURE 25-1: SIMPLI FI ED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR

0000

0001

0010

0011

0100

0101

0110

0111

1011

1100

1000

1001

1010

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1011

1100

1000

1001

1010

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1011

1100

1000

1001

1010

1101

1110

1111

SYNC

DSM

MDOPOL

MDCHPOL

MDCLPOL

MDCLSYNC

MDCHSYNC

CARL

CARH

MOD

MDCH<3:0>

MDMS<3:0>

MDCL<3:0>

VSS

MDCIN1

MDCIN2

CLKR

PWM5

PWM6

1&2

RHVHUYHG

FOSC

HFINTOSC

CLC1

CLC2

5HVHUYHG

CCP1

CCP2

VSS

MDCIN1

MDCIN2

CLKR

CCP1

CCP2

PWM5

PWM6

1&2

RHVHUYHG

5HVHUYHG

FOSC

HFINTOSC

CLC1

CLC2

MDBIT

MDMIN

CCP1

CCP2

PWM5

PWM6

SDO1

5HVHUYHG

EUSART TX

1&2

CLC1

CLC2

5HVHUYHG

Data Signal Modulator

PIC16(L)F18313/18323

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25.1 DSM Operation

The DSM module can be enabled by setting the MDEN

bit in the MDCON register. Clearing the MDEN bit in the

MDCON register, disables the DSM module by auto-

matically switching the carrier high and carrier low sig-

nals to the VSS signal source. The modulator signal

source is also switched to the MDBIT in the MDCON

inactive, but that it is also consuming the least amount

of current.

The values used to select the carrier high, carrier low,

and modulator sources held by the Modulation Source,

Modulation High Carrier, and Modulation Low Carrier

control registers are not affected when the MDEN bit is

cleared and the DSM module is disabled. The values

inside these registers remain unchanged while the

DSM is inactive. The sources for the carrier high, car-

rier low and modulator signals will once again be

selected when the MDEN bit is set and the DSM

module is again enabled and active.

The modulated output signal can be disabled without

shutting down the DSM module. The DSM module will

remain active and continue to mix signals, but the out-

put value will not be sent to the DSM pin. During the

time that the output is disabled, the DSM pin will remain

low. The modulated output can be disabled by clearing

the MDEN bit in the MDCON register.

25.2 Modulator Signal Sources

The modulator signal can be supplied from the follow-

ing sources:

• CCP1 Output

• CCP2 Output

• PWM5 Output

• PWM6 Output

• MSSP1 SDO1 (SPI mode only)

• Comparator C1 Output

• Comparator C2 Output (PIC16(L)F18323 only)

• EUSART1 TX Output

• External Signal on MDMIN pin

• NCO1 Output

• CLC1 Output

• CLC2 Output

• MDBIT bit in the MDCON register

The modulator signal is selected by configuring the

MDMS <3:0> bits in the MDSRC register.

25.3 Carrier Signal Sources

The carrier high signal and carrier low signal can be

supplied from the following sources:

• CCP1 Output

• CCP2 Output

•PWM5 Output

•PWM6 Output

• NCO1 Output

•FOSC (System Clock)

•HFINTOSC

• CLC1 Output

• CLC2 Output

•CLKR

• External Signal on MDCIN1 pin

• External Signal on MDCIN2 pin

•V

The carrier high signal is selected by configuring the

MDCH <3:0> bits in the MDCARH register. The carrier

low signal is selected by configuring the MDCL <3:0>

bits in the MDCARL register.

25.4 Carrier Synchronization

During the time when the DSM switches between

carrier high and carrier low signal sources, the carrier

data in the modulated output signal can become

truncated. To prevent this, the carrier signal can be

synchronized to the modulator signal. When the

modulator signal transitions away from the

synchronized carrier, the unsynchronized carrier

source is immediately active, while the synchronized

carrier remains active until its next falling edge. When

the modulator signal transitions back to the

synchronized carrier, the unsynchronized carrier is

immediately disabled, and the modulator waits until the

next falling edge of the synchronized carrier before the

synchronized carrier becomes active.

Synchronization is enabled separately for the carrier

high and carrier low signal sources. Synchronization for

the carrier high signal is enabled by setting the

MDCHSYNC bit in the MDCARH register.

Synchronization for the carrier low signal is enabled by

setting the MDCLSYNC bit in the MDCARL register.

Figure 25-1 through Figure 25-6 show timing diagrams

of using various synchronization methods.

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FIGURE 25-2: ON OFF KEYING (OOK) SYNCHRONIZATION

FIGURE 25-3: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)

FIGURE 25-4: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)

Carrier Low (CARL)

MDCHSYNC = 1

MDCLSYNC = 0

MDCHSYNC = 1

MDCLSYNC = 1

MDCHSYNC = 0

MDCLSYNC = 0

MDCHSYNC = 0

MDCLSYNC = 1

Carrier High (CARH)

Modulator (MOD)

MDCHSYNC = 0

MDCLSYNC = 0

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

MDCHSYNC = 1

MDCLSYNC = 0

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier

CARH CARL CARL

CARH

State

both both

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FIGURE 25-5: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)

FIGURE 25-6: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)

MDCHSYNC = 0

MDCLSYNC = 1

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

MDCHSYNC = 1

MDCLSYNC = 1

Modulator (MOD)

Carrier High (CARH)

Carrier Low (CARL)

Active Carrier CARH CARL CARL

CARH

State

Falling edges

used to sync

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25.5 Carrier Source Polarity Select

The signal provided from any selected input source for

the carrier high and carrier low signals can be inverted.

Inverting the signal for the carrier high source is

enabled by setting the MDCHPOL bit of the MDCARH

enabled by setting the MDCLPOL bit of the MDCARL

25.6 Programmable Modulator Data

The MDBIT of the MDCON register can be selected as

the source for the modulator signal. This gives the user

the ability to program the value used for modulation.

25.7 Modulated Output Polarity

The modulated output signal provided on the DSM pin

can also be inverted. Inverting the modulated output

signal is enabled by setting the MDOPOL bit of the

MDCON register.

25.8 Slew Rate Control

The slew rate limitation on the output port pin can be

disabled. The slew rate limitation can be removed by

clearing the SLR bit of the SLRCON register

associated with that pin. For example, clearing the slew

rate limitation for pin RA5 would require clearing the

SLRA5 bit of the SLRCONA register.

25.9 Operation in Sleep Mode

The DSM module is not affected by Sleep mode. The

DSM can still operate during Sleep, if the Carrier and

Modulator input sources are also still operable during

Sleep.

25.10 Effects of a Reset

Upon any device Reset, the DSM module is disabled.

The user’s firmware is responsible for initializing the

module before enabling the output. The registers are

reset to their default values.

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25.11 Register Definitions: Modulation Control

R/W-0/0 U-0 U-0 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0

MDEN —— MDOPOL MDOUT ——MDBIT

(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 MDEN: Modulator Module Enable bit

1 = Modulator module is enabled and mixing input signals

0 = Modulator module is disabled and has no output

bit 6-5 Unimplemented: Read as ‘0’

bit 4 MDOPOL: Modulator Output Polarity Select bit

1 = Modulator output signal is inverted; idle high output

0 = Modulator output signal is not inverted; idle low output

bit 3 MDOUT: Modulator Output bit

Displays the current output value of the modulator module.(1)

bit 2-1 Unimplemented: Read as ‘0’

bit 0 MDBIT: Allows software to manually set modulation source input to module(2)

Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this

2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.

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U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— — — —MDMS<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 MDMS<3:0> Modulation Source Selection bits

1111-1110 =Reserved. No channel connected.

1101 = CLC2 output

1100 = CLC1 output

1011 = NCO1 output

1010 = EUSART1 TX output

1000 = MSSP1 SDO1 output

0111 = C2 (Comparator 2) output(1)

0110 = C1 (Comparator 1) output

0101 = PWM6 output

0100 = PWM5 output

0011 = CCP2 output (PWM Output mode only)

0010 = CCP1 output (PWM Output mode only)

0001 = MDMINPPS

0000 = MDBIT bit of MDCON register is modulation source

Note 1: PIC16(L)F18323 only.

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U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— MDCHPOL MDCHSYNC — MDCH<3:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit

1 = Selected high carrier signal is inverted

0 = Selected high carrier signal is not inverted

bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit

1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the

low time carrier

0 = Modulator output is not synchronized to the high time carrier signal(1)

bit 4 Unimplemented: Read as ‘0’

bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits (1)

1111-1110 =Reserved. No channel connected

1101 = CLC2 output

1100 = CLC1 output

1011 =HFINTOSC

1010 = FOSC

1001 = Reserved. No channel connected.

1000 = NCO1 output

0111 = PWM6 output

0110 = PWM5 output

0101 = CCP2 output (PWM Output mode only)

0100 = CCP1 output (PWM Output mode only)

0011 = Reference clock module signal (CLKR)

0010 = MDCIN2PPS

0001 = MDCIN1PPS

0000 =V

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

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U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u

— MDCLPOL MDCLSYNC — MDCL<3:0>(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit

1 = Selected low carrier signal is inverted

0 = Selected low carrier signal is not inverted

bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit

1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high

time carrier

0 = Modulator output is not synchronized to the low time carrier signal(1)

bit 4 Unimplemented: Read as ‘0’

bit 3-0 MDCL<3:0>: Modulator Data High Carrier Selection bits (1)

1111-1110 =Reserved. No channel connected

1101 = CLC2 output

1100 = CLC1 output

1011 =HFINTOSC

1010 = FOSC

1001 = Reserved. No channel connected.

1000 = NCO1 output

0111 = PWM6 output

0110 = PWM5 output

0101 = CCP2 output (PWM Output mode only)

0100 = CCP1 output (PWM Output mode only)

0011 = Reference clock module signal (CLKR)

0010 = MDCIN2PPS

0001 = MDCIN1PPS

0000 =V

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

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TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

SLRCONA ― ― SLRA5 SLRA4 ―SLRA2 SLRA1 SLRA0 134

INLVLA ― ― INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 134

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

SLRCONC(1) ― ― SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 140

INLVLC(1) ― ― INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 141

MDCON MDEN ― ― MDOPOL MDOUT ― ― MDBIT 252

MDSRC ― ― ― ― MDMS<3:0> 253

MDCARH ―MDCHPOL MDCHSYNC ―MDCH<3:0> 254

MDCARL ―MDCLPOL MDCLSYNC ―MDCL<3:0> 255

MDCIN1PPS ― ― ― MDCIN1PPS<4:0> 144

MDCIN2PPS ― ― ― MDCIN2PPS<4:0> 144

MDMINPPS ― ― ― MDMINPPS<4:0> 144

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.

Note 1: PIC16(L)F18323 only.

2: Unimplemented. Read as ‘1’.

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26.0 T IMER0 MODULE

The Timer0 module is an 8/16-bit timer/counter with the

following features:

• 16-bit timer/counter

• 8-bit timer/counter with programmable period

• Synchronous or asynchronous operation

• Selectable clock sources

• Programmable prescaler (independent of

Watchdog Timer)

• Programmable postscaler

• Operation during Sleep mode

• Interrupt on match or overflow

• Output on I/O pin (via PPS) or to other peripherals

26.1 Timer0 Operation

Timer0 can operate as either an 8-bit timer/counter or

a 16-bit timer/counter. The mode is selected with the

T016BIT bit of the T0CON register.

When used with the FOSC/4 clock source, the module

is a timer and increments on every instruction cycle.

When used with any other clock source, the module

can be used as either a timer or a counter and

increments on every rising edge of the external source.

26.1.1 16-BIT MODE

In normal operation, TMR0 increments on the rising

edge of the clock source. A 15-bit prescaler on the

clock input gives several prescale options (see

prescaler control bits, T0CKPS<3:0> in the T0CON1

26.1.1.1 Timer0 Reads and Writes in 16-bit

Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0, which is neither directly readable nor

writable (see Figure 26-1). TMR0H is updated with the

contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte was valid, due to a rollover between

successive reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

26.1.2 8-BIT MODE

In normal operation, TMR0 increments on the rising

edge of the clock source. A 15-bit prescaler on the

clock input gives several prescale options (see

prescaler control bits, T0CKPS<3:0> in the T0CON1

In 8-bit mode, TMR0H no longer functions as the

Timer0 high byte, but instead functions as the Period

of TMR0H on each clock cycle. When the two values

match, the following events happen:

• TMR0_out goes high for one prescaled clock

period

•TMR0L is reset

• The contents of TMR0H are copied to the period

buffer

In 8-bit mode, the TMR0L and TMR0H registers are

both directly readable and writable. The TMR0L

TMR0H register initializes at FFh.

Both the prescaler and postscaler counters are cleared

on the following events:

• A write to the TMR0L register

• A write to either the T0CON0 or T0CON1

registers.

• Any device Reset – Power-on Reset

(POR),MCLR Reset, Watchdog Timer Reset

(WDTR) or Brown-out Reset (BOR)

26.1.3 COUNTER MODE

In Counter mode, the prescaler is normally disabled by

setting the T0CKPS bits of the T0CON1 register to

‘0000’. Each rising edge of the clock input (or the

output of the prescaler if the prescaler is used)

increments the counter by ‘1’.

26.1.4 TIMER MODE

In Timer mode, the Timer0 module will increment every

instruction cycle as long as there is a valid clock signal

and the T0CKPS bits of the T0CON1 register

(Register 26-4) are set to ‘0000’. When a prescaler is

added, the timer will increment at the rate based on the

prescaler value.

26.1.5 ASYNCHRONOUS MODE

When the T0ASYNC bit of the T0CON1 register is set

(T0ASYNC = 1), the counter increments with each

rising edge of the input source (or output of the

prescaler, if used). Asynchronous mode allows the

counter to continue operation during Sleep mode

provided that the clock also continues to operate during

Sleep.

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26.1.6 SYNCHRONOUS MODE

When the T0ASYNC bit of the T0CON1 register is clear

(T0ASYNC = 0), the counter clock is synchronized to

the system oscillator (FOSC/4). When operating in

Synchronous mode, the counter clock frequency

cannot exceed FOSC/4.

26.2 Clock Source Selection

The T0CS<2:0> bits of the T0CON1 register are used

to select the clock source for Timer0. Register 26-4

displays the clock source selections.

26.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected, Timer0

operates as a timer and will increment on multiples of

the clock source, as determined by the Timer0

prescaler.

26.2.2 EXTERNAL CLOCK SOURCE

When an external clock source is selected, Timer0 can

operate as either a timer or a counter. Timer0 will

increment on multiples of the rising edge of the external

clock source, as determined by the Timer0 prescaler.

26.3 Programmable Prescaler

A software programmable prescaler is available for

exclusive use with Timer0. There are 16 prescaler

options for Timer0 ranging in powers of two from 1:1 to

1:32768. The prescaler values are selected using the

T0CKPS<3:0> bits of the T0CON1 register.

The prescaler is not directly readable or writable.

Clearing the prescaler register can be done by writing

to the TMR0L register, the T0CON0 register, or the

T0CON1 register.

26.4 Programmable Postscaler

A software programmable postscaler (output divider) is

available for exclusive use with Timer0. There are 16

postscaler options for Timer0 ranging from 1:1 to 1:16.

The postscaler values are selected using the

T0OUTPS<3:0> bits of the T0CON0 register.

The postscaler is not directly readable or writable.

Clearing the postscaler register can be done by writing

to the TMR0L register, the T0CON0 register, or the

T0CON1 register.

26.5 Operation During Sleep

When operating synchronously, Timer0 will halt. When

operating asynchronously, Timer0 will continue to

increment and wake the device from Sleep (if Timer0

interrupts are enabled) provided that the input clock

source is active.

26.6 Timer0 Interrupts

The Timer0 Interrupt Flag bit (TMR0IF) is set when

either of the following conditions occur:

• 8-bit TMR0L matches the TMR0H value

• 16-bit TMR0 rolls over from FFFFh

When the postscaler bits (T0OUTPS<3:0>) are set to

1:1 operation (no division), the T0IF Flag bit will be set

with every TMR0 match or rollover. In general, the

TMR0IF Flag bit will be set every T0OUTPS +1

matches or rollovers.

If Timer0 interrupts are enabled (TMR0IE bit of the

PIE0 register = 1), the CPU will be interrupted and the

device may wake from Sleep (see Section 26.5

“Operat ion During Sleep” for more details).

26.7 Timer0 Output

The Timer0 output can be routed to any I/O pin via the

RxyPPS output selection register (see Section 13.0

“Peripheral Pin Select (PPS) Module” for additional

information). The Timer0 output can also be used by

other peripherals, such as the auto-conversion trigger

of the Analog-to-Digital Converter. Finally, the Timer0

output can be monitored through software via the

Timer0 Output bit (T0OUT) of the T0CON0 register

(Register 26-3).

TMR0_out will be one postscaled clock period when a

match occurs between TMR0L and TMR0H in 8-bit

mode, or when TMR0 rolls over in 16-bit mode. When

a match condition occurs, the Timer0 output will toggle

every T0OUTPS + 1 match. The total Timer0 period

takes two match events to occur, and creates a 50%

duty cycle output.

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FIGURE 26-1: BLOCK DIAGRAM OF TIMER0

Rev. 10-000017B

4/6/2017

000

011

010

001

100

101

110

111

T0CKIPPS

FOSC/4

HFINTOSC

LFINTOSC

Reserved

SOSC

CLC1

T0CKIPPS

(Inverted)

T0CS<2:0>

T0CKPS<3:0>

Prescaler

OSC

T0ASYNC

T016BIT

T0OUTPS<3:0> T0IF

T0_out

Peripherals

TMR0

Postscaler

TMR0L

COMPARATOR

TMR0 High

Byte(1)

TMR0H

T0_match

Clear

Latch

Enable

8-bit TMR0 Body Diagram (T016BIT = 0)

TMR0L

TMR0H

Internal Data Bus

16-bit TMR0 Body Diagram (T016BIT = 1)

SYNC

IN OUT

TMR0

BODY

PPS

RxyPPS

OUT

TMR0 High

Byte(1)

IN OUT

Read TMR0L

Write TMR0L

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26.8 Register Definitions: Timer0 Register

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR0L<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TMR0L<7:0>:TMR0 Counter bits 7..0

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

TMR0H<7:0> or TMR0<15:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 When T016BIT = 0

TMR0H<7:0>:TMR0 Period Register Bits 7..0

When T016BIT = 1

TMR0<15:8>: TMR0 Counter bits 15..8

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R/W-0/0 U-0 R-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

T0EN — T0OUT T016BIT T0OUTPS<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 T0EN:TMR0 Enable bit

1 = The module is enabled and operating

0 = The module is disabled and in the lowest power mode

bit 6 Unimplemented: Read as ‘0’

bit 5 T0OUT:TMR0 Output (read-only)

TMR0 output bit

bit 4 T016BIT: TMR0 Operating as 16-bit Timer Select bit

1 = TMR0 is a 16-bit timer

0 = TMR0 is an 8-bit timer

bit 3-0 T0OUTPS<3:0>: TMR0 Output Postscaler (divider) Select bits

0000 = 1:1 Postscaler

0001 = 1:2 Postscaler

0010 = 1:3 Postscaler

0011 = 1:4 Postscaler

0100 = 1:5 Postscaler

0101 = 1:6 Postscaler

0110 = 1:7 Postscaler

0111 = 1:8 Postscaler

1000 = 1:9 Postscaler

1001 = 1:10 Postscaler

1010 = 1:11 Postscaler

1011 = 1:12 Postscaler

1100 = 1:13 Postscaler

1101 = 1:14 Postscaler

1110 = 1:15 Postscaler

1111 = 1:16 Postscaler

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

T0CS<2:0> T0ASYNC T0CKPS<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-5 T0CS<2:0>:Timer0 Clock Source Select bits

000 = T0CKIPPS (True)

001 = T0CKIPPS (Inverted)

010 = FOSC/4

011 = HFINTOSC

100 = LFINTOSC

101 = Reserved

110 = SOSC

111 = CLC1

bit 4 T0ASYNC: TMR0 Input Asynchronization Enable bit

1 = The input to the TMR0 counter is not synchronized to system clocks

0 = The input to the TMR0 counter is synchronized to FOSC/4

bit 3-0 T0CKPS<3:0>: Prescaler Rate Select bit

0000 = 1:1

0001 = 1:2

0010 = 1:4

0011 = 1:8

0100 = 1:16

0101 = 1:32

0110 = 1:64

0111 = 1:128

1000 = 1:256

1001 = 1:512

1010 = 1:1024

1011 = 1:2048

1100 = 1:4096

1101 = 1:8192

1110 = 1:16384

1111 = 1:32768

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TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

TMR0L TMR0L<7:0> 260

TMR0H TMR0H<7:0> or TMR0<15:8> 260

T0CON0 T0EN ―T0OUT T016BIT T0OUTPS<3:0> 261

T0CON1 T0CS<2:0> T0ASYNC T0CKPS<3:0> 262

T0CKIPPS ― ― ― T0CKIPPS<4:0> 144

TMR0PPS ― ― ― TMR0PPS<4:0> 144

ADACT ― ― ― ADACT<4:0> 227

CLCxSELy ― ― LCxDyS<5:0> 210

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 274

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR0 ― ― TMR0IF IOCIF ― ― ― INTF 95

PIE0 ― ― TMR0IE IOCIE ― ― ― INTE 90

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

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27.0 TIMER1 MODULE WITH GATE

CONTROL

Timer1 module is a 16-bit timer/counter, with the follow-

ing features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Clock source for optional comparator

synchronization

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function with

the CCP modules

• Auto-Conversion Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single-Pulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 27-1 is a block diagram of the Timer1 module.

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FIGURE 27-1: TIMER1 BLOCK DIAGRAM

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep

T1G

T0_overflow

C1OUT_sync

C2OUT_sync

T1GSS<1:0>

T1GPOL

Single Pulse

Acq. Control

T1GSPM

TMR1ON

T1GTM

TMR1GE

TMR1ON

TMR1LTMR1H

T1_overflow

set flag bit

TMR1IF

TMR1(2)

Fosc

Internal Clock

Fosc/4

Internal Clock

LFINTOSC

TMR1CS<1:0>

Prescaler

1,2,4,8

T1SYNC

Sleep

Input

Fosc/2

Internal

Clock

T1CKPS<1:0>

Synchronized Clock Input

det

Synchronize(3)

(1)

QCK

T1GGO/DONE

T1CLK

T1CKI

set bit

TMR1GIF

T1GVAL

det

Interrupt

SOSC_clk 1

T1SOSC

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27.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing timer which

is accessed through the TMR1H:TMR1L register pair.

Writes to TMR1H or TMR1L directly update the timer.

The module can be used with either internal or external

clock sources, and has the Timer1 Gate Enable

function. When Timer1 is used with the Timer1 Gate

Enable, the timer can measure time intervals or count

signal pulses between two points of interest. When

used without the Timer1 Gate Enable, the timer simply

measures time intervals.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 27-1 displays the Timer1 enable

selections.

27.2 Clock Source Selection

The TMR1CS<1:0> and T1OSC bits of the T1CON

Table 27-2 displays the clock source selections. The

TMR1H:TMR1L register pair will increment on

multiples of the clock source as determined by the

Timer1 prescaler.

When either the FOSC or LFINTOSC clock source is

selected, the TMR1H:TMR1L register pair will

increment every rising clock edge. Reading from the

TMR1H:TMR1L register pair when either the FOSC or

LFINTOSC is the clock source will cause a 2 LSb loss

in resolution, which can be mitigated by using an

asynchronous input signal to gate the Timer1 clock

input (see Section 26.5 “Operation During Sleep” for

more information on the Timer1 Gate Enable).

When the FOSC/4 clock source is selected, the

TMR1H:TMR1L register pair increments every

instruction cycle (once every four FOSC pulses).

In addition to the internal clock sources, Timer1 has a

dedicated external clock input pin, T1CKI. T1CKI can

be either synchronized to the system clock or can run

asynchronously via the T1SYNC bit of the T1CON

source, the TMR1H:TMR1L register pair increments on

the rising edge of the T1CKI clock input.

TABLE 27-1: TIMER1 ENABLE

SELECTIONS

TMR1ON TMR1GE Timer1

Operation

00Off

01Off

10Always On

11Count Enabled

Note: When using Timer1 to count events, a

falling edge must be registered by the

counter prior to the first incrementing

rising edge after any one or more of the

following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 27-2: CLOCK SOURCE SELECTIONS

TMR1CS<1:0> Clock Source

11 LFINTOSC

10 External Clocking on T1CKI Pin

01 System Clock (FOSC)

00 Instruction Clock (FOSC/4)

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27.2.1 TIMER1 (SECONDARY)

OSCILLATOR

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins SOSCI (input) and SOSCO

(amplifier output). This internal circuit is designed to be

used in conjunction with an external 32.768 kHz

crystal. The oscillator circuit is enabled by setting the

T1SOSC bit of the T1CON register. The oscillator will

continue to run during Sleep.

27.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

27.4 Timer1 Operation in

Asynchronous Mode

If the control bit T1SYNC of the T1CON register is set,

the external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 27.4.1 “Reading and Writing Timer1 in

Asynchronous Mode” ).

27.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

27.5 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate

circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable

sources.

27.5.1 TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 27-3 for timing details.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1SOSC should be set and a suitable

delay observed prior to using Timer1. A

suitable delay similar to the OST delay

can be implemented in software by

clearing the TMR1IF bit then presetting

the TMR1H:TMR1L register pair to

FC00h. The TMR1IF flag will be set when

1024 clock cycles have elapsed, thereby

indicating that the oscillator is running and

reasonably stable.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 27-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL T1G Timer1 Operation

00Counts

01Holds Count

10Holds Count

11Counts

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27.5.2 TIMER1 GATE SOURCE

SELECTION

Timer1 gate source selections are shown in Table 27-4.

Source selection is controlled by the T1GSS bits of the

T1GCON register. The polarity of the selected input is

configurable. Polarity selection is controlled by the

T1GPOL bit of the T1GCON register.

27.5.2.1 T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1

gate circuitry.

27.5.2.2 Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a

low-to-high pulse will automatically be generated and

internally supplied to the Timer1 gate circuitry.

27.5.2.3 Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can

be selected as a source for Timer1 gate control. The

Comparator 1 output can be synchronized to the Timer1

clock or left asynchronous. For more information see

Section 18.4.1 “Comparator Output

Synchronization”.

27.5.2.4 Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation

can be selected as a source for Timer1 gate control.

The Comparator 2 output can be synchronized to the

Timer1 clock or left asynchronous. For more

information see Section 18.4.1 “Comparator Output

Synchronization”.

27.5.3 TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is

possible to measure the full period of a Timer1 gate

signal, as opposed to the duration of a single pulse.

The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the

signal. See Figure 27-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

27.5.4 TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single-pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next

incrementing edge of the Timer1 gate signal. On the

next trailing edge of the Timer1 gate signal, the

T1GGO/DONE bit will automatically be cleared. No

other gate events will be allowed to increment Timer1

until the T1GGO/DONE bit is once again set in

software. See Figure 27-5 for timing details.

If the Single-Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the period of the Timer1 gate

source to be measured. See Figure 27-6 for timing

details.

27.5.5 TIMER1 GATE VALUE STATUS

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

gate is not enabled (TMR1GE bit is cleared).

TABLE 27-4: TIMER1 GATE SOURCES

T1GSS Tim er1 Ga te Sour ce

00 Timer1 Gate Pin

01 Overflow of Timer0

(TMR0 increments from FFh to 00h)

10 Comparator 1 Output

(optionally Timer1 synchronized output)

11 Comparator 2 Output

(optionally Timer1 synchronized output)

Note: Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

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27.6 Timer1 Interr upt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

27.6.1 TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of T1GVAL

occurs, the TMR1GIF flag bit in the PIR1 register will be

set. If the TMR1GIE bit in the PIE1 register is set, then

an interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1

gate is not enabled (TMR1GE bit is cleared).

27.7 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous mode. In this mode, an external crystal

or clock source can be used to increment the timer. To

set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be

configured

• T1SOSC bit of the T1CON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

Routine.

Secondary oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

27.8 CCP Capture/Compare Time Base

The CCP modules use the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be an

Auto-conversion Trigger.

For more information, see Section 29.0

“Capture/Compare/PWM Modules”.

27.9 CCP Auto-Conversion Trigger

When any of the CCP’s are configured to trigger an

auto-conversion, the trigger will clear the

TMR1H:TMR1L register pair. This auto-conversion

does not cause a Timer1 interrupt. The CCP module

may still be configured to generate a CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1 should be synchronized and FOSC/4 should be

selected as the clock source in order to utilize the

Auto-conversion Trigger. Asynchronous operation of

Timer1 can cause an Auto-conversion Trigger to be

missed.

In the event that a write to TMR1H or TMR1L coincides

with an Auto-conversion Trigger from the CCP, the

write will take precedence.

For more information, see Section 29.2.3 “Auto - Con-

version Trigger”.

Note: The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

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FIGURE 27-2: TIMER1 INCREMENTING EDGE

FIGURE 27-3: TIMER1 GATE ENABLE MODE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate timer increments.

2: When used to count events, a falling edge must be registered by the counter prior to the first incrementing rising edge

of the clock.

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1 N N + 1 N + 2 N + 3 N + 4

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FIGURE 27-4: TIMER1 GATE TOGGLE MODE

FIGURE 27-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GTM

t1g_in

T1CKI

T1GVAL

Timer1

N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1 N N + 1 N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on

falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

Counting enabled on

rising edge of T1G

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FIGURE 27-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

t1g_in

T1CKI

T1GVAL

Timer1 NN + 1

N + 2

T1GSPM

T1GGO/

DONE

Set by software

Cleared by hardware on

falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by software

Cleared by

software

TMR1GIF

T1GTM

Counting enabled on

rising edge of T1G

N + 4

N + 3

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27.10 Register Definitions: Timer1 Control

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u

TMR1CS<1:0> T1CKPS<1:0> T1SOSC T1SYNC —TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Timer1 clock Source is LFINTOSC

10 = Timer1 clock source is pin or oscillator:

If T1SOSC = 0:

External clock from T1CKIPPS pin (on the rising edge)

If T1SOSC = 1:

Clock from SOSC, either crystal oscillator on T1SOSCI/T1SOSCO pins, or SOSCIN input

01 = Timer1 clock source is system clock (FOSC)

00 = Timer1 clock source is instruction clock (FOSC/4)

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1SOSC: LP Oscillator Enable Control bit

1 = SOSC requested as the clock source

0 = T1CKI enabled as the clock source

bit 2 T1SYNC: Timer1 Synchronization Control bit

TMR1CS<1:0> = 1x

1 = Do not synchronize external clock input

0 = Synchronize external clock input with system clock

TMR1CS<1:0> = 0x

This bit is ignored. Timer1 uses the internal clock and no additional synchronization is performed.

bit 1 Unimplemented: Read as ‘0’

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1 and clears Timer1 gate flip-flop

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R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 gate function

0 = Timer1 is always counting

bit 6 T1GPOL: Timer1 Gate Polarity bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high)

0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 5 T1GTM: Timer1 Gate Toggle Mode bit

1 = Timer1 Gate Toggle mode is enabled

0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit

1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate

0 = Timer1 Gate Single-Pulse mode is disabled

bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge

0 = Timer1 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when T1GSPM is cleared

bit 2 T1GVAL: Timer1 Gate Value Status bit (read-only)

Indicates the current state of the Timer1 gate, latched at Q1, provided to TMR1H:TMR1L

Unaffected by Timer1 Gate Enable (TMR1GE)

bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits

11 = Comparator 2 optionally synchronized output(1)

10 = Comparator 1 optionally synchronized output

01 = Timer0 overflow output

00 = Timer1 gate pin

Note 1: PIC16(L)F18323 only; otherwise Reserved - do not use.

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

TMR1L<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TMR1L<7:0>: TMR1 Low Byte bits

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

TMR1H<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TMR1H<7:0>: TMR1 High Byte bits

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TABLE 27-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 B it 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 B it 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIR3 OSFIF CSWIF ― ― ― ― CLC2IF CLC1IF 98

PIE3 OSFIE CSWIE ― ― ― ― CLC2IE CLC1IE 93

PIR4 ―CWG1IF ― ― ― ― CCP2IF CCP1IF 99

PIE4 ―CWG1IE ― ― ― ― CCP2IE CCP1IE 94

T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSC T1SYNC ―TMR1ON 273

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 274

TMR1L TMR1L<7:0> 275

TMR1H TMR1H<7:0> 275

T1CKIPPS ― ― ― T1CKIPPS<4:0> 144

T1GPPS ― ― ― T1GPPS<4:0> 144

T0CON0 T0EN ―T0OUT T016BIT T0OUTPS<3:0> 261

CMxCON0 CxON CxOUT ―CxPOL ―CxSP CxHYS CxSYNC 171

CCPxCON CCPxEN ―CCPxOUT CCPxFMT CCPxMODE<3:0> 289

CLCxSELy ― ― ― LCxDyS<4:0> 210

ADACT ― ― ― ― ADACT<3:0> 227

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

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28.0 TIMER2 MODULE

Timer2 module is an 8-bit timer that incorporates the

following features:

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16,

and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match with PR2

• Optional use as the shift clock for the MSSP1

module

See Figure 28-1 for a block diagram of Timer2.

FIGURE 28-1: TIMER2 BLOCK DIAGRAM

Prescaler

1:1, 1:4, 1:16, 1:64

Fosc/4

TCKPS<1:0> Comparator Postscaler

1:1 to 1:16

TOUTPS<3:0>

set bit

TMRIF

TMR2 R

PR2

T_match

To Peripherals

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28.1 Timer2 Operation

The clock input to the Timer2 modules is the system

instruction clock (FOSC/4).

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

T2CKPS<1:0> of the T2CON register. The value of

TMR2 is compared to that of the Period register, PR2, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMR2 to 00h

on the next cycle and drives the output

counter/postscaler (see Section 28.2 “Timer2

Interrupt”).

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, whereas the PR2 register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• A write to the TMR2 register

• A write to the T2CON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR

Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

•RESET Instruction

28.2 Timer2 Interr upt

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2-to-PR2 match)

provides the input for the 4-bit counter/postscaler. This

counter generates the TMR2 match interrupt flag which

is latched in TMR2IF of the PIR1 register. The interrupt

is enabled by setting the TMR2 Match Interrupt Enable

bit, TMR2IE, of the PIE1 register.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0>, of the T2CON register.

28.3 Timer2 Output

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSP1 module operating in SPI mode.

Additional information is provided in Section 30.0

“Master Synchro nous Serial Port (MSSP1) Module”

28.4 Timer2 Operation During Sleep

The Timer2 timers cannot be operated while the

processor is in Sleep mode. The contents of the TMR2

and PR2 registers will remain unchanged while the

processor is in Sleep mode.

Note: TMR2 is not cleared when T2CON is

written.

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28.5 Re g ister De finitions : Tim e r2 C o n tr o l

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits

1111 = 1:16 Postscaler

1110 = 1:15 Postscaler

1101 = 1:14 Postscaler

1100 = 1:13 Postscaler

1011 = 1:12 Postscaler

1010 = 1:11 Postscaler

1001 = 1:10 Postscaler

1000 = 1:9 Postscaler

0111 = 1:8 Postscaler

0110 = 1:7 Postscaler

0101 = 1:6 Postscaler

0100 = 1:5 Postscaler

0011 = 1:4 Postscaler

0010 = 1:3 Postscaler

0001 = 1:2 Postscaler

0000 = 1:1 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

11 = Prescaler is 64

10 = Prescaler is 16

01 =Prescaler is 4

00 =Prescaler is 1

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

TMR2<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TMRx<7:0>: TMR2 Counter bits 7..0

R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

PR2<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 PRx<7:0>: TMR2 Counter bits 7..0

When TMR2 = PR2, the next clock will reset the counter; counter period is (PR2+1)

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TABLE 28-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIR2 ―C2IF(1) C1IF NVMIF ― ― ― NCO1IF 97

PIE2 ―C2IE(1) C1IE NVMIE ― ― ― NCO1IE 92

T2CON ―T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 279

TMR2 TMR2<7:0> 280

PR2 PR2<7:0> 280

ADACT ― ― ― ― ADACT<3:0> 227

CLCxSELy ― ― ― LCxDyS<4:0> 210

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

Note 1: PIC16(L)F18323 only.

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29.0 CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral

that allows the user to time and control different events

and to generate Pulse-Width Modulation (PWM)

signals. In Capture mode, the peripheral allows the

timing of the duration of an event. The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate Pulse-Width Modulated signals of

varying frequency and duty cycle.

This family of devices contains two standard

Capture/Compare/PWM modules (CCP1 and CCP2.

The Capture and Compare functions are identical for all

CCP modules.

29.1 Capture Mode

Capture mode makes use of either the 16-bit Timer0 or

Timer1 resource. When an event occurs on the capture

source, the 16-bit CCPRxH:CCPRxL register pair

captures and stores the 16-bit value of the

TMR0H:TMR0L or TMR1H:TMR1L register pair,

respectively. An event is defined as one of the following

and is configured by the CCPxMODE<3:0> bits of the

CCPxCON register:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCPxIF of the PIR4 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value.

Figure 29-1 shows a simplified diagram of the capture

operation.

29.1.1 CAPTURE SOURCES

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

The capture source is selected by configuring the

CCPxCTS<3:0> bits of the CCPxCAP register. The

following sources can be selected:

• CCPxPPS input

• C1_output

• C2_output (PIC16(L)F18323 only)

• NCO_output

• IOC_interrupt

• LC1_output

• LC2_output

Note 1: In devices with more than one CCP

module, it is very important to pay close

attention to the register names used. A

number placed after the module acronym

is used to distinguish between separate

modules. For example, the CCP1CON

and CCP2CON control the same

operational aspects of two completely

different CCP modules.

2: Throughout this section, generic

references to a CCP module in any of its

operating modes may be interpreted as

being equally applicable to CCPx module.

and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular module,

when required.

Note: If the CCPx pin is configured as an output,

a write to the port can cause a Capture

condition.

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FIGURE 29-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

Rev. 10-000158I

8/29/2016

CCPRxH CCPRxL

TMR1H TMR1L

Prescaler

1,4,16

CCPx

TRIS Control

set CCPxIF

CCPx

MODE <3:0>

and

Edge Detect

C1OUT_sync

C2OUT_sync

IOC_interrupt

RxyPPS

CCPxCTS<1:0>

000

011

010

001

100

101

110

111

NCO

LC1_output

LC2_output

Reserved

Capture

Enable

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29.1.2 TIMER1 MODE RESOURCE

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

See Section 27.0 “Timer1 Module with Gate

Control” for more information on configuring Timer1.

29.1.3 SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIE4 register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIR4 register

following any change in Operating mode.

29.1.4 CCP PRESCALER

There are four prescaler settings specified by the

CCPxMODE<3:0> bits of the CCPxCON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler. Example 29-1 demonstrates the code to

perform this function.

EXAMPLE 29-1: CHANGIN G BETW EE N

CAPTURE PRESCALERS

29.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1 is

clocked by an external clock source.

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

BANKSEL CCPxCON ;Set Bank bits to point

;to CCPxCON

CLRF CCPxCON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

;the new prescaler

;move value and CCP ON

MOVWF CCPxCON ;Load CCPxCON with this

;value

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29.2 Compare Mode

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPRxH:CCPRxL

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate an Auto-conversion Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxMODE<3:0> control bits of the CCPxCON regis-

ter. At the same time, the interrupt flag CCPxIF bit is

set, and an ADC conversion can be triggered, if

selected.

All Compare modes can generate an interrupt and

trigger an ADC conversion.

Figure 29-2 shows a simplified diagram of the compare

operation.

FIGUR E 29 -2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

29.2.1 CCPX PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit and defining the

appropriate output pin through the RxyPPS registers.

See Section 13.0 “Peripheral Pin Select (PPS)

Module” for more details.

29.2.2 TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized mode. The compare

operation may not work in Asynchronous mode.

See Section 27.0 “T imer1 Module with Gate Control”

for more information on configuring Timer1.

29.2.3 AUTO-CONVERSION TRIGGER

All CCPx modes set the CCP interrupt flag

(CCPxIF). When this flag is set as a match occurs,

an auto-conversion trigger can occur if the CCP

module is selected as the conversion trigger source.

Refer to Section 22.2.5 “Auto-Conversion Trigger”

for more information.

29.2.4 COMPARE DURING SLEEP

Since FOSC is shut down during Sleep mode, the

Compare mode will not function properly during Sleep,

unless the timer is running. The device will wake on

interrupt (if enabled).

29.2.5 COMPARE INTERRUPTS

The CCPxIF interrupt flag will be set when a match

between the CCPRxH:CCPRxL register pair and the

TMR1H:TMR1L register pair occurs. If the device is in

Sleep and interrupts are enabled (CCPxIE = 1), the

device will wake up, assuming Timer1 is operating

during Sleep.

Note: When the CCP is configured in Compare

mode using the ‘toggle output on match’

setting (CCPxMODE<3:0> bits = 0010)

and the reference timer is set for an input

clock prescale other than 1:1, the output

of the CCP will toggle multiple times until

finally settling a ‘0’ logic level. To avoid

this, the timer input clock prescale select

bits must be set to a 1:1 ratio

(TxCKPS = 00).

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

Output

Logic

Auto-conversion Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxMODE<3:0>

Mode Select

Output Enable

CCPx

Note: Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

Note: Removing the Match condition by chang-

ing the contents of the CCPRxH and

CCPRxL register pair, between the clock

edge that generates the Auto-conversion

Trigger and the clock edge that generates

the Timer Reset, will preclude the Reset

from occurring.

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29.3 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the on state and the low portion of the signal

is considered the off state. The high portion, also known

as the pulse width, can vary in time and is defined in

steps. A larger number of steps applied, which

lengthens the pulse width, also supplies more power to

the load. Lowering the number of steps applied, which

shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete

cycle or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and in turn the power that is applied to the

load.

The term duty cycle describes the proportion of the on

time to the off time and is expressed in percentages,

where 0% is fully off and 100% is fully on. A lower duty

cycle corresponds to less power applied and a higher

duty cycle corresponds to more power applied.

Figure 29-3 shows a typical waveform of the PWM

signal.

29.3.1 STANDARD PWM OPERATION

The standard PWM mode generates a Pulse-Width

Modulation (PWM) signal on the CCPx pin with up to

ten bits of resolution. The period, duty cycle, and

resolution are controlled by the following registers:

• PR2 register

• T2CON register

• CCPRxL registers

• CCPxCON registers

Figure 29-4 shows a simplified block diagram of PWM

operation.

FIGURE 29-3: CCP PWM OUTPUT SIGNAL

FIGURE 29-4: SIMPLIFIED PWM BLOCK DIAGRAM

Note: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

Period

Pulse Width

TMR2/4/6 = 0

TMR2/4/6 = CCPRxH:CCPRxL

TMR2 = PR2

Rev. 10-000157B

2/27/2014

CCPRxH

Duty cycle registers

10-bit Latch(2)

(Not accessible by user)

Comparator

PR2

(1)

TMR2

TMR2 Module

CCPx

CCPx_out To Peripherals

TRIS Control

CCPRxL

set CCPIF

CCPx_pset

ERS logic

Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to

create 10-bit time-base.

2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.

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29.3.2 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for standard PWM operation:

1. Use the desired output pin RxyPPS control to

select CCPx as the source and disable the

CCPx pin output driver by setting the associated

TRIS bit.

2. Load the PR2 register with the PWM period

value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

4. Load the CCPRxL register and the CCPRxH

configure the CCPxFMT bit of the CCPxCON

5. Configure and start Timer2.

• Clear the TMR2IF interrupt flag bits of the

PIR4 register. See Note below.

• Configure the T2CKPS bits of the T2CON

• Enable the Timer by setting the TMR2ON

bit of the T2CON register.

6. Enable PWM output pin:

• Wait until the Timer overflows and the

TMR2IF bits of the PIR4 register is set. See

Note below.

• Enable the CCPx pin output driver by

clearing the associated TRIS bit.

29.3.3 TIMER2 TIMER RESOURCE

The PWM standard mode makes use of the 8-bit

Timer2 timer resources to specify the PWM period.

29.3.4 PWM PERIOD

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 29-1.

EQUATION 29-1: PWM PERIOD

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM duty cycle is transferred from the

CCPRxL/H register pair into a 10-bit buffer.

29.3.5 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to the CCPRxH:CCPRxL register pair. The

alignment of the 10-bit value is determined by the

CCPRxFMT bit of the CCPxCON register (see

Figure 29-5). The CCPRxH:CCPRxL register pair can

be written to at any time; however, the duty cycle value

is not latched into the 10-bit buffer until after a match

between PR2 and TMR2.

Equation 29-2 is used to calculate the PWM pulse

width.

Equation 29-3 is used to calculate the PWM duty cycle

ratio.

FIGURE 29-5: PWM 10-BIT ALIGNMENT

BLOCK DIAGRAM

Note: In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

Note: The Timer postscaler (see Section 28.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency.

PWM Period PR221+4TOSC =

(TM R2 Prescale Valu e)

Note: TOSC = 1/FOSC

Rev . 10-000 160A

12/9 /201 3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CCPRxH CCPRxL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

CCPRxH CCPRxL

FMT = 0

FMT = 1

7 6 5 4 3 2 1 09 8

10-bit Duty Cycle

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EQUATION 29-2: PULSE WIDTH

EQUATION 29-3: DUTY CYCLE RATIO

The CCPRxH:CCPRxL register pair and a 2-bit internal

latch are used to double buffer the PWM duty cycle.

This double buffering provides glitchless PWM

operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two bits

of the prescaler, to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the

CCPRxH:CCPRxL register pair, then the CCPx pin is

cleared (see Figure 29-4).

29.3.6 PWM RESOLUTION

PWM resolution, expressed in number of bits, defines

the maximum number of discrete steps that can be

present in a single PWM period. For example, a 10-bit

resolution will result in 1024 discrete steps, whereas

an 8-bit resolution will result in 256 discrete steps.

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 29-4.

EQUATION 29-4: PWM RESOLUTION

29.3.7 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCPx

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

29.3.8 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 7.0 “Oscillator Module” for additional

details.

29.3.9 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

Pulse Width CCPRxH:CCPRxL register pair



TOSC



(TMR2 Prescale Value)

Duty Cycle Ratio CCPRxH:CCPRxL register pair

4PR21+

----------------------------------------------------------------------------------=

Note: If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

Resolution 4PR21+log 2log

------------------------------------------ bits=

TABLE 29-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 29-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale 16 4 1 1 1 1

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resolution (bits) 8 8 8 6 5 5

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29.4 Re g is ter De finiti o n s : C C P Co n t ro l

R/W-0/0 U-0 R-x/x R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CCPxEN — CCPxOUT CCPxFMT CCPxMODE<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CCPxEN: CCP Module Enable bit

0 = CCP is disabled

1 = CCP is enabled

bit 6 Unimplemented: Read as ‘0’

bit 5 CCPxOUT: CCPx Output Data (read-only) bit

bit 4 CCPxFMT: CCPW (pulse width) Alignment bit

CCPxMODE = Capture mode

Unused

CCPxMODE = Compare mode

Unused

CCPxMODE = PWM mode

0 = Right-aligned format

1 = Left-aligned format

bit 3-0 CCPxMODE<3:0>: CCPx Mode Select bits(1)

1111 = PWM mode

1110 = Reserved

1101 = Reserved

1100 = Reserved

1011 = Compare mode: output will pulse 0-1-0; Clears TMR1

1010 = Compare mode: output will pulse 0-1-0

1001 = Compare mode: clear output on compare match

1000 = Compare mode: set output on compare match

0111 = Capture mode: every 16th rising edge of CCPx input

0110 = Capture mode: every 4th rising edge of CCPx input

0101 = Capture mode: every rising edge of CCPx input

0100 = Capture mode: every falling edge of CCPx input

0011 = Capture mode: every edge of CCPx input

0010 = Compare mode: toggle output on match

0001 = Compare mode: toggle output on match; clear TMR1

0000 = Capture/Compare/PWM off (resets CCPx module)

Note 1: All modes will set the CCPxIF bit and will trigger an ADC conversion if CCPx is selected as the ADC trigger

source.

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U-0 U-0 U-0 U-0 U-0 R/W-0/x R/W-0/x R/W-0/x

— — — — —CCPxCTS<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 CCPxCTS<2:0>: CCPx Capture Mode Data Select bits

Note 1: PIC16(L)F18323 only.

CTS<2:0> CCP1CAP

CAPTURE INPUT CCP2CAP

CAPTURE INPUT

000 CCP1PPS CCP2PPS

001 C1OUT

010 C2OUT(1)

011 NCO1

100 IOC_interrupt

101 LC1_output

110 LC2_output

111 Reserved

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R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x

CCPRxL<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 CCPxMODE = Capture mode

CCPRxL<7:0>: Captured value of TMR1L

CCPxMODE = Compare mode

CCPRxL<7:0>: LS Byte compared to TMR1L

CCPxMODE = PWM modes when CCPxFMT = 0

CCPRxL<7:0>: CCPW<7:0> – Pulse-width Least Significant eight bits

CCPxMODE = PWM modes when CCPxFMT = 1

CCPRxL<7:6>: CCPW<1:0> – Pulse-width Least Significant two bits

CCPRxL<5:0>: Not used.

R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x

CCPRxH<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 CCPxMODE = Capture mode

CCPRxH<7:0>: Captured value of TMR1H

CCPxMODE = Compare mode

CCPRxH<7:0>: MS Byte compared to TMR1H

CCPxMODE = PWM modes when CCPxFMT = 0

CCPRxH<7:2>: Not used

CCPRxH<1:0>: CCPW<9:8> – Pulse-width Most Significant two bits

CCPxMODE = PWM modes when CCPxFMT = 1

CCPRxH<7:0>: CCPW<9:2> – Pulse-width Most Significant eight bits

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TABLE 29-3: SUMMARY OF REGISTERS ASSOCIATED WITH CCPx

Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISC7(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC7(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR4 ―CWG1IF ― ― ― ― CCP2IF CCP1IF 99

PIE4 ―CWGIE ― ― ― ― CCP2IE CCP1IE 94

CCPxCON CCPxEN ―CCPxOUT CCPxFMT CCPxMODE<3:0> 289

CCPxCAP ― ― ― ― ― CCPxCTS<2:0> 290

CCPRxL CCPRx<7:0> 291

CCPRxH CCPRx<15:8> 291

CCP1PPS ― ― ― CCP1PPS<4:0> 144

CCP2PPS ― ― ― CCP2PPS<4:0> 144

ADACT ― ― ― ― ADACT<3:0> 227

CLCxSELy ― ― ― LCxDyS<4:0> 210

CWG1DAT ― ― ― ― DAT<3:0> 196

MDSRC ― ― ― ― MDMS<3:0> 253

MDCARH ―MDCHPOL MDCHSYNC ―MDCH<3:0> 254

MDCARL ―MDCLPOL MDCLSYNC ―MDCL<3:0> 255

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

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30.0 MASTER SYNCHRONOUS

SERIAL PORT (MS SP1)

MODULE

30.1 MSSP1 Module Overview

The Master Synchronous Serial Port (MSSP1) module

is a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D Converters, etc. The MSSP1

module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C)

The SPI interface supports the following modes and

features:

•Master mode

• Slave mode

• Clock Polarity

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

Figure 30-1 is a block diagram of the SPI interface

module.

FIGURE 30-1: MSSP BLOCK DIAGRAM (SPI MODE)

( )

Read Write

Data Bus

SSP1SR Reg

SSPM<3:0>

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

T2_match

Edge

Select

2 (CKP, CKE)

TRIS bit

SDO

SSP1BUF Reg

SDI

SCK TOSC

Prescaler

4, 16, 64

Baud Rate

Generator

(SSP1ADD)

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The I2C interface supports the following modes and

features:

•Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

• Clock stretching

• Bus collision detection

• General call address matching

•Address masking

• Selectable SDA hold times

Figure 30-2 is a block diagram of the I2C interface

module in Master mode. Figure 30-3 is a diagram of the

I2C interface module in Slave mode.

FIGURE 30-2: MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Read Write

SSP1SR

Start bit, Stop bit,

Start bit detect,

SSP1BUF

Internal

data bus

Set/Reset: S, P, SSP1STAT, WCOL, SSPOV

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate (SSP1CON2)

Stop bit detect

Write collision detect

Clock arbitration

State counter for

end of XMIT/RCV

SCL

SCL in

Bus Collision

SDA in

Receive Enable (RCEN)

Clock Cntl

Clock arbitrate/BCOL detect

(Hold off clock source)

[SSPM<3:0>]

Baud Rate

Reset SEN, PEN (SSP1CON2)

Generator

(SSP1ADD)

Address Match detect

Set SSP1IF, BCLxIF

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FIGURE 30-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE)

Read Write

SSP1SR Reg

Match Detect

SSP1ADD Reg

Start and

Stop bit Detect

SSP1BUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSP1STAT Reg)

SCL

SDA

Shift

Clock

MSb LSb

SSP1MSK Reg

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30.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that

operates in Full-Duplex mode. Devices communicate

in a master/slave environment where the master device

initiates the communication. A slave device is

controlled through a Chip Select known as Slave

Select.

The SPI bus specifies four signal connections:

• Serial Clock (SCK)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Slave Select (SS)

Figure 30-1 shows the block diagram of the MSSP1

module when operating in SPI mode.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select

connection can be used to address each slave

individually.

Figure 30-4 shows a typical connection between a

master device and multiple slave devices.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. Data is

always shifted out one bit at a time, with the Most

Significant bit (MSb) shifted out first. At the same time,

a new Least Significant bit (LSb) is shifted into the

same register.

Figure 30-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the

programmed clock edge and latched on the opposite

edge of the clock.

The master device transmits information out on its SDO

output pin which is connected to, and received by, the

slave’s SDI input pin. The slave device transmits

information out on its SDO output pin, which is

connected to, and received by, the master’s SDI input

pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

During each SPI clock cycle, a full-duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

its SDO pin) and the slave device is reading this bit and

saving it as the LSb of its shift register, that the slave

device is also sending out the MSb from its shift register

(on its SDO pin) and the master device is reading this

bit and saving it as the LSb of its shift register.

After eight bits have been shifted out, the master and

slave have exchanged register values.

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends useful data and slave sends dummy

data.

• Master sends useful data and slave sends useful

data.

• Master sends dummy data and slave sends useful

data.

Transmissions must be performed in multiples of eight

clock pulses. When there is no more data to be

transmitted, the master stops sending the clock signal

and it deselects the slave.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

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FIGURE 30-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION

30.2.1 SPI MODE REGISTERS

The MSSP1 module has five registers for SPI mode

operation. These are:

• MSSP1 STATUS register (SSP1STAT)

• MSSP1 Control register 1 (SSP1CON1)

• MSSP1 Control register 3 (SSP1CON3)

• MSSP1 Data Buffer register (SSP1BUF)

• MSSP1 Address register (SSP1ADD)

• MSSP1 Shift register (SSP1SR)

(Not directly accessible)

SSP1CON1 and SSPSTAT are the control and

STATUS registers in SPI mode operation. The

SSP1CON1 register is readable and writable. The

lower six bits of the SSP1STAT are read-only. The

upper two bits of the SSP1STAT are read/write.

In one SPI Master mode, SSP1ADD can be loaded

with a value used in the Baud Rate Generator. More

information on the Baud Rate Generator is available in

Section 30.7 “Baud Rate Generator”.

SSP1SR is the shift register used for shifting data in

and out. SSP1BUF provides indirect access to the

SSP1SR register. SSP1BUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSP1SR and SSP1BUF

together create a buffered receiver. When SSP1SR

receives a complete byte, it is transferred to SSP1BUF

and the SSP1IF interrupt is set.

During transmission, the SSP1BUF is not buffered. A

write to SSP1BUF will write to both SSP1BUF and

SSP1SR.

30.2.2 SPI MODE OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSP1CON1<3:0> and SSP1STAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN of the

SSP1CON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSP1CONy registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as

follows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

•SS

must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

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The MSSP1 consists of a transmit/receive shift register

(SSP1SR) and a buffer register (SSP1BUF). The

SSP1SR shifts the data in and out of the device, MSb

first. The SSP1BUF holds the data that was written to

the SSP1SR until the received data is ready. Once the

eight bits of data have been received, that byte is

moved to the SSP1BUF register. Then, the Buffer Full

Detect bit, BF of the SSP1STAT register, and the

interrupt flag bit, SSP1IF, are set. Any write to the

SSP1BUF register during transmission/reception of

data will be ignored and the write collision detect bit,

WCOL, of the SSP1CON1 register, will be set. User

software must clear the WCOL bit to allow the following

write(s) to the SSP1BUF register to complete

successfully.

When the application software is expecting to receive

valid data, the SSP1BUF should be read before the

next byte of data to transfer is written to the SSP1BUF.

The Buffer Full bit, BF of the SSP1STAT register,

indicates when SSP1BUF has been loaded with the

received data (transmission is complete). When the

SSP1BUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSP interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

The SSP1SR is not directly readable or writable and

can only be accessed by addressing the SSP1BUF

FIGURE 30-5: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSP1BUF)

Shift Register

(SSP1SR)

MSb LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buffer

(SSP1BUF)

Shift Register

(SSP1SR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

Slave Select

General I/O (optional)

= 1010

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30.2.3 SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK line. The master

determines when the slave (Processor 2, Figure 30-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSP1BUF register is written to. If the SPI

is only going to receive, the SDO output could be

disabled (programmed as an input). The SSP1SR

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSP1BUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

The clock polarity is selected by appropriately

programming the CKP bit of the SSP1CON1 register

and the CKE bit of the SSP1STAT register. This then,

would give waveforms for SPI communication as

shown in Figure 30-6, Figure 30-8, Figure 30-9 and

Figure 30-10, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 * TCY)

•FOSC/64 (or 16 * TCY)

• Timer2 output/2

•F

OSC/(4 * (SSPADD + 1))

Figure 30-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSP1BUF is loaded with the received

data is shown.

FIGURE 30-6: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSP1IF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSP1SR to

SSP1BUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

bit 0

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30.2.4 SPI SLAVE MODE

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last

bit is latched, the SSP1IF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSP1CON1 register.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCK pin

input and when a byte is received, the device will

generate an interrupt. If enabled, the device will

wake-up from Sleep.

30.2.4.1 Daisy-Chain Configuration

The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is

connected to the second slave input, the second slave

output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The

daisy-chain feature only requires a single Slave Select

line from the master device.

Figure 30-7 shows the block diagram of a typical

daisy-chain connection when operating in SPI mode.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSP1CON3 register will enable writes

to the SSP1BUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

30.2.5 SLAVE SELECT

SYNCHRONIZATION

The Slave Select can also be used to synchronize

communication. The Slave Select line is held high until

the master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will

eventually become out of sync with the master. If the

slave misses a bit, it will always be one bit off in future

transmissions. Use of the Slave Select line allows the

slave and master to align themselves at the beginning

of each transmission.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSP1CON1<3:0> = 0100).

When the SS pin is low, transmission and reception are

enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSP1CON1<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SS pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSP1STAT register must

remain clear.

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FIGURE 30-7: SPI DAISY-CHAIN CONNECTION

FIGURE 30-8: SL AVE SELECT SYNCHRONOUS WAVEFORM

SPI Master SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 7

SSP1IF

Interrupt

CKE = 0)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

bit 0

bit 7

bit 0

bit 6

SSP1BUF to

SSP1SR

Shift register SSP1SR

and bit count are reset

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FIGURE 30-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 30-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSP1IF

Interrupt

CKE = 0)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

Optional

bit 0

detection active

Write Collision

Valid

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSP1IF

Interrupt

CKE = 1)

Write to

SSP1BUF

SSP1SR to

SSP1BUF

Flag

Not Optional

Write Collision

detection active

Valid

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30.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes. After the device returns to Run mode,

the module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

MSSP interrupt flag bit will be set and if enabled, will

wake the device.

30.3 I2C Mode Overview

The Inter-Integrated Circuit (I2C) bus is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A slave device is

controlled through addressing.

The I2C bus specifies two signal connections:

• Serial Clock (SCL)

• Serial Data (SDA)

Figure 30-2 and Figure 30-3 show the block diagrams

of the MSSP1 module when operating in I2C mode.

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

Figure 30-11 shows a typical connection between two

processors configured as master and slave devices.

The I2C bus can operate with one or more master

devices and one or more slave devices.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, the master device sends out

a Start condition followed by the address byte of the

slave it intends to communicate with. This is followed

by a single Read/Write bit, which determines whether

the master intends to transmit to or receive data from

the slave device.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues to either transmit or receive

data from the slave.

FIGURE 30-11: I2C MASTER/

SLAVE CONNECTION

Master

SCL

SDA

SCL

SDA

Slave

VDD

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On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends a

NACK in place of the last ACK bit. A Stop bit is

indicated by a low-to-high transition of the SDA line

while the SCL line is held high.

In some cases, the master may want to maintain

control of the bus and re-initiate another transmission.

If so, the master device may send a Restart condition

in place of the Stop bit or last ACK bit when it is in

Receive mode.

The I2C bus specifies three message protocols;

• Single message where a master writes data to a

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

30.3.1 CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of clock stretching. An addressed slave device

may hold the SCL clock line low after receiving or send-

ing a bit, indicating that it is not yet ready to continue.

The master that is communicating with the slave will

attempt to raise the SCL line in order to transfer the

next bit, but will detect that the clock line has not yet

been released. Because the SCL connection is

open-drain, the slave has the ability to hold that line low

until it is ready to continue communicating.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

30.3.2 ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDA data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels do not match, loses arbitra-

tion, and must stop transmitting on the SDA line.

For example, if one transmitter holds the SDA line to a

logical one (lets it float) and a second transmitter holds

it to a logical zero (pulls it low), the result is that the

SDA line will be low. The first transmitter then observes

that the level of the line is different than expected and

concludes that another transmitter is communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDA

line. If this transmitter is also a master device, it also

must stop driving the SCL line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDA line continues with its

original transmission.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less

common.

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30.4 I2C MODE OPERATION

All MSSP I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC®

microcontroller and user software. Two pins, SDA and

SCL, are exercised by the module to communicate

with other external I2C devices.

30.4.1 BYTE FORMAT

All communication in I2C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa,

followed by an Acknowledge bit sent back. After the

eighth falling edge of the SCL line, the device output-

ting data on the SDA changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

30.4.2 DEFINITION OF I2C TERMINOLOGY

There is language and terminology in the description

of I2C communication that have definitions specific to

I2C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I2C

specification.

30.4.3 SDA AND SCL PINS

When selecting any I2C mode, the SCL and SDA pins

should be set by the user to inputs by setting the

appropriate TRIS bits.

30.4.4 SDA HOLD TIME

The hold time of the SDA pin is selected by the SDAHT

bit of the SSP1CON3 register. Hold time is the time

SDA is held valid after the falling edge of SCL. Setting

the SDAHT bit selects a longer 300 ns minimum hold

time and may help on buses with large capacitance.

Note: Any device pin can be selected for SDA

and SCL functions with the PPS

peripheral. These functions are

bidirectional. The SDA input is selected

with the SSPDATPPS registers. The SCL

input is selected with the SSPCLKPPS

registers. Outputs are selected with the

RxyPPS registers. It is the user’s

responsibility to make the selections so

that both the input and the output for each

function is on the same pin.

TABLE 30-1: I2C BUS TERMS

TERM Description

Transmitter The device which shifts data out

onto the bus.

Receiver The device which shifts data in

from the bus.

Master The device that initiates a transfer,

generates clock signals and

terminates a transfer.

Slave The device addressed by the

master.

Multi-master A bus with more than one device

that can initiate data transfers.

Arbitration Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle No master is controlling the bus,

and both SDA and SCL lines are

high.

Active Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPADD.

Write Request Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Read Request Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

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30.4.5 START CONDITION

The I2C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an Active state. Figure 30-12 shows wave

forms for Start and Stop conditions.

30.4.6 STOP CONDITION

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

30.4.7 RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave. Figure 30-13 shows the wave form for a

Restart condition.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

30.4.8 START/STOP CONDITION

INTERRUPT MASKING

The SCIE and PCIE bits of the SSP1CON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 30-12 : I2C START AND STOP CONDITIONS

FIGURE 30-13 : I2C RESTART CONDITION

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

SDA

SCL

Stop

Condition

Start

Condition

Change of

Data Allowed

Change of

Data Allowed

Restart

Condition

Change of

Data Allowed

Change of

Data Allowed

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30.4.9 ACKNOWLEDGE SEQUENCE

The ninth SCL pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicates to the transmitter that the

device has received the transmitted data and is ready

to receive more.

The result of an ACK is placed in the ACKSTAT bit of

the SSP1CON2 register.

Slave software, when the AHEN and DHEN bits are

set, the clock is stretched, allowing the slave time to

change the ACK value before it is sent back to the

transmitter. The ACKDT bit of the SSP1CON2 register

is set/cleared to determine the response.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSP1STAT

are set when a byte is received.

When the module is addressed, after the eighth falling

edge of SCL on the bus, the ACKTIM bit of the

SSP1CON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

30.5 I2C SLAVE MODE OPERATION

The MSSP Slave mode operates in one of four modes

selected by the SSPM bits of SSP1CON1 register. The

modes can be divided into 7-bit and 10-bit Addressing

mode. 10-bit Addressing modes operate the same as

7-bit with some additional overhead for handling the

larger addresses.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSP1IF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

30.5.1 SLAVE MODE ADDRESSES

The SSP1ADD register (Register 30-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSP1BUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the

software that anything happened.

The SSP Mask register (Register 30-5) affects the

address matching process. See Section 30.5.9 “SSP

Mask Register” for more information.

30.5.1.1 I2C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

30.5.1.2 I2C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb’s of the 10-bit address and

stored in bits 2 and 1 of the SSP1ADD register.

After the acknowledge of the high byte the UA bit is set

and SCL is held low until the user updates SSP1ADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSP1ADD. Even if there is not an address

match; SSP1IF and UA are set, and SCL is held low

until SSP1ADD is updated to receive a high byte

again. When SSP1ADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave

hardware will then acknowledge the read request and

prepare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

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30.5.2 SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSP1STAT register is

cleared. The received address is loaded into the

SSP1BUF register and acknowledged.

When the Overflow condition exists for a received

address, then not Acknowledge is given. An Overflow

condition is defined as either bit BF of the SSP1STAT

is set. The BOEN bit of the SSP1CON3 register modi-

fies this operation. For more information see

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSP1IF, must be cleared by

software.

When the SEN bit of the SSP1CON2 register is set,

SCL will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSP1CON1 register.

30.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C slave in

7-bit Addressing mode. Figure 30-14 and Figure 30-15

is used as a visual reference for this description.

This is a step-by-step process of what typically must

be done to accomplish I2C communication.

1. Start bit detected.

2. S bit of SSP1STAT is set; SSP1IF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit clear is received.

4. The slave pulls SDA low sending an ACK to the

master, and sets SSP1IF bit.

5. Software clears the SSP1IF bit.

6. Software reads received address from

SSP1BUF clearing the BF flag.

7. If SEN = 1; Slave software sets CKP bit to

release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low sending an ACK to the

master, and sets SSP1IF bit.

10. Software clears SSP1IF.

11. Software reads the received byte from

SSP1BUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the master.

13. Master sends Stop condition, setting P bit of

SSP1STAT, and the bus goes idle.

30.5.2.2 7-bit Reception with AHEN and

DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the eighth

falling edge of SCL. These additional interrupts allow

time for the slave software to decide whether it wants

to ACK the receive address or data byte.

This list describes the steps that need to be taken by

slave software to use these options for I2C communi-

cation. Figure 30-16 displays a module using both

address and data holding. Figure 30-17 includes the

operation with the SEN bit of the SSP1CON2 register

set.

1. S bit of SSP1STAT is set; SSP1IF is set if

interrupt on Start detect is enabled.

2. Matching address with R/W bit clear is clocked

in. SSP1IF is set and CKP cleared by hardware

after the eighth falling edge of SCL.

3. Slave clears the SSP1IF.

4. Slave can look at the ACKTIM bit of the

SSP1CON3 register to determine if the SSP1IF

was after or before the ACK.

5. Slave reads the address value from SSP1BUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

7. Slave software releases the clock by setting

CKP.

8. SSP1IF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSP1IF.

11. SSP1IF set, and CKP is cleared by hardware

after eighth falling edge of SCL for a received

data byte.

12. Slave looks at ACKTIM bit of SSP1CON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSP1BUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK =1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSP1STAT register.

Note: SSP1IF is still set after the ninth falling edge

of SCL even if there is no clock stretching

and BF has been cleared. Only if NACK is

sent to master is SSP1IF not set

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FIGURE 30-14 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Data

ACK

Receiving Data ACK =1

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSP1IF

SSPOV

12345678 12345678 12345678

999

ACK is not sent.

SSPOV set because

SSP1BUF is still full.

Cleared by software

First byte

of data is

available

in SSP1BUF

SSP1BUF is read

SSP1IF set on 9th

falling edge of

SCL

Cleared by software

Bus Master sends

Stop condition

From Slave to Master

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FIGURE 30-15 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SEN SEN

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL 123456789 123456789 123456789 P

SSP1IF set on 9th

SCL is not held

CKP is written to ‘1’ in software,

ACK

low because

falling edge of SCL

releasing SCL

ACK is not sent.

Bus Master sends

CKP

SSPOV

SSP1IF

SSPOV set because

SSP1BUF is still full.

Cleared by software

First byte

of data is

available

in SSP1BUF

ACK=1

Cleared by software

SSP1BUF is read

Clock is held low until CKP is set to ‘1’

releasing SCL

Stop condition

ACK

Receive Address Receive Data Receive Data

R/W=0

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FIGURE 30-16 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

Receiving Address Receiving Data Received Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

CKP

12 3 4 56 7 8 912345678 9

12345678

Master sends

Stop condition

Data is read from SSP1BUF

Cleared by software

SSP1IF is set on

9th falling edge of

SCL, after ACK

CKP set by software,

SCL is released

Slave software

ACKTIM cleared by

hardware in 9th

rising edge of SCL

sets ACKDT to

not ACK

When DHEN = 1:

CKP is cleared by

hardware on 8th falling

edge of SCL

Slave software

clears ACKDT to

ACK the received

byte

ACKTIM set by hardware

on 8th falling edge of SCL

When AHEN=1:

CKP is cleared by hardware

and SCL is stretched

Address is

read from

SSP1BUF

ACKTIM set by hardware

on 8th falling edge of SCL

ACK

Master Releases SDA

to slave for ACK sequence

No interrupt

after not ACK

from Slave

ACK=1

ACK

ACKDT

ACKTIM

SSP1IF

If AHEN = 1:

SSP1IF is set

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FIGURE 30-17 : I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

Receiving Address Receive Data Receive Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSP1IF

ACKDT

CKP

ACK

S12

345678 912

34567 8 9 1234 5 67 8 9

ACK

Cleared by software

ACKTIM is cleared by hardware

SSP1BUF can be

Set by software,

read any time before

next byte is loaded

release SCL

on 9th rising edge of SCL

Received

address is loaded into

SSP1BUF

Slave software clears

ACKDT to ACK

R/W = 0Master releases

SDA to slave for ACK sequence

the received byte

When AHEN = 1;

on the 8th falling edge

of SCL of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCL

When DHEN = 1;

on the 8th falling edge

of SCL of a received

data byte, CKP is cleared

Received data is

available on SSP1BUF

Slave sends

not ACK

CKP is not cleared

if not ACK

Master sends

Stop condition

No interrupt after

if not ACK

from Slave

ACKTIM

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30.5.3 SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSP1STAT register is set. The received address is

loaded into the SSP1BUF register, and an ACK pulse

is sent by the slave on the ninth bit.

Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 30.5.6

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

The transmit data must be loaded into the SSP1BUF

the SCL pin should be released by setting the CKP bit

of the SSP1CON1 register. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. This ACK

value is copied to the ACKSTAT bit of the SSP1CON2

transfer is complete. When the not ACK is latched by the

slave, the slave goes idle and waits for another

occurrence of the Start bit. If the SDA line was low

(ACK), the next transmit data must be loaded into the

SSP1BUF register. Again, the SCL pin must be released

by setting bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSP1IF bit must be cleared by software and

the SSP1STAT register is used to determine the status

of the byte. The SSP1IF bit is set on the falling edge of

the ninth clock pulse.

30.5.3.1 Slave Mode Bus Collision

A slave receives a Read request and begins shifting

data out on the SDA line. If a bus collision is detected

and the SBCDE bit of the SSP1CON3 register is set,

the BCLIF bit of the PIR register is set. Once a bus col-

lision is detected, the slave goes idle and waits to be

addressed again. User software can use the BCLIF bit

to handle a slave bus collision.

30.5.3.2 7-bit Transmission

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish a standard transmission.

Figure 30-18 can be used as a reference to this list.

1. Master sends a Start condition on SDA and

SCL.

2. S bit of SSP1STAT is set; SSP1IF is set if

interrupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSP1IF bit.

4. Slave hardware generates an ACK and sets

SSP1IF.

5. SSP1IF bit is cleared by software.

6. Software reads the received address from

SSP1BUF, clearing BF.

7. R/W is set so CKP was automatically cleared by

hardware after the ACK.

8. The slave software loads the transmit data into

SSP1BUF.

9. CKP bit is set by software, releasing SCL, allow-

ing the master to clock the data out of the slave.

10. SSP1IF is set after the ACK response from the

master is loaded into the ACKSTAT bit

11. SSP1IF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

13. Steps 9-13 are repeated for each transmitted

byte.

14. If the master sends a not ACK; the clock is not

held, but SSP1IF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCL (9th) rather than the

falling.

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FIGURE 30-18 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSP1IF

CKP

ACKSTAT

R/W

D/A

Received address

When R/W is set

R/W is copied from the

Indicates an address

is read from SSP1BUF

SCL is always

held low after 9th SCL

falling edge

matching address byte

has been received

Masters not ACK

is copied to

ACKSTAT

CKP is not

held for not

ACK

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSP1BUF

Set by software

Cleared by software

ACK

R/W =1

Master sends

Stop condition

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30.5.3.3 7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSP1CON3 register

enables additional clock stretching and interrupt

generation after the eighth falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSP1IF

interrupt is set.

Figure 30-19 displays a standard waveform of a 7-bit

address slave transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit of

SSP1STAT is set; SSP1IF is set if interrupt on

Start detect is enabled.

3. Master sends matching address with R/W bit

set. After the eighth falling edge of the SCL line

the CKP bit is cleared by hardware and SSP1IF

interrupt is generated.

4. Slave software clears SSP1IF.

5. Slave software reads ACKTIM bit of SSP1CON3

6. Slave reads the address value from the

SSP1BUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets the ACKDT

bit of the SSP1CON2 register accordingly.

8. Slave software sets the CKP bit releasing SCL.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSP1IF after the ACK if the R/W bit is

set.

11. Slave software clears SSP1IF.

12. Slave loads value to transmit to the master into

SSP1BUF setting the BF bit.

13. Slave software sets the CKP bit releasing the

clock.

14. Master clocks out the data from the slave and

sends an ACK value on the ninth SCL pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSP1CON2 register.

16. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: SSP1BUF cannot be loaded until after the

ACK.

Note: Master must send a not ACK on the last

byte to ensure that the slave releases the

SCL line to receive a Stop.

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FIGURE 30-19 : I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

Receiving Address Automatic Transmitting Data Automatic Transmitting Data

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

SSP1IF

ACKDT

ACKSTAT

CKP

R/W

D/A

Received address

is read from SSP1BUF

BF is automatically

cleared after 8th falling

edge of SCL

Data to transmit is

loaded into SSP1BUF

Cleared by software

Slave clears

ACKDT to ACK

address

Master’s ACK

response is copied

to SSP1STAT

CKP not cleared

after not ACK

Set by software,

releases SCL

ACKTIM is cleared

on 9th rising edge of SCL

ACKTIM is set on 8th falling

edge of SCL

When AHEN = 1;

CKP is cleared by hardware

after receiving matching

address.

When R/W = 1;

CKP is always

cleared after ACK

Master sends

Stop condition

ACK

R/W =1

Master releases SDA

to slave for ACK sequence

ACK

ACKTIM

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30.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

This section describes a standard sequence of events

for the MSSP1 module configured as an I2C slave in

10-bit Addressing mode.

Figure 30-20 is used as a visual reference for this

description.

This is a step-by-step process of what must be done

by slave software to accomplish I2C communication.

1. Bus starts Idle.

2. Master sends Start condition; S bit of

SSP1STAT is set; SSP1IF is set if interrupt on

Start detect is enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSP1STAT register is set.

4. Slave sends ACK and SSP1IF is set.

5. Software clears the SSP1IF bit.

6. Software reads received address from

SSP1BUF clearing the BF flag.

7. Slave loads low address into SSP1ADD,

releasing SCL.

8. Master sends matching low address byte to the

slave; UA bit is set.

9. Slave sends ACK and SSP1IF is set.

10. Slave clears SSP1IF.

11. Slave reads the received matching address

from SSP1BUF clearing BF.

12. Slave loads high address into SSP1ADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the ninth SCL

pulse; SSP1IF is set.

14. If SEN bit of SSP1CON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSP1IF.

16. Slave reads the received byte from SSP1BUF

clearing BF.

17. If SEN is set the slave software sets CKP to

release the SCL.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

30.5.5 10-BIT ADDRESSING WITH

ADDRESS OR DATA HOLD

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSP1ADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCL line is held low are the

same. Figure 30-21 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 30-22 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

Note: Updates to the SSP1ADD register are not

allowed until after the ACK sequence.

Note: If the low address does not match, SSP1IF

and UA are still set so that the slave

software can set SSP1ADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

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FIGURE 30-20 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

SSP1IF

Receive First Address Byte

ACK

Receive Second Address Byte

ACK

Receive Data

ACK

Receive Data

ACK

11110

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

CKP

12345678912345678

9 1234567891 23456789P

Master sends

Stop condition

Cleared by software

Receive address is

Software updates SSP1ADD

Data is read

SCL is held low

Set by software,

while CKP =

from SSP1BUF

releasing SCL

When SEN =

;

CKP is cleared after

9th falling edge of received byte

read from SSP1BUF

and releases SCL

When UA =

;

If address matches

Set by hardware

on 9th falling edge

SSP1ADD it is loaded into

SSP1BUF

SCL is held low

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FIGURE 30-21 : I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

Receive First Address Byte

Receive Second Address Byte

Receive Data

ACK

Receive Data

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5

SDA

SCL

SSP1IF

ACKDT

CKP

ACKTIM

12345678 9

ACK

12345678 9 123456789 12

SSP1BUF

is read from

Received data

SSP1BUF can be

read anytime before

the next received byte

Cleared by software

falling edge of SCL

not allowed until 9th

Update to SSP1ADD is

Set CKP with software

releases SCL

SCL

clears UA and releases

Update of SSP1ADD,

Set by hardware

on 9th falling edge

Slave software clears

ACKDT to ACK

the received byte

If when AHEN = 1;

on the 8th falling edge

of SCL of an address

byte, CKP is cleared

ACKTIM is set by hardware

on 8th falling edge of SCL

Cleared by software

R/W = 0

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FIGURE 30-22 : I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

Receiving Address

ACK

Receiving Second Address Byte

Receive First Address Byte

ACK

Transmitting Data Byte

1 1 1 1 0

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 0

A9 A8 D7 D6 D5 D4 D3 D2 D1 D0

SDA

SCL

SSP1IF

CKP

R/W

D/A

123456789 123456789 123 4 56789 123456789

ACK = 1

Master sends

Stop condition

Master sends

not ACK

Master sends

Restart event

ACK

R/W = 0

Cleared by software

After SSP1ADD is

updated, UA is cleared

and SCL is released

High address is loaded

Received address is Data to transmit is

Set by software

Indicates an address

When R/W = 1;

R/W is copied from the

Set by hardware

UA indicates SSP1ADD

SSP1BUF loaded

with received address

must be updated

has been received

loaded into SSP1BUF

releases SCL

Masters not ACK

is copied

matching address byte

CKP is cleared on

9th falling edge of SCL

read from SSP1BUF

back into SSP1ADD

ACKSTAT

Set by hardware

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30.5.6 CLOCK STRETCHING

Clock stretching occurs when a device on the bus

holds the SCL line low, effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle data or prepare a response for the

master device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and

handled by the hardware that generates SCL.

The CKP bit of the SSP1CON1 register is used to

control stretching. Any time the CKP bit is cleared, the

module will wait for the SCL line to go low and then

hold it. Setting CKP will release SCL and allow more

communication.

30.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSP1STAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSP1BUF with data to

transfer to the master. If the SEN bit of SSP1CON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

30.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time the SCL

is stretched without CKP being cleared. SCL is

released immediately after a write to SSP1ADD.

30.5.6.3 Byte NACKing

When AHEN bit of SSP1CON3 is set; CKP is cleared

by hardware after the eighth falling edge of SCL for a

received matching address byte. When DHEN bit of

SSP1CON3 is set; CKP is cleared after the eighth

falling edge of SCL for received data.

Stretching after the eighth falling edge of SCL allows

the slave to look at the received address or data and

decide if it wants to ACK the received data.

30.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low

until the SCL output is already sampled low. There-

fore, the CKP bit will not assert the SCL line until an

external I2C master device has already asserted the

SCL line. The SCL output will remain low until the CKP

bit is set and all other devices on the I2C bus have

released SCL. This ensures that a write to the CKP bit

will not violate the minimum high time requirement for

SCL (see Figure 30-23).

FIGURE 30-23: CLOCK SYNCHRONIZATION TIMING

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

SDA

SCL

DX ‚ – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSP1CON1

CKP

Master device

releases clock

Master device

asserts clock

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30.5.8 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

The general call address is a reserved address in the

I2C protocol, defined as address 0x00. When the

GCEN bit of the SSP1CON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSP1ADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSP1BUF and respond.

Figure 30-24 shows a general call reception

sequence.

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

If the AHEN bit of the SSP1CON3 register is set, just

as with any other address reception, the slave hard-

ware will stretch the clock after the eighth falling edge

of SCL. The slave must then set its ACKDT value and

release the clock with communication progressing as it

would normally.

FIGURE 30-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

30.5.9 SSP MASK REGISTER

An SSP Mask (SSPMSK) register (Register 30-5) is

available in I2C Slave mode as a mask for the value

held in the SSP1SR register during an address

comparison operation. A zero (‘0’) bit in the SSP1MSK

of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

SDA

SCL

SSP1IF

BF (SSP1STAT<0>)

Cleared by software

SSP1BUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

GCEN (SSP1CON2<7>)

’1’

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30.6 I2C Master Mode

Master mode is enabled by setting and clearing the

appropriate SSPM<3:0> bits in the SSP1CON1 regis-

ter and by setting the SSPEN bit. In Master mode, the

SDA and SCK pins must be configured as inputs. The

MSSP peripheral hardware will override the output

driver TRIS controls when necessary to drive the pins

low.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP1 module is disabled.

Control of the I2C bus may be taken when the P bit is

set, or the bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDA and SCL lines.

The following events will cause the SSP Interrupt Flag

bit, SSP1IF, to be set (SSP interrupt, if enabled):

• Start condition generation

• Stop condition generation

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

30.6.1 I2C MASTER MODE OPERATION

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received eight bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

A Baud Rate Generator is used to set the clock

frequency output on SCL. See Section 30.7 “Baud

Rate Generator” for more detail.

Note 1: The MSSP1 module, when configured in

I2C Master mode, does not allow queuing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSP1BUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSP1BUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSP1BUF did not occur

2: When in Master mode, Start/Stop

detection is masked and an interrupt is

generated when the SEN/PEN bit is

cleared and the generation is complete.

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30.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate

Generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSP1ADD<7:0> and begins count-

ing. This ensures that the SCL high time will always be

at least one BRG rollover count in the event that the

clock is held low by an external device (Figure 30-25).

FIGURE 30-25: BAUD RATE GENER ATOR TIMING WITH CLOCK ARBITRATION

30.6.3 WCOL STATUS FLAG

If the user writes the SSP1BUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSP1BUF

was attempted while the module was not idle.

SDA

SCL

SCL deasserted but slave holds

DX ‚ – 1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note: Because queuing of events is not allowed,

writing to the lower five bits of SSP1CON2

is disabled until the Start condition is

complete.

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30.6.4 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition (Figure 30-26), the user

sets the Start Enable bit, SEN bit of the SSP1CON2

the Baud Rate Generator is reloaded with the contents

of SSP1ADD<7:0> and starts its count. If SCL and

SDA are both sampled high when the Baud Rate

Generator times out (TBRG), the SDA pin is driven low.

The action of the SDA being driven low while SCL is

high is the Start condition and causes the S bit of the

SSP1STAT register to be set. Following this, the Baud

Rate Generator is reloaded with the contents of

SSP1ADD<7:0> and resumes its count. When the

Baud Rate Generator times out (TBRG), the SEN bit of

the SSP1CON2 register will be automatically cleared

by hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

FIGURE 30-26: FIRST START BIT TIMING

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already

sampled low, or if during the Start condi-

tion, the SCL line is sampled low before

the SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is

aborted and the I2C module is reset into

its idle state.

2: The Philips I2C specification states that a

bus collision cannot occur on a Start.

SDA

SCL

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSP1BUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSP1STAT<3>)

and sets SSP1IF bit

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30.6.5 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition (Figure 30-27) occurs when

the RSEN bit of the SSP1CON2 register is

programmed high and the master state machine is no

longer active. When the RSEN bit is set, the SCL pin is

asserted low. When the SCL pin is sampled low, the

Baud Rate Generator is loaded and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be deasserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

and begins counting. SDA and SCL must be sampled

high for one TBRG. This action is then followed by

assertion of the SDA pin (SDA = 0) for one TBRG while

SCL is high. SCL is asserted low. Following this, the

RSEN bit of the SSP1CON2 register will be

automatically cleared and the Baud Rate Generator will

not be reloaded, leaving the SDA pin held low. As soon

as a Start condition is detected on the SDA and SCL

pins, the S bit of the SSP1STAT register will be set. The

SSP1IF bit will not be set until the Baud Rate Generator

has timed out.

FIGURE 30-27: REPEATED START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL

goes from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting

to transmit a data ‘1’.

SDA

SCL

Repeated Start

Write to SSP1CON2

Write to SSP1BUF occurs here

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDA = 1,SDA = 1,

SCL (no change) SCL = 1

occurs here

TBRG TBRG TBRG

and sets SSP1IF

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30.6.6 I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSP1BUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received

properly. The status of ACK is written into the

ACKSTAT bit on the rising edge of the ninth clock. If the

master receives an Acknowledge, the Acknowledge

Status bit, ACKSTAT, is cleared. If not, the bit is set.

After the ninth clock, the SSP1IF bit is set and the

master clock (Baud Rate Generator) is suspended until

the next data byte is loaded into the SSP1BUF, leaving

SCL low and SDA unchanged (Figure 30-28).

After the write to the SSP1BUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSP1CON2

transmission of the address, the SSP1IF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSP1BUF takes place,

holding SCL low and allowing SDA to float.

30.6.6.1 BF Status Flag

In Transmit mode, the BF bit of the SSP1STAT register

is set when the CPU writes to SSP1BUF and is cleared

when all eight bits are shifted out.

30.6.6.2 WCOL Status Flag

If the user writes the SSP1BUF when a transmit is

already in progress (i.e., SSP1SR is still shifting out a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

30.6.6.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSP1CON2

Acknowledge (ACK =0) and is set when the slave

does not Acknowledge (ACK =1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

30.6.6.4 Typical Transmit Sequence

1. The user generates a Start condition by setting

the SEN bit of the SSP1CON2 register.

2. SSP1IF is set by hardware on completion of the

Start.

3. SSP1IF is cleared by software.

4. The MSSP1 module will wait the required start

time before any other operation takes place.

5. The user loads the SSP1BUF with the slave

address to transmit.

6. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSP1BUF is written to.

7. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

8. The MSSP1 module generates an interrupt at

the end of the ninth clock cycle by setting the

SSP1IF bit.

9. The user loads the SSP1BUF with eight bits of

data.

10. Data is shifted out the SDA pin until all eight bits

are transmitted.

11. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSP1CON2 register. Interrupt is generated

once the Stop/Restart condition is complete.

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FIGURE 30-28 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

SDA

SCL

SSP1IF

BF (SSP1STAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared by software service routine

SSP1BUF is written by software

from SSP interrupt

After Start condition, SEN cleared by hardware

SSP1BUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSP1IF

SEN = 0

of 10-bit Address

Write SSP1CON2<0> SEN = 1

Start condition begins From slave, clear ACKSTAT bit SSP1CON2<6>

ACKSTAT in

SSP1CON2 = 1

Cleared by software

SSP1BUF written

PEN

R/W

Cleared by software

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30.6.7 I2C MASTER MODE RECEPTION

Master mode reception (Figure 30-29) is enabled by

programming the Receive Enable bit, RCEN bit of the

SSP1CON2 register.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSP1SR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the

contents of the SSP1SR are loaded into the SSP1BUF,

the BF flag bit is set, the SSP1IF flag bit is set and the

Baud Rate Generator is suspended from counting,

holding SCL low. The MSSP1 is now in Idle state

awaiting the next command. When the buffer is read by

the CPU, the BF flag bit is automatically cleared. The

user can then send an Acknowledge bit at the end of

reception by setting the Acknowledge Sequence

Enable, ACKEN bit of the SSP1CON2 register.

30.6.7.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSP1BUF from SSP1SR. It

is cleared when the SSP1BUF register is read.

30.6.7.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight

bits are received into the SSP1SR and the BF flag bit is

already set from a previous reception.

30.6.7.3 WCOL Status Flag

If the user writes the SSP1BUF when a receive is

already in progress (i.e., SSP1SR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

30.6.7.4 Typical Receive Sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSP1CON2 register.

2. SSP1IF is set by hardware on completion of the

Start.

3. SSP1IF is cleared by software.

4. User writes SSP1BUF with the slave address to

transmit and the R/W bit set.

5. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSP1BUF is written to.

6. The MSSP1 module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSP1CON2 register.

7. The MSSP1 module generates an interrupt at

the end of the ninth clock cycle by setting the

SSP1IF bit.

8. User sets the RCEN bit of the SSP1CON2 regis-

ter and the master clocks in a byte from the slave.

9. After the eighth falling edge of SCL, SSP1IF and

BF are set.

10. Master clears SSP1IF and reads the received

byte from SSP1BUF, clears BF.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSP1CON2 register and initiates the

ACK by setting the ACKEN bit.

12. Master’s ACK is clocked out to the slave and

SSP1IF is set.

13. Software clears SSP1IF.

14. Steps 8-13 are repeated for each received byte

from the slave.

15. Master sends a not ACK or Stop to end

communication.

Note: The MSSP1 module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

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FIGURE 30-29 : I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678 9 1234

Bus master

terminates

transfer

ACK

Receiving Data from Slave

D3D4

D6D7

ACK

R/W

Transmit Address to Slave

SSP1IF

ACK is not sent

Write to SSP1CON2<0>(SEN = 1),

Write to SSPBUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSP1CON2<3> (RCEN = 1)

PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared by software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSP1STAT<0>)

ACK

Cleared by software

Set SSP1IF interrupt

at end of receive

Set P bit

(SSP1STAT<4>)

and SSP1IF

Cleared in

software

ACK from Master

Set SSP1IF at end

Set SSP1IF interrupt

at end of Acknowledge

sequence

Set SSP1IF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SSPOV is set because

SSP1BUF is still full

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSP1CON2<4>

to start Acknowledge sequence

SDA = ACKDT (SSP1CON2<5>) = 0

RCEN cleared

automatically

responds to SSP1IF

ACKEN

begin Start condition

Cleared by software

SDA = ACKDT = 0

Last bit is shifted into SSP1SR and

contents are unloaded into SSP1BUF

RCEN

Master configured as a receiver

by programming SSP1CON2<3> (RCEN = 1)

RCEN cleared

automatically

ACK from Master

SDA = ACKDT = 0 RCEN cleared

automatically

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30.6.8 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSP1CON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCL pin is deasserted (pulled high).

When the SCL pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCL pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSP1 module then goes into Idle mode

(Figure 30-30).

30.6.8.1 WCOL Status Flag

If the user writes the SSP1BUF when an Acknowledge

sequence is in progress, then WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

30.6.9 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSP1CON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSP1STAT register is set. A TBRG later, the PEN bit is

cleared and the SSP1IF bit is set (Figure 30-31).

30.6.9.1 WCOL Status Flag

If the user writes the SSP1BUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

FIGURE 30-30: ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 30-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

SSP1IF set at

Acknowledge sequence starts here,

write to SSP1CON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSP1IF

software SSP1IF set at the end

of Acknowledge sequence

Cleared in

software

ACK

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSP1CON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSP1STAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSP1CON2<2>) is cleared by

hardware and the SSP1IF bit is set

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30.6.10 SLEEP OPERATION

While in Sleep mode, the I2C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

30.6.11 EFFECTS OF A RESET

A Reset disables the MSSP1 module and terminates

the current transfer.

30.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP1 module is disabled. Control of the I2C bus may

be taken when the P bit of the SSP1STAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCL1IF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

30.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I2C port to its Idle state (Figure 30-32).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSP1BUF can be written to. When the user services

the bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSP1CON2 register are cleared. When the user

services the bus collision Interrupt Service Routine and

if the I2C bus is free, the user can resume

communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSP1IF bit will be set.

A write to the SSP1BUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I2C bus

can be taken when the P bit is set in the SSP1STAT

cleared.

FIGURE 30-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCL1IF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data does not match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCL1IF)

by the master.

by master

Data changes

while SCL = 0

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30.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 30-33).

b) SCL is sampled low before SDA is asserted low

(Figure 30-34).

During a Start condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCL1IF flag is set and

• the MSSP1 module is reset to its Idle state

(Figure 30-33).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 30-35). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

FIGURE 30-33: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collision is not a

factor during a Start condition is that no

two bus masters can assert a Start condi-

tion at the exact same time. Therefore,

one master will always assert SDA before

the other. This condition does not cause a

bus collision because the two masters

must be allowed to arbitrate the first

address following the Start condition. If the

address is the same, arbitration must be

allowed to continue into the data portion,

Repeated Start or Stop conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSP1IF set because

SSP module Reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSP1IF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCL1IF

SSP1IF

SDA = 0, SCL = 1.

SSP1IF and BCL1IF are

cleared by software

SSP1IF and BCL1IF are

cleared by software

Set BCL1IF,

Start condition. Set BCL1IF.

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FIGURE 30-34: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 30-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN bus collision occurs. Set BCL1IF.

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCL1IF

SSP1IF

Interrupt cleared

by software

bus collision occurs. Set BCL1IF.

SCL = 0 before BRG time-out,

’0’’0’

SDA

SCL

SEN

Set S

Less than TBRG TBRG

SDA = 0, SCL = 1

BCL1IF

SSP1IF

Interrupts cleared

by software

set SSP1IF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time-out

Set SSP1IF

’0’

SDA pulled low by other master.

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

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30.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level (Case 1).

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’ (Case 2).

When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSP1ADD and

counts down to zero. The SCL pin is then deasserted

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 30-36).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 30-37.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 30-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 30-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCL1IF

SSP1IF

Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.

Cleared by software

’0’

SDA

SCL

BCL1IF

RSEN

SSP1IF

Interrupt cleared

by software

SCL goes low before SDA,

set BCL1IF. Release SDA and SCL.

TBRG TBRG

’0’

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30.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out (Case 1).

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high (Case 2).

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSP1ADD and

counts down to zero. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 30-38). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 30-39).

FIGURE 30-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 30-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCL1IF

PEN

SSP1IF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCL1IF

’0’

SDA

SCL

BCL1IF

PEN

SSP1IF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCL1IF

’0’

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30.7 Baud Rate Generator

The MSSP1 module has a Baud Rate Generator avail-

able for clock generation in both I2C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSP1ADD register (Register 30-6).

When a write occurs to SSP1BUF, the Baud Rate

Generator will automatically begin counting down.

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

An internal signal “Reload” in Figure 30-40 triggers the

value from SSP1ADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSP1 is

being operated in.

Table 30-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

EQUATION 30-1:

FIGURE 30-40: BAUD RATE GENER ATOR BLOCK DIAGRAM

FCLOCK FOSC

SSP1ADD 1+4

--------------------------------------------------=

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSP1ADD when used as a Baud Rate

Generator for I2C. This is an implementation

limitation.

SSPM<3:0>

BRG Down Counter

SSPxCLK FOSC/2

SSP1ADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

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TABLE 30-2: MSSP CLOCK RATE W/BRG

FOSC FCY BRG Value FCLOCK

(2 Rollovers of BRG)

32 MHz 8 MHz 13h 400 kHz

32 MHz 8 MHz 19h 308 kHz

32 MHz 8 MHz 4Fh 100 kHz

16 MHz 4 MHz 09h 400 kHz

16 MHz 4 MHz 0Ch 308 kHz

16 MHz 4 MHz 27h 100 kHz

4 MHz 1 MHz 09h 100 kHz

Note: Refer to the I/O port electrical specifications in Tab le 35- 4 to ensure the system is designed to support IOL

requirements.

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30.8 Register Definitions: MSSP Control

R/W-0/0 R/W-0/0 R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0

SMP CKE(1) D/A P(2) S(2) R/W UA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear

bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

In I2 C Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)(1)

In SPI Master or Slave mode:

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

In I2 C™ mode only:

1 = Enable input logic so that thresholds are compliant with SMBus specification

0 = Disable SMBus specific inputs

bit 5 D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit(2)

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0 = Stop bit was not detected last

bit 3 S: Start bit (2)

(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0 = Start bit was not detected last

bit 2 R/W: Read/Write bit information (I2C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address

match to the next Start bit, Stop bit, or not ACK bit.

In I2 C Slave mode:

1 = Read

0 = Write

In I2 C Master mode:

1 = Transmit is in progress

0 = Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive (SPI and I2 C modes):

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I2 C mode only):

1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full

0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit of the SSP1CON register.

2: This bit is cleared on Reset and when SSPEN is cleared.

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R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

WCOL SSPOV(1) SSPEN CKP SSPM<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared

bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

In SPI mode:

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,

the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit

is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register

(must be cleared in software).

0 = No overflow

In I2 C mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode (must be cleared in software).

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, the following pins must be properly configured as input or output

In SPI mode:

1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2 C Slave mode:

SCL release control

1 = Enable clock

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

In I2 C Master mode:

Unused in this mode

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bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1101 = Reserved

1100 = Reserved

1011 = I2C firmware controlled Master mode (slave idle)

1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)

1001 = Reserved

1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)

0111 = I2C Slave mode, 10-bit address

0110 = I2C Slave mode, 7-bit address

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled

0011 = SPI Master mode, clock = T2_match/2

0010 = SPI Master mode, clock = FOSC/64

0001 = SPI Master mode, clock = FOSC/16

0000 = SPI Master mode, clock = FOSC/4

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, these pins must be properly configured as input or output. Use SSP1SSPPS,

SSP1CLKPPS, SSP1DATPPS, and RxyPPS to select the pins.

3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSP1CLKPPS, SSP1DATPPS,

and RxyPPS to select the pins.

4: SSPADD values of 0, 1 or 2 are not supported for I2C mode.

5: SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

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R/W-0/0 R/HS/HC-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0

GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set

bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)

1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)

1 = Acknowledge was not received

0 = Acknowledge was received

bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1 = Not Acknowledge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)

In Master Receive mode:

1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence idle

bit 3 RCEN: Receive Enable bit (in I2C Master mode only)

1 = Enables Receive mode for I2C

0 = Receive idle

bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition idle

bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition idle

bit 0 SEN: Start Condition Enable/Stretch Enable bit

In Master mode:

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle state, these bits may not be

set (no spooling) and the SSPBUF may not be written.

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R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock

0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled(2)

bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled(2)

bit 4 BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:(1)

1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit

0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the

SSP1CON1 register is set, and the buffer is not updated

In I2C Master mode and SPI Master mode:

This bit is ignored.

In I2C Slave mode:

1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state

of the SSPOV bit only if the BF bit = 0.

0 = SSPBUF is only updated when SSPOV is clear

bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only)

1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL

0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL

bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the

BCL1IF bit of the PIR1 register is set, and bus goes idle

1 = Enable slave bus collision interrupts

0 = Slave bus collision interrupts are disabled

bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the

SSP1CON1 register will be cleared by hardware and the SCL will be held low.

0 = Address holding is disabled

bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP

bit of the SSP1CON1 register and SCL is held low.

0 = Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1

SSP1MSK<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 SSP1MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match

0 = The received address bit n is not used to detect I2C address match

bit 0 SSP1MSK<0>: Mask bit for I2C Slave mode, 10-bit Address

I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):

1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match

0 = The received address bit 0 is not used to detect I2C address match

I2C Slave mode, 7-bit address:

MSK0 bit is ignored.

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

SSP1ADD<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

Master mode:

bit 7-0 SSP1ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-bit Slave mode – Most Significant Address Byte:

bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit

pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1 SSP1ADD<2:1>: Two Most Significant bits of 10-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

10-bit Slave mode – Least Significant Address Byte:

bit 7-0 SSP1ADD<7:0>: Eight Least Significant bits of 10-bit address

7-bit Slave mode:

bit 7-1 SSP1ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

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R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

SSP1BUF<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 SSP1BUF<7:0>: MSSP Buffer bits

TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH MSSP1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(3) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

INLVLA(1) ― ― INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 134

TRISC(2) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(2) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

INLVLC(1,2) ― ― INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 141

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

PIR2 ―C2IF(2) C1IF NVMIF ―――NCO1IF 97

PIE2 ―C2IE(2) C1IE NVMIE ―――NCO1IE 92

SSP1STAT SMP CKE D/A PSR/WUA BF 339

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 340

SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 342

SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 343

SSP1MSK SSP1MSK<7:0> 344

SSP1ADD SSP1ADD<7:0> 344

SSP1BUF SSP1BUF<7:0> 345

SSP1CLKPPS ― ― ― SSP1CLKPPS<4:0> 144

SSP1DATPPS ― ― ― SSP1DATPPS<4:0> 144

SSP1SSPPS ― ― ― SSP1SSPPS<4:0> 144

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module

Note 1: When using designated I2C pins, the associated pin values in INLVLx will be ignored.

2: PIC16(L)F18323 only.

3: Unimplemented, read as ‘1’.

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31.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART1)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART1) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART1, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The EUSART1 module includes the following

capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

The EUSART1 module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART1 transmitter and

receiver are shown in Figure 31-1 and Figure 31-2.

The EUSART1 transmit output (TX_out) is available to

the TX/CK pin and internally to the following peripherals:

• Configurable Logic Cell (CLC)

FIGURE 31-1: EUSART1 TRANSMIT BLOCK DIAGRAM

TXIF

TXIE

Interrupt

TXEN

TX9D

MSb LSb

Data Bus

TX1REG Register

Transmit Shift Register (TSR)

(8) 0

TX9

TRMT

TX/CK pin

Pin Buffer

and Control

SP1BRGLSP1BRGH

BRG16

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1XXX X

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

•••

TX_out

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FIGURE 31-2: EUSART1 RECEIVE BLOCK DIAGRAM

The operation of the EUSART1 module is controlled

through three registers:

• Transmit Status and Control (TX1STA)

• Receive Status and Control (RC1STA)

• Baud Rate Control (BAUD1CON)

These registers are detailed in Register 31-1,

The RX and CK input pins are selected with the RXPPS

and CKPPS registers, respectively. TX, CK, and DT

output pins are selected with each pin’s RxyPPS register.

Since the RX input is coupled with the DT output in

Synchronous mode, it is the user’s responsibility to select

the same pin for both of these functions when operating

in Synchronous mode. The EUSART1 control logic will

control the data direction drivers automatically.

RX/DT pin

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR

FERR

RSR Register

MSb LSb

RX9D RC1REG Register FIFO

Interrupt

RCIF

RCIE

Data Bus

Stop Start

(8) 7 1 0

RX9

• • •

SP1BRGLSP1BRGH

BRG16

RCIDL

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 1X00 0

BRGH X110 0

BRG16 X101 0

Baud Rate Generator

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31.1 EUSART1 Asynchronous Mode

The EUSART1 transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL Space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud Rate). An on-chip dedicated

8-bit/16-bit Baud Rate Generator is used to derive

standard baud rate frequencies from the system

oscillator. See Tabl e 31-3 for examples of baud rate

configurations.

The EUSART1 transmits and receives the LSb first.

The EUSART1’s transmitter and receiver are function-

ally independent, but share the same data format and

baud rate. Parity is not supported by the hardware, but

can be implemented in software and stored as the ninth

data bit.

31.1.1 EUSART1 ASYNCHRONOUS

TRANSMITTER

The EUSART1 transmitter block diagram is shown in

Figure 31-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TX1REG register.

31.1.1.1 Enabling the Transmitter

The EUSART1 transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

•TXEN = 1

• SYNC = 0

• SPEN = 1

All other EUSART1 control bits are assumed to be in

their default state.

Setting the TXEN bit of the TX1STA register enables the

transmitter circuitry of the EUSART1. Clearing the

SYNC bit of the TX1STA register configures the

EUSART1 for asynchronous operation. Setting the

SPEN bit of the RC1STA register enables the EUSART1

and automatically configures the TX/CK I/O pin as an

output. If the TX/CK pin is shared with an analog

peripheral, the analog I/O function must be disabled by

clearing the corresponding ANSEL bit.

31.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the

TX1REG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TX1REG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TX1REG until the Stop bit of the

previous character has been transmitted. The pending

character in the TX1REG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TX1REG.

31.1.1.3 Transmit Data Polarity

The polarity of the transmit data can be controlled with

the SCKP bit of the BAUD1CON register. The default

state of this bit is ‘0’ which selects high true transmit idle

and data bits. Setting the SCKP bit to ‘1’ will invert the

transmit data resulting in low true idle and data bits. The

SCKP bit controls transmit data polarity in

Asynchronous mode only. In Synchronous mode, the

SCKP bit has a different function. See Section 31.4.1.2

“Clock Polarity”.

31.1.1.4 Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART1 transmitter is enabled and no

character is being held for transmission in the TX1REG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TX1REG. The TXIF flag

bit is not cleared immediately upon writing TX1REG.

TXIF becomes valid in the second instruction cycle

following the write execution. Polling TXIF immediately

following the TX1REG write will return invalid results.

The TXIF bit is read-only, it cannot be set or cleared by

software.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TX1REG is

empty, regardless of the state of TXIE enable bit.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TX1REG.

Note: The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

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31.1.1.5 TSR Status

The TRMT bit of the TX1STA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

31.1.1.6 Transmitting 9-bit Characters

The EUSART1 supports 9-bit character transmissions.

When the TX9 bit of the TX1STA register is set, the

EUSART1 will shift nine bits out for each character

transmitted. The TX9D bit of the TX1STA register is the

ninth, and Most Significant data bit. When transmitting

9-bit data, the TX9D data bit must be written before

writing the eight Least Significant bits into the TX1REG.

All nine bits of data will be transferred to the TSR shift

A special 9-bit Address mode is available for use with

multiple receivers. See Section 31.1.2.7 “Address

Detection” for more information on the Address mode.

31.1.1.7 Asynchronous Transmission Set-up

1. Initialize the SP1BRGH, SP1BRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 31.3 “EUSART1

Baud Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the eight Least Significant data bits are an

address when the receiver is set for address

detection.

4. Set SCKP bit if inverted transmit is desired.

5. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

6. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

7. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

8. Load 8-bit data into the TX1REG register. This

will start the transmission.

FIGURE 31-3: ASYNCHRONOUS TRANSMISSION

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1

Stop bit

Word 1

Transmit Shift Reg.

Start bit bit 0 bit 1 bit 7/8

Write to TX1REG

Word 1

BRG Output

(Shift Clock)

TX/CK

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

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FIGURE 31-4: ASYNCHR ON OUS TRANSM IS SION (BACK-TO-BACK)

31.1.2 EUSART1 ASYNCHRONOUS

RECEIVER

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 31-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

or nine bits of the character have been shifted in, they

are immediately transferred to a two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART1 receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RC1REG

31.1.2.1 Enabling the Receiver

The EUSART1 receiver is enabled for asynchronous

operation by configuring the following three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART1 control bits are assumed to be in

their default state.

Setting the CREN bit of the RC1STA register enables

the receiver circuitry of the EUSART1. Clearing the

SYNC bit of the TX1STA register configures the

EUSART1 for asynchronous operation. Setting the

SPEN bit of the RC1STA register enables the

EUSART1. The programmer must set the

corresponding TRIS bit to configure the RX/DT I/O pin

as an input.

31.1.2.2 Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 31.1.2.4 “Receive Framing

Error” for more information on framing errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART1 receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RC1REG register.

Transmit Shift Reg.

Write to TX1REG

SPR1BRG Output

(Shift Clock)

TX/CK

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

Note: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

Note: If the receive FIFO is overrun, no additional

characters will be received until the

Overrun condition is cleared. See

Section 31.1.2.5 “Receive Overrun

Error” for more information on overrun

errors.

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31.1.2.3 Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART1 receiver is enabled and there

is an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE, Interrupt Enable bit of the PIE1 register

• PEIE, Peripheral Interrupt Enable bit of the

INTCON register

• GIE, Global Interrupt Enable bit of the INTCON

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

31.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RC1STA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RC1REG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RC1STA register which resets the EUSART1.

Clearing the CREN bit of the RC1STA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

31.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RC1STA register is

set. The characters already in the FIFO buffer can be

read but no additional characters will be received until

the error is cleared. The error must be cleared by either

clearing the CREN bit of the RC1STA register or by

resetting the EUSART1 by clearing the SPEN bit of the

RC1STA register.

31.1.2.6 Receiving 9-bit Characters

The EUSART1 supports 9-bit character reception.

When the RX9 bit of the RC1STA register is set the

EUSART1 will shift nine bits into the RSR for each

character received. The RX9D bit of the RC1STA reg-

ister is the ninth and Most Significant data bit of the top

unread character in the receive FIFO. When reading

9-bit data from the receive FIFO buffer, the RX9D data

bit must be read before reading the eight Least Signifi-

cant bits from the RC1REG.

31.1.2.7 Address Detection

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RC1STA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note: If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RC1REG will not clear the FERR bit.

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31.1.2.8 Asynchronous Reception Setup

1. Initialize the SP1BRGH, SP1BRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 31.3

“EUSART1 Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

8. Read the RC1STA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RC1REG

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

31.1.2.9 9-bit Address Detection Mode Setup

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SP1BRGH, SP1BRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 31.3

“EUSART1 Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Read the RC1STA register to get the error flags.

The ninth data bit will always be set.

10. Get the received eight Least Significant data bits

from the receive buffer by reading the RC1REG

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 31-5: ASYNCHRONOUS RECEPTION

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX/DT pin

Reg

Rcv Buffer Reg.

Rcv Shift

Read Rcv

Buffer Reg.

RC1REG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RC1REG

Word 2

RC1REG

Stop

bit

Note: This timing diagram shows three words appearing on the RX input. The RC1REG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

RCIDL

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31.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (INTOSC). However, the INTOSC frequency

may drift as VDD or temperature changes, and this

directly affects the asynchronous baud rate. Two

methods may be used to adjust the baud rate clock, but

both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See

Section 7.2.2.3 “Internal Oscillator Frequency

Adjustment” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 31.3.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

31.3 EUSART1 Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART1 operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUD1CON register selects 16-bit

mode.

The SP1BRGH, SP1BRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the

TX1STA register and the BRG16 bit of the BAUD1CON

Table 31-1 contains the formulas for determining the

baud rate. Example 31-1 provides a sample calculation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 31-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

Writing a new value to the SP1BRGH, SP1BRGL reg-

ister pair causes the BRG timer to be reset (or cleared).

This ensures that the BRG does not wait for a timer

overflow before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is idle before

changing the system clock.

EXAMPLE 31-1: CALCULATIN G BAUD

RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit SPR1BRG:

Solving for SP1BRGH:SP1BRGL:

FOSC

Desired Ba ud R at e

---------------------------------------------

--------------------------------------------- 1–=

Desired Baud Rate FOSC

64 [SPBRGH:SPBRGL] 1+

------------------------------------------------------------------------=

16000000

9600

------------------------

------------------------1–=

25.04225==

Calculated Baud Rate 16000000

64 25 1+

---------------------------=

9615=

Error Calc. Bau d Rate Desired Baud Rat e –

Desired Baud Rate

--------------------------------------------------------------------------------------------=

9615 9600–

9600

---------------------------------- 0. 16 %==

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31.3.1 AUTO-BAUD DETECT

The EUSART1 module supports automatic detection

and calibration of the baud rate.

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Setting the ABDEN bit of the BAUD1CON register

starts the auto-baud calibration sequence. While the

ABD sequence takes place, the EUSART1 state

machine is held in Idle. On the first rising edge of the

receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Figure 31-6. The fifth rising edge will occur on the RX

pin at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SP1BRGH, SP1BRGL register pair, the

ABDEN bit is automatically cleared and the RCIF

interrupt flag is set. The value in the RC1REG needs to

be read to clear the RCIF interrupt. RC1REG content

should be discarded. When calibrating for modes that

do not use the SP1BRGH register the user can verify

that the SP1BRGL register did not overflow by

checking for 00h in the SP1BRGH register.

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 31-1. During ABD,

both the SP1BRGH and SP1BRGL registers are used

as a 16-bit counter, independent of the BRG16 bit set-

ting. While calibrating the baud rate period, the

SP1BRGH and SP1BRGL registers are clocked at

1/8th the BRG base clock rate. The resulting byte mea-

surement is the average bit time when clocked at full

speed.

FIGURE 31-6: AUTOMATIC BAUD RATE CALIBRATION

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

Section 31.3.3 “Auto-Wake-up on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART1 baud rates are not possible.

3: During the auto-baud process, the

auto-baud counter starts counting at one.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SP1BRGH:SP1BRGL

TABLE 31-1: BRG COUNTER CLOCK RATES

BRG16 BRGH BRG Base

Clock BRG ABD

Clock

00FOSC/64 FOSC/512

01FOSC/16 FOSC/128

10FOSC/16 FOSC/128

11 FOSC/4 FOSC/32

Note: During the ABD sequence, SP1BRGL and

SP1BRGH registers are both used as a

16-bit counter, independent of the BRG16

setting.

SPR1BRG Value

RX pin

ABDEN bit

RCIF bit

bit 0 bit 1

(Interrupt)

Read

RC1REG

SPR1BRG Clock

Start

Auto Cleared

Set by User

XXXXh 0000h

Edge #1

bit 2 bit 3

Edge #2

bit 4 bit 5

Edge #3

bit 6 bit 7

Edge #4

Stop bit

Edge #5

001Ch

Note 1: The ABD sequence requires the EUSART1 module to be configured in Asynchronous mode.

SP1BRGL XXh 1Ch

SP1BRGH XXh 00h

RCIDL

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31.3.2 AUTO-BAUD OVERFLOW

During the course of automatic-baud detection, the

ABDOVF bit of the BAUD1CON register will be set if

the baud rate counter overflows before the fifth rising

edge is detected on the RX pin. The ABDOVF bit

indicates that the counter has exceeded the maximum

count that can fit in the 16 bits of the

SP1BRGH:SP1BRGL register pair. The Overflow

condition will set the RCIF flag. The counter continues

to count until the fifth rising edge is detected on the RX

pin. The RCIDL bit will remain false (‘0’) until the fifth

rising edge at which time the RCIDL bit will be set. If the

RC1REG is read after the overflow occurs but before

the fifth rising edge, then the fifth rising edge will set the

RCIF again.

Terminating the auto-baud process early to clear an

Overflow condition will prevent proper detection of the

sync character fifth rising edge. If any falling edges of

the sync character have not yet occurred when the

ABDEN bit is cleared, then those will be falsely

detected as Start bits. The following steps are

recommended to clear the Overflow condition:

1. Read RC1REG to clear RCIF

2. If RCIDL is zero, then wait for RCIF and repeat

step 1

3. Clear the ABDOVF bit

31.3.3 AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART1 are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUD1CON register. Once set, the

normal receive sequence on RX/DT is disabled, and the

EUSART1 remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The EUSART1 module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 31-7), and asynchronously if

the device is in Sleep mode (Figure 31-8). The Interrupt

condition is cleared by reading the RC1REG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART1 module is in Idle mode waiting to

receive the next character.

31.3.3.1 Special Considerations

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be ten or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the

EUSART1.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The Interrupt

condition is then cleared in software by reading the

RC1REG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

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FIGURE 31-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

FIGURE 31-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

31.3.4 BREAK CHARACTER SEQUENCE

The EUSART1 module has the capability of sending

the special Break character sequences that are

required by the LIN bus standard. A Break character

consists of a Start bit, followed by 12 ‘0’ bits and a Stop

bit.

To send a Break character, set the SENDB and TXEN

bits of the TX1STA register. The Break character trans-

mission is then initiated by a write to the TX1REG. The

value of data written to TX1REG will be ignored and all

‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The TRMT bit of the TX1STA register indicates when the

transmit operation is active or idle, just as it does during

normal transmission. See Figure 31-9 for the timing of

the Break character sequence.

31.3.4.1 Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART1 for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TX1REG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TX1REG to load the Sync charac-

ter into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TX1REG becomes empty, as indicated by

the TXIF, the next data byte can be written to TX1REG.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit set by user Auto Cleared

Cleared due to User Read of RC1REG

Note 1: The EUSART1 remains in Idle while the WUE bit is set.

Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1

WUE bit

RX/DT Line

RCIF

Bit Set by User Auto Cleared

Cleared due to User Read of RC1REG

Sleep Command Executed

Note 1

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART1 remains in Idle while the WUE bit is set.

Sleep Ends

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31.3.5 RECEIVING A BREAK CHARACTER

The EUSART1 module can receive a Break character

in two ways.

The first method to detect a Break character uses the

FERR bit of the RC1STA register and the received data

as indicated by RC1REG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RC1REG = 00h

The second method uses the Auto-Wake-up feature

described in Section 31.3.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART1 will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUD1CON register before placing the EUSART1

in Sleep mode.

FIGURE 31-9: SEND BREAK CHARACTER SEQUENCE

Write to TX1REG Dummy Write

SPR1BRG Output

(Shift Clock)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

TXIF bit

(Transmit

Interrupt Flag)

TX (pin)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB

(send Break

control bit)

SENDB Sampled Here Auto Cleared

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31.4 EUSART1 Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART1 can operate as either a master or slave

device.

Start and Stop bits are not used in synchronous

transmissions.

31.4.1 SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART1

for synchronous master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TX1STA register configures

the device for synchronous operation. Setting the CSRC

bit of the TX1STA register configures the device as a

master. Clearing the SREN and CREN bits of the

RC1STA register ensures that the device is in the

Transmit mode, otherwise the device will be configured

to receive. Setting the SPEN bit of the RC1STA register

enables the EUSART1.

31.4.1.1 Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART1 is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the

trailing edge of each clock. One clock cycle is gener-

ated for each data bit. Only as many clock cycles are

generated as there are data bits.

31.4.1.2 Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUD1CON register. Setting the SCKP bit

sets the clock Idle state as high. When the SCKP bit is

set, the data changes on the falling edge of each clock.

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

31.4.1.3 Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART1 is configured for

synchronous master transmit operation.

A transmission is initiated by writing a character to the

TX1REG register. If the TSR still contains all or part of

a previous character the new character data is held in

the TX1REG until the last bit of the previous character

has been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TX1REG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TX1REG.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

31.4.1.4 Synchronous Master Transmission

Set-up

1. Initialize the SP1BRGH, SP1BRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 31.3

“EUSART1 Baud Rate Generator (BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the

TX1REG register.

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

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FIGURE 31-10: SY NCHRONOUS TRANSMISSION

FIGURE 31-11: SYNCHRONOUS TRANSM ISS ION (THROUGH TXEN)

31.4.1.5 Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART1 is configured for synchronous master

receive operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RC1STA register) or the Continuous Receive Enable

bit (CREN of the RC1STA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RC1REG.

The RCIF bit remains set as long as there are unread

characters in the receive FIFO.

bit 0 bit 1 bit 7

Word 1

bit 2 bit 0 bit 1 bit 7

RX/DT

Write to

TX1REG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SP1BRGL = 0, continuous transmission of two 8-bit words.

TX/CK pin

(SCKP = 0)

(SCKP = 1)

RX/DT pin

TX/CK pin

Write to

TX1REG reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

Note: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

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31.4.1.6 Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver is automatically disabled when

the device is configured for synchronous slave transmit

or receive operation. Serial data bits change on the

leading edge to ensure they are valid at the trailing edge

of each clock. One data bit is transferred for each clock

cycle. Only as many clock cycles should be received as

there are data bits.

31.4.1.7 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RC1REG is read to access

the FIFO. When this happens the OERR bit of the

RC1STA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the Overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RC1REG. If the overrun occurred when the CREN bit is

set then the Error condition is cleared by either clearing

the CREN bit of the RC1STA register or by clearing the

SPEN bit which resets the EUSART1.

31.4.1.8 Receiving 9-bit Characters

The EUSART1 supports 9-bit character reception.

When the RX9 bit of the RC1STA register is set the

EUSART1 will shift nine bits into the RSR for each

character received. The RX9D bit of the RC1STA

top unread character in the receive FIFO. When read-

ing 9-bit data from the receive FIFO buffer, the RX9D

data bit must be read before reading the eight Least

Significant bits from the RC1REG.

31.4.1.9 Synchronous Master Reception

Set-up

1. Initialize the SP1BRGH, SP1BRGL register pair

for the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. Ensure bits CREN and SREN are clear.

5. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set bit RX9.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RC1STA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RC1REG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RC1STA

the EUSART1.

FIGURE 31-12: SY NCHRONOUS RECEPTION (MASTER MODE, SREN)

Note: If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be cleared.

CREN bit

RX/DT

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RC1REG

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TX/CK pin

(SCKP = 0)

(SCKP = 1)

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31.4.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART1

for synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TX1STA register configures

the device for synchronous operation. Clearing the

CSRC bit of the TX1STA register configures the device

as a slave. Clearing the SREN and CREN bits of the

RC1STA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to

receive. Setting the SPEN bit of the RC1STA register

enables the EUSART1.

31.4.2.1 EUSART1 Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (see Section 31.4.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TX1REG and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The second word will remain in the TX1REG

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TX1REG register will transfer the

second character to the TSR and the TXIF bit will

now be set.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

31.4.2.2 Synchronous Slave Transmission

Set-up

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

4. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant eight bits to the TX1REG register.

31.4.2.3 EUSART1 Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 31.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RC1REG register. If the RCIE enable bit is set,

the interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

31.4.2.4 Synchronous Slave Reception

Set-up

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RC1STA

8. Retrieve the eight Least Significant bits from the

receive FIFO by reading the RC1REG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RC1STA

the EUSART1.

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31.5 EUSART1 Operation During Sleep

The EUSART1 will remain active during Sleep only in

the Synchronous Slave mode. All other modes require

the system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

31.5.1 SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RC1STA and TX1STA Control registers must be

configured for Synchronous Slave Reception (see

Section 31.4.2.4 “Synchronous Slave

Reception Set-up”).

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• The RCIF interrupt flag must be cleared by read-

ing RC1REG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit of the INTCON register is

also set, then the Interrupt Service Routine at address

004h will be called.

31.5.2 SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• The RC1STA and TX1STA Control registers must

be configured for synchronous slave transmission

(see Section 31.4.2.2 “Synchronous Slave

Transmission Set-up”).

• The TXIF interrupt flag must be cleared by writing

the output data to the TX1REG, thereby filling the

TSR and transmit buffer.

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

• Interrupt enable bits TXIE of the PIE1 register and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TX1REG will transfer to the TSR

and the TXIF flag will be set. Thereby, waking the pro-

cessor from Sleep. At this point, the TX1REG is avail-

able to accept another character for transmission,

which will clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

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31.6 Register Definitions: EUSART1 Control

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Unused in this mode – value ignored

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART1 Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop

bit; cleared by hardware upon completion

0 = SYNCH BREAK transmission disabled or completed

Synchronous mode:

Unused in this mode – value ignored

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode – value ignored

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x

SPEN(1) RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPEN: Serial Port Enable bit(1)

1 = Serial port enabled

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Unused in this mode – value ignored

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Unused in this mode – value ignored

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared

0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in

the receive buffer is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Unused in this mode – value ignored

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RC1REG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The EUSART1 module automatically changes the pin from tri-state to drive as needed. Configure the

associated TRIS bits for TX/CK and RX/DT to 1.

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R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1 = Auto-baud timer overflowed

0 = Auto-baud timer did not overflow

Synchronous mode:

Don’t care

bit 6 RCIDL: Receive Idle Flag bit

Asynchronous mode:

1 = Receiver is idle

0 = Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5 Unimplemented: Read as ‘0’

bit 4 SCKP: Clock/Transmit Polarity Select bit

Asynchronous mode:

1 = Idle state for transmit (TX) is a low level

0 = Idle state for transmit (TX) is a high level

Synchronous mode:

1 = Idle state for clock (CK) is a high level

0 = Idle state for clock (CK) is a low level

bit 3 BRG16: 16-bit Baud Rate Generator bit

1 = 16-bit Baud Rate Generator is used

0 = 8-bit Baud Rate Generator is used

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = EUSART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge.

0 = RX pin not monitored nor rising edge detected

Synchronous mode:

Unused in this mode – value ignored

bit 0 ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field

(55h);cleared in hardware upon completion

0 = Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode – value ignored

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R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RC1REG<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 RC1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 31-2)

Note 1: RC1REG (including the ninth bit) is double buffered, and data is available while new data is being

received.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TX1REG<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 TX1REG<7:0>: Lower eight bits of the transmit data; read-only; see also TX9D (Register 31-1)

Note 1: TX1REG (including the ninth bit) is double buffered, and can be written when previous data has started

shifting.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SP1BRG<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 SP1BRG<7:0>: Lower eight bits of the Baud Rate Generator

Note 1: Writing to SP1BRG resets the BRG counter.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SP1BRG<15:8>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SP1BRG<15:8>: Upper eight bits of the Baud Rate Generator

Note 1: SP1BRGH value is ignored for all modes unless BAUD1CON<BRG16> is active.

2: Writing to SP1BRGH resets the BRG counter.

TABLE 31-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

ANSELA ― ― ANSA5 ANSA4 ―ANSA2 ANSA1 ANSA0 132

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

ANSELC(1) ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139

INTCON GIE PEIE ― ― ― ― ― INTEDG 89

PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96

PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91

RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 364

TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 363

BAUD1CON ABDOVF RCIDL ―SCKP BRG16 ―WUE ABDEN 365

RC1REG RC1REG<7:0> 366

TX1REG TX1REG<7:0> 366

SP1BRGL SP1BRG<7:0> 366

SP1BRGH SP1BRG<15:8> 367

RXPPS ― ― ― RXPPS<4:0> 144

CLCxSELy ― ― ― LCxDyS<4:0> 210

MDSRC ― ― ― ― MDMS<3:0> 253

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART1 module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

TABLE 31-3: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART1 Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n+1)]

Legend: x = Don’t care, n = value of SP1BRGH, SP1BRGL register pair.

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001 8-bit/Asynchronous FOSC/[16 (n+1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n+1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

TABLE 31-3: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART1 Mode Baud Rate Formula

SYNC BRG16 BRGH

Legend: x = Don’t care, n = value of SP1BRGH, SP1BRGL register pair.

TABLE 31-4: BAUD RATE FOR ASYNCHRONOUS MODES

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300—— — —— — —— — —— —

1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143

2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71

9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17

10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16

19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8

57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 — — — 300 0.16 207 300 0.00 191 300 0.16 51

1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12

2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —

9600 9615 0.16 12 — — — 9600 0.00 5 — — —

10417 10417 0.00 11 10417 0.00 5 — — — — — —

19.2k — — — — — — 19.20k 0.00 2 — — —

57.6k — — — — — — 57.60k 0.00 0 — — —

115.2k — — — — — — — — — — — —

 2015-2017 Microchip Technology Inc. DS40001799C-page 369

PIC16(L)F18313/18323

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 —— — —— — —— — —— —

1200 — — — — — — — — — — — —

2400 — — — — — — — — — —— —

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MH z FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 —— — — — — — — — 300 0.16 207

1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303

1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575

2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287

9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71

10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65

19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35

57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11

115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5

TABLE 31-4: BAUD RATE FOR AS YNCHRONOUS MODES (CONTINUED)

PIC16(L)F18313/18323

DS40001799C-page 370  2015-2017 Microchip Technology Inc.

BAUD

RATE

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MH z FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207

1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215

1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303

2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151

9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287

10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264

19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143

57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47

115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23

BAUD

RATE

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 8.000 MHz FOSC = 4.000 MH z FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832

1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207

2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103

9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25

10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23

19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12

57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —

115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

TABLE 31-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)

 2015-2017 Microchip Technology Inc. DS40001799C-page 371

PIC16(L)F18313/18323

32.0 REFERENCE CLOCK OUTPUT

MODULE

The Reference Clock Output module provides the

ability to send a clock signal to the clock reference

output pin (CLKR). The Reference Clock Output can

also be used as a signal for other peripherals, such as

the Data Signal Modulator (DSM).

The Reference Clock Output module has the following

features:

• System clock is the module source clock

• Programmable clock divider

• Selectable duty cycle

32.1 Clock Source

The Reference Clock Output module uses the system

clock (FOSC) as the clock source. Any device clock

switching will be reflected in the clock output.

32.1.1 CLOCK SYNCHRONIZATION

Once the reference clock enable (CLKREN) is set, the

module is ensured to be glitch-free at start-up.

When the Reference Clock Output is disabled, the

output signal will be disabled immediately.

Clock dividers and clock duty cycles can be changed

while the module is enabled, but glitches may occur on

the output. To avoid possible glitches, clock dividers

and clock duty cycles should be changed only when the

CLKREN is clear.

32.2 Programmable Clock Divider

The module takes the system clock input and divides it

based on the value of the CLKRDIV<2:0> bits of the

CLKRCON register (Register 32-1).

The following configurations can be made based on the

CLKRDIV<2:0> bits:

• Base FOSC value

•F

OSC divided by 2

•F

OSC divided by 4

•F

OSC divided by 8

•F

OSC divided by 16

•F

OSC divided by 32

•F

OSC divided by 64

•F

OSC divided by 128

The clock divider values can be changed while the

module is enabled; however, in order to prevent

glitches on the output, the CLKRDIV<2:0> bits should

only be changed when the module is disabled

(CLKREN = 0).

32.3 Selectable Duty Cycle

The CLKRDC<1:0> bits of the CLKRCON register can

be used to modify the duty cycle of the output clock. A

duty cycle of 25%, 50%, or 75% can be selected for all

clock rates, with the exception of the undivided base

FOSC value.

The duty cycle can be changed while the module is

enabled; however, in order to prevent glitches on the

output, the CLKRDC<1:0> bits should only be changed

when the module is disabled (CLKREN = 0).

32.4 Operation in Sleep M ode

The Reference Clock Output module clock is based on

the system clock. When the device goes to Sleep, the

module outputs will remain in their current state. This

will have a direct effect on peripherals using the

Reference Clock Output as an input signal.

Note: The CLKRDC1 bit is reset to ‘1’. This

makes the default duty cycle 50%.

PIC16(L)F18313/18323

DS40001799C-page 372  2015-2017 Microchip Technology Inc.

FIGURE 32-1: CLOCK REFERENCE BLOCK DIAGRAM

FIGURE 32-2: CLOCK REFERENCE TIMING

FOSC

CLKREN

FREEZE ENABLED(1)

ICD FREEZE MODE(1)

CLKRDIV<2:0>

Duty Cycle

CLKRDC<1:0>

CLKR

To Peripherals

Note 1: Freeze is used in Debug Mode only; otherwise read as ‘0’

000

011

010

001

100

101

110

111

FOSC/2

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FOSC/128

CLKREN Counter Reset

Clock Counter

FOSC

CLKREN

CLKRDIV[2:0] = 001

CLKRDC[1:0] = 10

CLKRDC[1:0] = 01

CLKRDIV[2:0] = 001

CLKR Output

Duty Cycle (25%)

Duty Cycle

(50%)

FOSC /2

P1 P2

CLKR Output

 2015-2017 Microchip Technology Inc. DS40001799C-page 373

PIC16(L)F18313/18323

R/W-0/0 U-0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

CLKREN —— CLKRDC<1:0> CLKRDIV<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CLKREN: Reference Clock Module Enable bit

1 = Reference clock module enabled

0 = Reference clock module is disabled

bit 6-5 Unimplemented: Read as ‘0’.

bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits (1)

11 = Clock outputs duty cycle of 75%

10 = Clock outputs duty cycle of 50%

01 = Clock outputs duty cycle of 25%

00 = Clock outputs duty cycle of 0%

bit 2-0 CLKRDIV<2:0>: Reference Clock Divider bits

111 = FOSC divided by 128

110 = FOSC divided by 64

101 = FOSC divided by 32

100 = FOSC divided by 16

011 = FOSC divided by 8

010 = FOSC divided by 4

001 = FOSC divided by 2

000 = FOSC

Note 1: Bits are valid for Reference Clock divider values of two or larger, the base clock cannot be further divided.

TABLE 32-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on Page

TRISA ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 131

TRISC(1) ― ― TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138

CLKRCON CLKREN ― ― CLKRDC<1:0> CLKRDIV<2:0> 208

CLCxSELy ― ― ― LCxDyS<4:0> 210

MDCARH ―MDCHPOL MDCHSYNC ―MDCH<3:0> 254

MDCARL ―MDCLPOL MDCLSYNC ―MDCL<3:0> 255

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.

Note 1: PIC16(L)F18323 only.

2: Unimplemented, read as ‘1’.

PIC16(L)F18313/18323

DS40001799C-page 374  2015-2017 Microchip Technology Inc.

33.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process, allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

• ICSPCLK

• ICSPDAT

•MCLR

/VPP

•VDD

•VSS

In Program/Verify mode the program memory, data

EEPROM, user IDs and the Configuration Words are

programmed through serial communications. The

ICSPDAT pin is a bidirectional I/O used for transferring

the serial data and the ICSPCLK pin is the clock input.

For more information on ICSP™ refer to the

“PIC16(L)F183XX Memory Programming

Specification” (DS40001738).

33.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

33.2 Low-Voltage Programming Entry

Mode

The Low-Voltage Programming Entry mode allows the

PIC® Flash MCUs to be programmed using VDD only,

without high voltage. When the LVP bit of Configuration

Words is set to ‘1’, the low-voltage ICSP programming

entry is enabled. To disable the Low-Voltage ICSP

mode, the LVP bit must be programmed to ‘0’. The LVP

bit can only be reprogrammed to ‘0’ by using the

High-Voltage Programming mode.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2. A 32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Secti on 6.4 “MCLR” for more

information.

33.3 Common Programming Interfaces

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6-pin,

6-connector) configuration. See Figure 33-1.

FIGURE 33-1: ICD RJ-11 STYLE

CONNECTOR INTERFACE

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 33-2.

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 33-3 for more

information.

Target

Bottom Side

PC Board

VPP/MCLR VSS

ICSPCLK

VDD

ICSPDAT

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

 2015-2017 Microchip Technology Inc. DS40001799C-page 375

PIC16(L)F18313/18323

FIGURE 33-2: PI Ckit™ PROGRAMME R STYLE CONNECTOR INTERFACE

FIGURE 33-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

* The 6-pin header (0.100" spacing) accepts 0.025" square pins.

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

Pin 1 Indicator

VDD

VPP

VSS

External

Device to be

Data

Clock

VDD

MCLR/VPP

VSS

ICSPDAT

ICSPCLK

To Normal Connections

*Isolation devices (as required).

Programming

Signals Programmed

VDD

PIC16(L)F18313/18323

DS40001799C-page 376  2015-2017 Microchip Technology Inc.

34.0 INSTRUCTION SET SUMMARY

Each instruction is a 14-bit word containing the opera-

tion code (opcode) and all required operands. The

opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most

varied instruction word format.

Table 34-3 lists the instructions recognized by the

MPASM™ assembler.

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

• Subroutine entry takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

34.1 Read-Modify-Write Operations

Any write instruction that specifies a file register as part

of the instruction performs a Read-Modify-Write

(R-M-W) operation. The register is read, the data is

modified, and the result is stored in either the working

(W) register, or the originating file register, depending

on the state of the destination designator 'd' (see

Table 34-1 for more information). A read operation is

performed on a register even if the instruction writes to

that register.

TABLE 34-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f Register file address (0x00 to 0x7F)

W Working register (accumulator)

b Bit address within an 8-bit file register

k Literal field, constant data or label

x Don’t care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in file register f.

n FSR or INDF number. (0-1)

mm Pre-post increment-decrement mode

selection

TABLE 34-2: ABBREVIATION

DESCRIPTIONS

Field Description

PC Program Counter

TO Time-Out bit

C Carry bit

DC Digit Carry bit

Z Zero bit

PD Power-Down bit

 2015-2017 Microchip Technology Inc. DS40001799C-page 377

PIC16(L)F18313/18323

FIGURE 34-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriente d file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

MOVLP instruction only

13 5 4 0

OPCODE k (literal)

k = 5-bit immediate value

MOVLB instruction only

13 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

BRA instruction only

FSR Offset instructions

13 7 6 5 0

OPCODE n k (literal)

n = appropriate FSR

FSR Increment instructions

13 7 6 0

OPCODE k (literal)

k = 7-bit immediate value

13 3 2 1 0

OPCODE n m (mode)

n = appropriate FSR

m = 2-bit mode value

k = 6-bit immediate value

13 0

OPCODE

OPCODE only

PIC16(L)F18313/18323

DS40001799C-page 378  2015-2017 Microchip Technology Inc.

TABLE 34-3: PIC16(L)F18313/18323 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC

ANDWF

ASRF

LSLF

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB

SWAPF

XORWF

f, d

–

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

0111

1101

0101

0111

0101

0110

0001

1001

0011

1010

0100

1000

0000

1101

1100

0010

1011

1110

0110

dfff

lfff

0000

dfff

1fff

dfff

ffff

00xx

ffff

C, DC, Z

C, Z

C, DC, Z

BYTE ORIENTED SKIP OPERATIONS

DECFSZ

INCFSZ

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00 1011

1111 dfff

dfff ffff

ffff 1, 2

1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

f, b

Bit Clear f

Bit Set f

01 00bb

01bb bfff

bfff ffff

ffff 2

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01 10bb

11bb bfff

bfff ffff

ffff 1, 2

1, 2

LITERAL OPE RATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

Subtract W from literal

Exclusive OR literal with W

1110

1001

1000

0000

0001

0000

1100

1010

kkkk

001k

1kkk

kkkk

C, DC, Z

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

001k

0000

0kkk

0000

1kkk

0000

0100

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

1011

kkkk

1010

kkkk

1001

kkkk

1000

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Section 34.2 “Instruction Descriptions” for detailed MOVIW and MOVWI instruction descriptions.

 2015-2017 Microchip Technology Inc. DS40001799C-page 379

PIC16(L)F18313/18323

INHERENT OPERATIONS

CLRWDT

NOP

RESET

SLEEP

TRIS

–

Clear Watchdog Timer

No Operation

Software device Reset

Go into Standby mode

Load TRIS register with W

0000

0110

0000

0110

0100

0000

0001

0011

0fff

TO, PD

C-COMPILER OPTIMIZED

ADDFSR

MOVIW

MOVWI

n, k

n mm

k[n]

n mm

k[n]

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

Move W to INDFn, Indexed Indirect.

0001

0000

1111

0000

1111

0nkk

0001

0nkk

0001

1nkk

kkkk

0nmm

kkkk

1nmm

kkkk

2, 3

TABLE 34-3: PIC16(L)F18313/18323 INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 14-bit Opcode Status

Affected Notes

MSb LSb

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Section 34.2 “Instruction Descriptions” for detailed MOVIW and MOVWI instruction descriptions.

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34.2 Instruction Descriptions

ADDFSR Add Literal to FSRn

Syntax: [ label ] ADDFSR FSRn, k

Operands: -32  k  31

n  [ 0, 1]

Operation: FSR(n) + k  FSR(n)

Status Affected: None

Description: The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

FSRn is limited to the range

0000h-FFFFh. Moving beyond these

bounds will cause the FSR to

wrap-around.

ADDLW Add literal and W

Syntax: [ label ] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register are

added to the 8-bit literal ‘k’ and the

result is placed in the W register.

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Description: Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

ADDWFC ADD W and CARRY bit to f

Syntax: [ label ] ADDWFC f {,d}

Operands: 0  f  127

d [0,1]

Operation: (W) + (f) + (C)  dest

Status Affected: C, DC, Z

Description: Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) .AND. (f)  (destination)

Status Affected: Z

Description: AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

back in register ‘f’.

ASRF Arithmetic Right Shift

Syntax: [ label ] ASRF f {,d}

Operands: 0  f  127

d [0,1]

Operation: (f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in

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BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BRA Relative Branch

Syntax: [ label ] BRA label

[ label ] BRA $+k

Operands: -256 label - PC + 1 255

-256  k  255

Operation: (PC) + 1 + k  PC

Status Affected: None

Description: Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 1 + k. This instruction is a

2-cycle instruction. This branch has a

limited range.

BRW Relative Branch with W

Syntax: [ label ] BRW

Operands: None

Operation: (PC) + (W)  PC

Status Affected: None

Description: Add the contents of W (unsigned) to

the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 1 + (W). This instruction is a

2-cycle instruction.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Affected: None

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affected: None

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOP is

executed instead, making this a

2-cycle instruction.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Description: If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next instruction

is discarded and a NOP is executed

instead, making this a 2-cycle

instruction.

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CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  2047

Operation: (PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<6:3>)  PC<14:11>

Status Affected: None

Description: Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The 11-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALL is a 2-cycle

instruction.

CALLW Subroutine Call With W

Syntax: [ label ] CALLW

Operands: None

Operation: (PC) +1  TOS,

(W)  PC<7:0>,

(PCLATH<6:0>) PC<14:8>

Status Affected: None

Description: Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the

contents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLW is a 2-cycle

instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Affected: Z

Description: The contents of register ‘f’ are cleared

and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z) is

set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Affected: TO, PD

Description: CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

COMF C omplement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Affected: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in

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DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOP is executed instead, making it a

2-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<6:3>  PC<14:11>

Status Affected: None

Description: GOTO is an unconditional branch. The

11-bit immediate value is loaded into

PC bits <10:0>. The upper bits of PC

are loaded from PCLATH<4:3>. GOTO

is a 2-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOP is

executed instead, making it a 2-cycle

instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Affected: Z

Description: The contents of the W register are

OR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destination)

Status Affected: Z

Description: Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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LSLF Logical Left Shift

Syntax: [ label ] LSLF f {,d}

Operands: 0  f  127

d [0,1]

Operation: (f<7>)  C

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

LSRF Logical Right Shift

Syntax: [ label ] LSRF f {,d}

Operands: 0  f  127

d [0,1]

Operation: 0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected: C, Z

Description: The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (dest)

Status Affected: Z

Description: The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0, destination is W

file register since status flag Z is

affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W = value in FSR register

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PIC16(L)F18313/18323

MOVIW Move INDFn to W

Syntax: [ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Operands: n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

Operation: INDFn  W

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

• Unchanged

Status Affected: Z

Mode Syntax mm

Preincrement ++FSRn 00

Predecrement --FSRn 01

Postincrement FSRn++ 10

Postdecrement FSRn-- 11

Description: This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

MOVLB Move literal to BSR

Syntax: [ label ] MOVLB k

Operands: 0  k  31

Operation: k  BSR

Status Affected: None

Description: The 5-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

MOVLP Move literal to PCLATH

Syntax: [ label ] MOVLP k

Operands: 0  k  127

Operation: k  PCLATH

Status Affected: None

Description: The 7-bit literal ‘k’ is loaded into the

PCLATH register.

MOVLW Move literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Affected: None

Description: The 8-bit literal ‘k’ is loaded into W reg-

ister. The “don’t cares” will assemble as

‘0’s.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  127

Operation: (W)  (f)

Status Affected: None

Description: Move data from W register to register

‘f’.

Words: 1

Cycles: 1

Example: MOVWF OPTION_REG

Before Instruction

OPTION_REG = 0xFF

W = 0x4F

After Instruction

OPTION_REG = 0x4F

W = 0x4F

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MOVWI Move W to INDFn

Syntax: [ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Operands: n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

Operation: W  INDFn

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be

either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

Unchanged

Status Affected: None

Mode Syntax mm

Preincrement ++FSRn 00

Predecrement --FSRn 01

Postincrement FSRn++ 10

Postdecrement FSRn-- 11

Description: This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range

0000h-FFFFh.

Incrementing/decrementing it beyond

these bounds will cause it to

wrap-around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affected: None

Description: No operation.

Words: 1

Cycles: 1

Example: NOP

RESET Software Reset

Syntax: [ label ] RESET

Operands: None

Operation: Execute a device Reset. Resets the

RI flag of the PCON register.

Status Affected: None

Description: This instruction provides a way to

execute a hardware Reset by

software.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE k

Operands: None

Operation: TOS  PC,

1  GIE

Status Affected: None

Description: Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a 2-cycle

instruction.

Words: 1

Cycles: 2

Example: RETFIE

After Interrupt

PC = TOS

GIE = 1

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RETLW Return with literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Affected: None

Description: The W register is loaded with the 8-bit

literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a 2-cycle

instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affected: None

Description: Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a 2-cycle instruction.

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W = 1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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SLEEP Enter Sleep mode

Syntax: [ label ]SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT prescaler,

1  TO,

0  PD

Status Affected: TO, PD

Description: The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

See Section 9.3 “Sleep Mode” for

more information.

SUBLW Subtract W from literal

Syntax: [ label ]SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

complement method) from the 8-bit

literal ‘k’. The result is placed in the W

C = 0W  k

C = 1W  k

DC = 0W<3:0>  k<3:0>

DC = 1W<3:0>  k<3:0>

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method) W

result is stored in the W

back in register ‘f.

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}

Operands: 0  f  127

d  [0,1]

Operation: (f) – (W) – (B) dest

Status Affected: C, DC, Z

Description: Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

the result is placed in the W register. If

‘d’ is ‘1’, the result is placed in register

‘f’.

C = 0W  f

C = 1W  f

DC = 0W<3:0>  f<3:0>

DC = 1W<3:0>  f<3:0>

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TRIS Load TRIS Register with W

Syntax: [ label ] TRIS f

Operands: 5  f  7

Operation: (W)  TRIS register ‘f’

Status Affected: None

Description: Move data from W register to TRIS

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

XORLW Exclusive OR literal with W

Syntax: [ label ]XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affected: Z

Description: The contents of the W register are

XOR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Affected: Z

Description: Exclusive OR the contents of the W

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in

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35.0 ELECTRICAL SPECIFICATIONS

35.1 Absolute Maximum Ratings(†)

Ambient temperature under bias...................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on pins with respect to VSS

on VDD pin

PIC16F18313/18323 ................................................................................................. -0.3V to +6.5V

PIC16LF18313/18323 ............................................................................................... -0.3V to +4.0V

on MCLR pin ........................................................................................................................... -0.3V to +9.0V

on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)

Maximum current

on VSS pin(1)

-40°C  TA  +85°C .............................................................................................................. 250 mA

+85°C  TA  +125°C ............................................................................................................. 85 mA

on VDD pin(1)

-40°C  TA  +85°C .............................................................................................................. 250 mA

+85°C  TA  +125°C ............................................................................................................. 85 mA

on any I/O pin ..................................................................................................................................... 50 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

Total power dissipation(2) .............................................................................................................................. 800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be

limited by the device package power dissipation characterizations, see Table 35-3 to calculate device

specifications.

2: Power dissipation is calculated as follows:

PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

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PIC16(L)F18313/18323

35.2 Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage: VDDMIN VDD VDDMAX

Operating Temperature: TA_MIN TA TA_MAX

VDD — Operating Supply Voltage(1)

PIC16LF18313/18323

VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V

VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V

VDDMAX .................................................................................................................................... +3.6V

PIC16F18313/18323

VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V

VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V

VDDMAX .................................................................................................................................... +5.5V

TA — Operating Ambient Temperature Range

Industrial Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................... +85°C

Extended Temperature

TA_MIN ...................................................................................................................................... -40°C

TA_MAX .................................................................................................................................. +125°C

Note 1: See Parameter D002, DC Characteristics: Supply Voltage.

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FIGURE 35-1: VOLTAGE FREQUENCY GRAPH, -40°C





+125°C, PIC16F18313/18323 ONLY

FIGURE 35-2: VOLTAGE FREQUENCY GRAPH, -40°C





+125°C, PIC16LF18313/18323

ONLY

2.5

Frequency (MHz)

VDD (V)

432

10 16

5.5

2.3

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.

1.8

2.5

Frequency (MHz )

VDD (V)

43210 16

3.6

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.

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PIC16(L)F18313/18323

35.3 DC Characteristics

TABLE 35-1: SUPPLY VOLTAGE

PIC16LF18313/18323 Stand ard Ope ratin g Condit ions (unless otherwise stated)

PIC16F18313/18323 Standard Operating Condit ions (unless otherwise stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

Supply Voltage

D002 VDD 1.8

2.5

—

3.6

FOSC  16 MHz

FOSC > 16 MHz

D002 VDD 2.3

2.5

—

5.5

FOSC  16 MHz:

FOSC > 16 MHz

RAM Data Retention(1)

D003 VDR 1.5 — — V Device in Sleep mode

D003 VDR 1.7 — — V Device in Sleep mode

Power-on Reset Release Voltage(2)

D004 VPOR — 1.6 — V BOR and LPBOR disabled(3)

D004 VPOR —1.6 — V BOR and LPBOR disabled(3)

Power-on Reset ReARM Voltage(2)

D005 VPORR — 0.8 — V BOR and LPBOR disabled(3)

D005 VPORR —1.5 — V BOR and LPBOR disabled(3)

VDD Rise Rate to ensure Internal Power-on Reset Signal(2)

D006 SVDD 0.05 — — V/ms BOR and LPBOR disabled(3)

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode or during a device Reset, without losing RAM

data.

2: See Figure 35-3.

3: Please see Table 3 5-11 for BOR and LPBOR trip point information.

PIC16(L)F18313/18323

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FIGURE 35-3: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR(1)

TPOR(3)

POR REARM

TVLOW(2)

SVDD

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

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PIC16(L)F18313/18323

TABLE 35-2: SUPPLY CURRENT (IDD)(1,2)

PIC16LF18313/18323 Standard Operating Conditions (unless otherwise stated)

PIC16F18313/18323 Standard Operating Conditions (unless otherwise stated)

Param.

No. Symbol Devi ce Characteristics Min. Typ .† Max. Units Conditions

VDD Note

D100 IDDXT4XT = 4 MHz — 262 310 uA 3.0V

D100 IDDXT4XT = 4 MHz —275 320 uA 3.0V

D101 IDDHFO16 HFINTOSC = 16 MHz — 1.1 1.3 mA 3.0V

D101 IDDHFO16 HFINTOSC = 16 MHz —1.1 1.4 mA 3.0V

D102 IDDHFOPLL HFINTOSC = 32 MHz — 2 2.4 mA 3.0V

D102 IDDHFOPLL HFINTOSC = 32 MHz —2.1 2.5 mA 3.0V

D103 IDDHSPLL32 HS+PLL = 32 MHz — 1.8 2 mA 3.0V

D103 IDDHSPLL32 HS+PLL = 32 MHz —1.9 2.1 mA 3.0V

D104 IDDIDLE IDLE Mode, HFINTOSC = 16 MHz — 644 780 uA 3.0V

D104 IDDIDLE IDLE Mode, HFINTOSC = 16 MHz —650 790 uA 3.0V

D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz,

DOZE Ratio = 16 — 698 — uA 3.0V

D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz,

DOZE Ratio = 16 —705 —uA 3.0V

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see Register 9-2).

PIC16(L)F18313/18323

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TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2,3)

PIC16LF18313/18323 Standard Operating Conditions (unless otherwise stated)

PIC16F18313/18323 Standard Operating Conditions (unless otherwise stated)

VREGPM = 1

Param.

No. Symbol Device Characteristics Min. Typ.† Max.

+85°C Max.

+125°C Units Conditions

VDD Note

D200 IPD IPD Base — 0.03 2 5.2 A3.0V

D200 IPD IPD Base —0.3 2.4 5.6 A3.0V

—12.8 22 27 A3.0V VREGPM = 0

D201 IPD_WDT Low-Frequency Internal

Oscillator/WDT

—0.42.9 6 A3.0V

D201 IPD_WDT Low-Frequency Internal

Oscillator/WDT

—0.5 3.3 6.6 A3.0V

D202 IPD_SOSC Secondary Oscillator (SOSC) — 1.3 2.8 6 A3.0V

D202 IPD_SOSC Secondary Oscillator (SOSC) —1.5 3.2 6.4 A3.0V

D203 IPD_FVR FVR — 45 74 76 A3.0V

D203 IPD_FVR FVR —40 70 75 A3.0V

D204 IPD_BOR Brown-out Reset (BOR) — 10.6 16 19 A3.0V

D204 IPD_BOR Brown-out Reset (BOR) —10.5 16.4 19.4 A3.0V

D205 IPD_LPBOR Low Power Brown-out Reset

(LPBOR)

— 0.3 2.5 5.5 A3.0V

D207 IPD_ADCA ADC - Non-converting — 0.3 2 5.2 A 3.0V ADC not

converting(4)

D207 IPD_ADCA ADC - Non-converting —0.3 2.4 5.6 A3.0V ADC not

converting(4)

D208 IPD_CMP Comparator — 30 45 50 A3.0V

D208 IPD_CMP Comparator —30 44 49 A3.0V

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this

peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.

3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is

available.

4: ADC clock source is ADCRC.

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TABLE 35-4: I/O PORTS

DC CHARACTER ISTIC S Standard Operating Conditions (unless otherwise stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

VIL Input Low Voltage

I/O PORT:

D300 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V

D301 — — 0.15 VDD V1.8V  VDD  4.5V

D302 with Schmitt Trigger buffer — — 0.2 VDD V2.0V  VDD  5.5V

D303 with I2C levels — — 0.3 VDD V

D304 with SMBus levels — — 0.8 V 2.7V  VDD  5.5V

D305 MCLR ——0.2VDD V

VIH Input High Voltage

I/O PORT:

D320 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V

D321 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V

D322 with Schmitt Trigger buffer 0.8 VDD —— V2.0V  VDD  5.5V

D323 with I2C levels 0.7 VDD —— V

D324 with SMBus levels 2.1 — — V 2.7V  VDD  5.5V

D325 MCLR 0.7 VDD —— V

IIL Input Leakage Current(2)

D340 I/O Ports — ± 5 ± 125 nA VSS  VPIN  VDD,

Pin at high-impedance, 85°C

D341 — ± 5 ± 1000 nA VSS  VPIN  VDD,

Pin at high-impedance, 125°C

D342 MCLR(2) — ± 50 ± 200 nA VSS  VPIN  VDD,

Pin at high-impedance, 85°C

IPUR Weak Pull-up Current

D350 25 120 200 AV

DD = 3.0V, VPIN = VSS

VOL Output Low Voltage(4)

D360 I/O ports — — 0.6 V IOL = 10.0 mA, VDD = 3.0V

VOH Output High Voltage(4)

D370 I/O ports VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V

D380 CIO All I/O pins —550pF

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Negative current is defined as current sourced by the pin.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

PIC16(L)F18313/18323

DS40001799C-page 398  2015-2017 Microchip Technology Inc.

TABLE 35-5: MEMORY SPECIFICATIONS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

High Voltage Entry Programming Mode Specifications

MEM01 VIHH Voltage on MCLR/VPP pin to

enter Programming mode 7.9 — 9 V Note 2

MEM02 IPPGM Current on MCLR/VPP pin during

Programming mode —— —uANote 2

Programming Mode Specifications

MEM10 VBE VDD for Bulk Erase — 2.7 — V

MEM11 IDDPGM Supply Current during

Programming Operation —— 5mA

Data EEPROM Memory Sp ecifications

MEM20 EDDataEE Byte Endurance 100k — — E/W -40°C  TA 85°C

MEM21 TD_RET Characteristic Retention — 40 — Year Provided no other

specifications are violated

MEM22 ND_REF Total Erase/Write Cycles before

Refresh — — 100k E/W

MEM23 VD_RW VDD for Read or Erase/Write

Operation VDDMIN —VDDMAX V

MEM24 TD_BEW Byte Erase and Write Cycle Time — 4.0 5.0 ms

Program Flash Memory Specifications

MEM30 EPFlash Memory Cell Endurance 10k — — E/W -40°C  Ta  85°C

(Note 1)

MEM32 TP_RET Characteristic Retention — 40 — Year Provided no other

specifications are violated

MEM33 VP_RD VDD for Read Operation VDDMIN —VDDMAX V

MEM34 VP_REW VDD for Row Erase or Write

Operation VDDMIN —VDDMAX V

MEM35 TP_REW Self-Timed Row Erase or

Self-Timed Write —2.02.5ms

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one

Self-Timed Write.

2: Required only if CONFIG3.LVP is disabled.

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TABLE 35-6: THERMAL CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Typ. Units Conditions

TH01 JA Thermal Resistance Junction to

Ambient

70.0 C/W 14-pin PDIP package

95.3 C/W 14-pin SOIC package

100.0 C/W 14-pin TSSOP package

51.5 C/W 16-pin UQFN 4x4mm package

62.2 C/W 20-pin PDIP package

87.3 C/W 20-pin SSOP package

77.7 C/W 20-pin SOIC package

43.0 C/W 20-pin UQFN 4x4mm package

TH02 JC Thermal Resistance Junction to

Case

32.75 C/W 14-pin PDIP package

31.0 C/W 14-pin SOIC package

24.4 C/W 14-pin TSSOP package

5.4 C/W 16-pin UQFN 4x4mm package

27.5 C/W 20-pin PDIP package

31.1 C/W 20-pin SSOP package

23.1 C/W 20-pin SOIC package

5.3 C/W 20-pin UQFN 4x4mm package

TH03 TJMAX Maximum Junction Temperature 150 C

TH04 PD Power Dissipation 0.800 W PD = PINTERNAL + PI/O

TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)

TH06 PI/OI/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)

Note1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature, TJ = Junction Temperature

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35.4 AC Characteristics

FIGURE 35-4: LOAD CONDITIONS

FIGURE 35-5: CLOCK TIMING

Load Condition

Note: CL = 50 pF for all pins

CLKIN

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

OS1

OS20

(CLKOUT Mode)

OS2

Note: See Table 35-10.

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TABLE 35-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

ECL Oscillator

OS1 FECL Clock Frequency — — 100 kHz

OS2 TECL_DC Clock Duty Cycle 40 — 60 %

ECM Oscillator

OS3 FECM Clock Frequency — — 8 MHz Note 4

OS4 TECM_DC Clock Duty Cycle 40 — 60 %

ECH Oscillator

OS5 FECH Clock Frequency — — 32 MHz

OS6 TECH_DC Clock Duty Cycle 40 — 60 %

LP Oscillator

OS7 FLP Clock Frequency — — 100 kHz Note 4

XT Oscillator

OS8 FXT Clock Frequency — — 4 MHz Note 4

HS Oscillator

OS9 FHS Clock Frequency — — 20 MHz Note 4

System Clock

OS20 FOSC System Clock Frequency — — 32 MHz Note 2, Note 3

OS21 FCY Instruction Frequency — FOSC/4 — MHz

OS22 TCY Instruction Period 125 1/FCY —ns

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min”

values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle

time limit is “DC” (no clock) for all devices.

2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in

Section 7.3 “Clock Switching”.

3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 35.2

“Standard Operating Conditions”. LP, XT and HS oscillator modes require an appropriate crystal or

resonator to be connected to the device.

4: For clocking the device with an external square wave, one of the EC mode selections must be used.

PIC16(L)F18313/18323

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FIGURE 35-6: PRECIS ION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE

VDD AND TEMPERATURE

TABLE 35-8: INTERNAL OSCILLATOR PARAMETERS(1)

Standard Operating Conditions (unless otherwise stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

OS20 FHFOSC Precision Calibrated HFINTOSC

Frequency

—4

— MHz -40°C to 125°C (2)

OS21 FHFOSCLP Low-Power Optimized HFINTOSC

Frequency

0.93

1.86

1.07

2.14

MHz

OS23 FLFOSC Internal LFINTOSC Frequency — 31 — kHz

OS24 THFOSCST HFINTOSC Wake-up from Sleep

Start-up Time

—11

—

s

VREGPM = 0

VREGPM = 1

OS26 TLFOSCST LFINTOSC Wake-up from Sleep

Start-up Time

—0.2 — ms

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 F and 0.01 F values in parallel are recommended.

2: See Figure 35-6.

125

2.0

VDD (V)

4.0 5.04.5

Temperature (°C)

2.3 3.0 3.5 5.51.8

-40

± 5%

± 2%

± 5%

± 3%

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FIGURE 35-7: CLKOUT AND I/O TIMING

TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

PLL01 FPLLIN PLL Input Frequency Range 4 — 8 MHz

PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz

PLL03 TPLLST PLL Lock Time from Start-up — 200 — s

PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 %

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FOSC

CLKOUT

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

IO1

IO8

IO3

IO7, IO8

IO10

IO12

IO5

IO4

IO2

IO7

Old Value New Value

Write Fetch Read ExecuteCycle

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TABLE 35-10: CLKOUT AND I/O TIMING SPECIFICATIONS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

IO1 TCLKOUTH CLKOUT rising edge delay

(rising edge FOSC (Q1 cycle) to

falling edge CLKOUT

—— 70ns

IO2 TCLKOUTL CLKOUT falling edge delay

(rising edge FOSC (Q3 cycle) to

rising edge CLKOUT

—— 72ns

IO3 TIO_VALID Port output valid time

(rising edge FOSC (Q1 cycle) to

port valid)

—50 70ns

IO4 TIO_SETUP Port input setup time

(Setup time before rising edge

FOSC - Q2 cycle)

20 — — ns

IO5 TIO_HOLD Port input hold time

(Hold time after rising edge

FOSC - Q2 cycle)

50 — — ns

IO6 TIOR_SLREN Port I/O rise time, slew rate

enabled

—25 —ns VDD = 3.0V

IO7 TIOR_SLRDIS Port I/O rise time, slew rate

disabled

—5 —ns VDD = 3.0V

IO8 TIOF_SLREN Port I/O fall time, slew rate

enabled

—25 —ns VDD = 3.0V

IO9 TIOF_SLRDIS Port I/O fall time, slew rate

disabled

—5 —ns VDD = 3.0V

IO10 TINT INT pin high or low time to trigger

an interrupt

25 — — ns

IO11 TIOC Interrupt-on-Change minimum

high or low time to trigger interrupt

25 — — ns

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25C unless otherwise stated.

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FIGURE 35-8: RESE T, WATC HDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMI NG

FIGURE 35-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Start-up Time

Internal Reset(1)

Watchdog Timer

RST01

I/O pins

Reset(1)

Note 1: Asserted low.

RST04

RST05

RST03

RST02 RST02

VBOR

VDD

(Device in Brown-out Reset) (Device not in Brown-out Reset)

33(1)

Reset

(due to BOR)

VBOR and VHYST

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if

PWRTE = 0.

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TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

BROWN-OUT RESET AND LOW POWER BROWN-OUT RESET SPECIFICATIONS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

RST01 TMCLR MCLR Pulse Width Low to

ensure Reset

2——s

RST02 TIOZ I/O high-impedance from

Reset detection

—— 2 s

RST03 TWDT Watchdog Timer Time-out

Period

10 16 27 ms 16 ms Nominal Reset Time

RST04* TPWRT Power-up Timer Period 40 65 140 ms

RST05 TOST Oscillator Start-up Timer

Period(1,2) —1024—TOSC (Note3)

RST06 VBOR Brown-out Reset Voltage(4) 2.55

2.30

1.80

2.70

2.45

1.90

2.85

2.60

2.10

BORV = 0

BORV = 1 (PIC16F18313/18323)

BORV = 1 (PIC16LF18313/18323)

RST07 VBORHYS Brown-out Reset Hysteresis 0 25 75 mV

RST08 TBORDC Brown-out Reset Response

Time

1335s

RST09 VLPBOR Low-Power Brown-out Reset

Voltage

1.8 2.1 2.5 V PIC16LF18313/18323

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator opera-

tion and/or higher than expected current consumption. All devices are tested to operate at “min” values

with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time

limit is “DC” (no clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

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TABLE 35-12: ANA LOG- TO- DIGITAL CONVERT ER (AD C) CH ARA CTERI STIC S(1,2)

S tandard Operating Conditions (unless othe rwis e stated)

VDD = 3.0V, TA = 25°C

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

AD01 NRResolution — — 10 bit

AD02 EIL Integral Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V

AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V

AD04 EOFF Offset Error — 0.5 ±2.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V

AD05 EGN Gain Error — ±0.2 ±2.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V

AD06 VADREF ADC Reference Voltage

(ADREF+)

1.8 — VDD V

AD07 VAIN Full-Scale Range VSS —ADREF+V

AD08 ZAIN Recommended Impedance

of Analog Voltage Source

—10 —k

AD09 RVREF ADC Voltage Reference

Ladder Impedance

—50 —k

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.

2: The ADC conversion result never decreases with an increase in the input and has no missing codes.

PIC16(L)F18313/18323

DS40001799C-page 408  2015-2017 Microchip Technology Inc.

FIGURE 35-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

TABLE 35-13: ANALOG-TO DIGITAL CONVERTER (ADC) CONVERSION TIMING

SPECIFICATIONS(1,2)

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

AD20 TAD ADC Clock Period 1 — 9 us Using FOSC as the ADC

clock source;

ADCS ! = x11

AD21 1 2 6 us Using ADCRC as the

ADC clock source;

ADCS = x11

AD22 TCNV Conversion Time — 11 — TAD Set of GO/DONE bit to

Clear of GO/DONE bit

AD23 TACQ Acquisition Time — 2 — us

AD24 THCD Sample and Hold Capacitor

Disconnect Time

0.5 — — TAD FOSC based clock source

0.5 — — TAD ADCRC based clock

source

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

AD131

AD130

BSF ADCON0, GO

ADC_clk

ADC Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

987 3210

1 TCY

AD133

1 TCY

AD132

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PIC16(L)F18313/18323

FIGURE 35-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC)

AD132

AD131

AD130

BSF ADCON0, GO

ADC_clk

ADC Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

9 7 3210

AD133

1 TCY

Note: If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This

allows the SLEEP instruction to be executed.

PIC16(L)F18313/18323

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TABLE 35-14: COMPARATOR SPECIFICATIONS

S tandard Operating Conditions (unless othe rwis e stated)

VDD = 3.0V, TA = 25°C

See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

Param

No. Sym. Characteristics Min. Typ. Max. Units Comments

CM01 VIOFF Input Offset Voltage — — ±50 mV VICM = VDD/2

CM02 VICM Input Common Mode Voltage GND — VDD V

CM03 CMRR Common Mode Input Rejection

Ratio

—50—dB

CM04 CHYST Comparator Hysteresis 15 25 35 mV

CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns

Response Time, Falling Edge — 220 500 ns

CM06* TMCV2VO(2) Mode Change to Valid Output — — 10 us

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS

to VDD.

2: A mode change includes changing any of the control register values, including module enable.

TABLE 35-15: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

S tandard Operating Conditions (unless othe rwis e stated)

VDD = 3.0V, TA = 25°C

Param

No. Sym. Characteristics Min. Typ.† Max. Units Comments

DSB01 VLSB Step Size — VDD/32 — V

DSB01 VACC Absolute Accuracy — —  0.5 LSb

DSB03* RUNIT Unit Resistor Value — 6000 — 

DSB04* TST Settling Time(1) ——10s

* These parameters are characterized but not tested.

†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.

TABLE 35-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Typ. Max. Units Conditions

FVR01 VFVR1 1x Gain (1.024V nominal) -4 —4%

VDD 2.5V, -40°C to 85°C

FVR02 VFVR2 2x Gain (2.048V nominal) -4 — 4 % VDD 2.5V, -40°C to 85°C

FVR03 VFVR4 4x Gain (4.096V nominal) -5 — 5 % VDD 4.75V, -40°C to 85°C

FVR04 TFVRST FVR Start-up Time — 35 — s

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PIC16(L)F18313/18323

FIGURE 35-12: TIM ER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 35-17: TI MER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* TT0P T0CKI Period Greater of:

20 or TCY + 40

— — ns N = prescale

value

45* TT1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous, with Prescaler 15 — — ns

Asynchronous 30 — — ns

46* TT1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous, with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* TT1P T1CKI Input

Period

Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale

value

Asynchronous 60 — — ns

48 FT1 Secondary Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.4 32.768 33.1 kHz

49* TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC —7 TOSC — Timers in Sync

mode

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

T0CKI

T1CKI

40 41

45 46

47 49

TMR0 or

TMR1

PIC16(L)F18313/18323

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FIGURE 35-13: CAPTURE/COMPARE/PWM (CCP) TIMINGS

TABLE 35-18: CAPTURE/COMPARE/PWM (CCP) CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

CC01* TccL CCPx Input Low Time No Prescaler 0.5TCY +

——ns

With Prescaler 20 — — ns

CC02* TccH CCPx Input High

Time

No Prescaler 0.5TCY +

——ns

With Prescaler 20 — — ns

CC03* TccP CCPx Input Period 3TCY + 40

— — ns N = prescale value

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

(Capture mode)

CC01 CC02

CC03

CCPx

Note: Refer to Figure 35-4 for Load conditions.

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PIC16(L)F18313/18323

FIGURE 35-14 : CLC PROPAGATION TIMING

LCx_in[n](1)

CLC

Output time

CLC

Input time LCx_out(1) CLCx

CLCxINn CLC

Module

CLC01 CLC02 CLC03

LCx_in[n](1) CLC

Output time

CLC

Input time LCx_out(1) CLCx

CLCxINn CLC

Module

Note 1: See Figure 21-1, "CLCx Simplified Block Diagram" to identify specific CLC signals.

TABLE 35-19: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Sym. Characteristic Min. Typ.† Max. Units Conditions

CLC01* TCLCIN CLC input time — 7 OS17 ns (Note 1)

CLC02* TCLC CLC module input to output progagation

time

—

VDD = 1.8V

VDD > 3.6V

CLC03* TCLCOUT CLC output time Rise Time — OS18 — — (Note 1)

Fall Time — OS19 — — (Note 1)

CLC04* FCLCMAX CLC maximum switching frequency — 32 FOSC MHz

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note1: See Table 35-10 for OS17, OS18 and OS19 rise and fall times.

PIC16(L)F18313/18323

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FIGURE 35-15: EUS ART SYNCHRONO US TRANSMISSION (MASTER/SLAVE) TIMING

FIGURE 35-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

US121 US121

US120 US122

Note: Refer to Figure 35-4 for Load conditions.

TABLE 35-20: EUSART SYN CHRONOUS TRANS MIS SION CHARACTERIST ICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

—80ns3.0V  VDD  5.5V

— 100 ns 1.8V  VDD  5.5V

US121 TCKRF Clock out rise time and fall time

(Master mode)

—45ns3.0V  VDD  5.5V

—50ns1.8V  VDD  5.5V

US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V

—50ns1.8V  VDD  5.5V

US125

US126

Note: Refer to Figure 35-4 for Load conditions.

TABLE 35-21: EUSART SYNCHRONOUS RECEIVE C HARACTE RIS TICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-setup before CK  (DT hold time) 10 — ns

US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

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PIC16(L)F18313/18323

FIGURE 35-17 : SPI MASTE R MODE TIMING (CKE = 0, SMP = 0)

FIGURE 35-18 : SPI MASTE R MODE TIMING (CKE = 1, SMP = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP81

SP71 SP72

SP73

SP74

SP75, SP76

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 35-4 for Load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP81

SP71 SP72

SP74

SP75, SP76

SP78

SP80

MSb

SP79

SP73

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 35-4 for Load conditions.

PIC16(L)F18313/18323

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FIGURE 35-19 : SPI SLAVE MODE TIMING (CKE = 0)

FIGURE 35-20 : SPI SLAVE MODE TIMING (CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP70

SP71 SP72

SP73

SP74

SP75, SP76 SP77

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

SP83

Note: Refer to Figure 35-4 for Load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP70

SP71 SP72

SP82

SP74

SP75, SP76

MSb bit 6 - - - - - -1 LSb

SP77

MSb In bit 6 - - - -1 LSb In

SP80

SP83

Note: Refer to Figure 35-4 for Load conditions.

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PIC16(L)F18313/18323

TABLE 35-22: SPI MODE CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Typ.† Max. Units Conditions

SP70* TSSL2SCH,

TSSL2SCL

SS to SCK or SCK input 2.25*TCY ——ns

SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns

SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns

SP73* TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK

edge

100 — — ns

SP74* TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK

edge

100 — — ns

SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V

—2550ns1.8V  VDD  5.5V

SP76* TDOF SDO data output fall time — 10 25 ns

SP77* TSSH2DOZSS to SDO output high-impedance 10 — 50 ns

SP78* TSCR SCK output rise time

(Master mode)

—1025ns3.0V  VDD  5.5V

—2550ns1.8V  VDD  5.5V

SP79* TSCF SCK output fall time (Master mode) — 10 25 ns

SP80* TSCH2DOV,

TSCL2DOV

SDO data output valid after SCK

edge

— — 50 ns 3.0V  VDD  5.5V

——145ns1.8V  VDD  5.5V

SP81* TDOV2SCH,

TDOV2SCL

SDO data output setup to SCK

edge

1 Tcy — — ns

SP82* TSSL2DOV SDO data output valid after SS

edge

——50ns

SP83* TSCH2SSH,

TSCL2SSH

SS after SCK edge 1.5 TCY + 40 — — ns

* These parameters are characterized but not tested.

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC16(L)F18313/18323

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FIGURE 35-21 : I2C BUS START/STOP BITS TIMING

FIGURE 35-22 : I2C BUS DATA TIMING

SP91

SP92

SP93

SCL

SDA

Start

Condition

Stop

Condition

SP90

Note: Refer to Figure 35-4 for Load conditions.

TABLE 35-23: I2C BUS START/STOP BITS CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Typ. Max. Units Conditions

SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated

Start condition

Setup time 400 kHz mode 600 — —

SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first

clock pulse is generated

Hold time 400 kHz mode 600 — —

SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —

SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

SP90

SP91 SP92

SP100

SP101

SP103

SP106 SP107

SP109 SP109

SP110

SP102

SCL

SDA

Out

Note: Refer to Figure 35-4 for Load conditions.

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PIC16(L)F18313/18323

TABLE 35-24: I2C BUS DATA CHARACTERISTICS

Standard Operating Conditions (unle ss othe rwis e stated)

Param.

No. Symbol Characteristic Min. Max. Units Conditions

SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — s Device must operate at a

minimum of 10 MHz

SSP module 1.5TCY —

SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — s Device must operate at a

minimum of 10 MHz

SSP module 1.5TCY —

SP102* TRSDA and SCL rise

time

100 kHz mode — 1000 ns

400 kHz mode 20 +

0.1CB

300 ns CB is specified to be from

10-400 pF

SP103* TFSDA and SCL fall

time

100 kHz mode — 250 ns

400 kHz mode 20 +

0.1CB

250 ns CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold

time

100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

SP107* TSU:DAT Data input setup

time

100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

SP109* TAA Output valid from

clock

100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — s

SP111 CBBus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the

requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I2C bus specification), before the SCL line is released.

PIC16(L)F18313/18323

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36.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Unless otherwise noted, all graphs apply to both the L and LF devices.

“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”

represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each

temperature range.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

PIC16(L)F18313/18323

DS40001799C-page 421  2015-2017 Microchip Technology Inc.

FIGURE 36-1: IDD, XT Oscillator, 4 MHz,

PIC16LF18313/18323 Only FIGURE 36-2: IDD, XT Oscillator, 4 MHz,

PIC16F1 8313 /18323 On ly

Typical

Max

100

150

200

250

300

350

400

450

500

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

IDD (µA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

DD (V)

Max

Typical

100

150

200

250

300

350

400

450

500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (µA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

FIGURE 36-3: IDD, HS Oscillator, 32 MHz,

PIC16LF18313/18323 Only FIGURE 36-4: IDD, HS Oscillator, 32 MHz,

PIC16F1 8313 /18323 On ly

Typical

Max

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

()

Max

Typical

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

FIGURE 36-5: IDD, HFINTOSC Mode,

FOSC = 32 MHz, PIC16LF18313/18323 Only FIGURE 36-6: IDD, HFINTOSC Mode,

FOSC = 32 MHz, PIC16F18313/18323 Only

Typical

Max

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

(V)

Max

Typical

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

()

 2015-2017 Microchip Technology Inc. DS40001799C-page 422

PIC16(L)F18313/18323

FIGURE 36-7: IDD, HFINTOSC Mode,

FOSC = 16 MHz, PIC16LF18313/18323 Only FIGURE 36-8: IDD, HFINTOSC Mode,

FOSC = 16 MHz, PIC16F18313/18323 Only

Typical

Max

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

Typical

Max

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (mA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

FIGURE 36-9: IDD, HFINTOSC IDLE Mode,

FOSC = 16 MHz, PIC16LF18313/18323 Only FIGURE 36-10: IDD, HFINTOSC IDLE Mode,

FOSC = 16 MHz, PIC16F18313/18323 Only

Typical

Max

200

400

600

800

1,000

1,200

1.61.82.02.22.42.62.83.03.23.43.63.8

(µA)

(V)

Max: 85°C + 3ı

Typical: 25°C

Max

Typical

200

400

600

800

1,000

1,200

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (µA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

()

FIGURE 36-11: IDD, HFINTOSC

DOZE Mode, FOSC = 16 MHz,

PIC16LF18313/18323 Only

FIGURE 36-12: IDD, HFINTOSC

DOZE Mode, FOSC = 16 MHz,

PIC16F1 8313 /18323 On ly

Typical

Max

200

400

600

800

1,000

1,200

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

IDD (µA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

Max

Typical

200

400

600

800

1,000

1,200

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

IDD (µA)

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

()

PIC16(L)F18313/18323

DS40001799C-page 423  2015-2017 Microchip Technology Inc.

FIGURE 36-13 : IPD BASE, Low-Power

Sleep Mode, PIC1 6LF 18 313 /18 323 On ly FIGURE 36-14: IPD, Watch Dog Timer

(WDT), PIC16LF18313/18323 Only

1.0

Max.

0.6

0.7

0.8

0.9

1.0

)

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0.2

0.3

0.4

0.5

0.6

IPD (µA)

0.0

0.1

0.2

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 36-15 : IPD, Watch Dog Timer

(WDT), PIC16F18313/18323 Only FIGURE 36-16: IPD, Fixed Voltage

Reference (FVR), PIC16LF18313/18323 Only

1.2

Max.

Typical

0.8

1.0

1.2

Typical

0.2

0.4

0.6

IPD (µA)

Max: 85°C + 3ı

ical: 25°C

0.0

0.2

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

M85

Max.

)

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

IPD (µA)

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

FIGURE 36-17 : IPD, Fixed Voltage

Reference (FVR), PIC16F18313/18323 Only FIGURE 36-18: IPD, Brown-out Reset

(BOR), BORV = 1, PIC16LF18313/18323 Only

Max.

µA)

ax.

Typical

IPD (µA)

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max.

(µA)

Max: 85°C + 3ı

Typical: 25°C

Typical

IPD (µA)

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

 2015-2017 Microchip Technology Inc. DS40001799C-page 424

PIC16(L)F18313/18323

FIGURE 36-19 : IPD, Brown-out Reset

(BOR), BORV = 1, PIC16F18313/18323 Only FIGURE 36-20: IPD, Low-Power Brown-out

Reset (LPB OR = 0), PIC16LF1 831 3/18 323 Only

Max: 85

C+3

Max: 85

C+3

Typical

Max.

)

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Typical

IPD (µA)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

0.5

Max.

0.3

0.4

0.5

Typical

0.1

0.2

0.3

IPD (µA)

Max: 85°C + 3ı

Typical: 25°C

Typical

0.1

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

VDD (V)

Max:

Typical: 25°C

FIGURE 36-21 : IPD, Low-Power Brown-out

Reset (LPBOR = 0), PIC16F 18 313/ 183 23 Only FIGURE 36-22: IPD, Comparator,

PIC16LF18313/18323 Only

0.8

Max.

Typical

0.5

0.6

0.7

0.8

Typical

0.2

0.3

0.4

0.5

(µA)

Max: 85°C + 3ı

Typical: 25°C

0.0

0.1

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(V)

Max:

Typical: 25°C

Max.

Typical

(µA)

Max: 85°C + 3ı

Typical: 25

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

(V)

Max: 85°C + 3ı

Typical: 25°C

FIGURE 36-23 : IPD, Comparator,

PIC16F18 313 /18323 On ly FIGURE 36-24: IPD BA SE , 01,

PIC16F1 8313 /18323 On ly

Max

Max.

Typical

IPD (µA)

Max: 85°C + 3ı

Typical: 25

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

Max: 85°C + 3ı

Typical: 25°C

Typical

IPD (µA)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

(V)

PIC16(L)F18313/18323

DS40001799C-page 425  2015-2017 Microchip Technology Inc.

FIGURE 36-25 : IPD BASE, 11,

PIC16F18 313 /18323 On ly FIGURE 36-26: HFINTOSC Typical

Frequency Error, PIC16LF18313/18323 Only

Max.

0.6

0.7

0.8

0.9

Max: 85°C + 3ı

Typical: 25°C

Max.

Typical

0.2

0.3

0.4

0.5

0.6

IPD (µA)

0.1

0.2

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

(V)

Max.

Typical

Min.

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

3.0%

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

Error (%)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

(V)

FIGURE 36-27 : HFINTOSC Typical

Frequency Error, PIC16F18313/18323 Only FIGURE 36-28: HFINTOSC Frequency Error

VDD = 3V, All devices

Max.

Typical

Min.

-5.0%

-4.0%

-3.0%

-2.0%

-1.0%

0.0%

1.0%

2.0%

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Error (%)

(V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

Max.

Typical

Min.

-2.0%

-1.5%

-1.0%

-0.5%

0.0%

0.5%

1.0%

1.5%

-50 0 50 100 150

Error (%)

Temperature (°C)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

FIGURE 36-29 : LFINTOSC Frequency,

PIC16LF18313/18323 Only FIGURE 36-30: LFINTOSC Frequency,

PIC16F1 8313 /18323 On ly

Max.

Typical

Min.

28,000

29,000

30,000

31,000

32,000

33,000

34,000

35,000

36,000

1.7 2.0 2.3 2.6 2.9 3.2 3.5

Frequency (Hz)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

Max.

Typical

Min.

28,000

29,000

30,000

31,000

32,000

33,000

34,000

35,000

36,000

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Frequency (Hz)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

 2015-2017 Microchip Technology Inc. DS40001799C-page 426

PIC16(L)F18313/18323

FIGURE 36-31 : Weak Pull-Up Current,

PIC16F18 313 /18323 On ly FIGURE 36-32: Weak Pull-Up Current,

PIC16LF18313/18323 Only

Max.

Typical

250

300

Max.

Typical

Min.

100

150

200

250

ll-Up Current (µA)

100

2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0

Pull-Up

(V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0

VDD (V)

180

Max.

Typical

Min.

100

120

140

160

180

nt (µA)

100

120

Pull-Up Current (µ

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

FIGURE 36-33 : VOH vs. IOH Over

Temperature, VDD = 5.5V,

PIC16F18 313 /18323 On ly

FIGURE 36-34: VOL vs. IOL Over

Temperature, VDD = 5.5V,

PIC16F1 8313 /18323 On ly

-40°C

Typical

125°C

-45 -40 -35 -30 -25 -20 -15 -10 -5 0

(V)

(mA)

Graph represents 3ıLimits

(mA)

-40°C

Typical

125°C

0 102030405060

VOL (V)

IOL (mA)

Graph represents 3ıLimits

FIGURE 36-35 : VOH vs. IOH Over

Temperature, VDD = 3.0V, All devices FIGURE 36-36: VOL vs. IOL Over

Temperature, VDD = 3.0V, All devices

-40°C

Typical

125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-30 -25 -20 -15 -10 -5 0

VOH (V)

IOH (mA)

Graph represents 3ıLimits

-40°C

125°C

Typical

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25 30 35 40 45 50 55 60

VOL (V)

IOL (mA)

Graph represents 3ıLimits

(mA)

PIC16(L)F18313/18323

DS40001799C-page 427  2015-2017 Microchip Technology Inc.

FIGURE 36-37 : VOH vs. IOH Over

Temperature, VDD = 1.8V,

PIC16LF18313/18323 Only

FIGURE 36-38: VOL vs. IOL Over

Temperature, VDD = 1.8V,

PIC16LF18313/18323 Only

-40°C

Typical

125°C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

(V)

(mA)

Graph represents 3ıLimits

-40°C

Typical

125°C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

01234567891011121314151617181920

VOL (V)

IOL (mA)

Graph represents 3ıLimits

FIGURE 36-39 : Brown- out Reset Voltage,

High Trip Point, (BOR V = 0), All devices FIGURE 36-40: Brown-out Reset

Hysteresis, Low Trip Point, (BORV = 0),

All devic es

Max.

Typical

Min.

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

Voltage (V)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical

2.40

2.45

2.50

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

Max.

Typical

Min.

10.0

20.0

30.0

40.0

50.0

60.0

70.0

Voltage (mV)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

0.0

10.0

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 36-41 : Brown- out Reset Voltage,

Trip Po int, (BORV = 1), PIC16LF1 8313 /18 323

Only

FIGURE 36-42: Br ow n- out Reset

Hysteresis, Trip Point, (BORV = 1),

PIC16LF18313/18323 Only

Max.

Typical

Min.

1.85

1.90

1.95

2.00

Voltage (V)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical

1.80

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

Max.

Typical

Min.

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

Voltage (mV)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

0.0

5.0

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Typical: Statistical mean

Min: Typical - 3ı

 2015-2017 Microchip Technology Inc. DS40001799C-page 428

PIC16(L)F18313/18323

FIGURE 36-43 : Brown- out Reset Voltage,

Trip Po int, (BORV = 1), PIC16F18 313/ 183 23

Only

FIGURE 36-44: Br ow n- out Reset

Hysteresis, Trip Point, (BORV = 1),

PIC16F1 8313 /18323 On ly

Max.

Typical

Min.

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

Voltage (V)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical

2.20

2.25

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

ax:

Typical: Statistical mean

Min: Typical - 3ı

Max.

Typical

Min.

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0

Voltage (mV)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

10.0

15.0

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 36-45 : LPBOR Reset Voltage,

PIC16LF18313/18323 Only FIGURE 36-46: LPBOR Reset Hysteresis,

PIC16LF18313/18323 Only

Max.

Typical

Min.

1.80

1.90

2.00

2.10

2.20

2.30

2.40

2.50

2.60

Voltage (V)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

1.70

1.80

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Max.

Typical

Min.

Voltage (mV)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 36-47 : BOR Response Time,

PIC16LF18313/18323 Only FIGURE 36-48: BOR Respon se Time,

PIC16F1 8313 /18323 On ly

Max.

Typical

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

Time (µs)

(V)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

(V)

Max.

Typical

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Time (µs)

(V)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

(V)

PIC16(L)F18313/18323

DS40001799C-page 429  2015-2017 Microchip Technology Inc.

FIGURE 36-49 : ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, VREF = 3.0V,

TAD = 1 µs, 25°C, All devices

FIGURE 36-50: ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, VREF = 3.0V,

TAD = 4 µs, 25°C, All devices

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

DNL (LSb)

Output CodeOutput Code

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

DNL (LSb)

Output CodeOutput Code

FIGURE 36-51 : ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, VREF = 3.0V,

TAD = 8 µs, 25°C, All devices

FIGURE 36-52: ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, VREF = 3.0V,

TAD = 1 µs, 25°C, All devices

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

DNL (LSb)

Output CodeOutput Code

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

INL (LSb)

Output CodeOutput Code

FIGURE 36-53 : ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, VREF = 3.0V,

TAD = 4 µs, 25°C, All devices

FIGURE 36-54: ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, VREF = 3.0V,

TAD = 8 µs, 25°C, All devices

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 512 1024 1536 2048 2560 3072 3584 4096

DNL (LSb)

Output Code

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

INL (LSb)

Output CodeOutput Code

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 512 1024 1536 2048 2560 3072 3584 4096

DNL (LSb)

Output Code

-1.0

-0.5

0.0

0.5

1.0

0 128 256 384 512 640 768 896 1024

INL (LSb)

Output CodeOutput Code

 2015-2017 Microchip Technology Inc. DS40001799C-page 430

PIC16(L)F18313/18323

FIGURE 36-55 : ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, VREF = 3.0V,

All devices

FIGURE 36-56: ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, VREF = 3.0V,

All devic es

-1.0

-0.5

0.0

0.5

1.0

0.5 0.8 1.0 2.0 4.0 8.0

DNL (LSb)

TAD (µs)

Max 25°C

Min 25°C

Max -40°C

Min -40°C

Max 85°C

Min 85°C

TAD (µs)

-1.0

-0.5

0.0

0.5

1.0

0.5 0.8 1.0 2.0 4.0 8.0

INL (LSb)

TAD (µs)

Max 25°C

Min 25°C

Max -40°C

Min -40°C

Max 85°C

Min 85°C

TAD (µs)

FIGURE 36-57 : ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, TAD = 1 µs,

All devices

FIGURE 36-58: ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, TAD = 1 µs,

All devic es

-1.0

-0.5

0.0

0.5

1.0

1.8 2.3 2.5 3.0

DNL(LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

VREF (V)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

1.8 2.3 2.5 3.0

INL(LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

FIGURE 36-59 : ADC 10-Bit Mode,

Single-Ended Gain Error , VDD = 3.0V , TAD = 1 µs,

All devices

FIGURE 36-60: ADC 10-Bit Mode,

Single-Ended Offset Error, VDD = 3.0V,

TAD = 1 µs, All devices

gμ

-6

-5

-4

-3

-2

-1

1.8 2.3 2.5 3.0

Gain Error (LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.8 2.3 2.5 3.0

Offset Error (LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

PIC16(L)F18313/18323

DS40001799C-page 431  2015-2017 Microchip Technology Inc.

FIGURE 36-61 : ADC 10-Bit Mode,

Single-Ended DNL, VDD = 3.0V, TAD = 4 µs,

All devices

FIGURE 36-62: ADC 10-Bit Mode,

Single-Ended INL, VDD = 3.0V, TAD = 4 µs,

All devic es

-1.0

-0.5

0.0

0.5

1.0

1.8 2.3 2.5 3.0

DNL(LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

()

Title ,g , ,μ

-1.0

-0.5

0.0

0.5

1.0

1.8 2.3 2.5 3.0

INL(LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

FIGURE 36-63 : ADC 10-Bit Mode,

Single-Ended Gain Error , VDD = 3.0V , TAD = 4 µs,

All devices

FIGURE 36-64: ADC 10-Bit Mode,

Single-Ended Offset Error, VDD = 3.0V,

TAD = 4 µs, All devices

-6

-5

-4

-3

-2

-1

1.8 2.3 2.5 3.0

Gain Error (LSb)

VREF (V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

-1.0

-0.5

0.0

0.5

1.0

1.8 2.3 2.5 3.0

Offset Error (LSb)

REF

(V)

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

REF

(V)

FIGURE 36-65 : ADC 10-Bit Mode,

Single-Ended Gain Error, VDD = 3.0V,

VREF = 3.0V, -40°C to 85°C, All devices

FIGURE 36-66: ADC 10-Bit Mode,

Single-Ended Offset Error, VDD = 3.0V,

VREF = 3.0V, -40°C to 85°C, All devices

Max.

Typical

Min.

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0.5 0.8 1.0 2.0 4.0 8.0

Gain Error (LSb)

(µs)

Max.

Typical

Min.

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0.5 0.8 1.0 2.0 4.0 8.0

Offset Error (LSb)

(µs)

0.5 0.8 1.0 2.0 4.0 8.0

(µs)

 2015-2017 Microchip Technology Inc. DS40001799C-page 432

PIC16(L)F18313/18323

FIGURE 36-67 : ADC RC Oscillator period,

PIC16LF18313/18323 Only FIGURE 36-68: ADC RC Oscillator period,

PIC16F1 8313 /18323 On ly

Max.

Typical

Min.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

Max.

Typical

Min.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

FIGURE 36-69 : Typical DAC DNL Error,

VDD = 3.0V, VREF = External 3V, All devices FIGURE 36-70: Typical DAC INL Error,

VDD = 3.0V, VREF = External 3V, All devices

-0.020

-0.015

-0.010

-0.005

0.000

0.005

0.010

0.015

0.020

0.025

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

DNL (LSb)

Output Code

-40°C

25°C

85°C

125°C

Output Code

-0.45

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

INL (LSb)

Output Code

-40°C

25°C

85°C

125°C

Output Code

FIGURE 36-71 : Typical DAC DNL Error,

VDD = 5.0V, VREF = External 5V,

PIC16F18 313 /18323 On ly

FIGURE 36-72: Typical DAC INL Error,

VDD = 5.0V, VREF = External 5V,

PIC16F1 8313 /18323 On ly

-0.015

-0.010

-0.005

0.000

0.005

0.010

0.015

0.020

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

DNL (LSb)

Output Code

-40°C

25°C

85°C

125°C

Output Code

-0.45

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

INL (LSb)

Output Code

-40°C

25°C

85°C

125°C

PIC16(L)F18313/18323

DS40001799C-page 433  2015-2017 Microchip Technology Inc.

FIGURE 36-73 : DAC INL Error, VDD = 3.0V,

PIC16LF18313/18323 Only FIGURE 36-74: Absolute V alue of DAC DNL

Error, VDD = 3.0V, VREF = VDD, All devices

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

-50 0 50 100 150

Absolute DNL (LSb)

Temperature (°C)

Vref = Int. Vdd

Vref = Ext. 1.8V

Vref = Ext. 2.0V

Vref = Ext. 3.0V

0.0

0.1

0.2

0.3

0.4

-60 -40 -20 0 20 40 60 80 100 120 140

Absolute DNL (LSb)

Temperature (°C)

VREF = INT. VDD

VREF = EXT. 1.8V

VREF = EXT. 2.0V

VREF = EXT. 3.0V

)

FIGURE 36-75 : Absolute Value of DAC INL

Error, VDD = 3.0V, VREF = VDD, All devices FIGURE 36-76: Absolute V alue of DAC DNL

Error, VDD = 5.0V, VREF = VDD,

PIC16F1 8313 /18323 On ly

-3.5

-3.3

-3.1

-2.9

-2.7

-2.5

-2.3

-2.1

0.0 1.0 2.0 3.0 4.0 5.0

Absolute INL (LSb)

Temperature (°C)

-40

125

0.78

0.80

0.82

0.84

0.86

0.88

0.90

-60 -40 -20 0 20 40 60 80 100 120 140

Absolute INL (LSb)

Temperature (°C)

VREF = INT. VDD

VREF = EXT. 1.8V

VREF = EXT. 2.0V

VREF = EXT. 3.0V

Temperature (

0.05

0.1

0.15

0.2

0.25

0.3

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Absolute DNL (LSb)

Temperature (°C)

-40

125

0.10

0.14

0.18

0.22

0.26

0.30

-60 -40 -20 0 20 40 60 80 100 120 140

Absolute DNL (LSb)

Temperature (°C)

VREF = Int. VDD

VREF = Ext. 1.8V

VREF = Ext. 2.0V

VREF = Ext. 3.0V

VREF = Ext. 5.0V

Temperature (

FIGURE 36-77 : Absolute Value of DAC INL

Error, VDD = 5.0V, VREF = VDD,

PIC16F18 313 /18323 On ly

FIGURE 36-78: Com parato r Hystere si s,

Normal Power Mode (CxSP = 1), VDD = 3.0V,

Typical Measured Values, All devices

-3.5

-3.3

-3.1

-2.9

-2.7

-2.5

-2.3

-2.1

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Absolute INL (LSb)

Temperature (°C)

-40

125

0.78

0.80

0.82

0.84

0.86

0.88

0.90

-60 -40 -20 0 20 40 60 80 100 120 140

Absolute INL (LSb)

Temperature (°C)

VREF = Int. VDD

VREF = Ext. 1.8V

VREF = Ext. 2.0V

VREF = Ext. 3.0V

VREF = Ext. 5.0V

Hysteresis (mV)

-40°C

25°C

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Common Mode Voltage (V)

125

85°C

 2015-2017 Microchip Technology Inc. DS40001799C-page 434

PIC16(L)F18313/18323

FIGURE 36-79 : Comparator Offset, Normal

Power Mode (CxSP = 1), VDD = 3.0V, Typical

Measured Values at 25°C, All devices

FIGURE 36-80: Com parato r Of fse t, Normal

Power Mode (CxSP = 1), VDD = 3.0V, Typical

Measured Values from -40°C to 125°C,

All devic es

Max.

Min.

-10

-5

Offset Voltage (mV)

-20

-15

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Common Mode Voltage (V)

Max.

Min.

-10

-5

Offset Voltage (mV)

-20

-15

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Common Mode Voltage (V)

FIGURE 36-81 : Comparator Hysteresis,

Normal Power Mod e (CxSP = 1), V DD = 5.5V,

Typical Measured Values,

PIC16F18 313 /18323 On ly

FIGURE 36-82: Com parato r Of fse t, Normal

Power Mode (CxSP = 1), VDD = 5.0V, Typical

Measured Values at 25°C,

PIC16F1 8313 /18323 On ly

Hysteresis (mV)

-40°C

25°C

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Voltage (V)

125

85°

Max.

Min.

-10

-5

Hysteresis (mV)

Min.

-20

-15

-10

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Common Mode Voltage (V)

FIGURE 36-83 : Comparator Offset, Normal

Power Mode (CxSP = 1), VDD = 5.5V, Typical

Measured Values from -40°C to 125°C,

PIC16F18 313 /18323 On ly

FIGURE 36-84: Comparator Response Time

Over Voltag e, Normal Power Mode (CxSP = 1),

VDD = 5.5V, Typical Measured Values

PIC16LF18313/18323 Only

Max.

Min.

-10

Offset Voltage (mV)

Min.

-20

-10

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Voltage (V)

Min.

Typical

Max.

100

120

140

Time (ns)

Max: Typical + 3ı(-40°C to +125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı(-40°C to +125°C)

Min.

1.7 2.0 2.3 2.6 2.9 3.2 3.5

(V)

PIC16(L)F18313/18323

DS40001799C-page 435  2015-2017 Microchip Technology Inc.

FIGURE 36-85 : Comparator Response Time

Over Voltage, No rmal Power Mode (CxSP = 1),

VDD = 5.5V, Typical Measured Values

PIC16F18 313 /18323 On ly

FIGURE 36-86: Com parato r Respon se Time

Falling edge, PIC16LF18313/18323 Only

Min.

Typical

Max.

Time (ns)

Max: Typical + 3ı(-40°C to +125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı(-40°C to +125°C)

2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5

(V)

Max.

Typical

100

150

200

250

300

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

Time (ns)

VDD (V)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

VDD (V)

FIGURE 36-87 : Comparator Response Time

Falling edge, PIC16F18313/18323 Only FIGURE 36-88: Comparator Respon se Time

Rising edge, PIC16LF18313/18323 Only

Max.

Typical

100

150

200

250

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Time (ns)

(

)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

(V)

Max.

Typical

100

200

300

400

500

600

700

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

Time (ns)

VDD (V)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

VDD (V)

FIGURE 36-89 : Comparator Response Time

Rising edge, PIC16F18313/18323 Only FIGURE 36-90: Bandgap Ready Time,

PIC16LF18313/18323 Only

Max.

Typical

100

200

300

400

500

600

700

800

900

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Time (ns)

VDD (V)

Max: Typical + 3ı @ 125°C

Typical: Statistical mean @ 25°C

VDD (V)

Max.

Typical

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

(V)

 2015-2017 Microchip Technology Inc. DS40001799C-page 436

PIC16(L)F18313/18323

FIGURE 36-91 : FVR Stabilization Period,

PIC16LF18313/18323 Only FIGURE 36-92: Typical FVR Voltage (1x),

PIC16LF18313/18323 Only

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

0.0%

0.1%

0.2%

0.3%

0.4%

0.5%

0.6%

0.7%

0.8%

0.9%

1.0%

1.1%

2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

Error (%)

(V)V

(V)

FIGURE 36-93 : FVR Voltage Error (1x),

PIC16F18 313 /18323 On ly FIGURE 36-94: FVR Voltage Error (2x),

PIC16LF18313/18323 Only

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

0.0%

0.2%

0.4%

0.6%

0.8%

1.0%

1.2%

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Error (%)

0.0%

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

VDD (V)

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

-0.4%

-0.2%

0.0%

0.2%

0.4%

0.6%

0.8%

1.0%

2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7

Error (%)

VDD (V)VDD (V)

FIGURE 36-95 : FVR Voltage Error (2x),

PIC16F18 313 /18323 On ly FIGURE 36-96: FVR Voltage Error (4x),

PIC16F1 8313 /18323 On ly

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

-0.2%

0.0%

0.2%

0.4%

0.6%

0.8%

1.0%

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Error (%)

DD (V)

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

VDD (V)

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

-0.4%

-0.2%

0.0%

0.2%

0.4%

0.6%

0.8%

1.0%

4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6

Error (%)

(V)

PIC16(L)F18313/18323

DS40001799C-page 437  2015-2017 Microchip Technology Inc.

FIGURE 36-97 : Schmitt T rigger High V alues,

All devices FIGURE 36-98: Schmitt Trigger Low Values,

All devic es

Max. Typical

Min.

3.0

3.5

4.0

Min.

1.0

1.5

2.0

2.5

3.0

Voltage (V)

0.0

0.5

1.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

VDD (V)

2.5

Max. Typical

Min.

1.5

2.0

2.5

ltage (V)

Min.

0.0

0.5

1.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Voltage

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

0.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Min:

Typical

(

125

FIGURE 36-99 : TTL Trip Thresholds, All

devices FIGURE 36-100: Rise Time, Slew Rate

Control Enabled, All devices

Max.

Typical

1.0

1.2

1.4

1.6

1.8

ge (V)

Min.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Voltage (V

)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

0.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Typical:

Statistical

mean

Min: Typical - 3ı (-40°C to 125°C)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Max.

Typical

Time (ns)

Typical

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

(V)

FIGURE 36-10 1: Fall Time, Slew Rate Control

Enabled, All devices FIGURE 36-102: Rise Time, Slew Rate

Control Disabled, All devices

Max: Typical

ı(

C to 125

Max.

e (ns)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

ax.

Typical

Time (n

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

Max: Typical + 3

ı(

C to 125

e (ns)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Max.

Typical

Time (ns

)

Typical

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

 2015-2017 Microchip Technology Inc. DS40001799C-page 438

PIC16(L)F18313/18323

FIGURE 36-10 3: Fall Time, Slew Rate Control

Disabled, All devices FIGURE 36-104: OSCTUNE Center

Freque ncy, PIC1 6LF18313/183 23 On ly

Max: Typical + 3

ı(

C to 125

e (ns)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Max.

Typical

Time (ns

)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

1 00%

2.00%

3.00%

4.00%

Max: Typical + 3ı(-40°C to +125°C)

Typical; statistical mean @ 25°C

Min: Typical - 3ı(-40°C to +125°C)

-2.00%

-1.00%

0.00%

1.00%

00%

Error (%)

Max

Min

Average

-4.00%

-3.00%

-2.00%

-32 -24 -16 -8 0 8 16 24 32

OSCTUNE Settin

Cente

Min Max

OSCTUNE Setting

Cente

Min Max

FIGURE 36-10 5: POR Release Voltage,

All devices FIGURE 36-106: POR Rearm Voltage,

Normal Power Mode, PIC16F18313/18323 Only

Max.

Typical

Min.

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

-60 -40 -20 0 20 40 60 80 100 120 140

Voltage (V)

Temperature (°C)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

1.58

1.59

1.6

1.61

1.62

1.63

1.64

-40 -20 0 20 40 60 80 100 120

Voltage (V)

Temperature (°C)

Max: Typical + 3ı

Typical: 25°C

Min: Typical - 3ı

Max.

Typical

Min.

1.50

1.55

1.60

1.65

1.70

1.75

1.80

-60 -40 -20 0 20 40 60 80 100 120 140

Voltage (V)

Temperature (°C)

Max: Typical + 3ı

Typical: Statistical mean

Min: Typical - 3ı

FIGURE 36-10 7: PWRT Period,

PIC16F18 313 /18323 On ly FIGURE 36-108: PWRT Period,

PIC16LF18313/18323 Only

Max.

Typical

Min.

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (ms)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

Max.

Typical

Min.

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

Time (ms)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

PIC16(L)F18313/18323

DS40001799C-page 439  2015-2017 Microchip Technology Inc.

FIGURE 36-10 9: Wake From Sleep,

VREGPM = 0, HFINTOSC = 4 MHz,

PIC16F18 313 /18323 On ly

FIGURE 36-110: ULP Wake From Sleep,

VREGPM = 1, HFINTOSC = 4 MHz,

PIC16F1 8313 /18323 On ly

Max.

Typical

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Max.

Typical

100

110

120

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

FIGURE 36-111 : Wake From Sleep,

VREGPM = 1, HFINTOSC = 16 MHz,

PIC16F18 313 /18323 On ly

FIGURE 36-112: ULP Wake From Sleep,

VREGPM = 1, HFINTOSC = 16 MHz,

PIC16F1 8313 /18323 On ly

Max.

Typical

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Max.

Typical

100

110

120

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

FIGURE 36-113: Wake From Sleep,

VREGPM = 1, LFINTOSC,

PIC16F18 313 /18323 On ly

FIGURE 36-114: Wake From Sleep,

LFINTOSC, PIC16LF18313/18 323 On ly

Max.

Typical

300

350

400

450

500

550

600

650

700

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

Time (µs)

(V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

(V)

Max.

Typical

300

350

400

450

500

550

600

650

700

1.7 2.2 2.7 3.2 3.7

Time (µs)

VDD (V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

 2015-2017 Microchip Technology Inc. DS40001799C-page 440

PIC16(L)F18313/18323

FIGURE 36-115: WD T Time- out Peri od,

PIC16F18 313 /18323 On ly FIGURE 36-116: WDT Time-out Period,

PIC16LF18313/18323 Only

Max.

Typical

Min.

3.8

3.9

4.0

4.1

4.2

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Time (ms)

(V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

(V)

Max.

Typical

Min.

3.8

3.9

4.0

4.1

4.2

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

Time (ms)

(V)

Max: Typical + 3ı (-40°C to 125°C)

Typical: Statistical mean @ 25°C

Min: Typical - 3ı (-40°C to 125°C)

 2015-2017 Microchip Technology Inc. DS40001799C-page 441

PIC16(L)F18313/18323

37.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers (MCU) and dsPIC® digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

• Integrated Development Environment

- MPLAB® X IDE Software

- MPLAB Xpress IDE Software

- Microchip Code Configurator (MCC)

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB X SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

- PICkit™ 3

• Device Programmers

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Third-party development tools

37.1 MPLAB X Integrated Development

Environment Software

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows®,

Linux and Mac OS® X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

Feature-Rich Editor:

• Color syntax highlighting

• Smart code completion makes suggestions and

provides hints as you type

• Automatic code formatting based on user-defined

rules

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

PIC16(L)F18313/18323

DS40001799C-page 442  2015-2017 Microchip Technology Inc.

37.2 MPLAB XC Compilers

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other relo-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

37.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

37.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

37.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

 2015-2017 Microchip Technology Inc. DS40001799C-page 443

PIC16(L)F18313/18323

37.6 MPLAB X SIM Software Simulator

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

37.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

The emulator is field upgradeable through future firm-

ware downloads in MPLAB X IDE. MPLAB REAL ICE

offers significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

37.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

37.9 PICkit 3 In-Circuit De bugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

37.10 MPLAB PM3 Device Program mer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

PIC16(L)F18313/18323

DS40001799C-page 444  2015-2017 Microchip Technology Inc.

37.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

tion software for analog filter design, KEELOQ® security

ICs, CAN, IrDA®, PowerSmart battery management,

SEEVAL® evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

37.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

• Demonstration Boards from companies, such as

MikroElektronika, Digilent® and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika®

 2015-2017 Microchip Technology Inc. DS40001799C-page 445

PIC16(L)F18313/18323

38.0 PACKAGING INFORMATION

38.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16F18313

-I/SO 1304017

8-Lead PDIP (300 mil) Example

XXXXXXXX

XXXXXNNN

YYWW

16F18313

P 017

1110

8-Lead SOIC (3.90 mm) Example

NNN

16F18313I

SN 1110

017

PIC16(L)F18313/18323

DS40001799C-page 446  2015-2017 Microchip Technology Inc.

Package Marking Information (Continue d)

8-Lead UDFN (3x3x0.9 mm) Example

XXXX

NNN

YYWW

PIN 1 PIN 1

MGR0

1110

017

14-Lead PDIP (300 mil) Example

PIC16F18323

1304017

14-Lead SOIC (3.90 mm) Example

PIC16F18323

1304017

14-Lead TSSOP (4.4 mm) Example

YYWW

NNN

XXXXXXXX

16F18323

1304

017

 2015-2017 Microchip Technology Inc. DS40001799C-page 447

PIC16(L)F18313/18323

Package Marking Information (Continue d)

16-Lead UQFN (4x4x0.9 mm) Example

PIN 1 PIN 1

PIC16

F18323

130417

PIC16(L)F18313/18323

DS40001799C-page 448  2015-2017 Microchip Technology Inc.

TABLE 38-1: 8-LEAD 3x3 UDFN (RF) TOP MARKING

Part Number Marking

PIC16F18313 RF MGG0

PIC16LF18313 RF MGH0

 2015-2017 Microchip Technology Inc. DS40001799C-page 449

PIC16(L)F18313/18323

38.2 Package Details

The following sections give the technical details of the packages.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

8X b

8X b1

PLANE

.010 C

NOTE 1

TOP VIEW

END VIEWSIDE VIEW

PIC16(L)F18313/18323

DS40001799C-page 450  2015-2017 Microchip Technology Inc.

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e.100 BSC

Top to Seating Plane A - - .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c.008 .010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b.014 .018 .022

Overall Row Spacing eB - - .430

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

protrusions shall not exceed .010" per side.

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

Pin 1 visual index feature may vary, but must be located within the hatched area.

§ Significant Characteristic

Dimensioning and tolerancing per ASME Y14.5M

DATUM A DATUM A

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

 2015-2017 Microchip Technology Inc. DS40001799C-page 451

PIC16(L)F18313/18323

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F18313/18323

DS40001799C-page 452  2015-2017 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2015-2017 Microchip Technology Inc. DS40001799C-page 453

PIC16(L)F18313/18323

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DS40001799C-page 454  2015-2017 Microchip Technology Inc.

0.10 C

0.10 C A B

(DATUM B)

(DATUM A)

SEATING

PLANE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

NOTE 1

0.10 C A B

0.05 C

Microchip Technology Drawing C04-254A Sheet 1 of 2

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]

(A3)

NOTE 1

8X be

 2015-2017 Microchip Technology Inc. DS40001799C-page 455

PIC16(L)F18313/18323

Microchip Technology Drawing C04-254A Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Terminal Width

Overall Width

Overall Length

Terminal Length

Exposed Pad Width

Exposed Pad Length

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

0.65 BSC

0.065 REF

1.40

2.20

0.35

0.25

0.45

0.00

0.30

3.00 BSC

0.45

2.30

1.50

0.50

0.02

3.00 BSC

MILLIMETERS

MIN NOM

1.60

2.40

0.55

0.35

0.55

0.05

MAX

K-0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]

PIC16(L)F18313/18323

DS40001799C-page 456  2015-2017 Microchip Technology Inc.

RECOMMENDED LAND PATTERN

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Dimension Limits

Units

Optional Center Pad Width

Optional Center Pad Length

Contact Pitch

2.40

1.60

MILLIMETERS

0.65 BSC

MIN

MAX

Contact Pad Length (X8)

Contact Pad Width (X8)

0.85

0.35

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

Microchip Technology Drawing C04-2254A

NOM

8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]

SILK SCREEN

CContact Pad Spacing 2.90

Contact Pad to Center Pad (X8) G2 0.30

Contact Pad to Contact Pad (X6) G1 0.20

 2015-2017 Microchip Technology Inc. DS40001799C-page 457

PIC16(L)F18313/18323

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%%*$% ^G  { 

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&%% Y G G 

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NOTE 1

123

A1 b1

  & \{|

PIC16(L)F18313/18323

DS40001799C-page 458  2015-2017 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2015-2017 Microchip Technology Inc. DS40001799C-page 459

PIC16(L)F18313/18323

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F18313/18323

DS40001799C-page 460  2015-2017 Microchip Technology Inc.

?@@&&&!!@$

 2015-2017 Microchip Technology Inc. DS40001799C-page 461

PIC16(L)F18313/18323

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F18313/18323

DS40001799C-page 462  2015-2017 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2015-2017 Microchip Technology Inc. DS40001799C-page 463

PIC16(L)F18313/18323

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F18313/18323

DS40001799C-page 464  2015-2017 Microchip Technology Inc.

0.20 C

0.10 C A B

(DATUM B)

(DATUM A)

SEATING

PLANE

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

NOTE 1

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-257A Sheet 1 of 2

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

(A3)

16X b

16X

 2015-2017 Microchip Technology Inc. DS40001799C-page 465

PIC16(L)F18313/18323

Microchip Technology Drawing C04-257A Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Pins

Overall Height

Terminal Width

Overall Width

Overall Length

Terminal Length

Exposed Pad Width

Exposed Pad Length

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

0.65 BSC

0.127 REF

2.50

0.30

0.25

0.45

0.00

0.30

4.00 BSC

0.40

2.60

0.50

0.02

4.00 BSC

MILLIMETERS

MIN NOM

2.70

0.50

0.35

0.55

0.05

MAX

K-0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]

PIC16(L)F18313/18323

DS40001799C-page 466  2015-2017 Microchip Technology Inc.

RECOMMENDED LAND PATTERN

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

SILK SCREEN

Dimension Limits

Units

Optional Center Pad Width

Contact Pad Spacing

Optional Center Pad Length

Contact Pitch

2.70

MILLIMETERS

0.65 BSC

MIN

MAX

4.00

Contact Pad Length (X16)

Contact Pad Width (X16)

0.80

0.35

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

Microchip Technology Drawing C04-2257A

NOM

16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body

C1 4.00Contact Pad Spacing

[UQFN]

 2015-2017 Microchip Technology Inc. DS40001799C-page 467

PIC16(L)F18313/18323

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (07/2015)

Initial release of the document.

Revision B (12/2016)

Minor updates brought to Table 1-1; Table 1-2; Table

1-3; Added new Chapter 2 “Guidelines for Getting

Started with PIC16(L)F183XX Microcontrollers”;

Updated Figure 3-1; Added Section 4.1.1.3 “NVMREG

Access”, Section 4.2.1 “BANK SELECTION”; Updated

Table 6-1; Updated Figure 7-1; Updated Register 7-6;

Updated Figure 8-2; Updated Register 9-1; Added Sec-

tion 10.2.4 “WDT IS ALWAYS OFF”; Updated Table

11-2; Updated Example 11-4; Removed Example 11-5;

Updated Figure 15-1; Updated Figure 18-2; Updated

Figure 22-1; Updated Figure 29-1; Updated Figure

31-1.

Revision C ( 7/2017)

Minor electrical specs updated, Char Graphs updated

for IDD.

PIC16(L)F18313/18323

DS40001799C-page 468  2015-2017 Microchip Technology Inc.

THE MICROCHIP WEBSITE

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the website

at: http://www.microchip.com/support

 2015-2017 Microchip Technology Inc. DS40001799C-page 469

PIC16(L)F18313/18323

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F18313, PIC16LF18313,

PIC16F18323, PIC16LF18323

Tape and Reel

Option: Blank = Standard packaging (tube or tray)

T = Tape and Reel(1)

Temperature

Range: I= -40C to +85C(Industrial)

E= -40

C to +125C (Extended)

Package:(2) JQ = UQFN

P=PDIP

ST = TSSOP

SL = SOIC-14

SN = SOIC-8

RF = UDFN

Pattern: QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC16LF18313- I/P

Industrial temperature

PDIP package

b) PIC16F18313- E/SS

Extended temperature,

SSOP package

Note 1: Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

2: Small form-factor packaging options may

be available. Check

www.microchip.com/packaging for

small-form factor package availability, or

contact your local Sales Office.

[X](1)

Tape and Reel

Option

DS40001799C-page 470  2015-2017 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT

logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,

Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK

MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST

logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32

logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,

SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are

registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,

CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,

ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-

Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,

MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,

PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,

RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial

Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,

Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Reserved.

ISBN: 978-1-5224-1966-2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperip herals, nonvola tile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

 2015-2017 Microchip Technology Inc. DS40001799C-page 471

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

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http://www.microchip.com/

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Web Address:

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Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

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Tel: 852-2943-5100

Fax: 852-2401-3431

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Fax: 86-25-8473-2470

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Tel: 86-532-8502-7355

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Tel: 86-21-3326-8000

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Tel: 86-24-2334-2829

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Tel: 86-755-8864-2200

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Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

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Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

ASIA/PACIFIC

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

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Tel: 886-7-213-7830

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Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Thailand - Bangko k

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

Finl a nd - Espoo

Tel: 358-9-4520-820

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

France - Saint Cloud

Tel: 33-1-30-60-70-00

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Tel: 49-8931-9700

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Tel: 49-2129-3766400

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Tel: 49-7131-67-3636

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Tel: 49-721-625370

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Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

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Tel: 49-8031-354-560

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Tel: 972-9-744-7705

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Tel: 39-0331-742611

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Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Worldwide Sales and Service

11/07/16

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Microchip:

PIC16LF18313-E/SN PIC16LF18323-E/SL PIC16LF18323-I/JQ PIC16F18323-E/JQ PIC16LF18313T-I/RF

PIC16F18313-I/RF PIC16F18323-I/JQ PIC16LF18313-I/SN PIC16LF18313-I/RF PIC16LF18313-I/P PIC16F18313T-

I/RF PIC16LF18313-E/RF PIC16LF18323-E/JQ PIC16F18313-E/RF PIC16F18323T-I/JQ PIC16LF18323-I/ST

PIC16LF18323T-I/SL PIC16LF18313T-I/SN PIC16LF18323-E/ST PIC16LF18323-I/P PIC16LF18313-E/P

PIC16LF18323T-I/ST PIC16LF18323-E/P PIC16LF18323-I/SL PIC16LF18323T-I/JQ PIC16F18313-E/MF

PIC16F18313-E/MS PIC16F18313-E/P PIC16F18313-E/SN PIC16F18313-I/MS PIC16F18313T-I/MS PIC16F18323-

E/P PIC16F18323-E/SL PIC16F18323-E/ST