AT6000LV Series - Atmel Corporation

AT6000 and AT6000LV Se-

ries

Coprocessor

Field

Programmable

Gate Arrays

Description

AT6000 S eries SRAM- Based Field P rogram mable G ate Arrays ( FPG As) are ideal for

use as reconfigurable cop rocessors a nd i mplementing compute int ensive logi c.

Supporting system speeds greater than 100 MHz and using a typical operating current

of 15 to 170 mA, A T6000 Series devices are ideal for high-speed, compute-intensive

designs. These FPG As ar e desi gned to implement C ache Logi c®, which provides th e

user wi th the ability to implem ent adapti ve har dware and per form hardw ar e accelera-

tion.

The patented AT6000 Series architecture employs a symmetrical grid of small yet

powerful cel l s connected t o a f l exi ble busi ng network. Independentl y controlled clocks

and reset s gover n ever y col umn of cells. T he ar ray is surr ounded by pr ogrammable

I/O.

(continued)

Features

•High Performance

System Speeds > 100 MHz

Flip-Flop Toggle Rates > 250 MHz

1.2 ns/1.5 ns Input Delay

3.0 ns/6.0 ns Output Delay

•Up to 204 User I/Os

•Thousands of Registers

•Cache Logic® Design

Complete/Partial In-System Reconfiguration

No Loss of Data or Machine State

Adaptive Hardware

•Low Voltage and Standard Voltage Operation

5.0 (VCC = 4.75V to 5.25V)

3.3 (VCC = 3.0V to 3.6V)

•Automatic Component Generators

Reusable Custom Hard Macro Functions

•Very Low Power Consumption

Standby Current of 500 µA/ 200 µA

Typical Operating Current of 15 to 170 mA

•Programmable Clock Options

Independently Controlled Column Clocks

Independently Controlled Column Resets

Clock Skew Less Than 1 ns Across Chip

•Independently Configurable I/O (PCI Compatible)

TTL/CMOS Input Thresholds

Open Collector/Tri-state Outputs

Programmable Slew-Rate Control

I/O Drive of 16 mA (combinable to 64 mA)

•Easy Migration to Atmel Gate Arrays for High Volume Production

AT6000 Se ries Field Programmable Gate Arrays

Device AT6002 AT6003 AT6005 AT6010

U sable Gat es 6,000 9, 000 15,000 30, 000

Cells 1,024 1,600 3,136 6,400

R egisters (m aximum ) 1,024 1,600 3,136 6, 400

I/ O (m axi m um ) 96 120 108 204

Typ. Operating Current (mA) 15-30 25- 45 40- 80 85-170

Cel l R ows x C olumns 32 x 32 40 x 40 56 x 56 80 x 80 0264E

AT6000/LV Series

2-3

Description (Conti nued)

Figure 1. Symmet rical A rray Surrounded by I/O

(continued)

Device s range in size from 4,000 to 30,000 usable gates,

and 102 4 to 6400 re gisters. Pin locations are consistent

throughout the A T6000 Series for easy design mi gration.

High-I/O versions are available for the lower gate count

devices.

AT6000 Series FPGAs utilize a reliable 0.6 µm single-

poly, double-metal CMOS process and are 100% factory-

test ed.

Atmel’s PC- and workstation-based Integrated Develop-

ment System is used to create AT6000 Series designs.

Mul tiple design entr y methods ar e suppor ted.

The Atmel architecture was developed to provide the high-

est levels of performance, functional density and design

flexibility in an FPGA. The cells in the Atmel array are

small, very efficient and contain the most important and

m ost commonly used logi c and wi ring f unct ions. The cel l’s

small size leads to arrays with large numbers of cells,

great ly multiplying the f uncti onality in each cell. A simple,

high-speed busing network provides fast, efficient com-

muni cation over medium and long distances.

The Symmetrical Array

A t the hear t of the At m el arch itecture is a sym m etrical ar -

ray of identical cells (Figure 1). The array is continuous

and compl etely unint errupt ed from one edge to the other,

excep t for bus

repeaters

spaced every eight cell s (Figure

2).

In addit ion to logic and st or age, cell s can also be used as

wires to connect functions together over short distances

and ar e useful fo r rout ing in tight spaces.

The Busing Network

Th ere are two kinds of buses: loca l and express (see Fig-

ures 2 and 3) .

Local buses ar e the li nk between the arra y of cell s and the

busing net work. There are two local buses— North-S outh

1 and 2 (NS1 and NS2)— for every column of cells, a nd

two loca l buses— East-West 1 and 2 (EW1 and EW2)—

for eve ry row of ce lls. In a sector (an 8 x 8 array of cells

enclosed by repeaters) each local bus is connected to

every cell in it s column or row, th us providin g ever y cel l i n

2-4 AT6000/LV Series

Figu r e 3. Cell -to-Cell and Bus- to- Bus Connections

Figu r e 2. Busing Network (one sector )

CELL

REPEATER

AT6000/LV Series

2-5

F igure 4. Cell Structure

(continued)

the array with read/write access to two North-South and

two East -West buses.

Each cell, in addit ion, provid es t he abilit y to rout e a sig nal

on a 90° turn between the NS1 bus and EW1 bus and

between the NS 2 bus and EW2 bus.

Express buses are not connected directly to cells, and

thus provide higher speeds. They are the fastest way to

cover long, straight-l ine distances within the ar ray.

Each exp ress bus is paired wi th a local bus, so there ar e

two express buses for every column and two express

buses for every row of cells.

Connective units, called repeaters, spaced every eight

cells, divide each bus, both local and express, into seg-

m ents spanning eight cells. Repeat ers are aligned i n rows

and columns thereby p artitioning the ar ray into 8 x 8 sec-

tors of cells. Each repeater is associated with a local/ex-

press pair, and on each side of the repeater are connec-

tions to a local-bus segment and an express-bus segment.

The repeater can be prog rammed to provide any one of

twenty-one connecting functions. These functions are

sym metric wi th respect t o bot h the tw o repeater sides and

the two t y pes of buses.

Among the functions provi ded are the abi lit y to:

•Isol ate bus segment s from one another

•C onnect two local-bus segme nts

•C onnect two express-bus segme nts

•Imp lement a local/express transf er

In al l of these cases, each connect ion provid es signal re-

generation and is thus unidirectional. For bidirectional

connections, t he basi c repeater f uncti on f or t he N S2 and

EW2 repeaters is augmented w ith a special programma-

ble connection allowing bidirectional communication be-

tween local-bus segm ents. Thi s option is primarily used to

implement l ong, tri-state buses .

D escrip tio n (Continued) The Cell Structure

Th e At mel cell (Fi gur e 4) is simple and small and yet can

be progra mmed to perform all t he logic and wiring func-

tions needed to i mplement any digi tal cir cuit. Its four sides

are functionally identical, so each cell is completely sym-

metrical.

Read/write access to the four local buses— NS1, EW1,

NS 2 and EW2— i s controlled, in part, by four bidirectional

pass gates connected directly to t he buses. To rea d a lo-

cal bus, the pass gate for that bus is turned on and the

thr ee-input multipl exer is set accor dingly. To write t o a lo-

cal bus, the pass gate for that bus and the pass gate for

the associated t ri-state dri ver are both t urned on. The two-

input multiplexer supplying the cont rol signal to the drivers

permits either: (1) active drive, or (2) dynamic tri-stating

controll ed by t he B i nput. Turning bet ween LNS1 and LEW1

or betw een LNS2 and LEW2 is accom plished by t urni ng on

the two associ ated pass gates. The operations of readi ng,

w riting and t ur ning are subject to the re striction t hat e ach

bus can be involved in no m or e than a sin gle operation.

In addition to the four local-bus connections, a cell re-

cei ves t wo input s and provides t wo outputs t o each of its

North (N), South (S), East (E) and West (W) neighbors.

These inputs and output s ar e divided into two classes: “A”

and “B.” There is an A input and a B input from each neigh-

boring cell and an A output and a B out put drivi ng all four

neighbors. Between cells, an A output is always con-

nected t o an A input and a B output to a B i nput.

Within the cell, the four A inputs and the four B inputs enter

two separate, independently configurable multiplexers.

C ell f lexibility is enhanced by allowi ng each multipl exer to

select also the logical constant “1.” The two multiplexer

outputs enter the two upstream AN D gates.

Dow nstream from these two A N D gates are an E xclusive-

OR ( XOR) gat e, a regi ster, an AN D gate, an inve rter a nd

tw o four-input multiplexers produci ng the A and B out put s.

These mul tiplexers are co ntrolled in tandem (unli ke the A

and B input multiplexers) and determine the function of the

cell.

•In S tate 0— cor respond ing to t he “0" inputs of the mul-

tiplexers— the output of the left-hand upstream AND

gat e is connected to the cel l’s A output , and the output

of the right-hand upstream AND gate is connected to

th e cell’s B out put.

•In S tate 1— cor respond ing to t he “1" inputs of the mul-

tiplexers— the output of the left-hand upstream AND

gate is connected to the cell’s B output, the output of the

right-hand upstream AND gate is connected to the cell’s

A outpu t.

•In S tate 2— cor respond ing to t he “2" inputs of the mul-

tiplexers— the XOR of the outputs from the two up-

stream AND gates is provided to the cell’s A output,

2-6 AT6000/LV Series

Figu re 5c. Physical Const ant s

Figure 6a. Two -Input AND Feeding XOR

Figure 6b. Cell C onfiguration ( A•L) XOR B

Figure 5b. Register S tates

Figure 5a. Combin ato r ia l Phy s ic al State s

"0" "0"

"0" "1"

"1" "0"

"1" "1"

BA, L

A, L

Q"0"

A, L

BB A

A, L

AT6000/LV Series

2-7

(continued)

Description (Continued)

"1"

GLOBAL

CLOCK

EXPRESS

BUS

GLOBAL

CLOCK

EXPRESS

BUS

CELL

EXPRESS

BUS

GLOBAL

RESET

EXPRESS

BUS

GLOBAL

RESET

CELL

"1"

Fi gur e 7. Col umn Cl ock and Column Reset

w hile t he NAND of t hese t wo outputs is provided to the

cel l’s B output .

•In St ate 3— corre sponding to the “3" inputs of th e m ul-

tiplexers— the XOR function of State 2 is provided to

the D input of a D- type fl ip-f lop, t he Q output of whi ch i s

connected t o the cell’s A o utput. Clo ck and asynchro-

nous reset signal s a re suppli ed exter nally as described

later. The AND of the outputs from the two upstream

A ND gates is pr ovided to the cell’s B outpu t.

Lo gic St at e s

The At mel cel l i mplements a rich and powerful set of logic

functions, stemming from 44 logical cell states which per-

mutate into 72 physical states. Some states use both A

and B inputs. Other st ates are cr eat ed by selecting the “1"

input on either or both of the inpu t mul tiplexers.

There are 28 combinatorial primitives created from the

cell’s tri-state capabilities and the 20 physical states repre-

sented i n the Figure 5a. Fi ve logi cal primit ives are deri ved

from the physical constants shown in Figure 5c. More

compl ex f unctions ar e cr eat ed by using cells in combina-

tion.

A tw o-input AND feedi ng an XOR (F igure 6a) i s produced

using a single cell (Figure 6b). A two-to-one multiplexer

selects the logical constant “0" and feeds it to the right-

hand AND gate. The AND gate acts as a feed-through,

letting t he B input pass t hrough to t he XOR. The thr ee-to-

one multip lexer on the right side selects the local-bus in-

put, LNS1, and passes it t o the left-hand AND gate. The A

and LNS1 si gnals are the inputs to t he AND gat e. The out-

put of the AND gate feeds into the XOR, producing the

logic state (A•L) XO R B.

Cl ock Di str ibu tio n

Along the top edge of the array is logic for distributing

clock signals t o t he D f li p-flop in each l ogic cell (Figure 7) .

The distribution network i s org anized by column and per -

mits columns of cells to be independently clocked. At t he

head of each column is a user-configurable multiplexer

providing the clock signal for that column. It has four in-

puts:

•Global clock supplied thr ough t he CLOCK pin

•Express bus adjacent t o t he di stribution logic

•“A” output of t he cell at the head of th e column

•Logical const ant “1" t o conserve power (no clock)

Through the global clock, th e network provides low-skew

distribution of an externally supplied clock to any or all of

the columns of the array. The global clock pi n is also con-

nected directly to the arra y via the A input of the upper lef t

and ri ght corner cells ( AW on the lef t, and AN on t he right).

The express bus i s usef ul in distributing a secondary clock

to multiple columns when the global clock line is used as

a primary clock. The A output of a cell is useful in providing

a clock si gnal to a single col umn. The constant “1" is used

to reduce pow er dissipation in columns using no r egi st er s.

Asynchronous Reset

Along the bottom edge of the array is logic f or asynchro-

nously r esetting the D f lip-flops in the logic cel ls (Figure 7).

Like t he cl ock network, the asynchronous reset net work is

organized by column and permits columns to be inde-

pen dentl y reset. At the bottom of each column is a user-

configur abl e multipl exer providing the reset sign al for t hat

col umn. It has four inputs:

•Global asynchronous reset supplied through th e

RESET pin

•Express bus adjacent t o t he di stribution logic

•“A” output of t he cell at the foot of the column

•Logical const ant “1"to conserve pow er

The asynchronous r eset l ogi c uses t hese f our i nputs in the

same way that the cl ock d istribution logic does. Throu gh

the global asynchronous reset, any or all columns can be

reset by an externally supplied signal. The global asyn-

chronous reset pi n is also connecte d direct ly t o t he ar r ay

vi a t he A input of t he l ower left and ri ght corne r cells (AS

on the left, and AE on the right) . The e xpress bus can be

used to distribute a secondary reset to multiple columns

w hen t he gl obal reset li ne is used as a pri mary r eset, t he

A output of a cell can al so pr ovi de an asynchronous reset

si gnal to a single column, and t he constant “1" is used by

col umns with registers r equi ring no reset. All register s are

reset dur ing power-up.

2-8 AT6000/LV Series

Figu re 8a. A-Type I/ O Logic F igure 8b. B-Type I/O Logic

Input/Output

The Atmel architecture provides a flexible interface be-

tween the logic array, the configuration control logic and

the I/ O pins.

Two adj acent cells— an “exit” and an “ entrance” cel l— on

the perimete r of the logic array are associated with each

I/O pi n.

There are two t ypes of I/Os: A-type (Figur e 8a) and B- type

(Figure 8b ). For A-type I/Os, the edge-facing A output of

an exit cell is connected t o an out put driver, and t he edge-

fa cing A input of the adj acent ent rance cell i s connected to

an input buffer. The output of the output driver and the

input of the input buffe r are connected to a common pi n.

B-type I/Os are the same as A-type I/Os, but use the B

inputs and outputs of their respective entrance and exit

cells. A- and B- type I/Os alter nate around the arr ay.

Control of the I/O logic is provided by user-configurable

m e mo ry b it s .

TTL/CMOS Inputs

A user-configurable bit determines the threshold level—

TTL or CMOS— of the input buffer.

Open Collector/Tri-state Outputs

A user- configura ble bit whi ch enabl es or disa bles the ac-

tiv e pull-up of the output device.

Slew Rate Control

A user-configurable bit controls the slew rate— fast or

slow— of the output buffer. A slow slew rate, which re-

duces noise and ground bounce, i s recommended for out-

D escrip tio n (Continued) puts that are not speed-critical. Fast and slow slew rates

have the same DC-current sinking capabilities, but the

rat e at whi ch each allo ws the out put devices t o r each f ull

drive differs.

Pull-up

A user-conf igurable bit cont rols t he pul l- up t ransistor in the

I/O pin. It’s primary function is to provide a logical “1" to

unused input pins. When on, it is approximately equivalent

to a 25K resistor to V CC.

Enable Select

User -confi gurable bit s determine the output-enable for the

output driver. The output driver can be static - - alw ays on

or always off - - or dynamically controlled by a signal gen-

erated in the array. Four options are available from the

array: ( 1) the control is lo w and alwa ys dr ivi ng; (2) t he con-

tro l is h igh and n ever d rivi ng; (3) t he control is connect ed

to a vertical local bus associated with the output cell; or (4)

the cont rol is connected to a horizontal local bus associ-

ated with the output cell. On power-up, the user I/Os are

configured as inputs with pull-up resisto rs.

In addition to the functionality provided by the I/O logic, the

entr ance and exit cells pr ovide the abilit y t o r egister bot h

inputs and outputs. Also, these perimeter cells (u nlike in-

terior cells) are connected dire ctly to express buses: the

edge-f acing A and B out put s of the entrance cell are con-

nected to express buses, as are the edge-facing A and B

inputs of the exit cell. These buses are perpendi cular to

the edge, and provide a rapid means of bringing I/O sig-

nals to and fro m the array interi or and the opposite edge

of the chip.

AT6000/LV Series

2-9

(continued)

Pin Function Description

This sect i on provides abbr e viat ed descript i ons of t he vari-

ous AT6000 Series pins. For m ore compl ete descri ptions,

ref er to t he A T6000 Series Configurat ion data sheet.

Pi nout t ables for t he AT6000 series of devices fol low.

Power Pins

VCC, VDD, GND, VSS

VCC and G ND are the I/O supply pins, VDD and VSS are

the inter nal logic supply pins. VCC and VDD sh ould be tie d

to the same t ra ce on the printed circuit board. GND and

VSS should be t ied to the same trace on the printed ci rcuit

board.

Input/Output Pins

All I/O pins can be used in the sam e way (refer to the I/O

section of t he archit ect ure descri ption). S ome I/O pi ns are

dual-function pins used during configuration of the array.

When not being used for confi guration , dual-function I/Os

ar e f ull y functional as normal I/O pins. O n initial pow er- up,

all I/Os are conf igur ed as TTL i nputs wi th a pul l-up.

Dedicated Timing and Control P ins

CON

Configuration- in-process pin. After power-up, CON stays-

Low unt i l pow er -up ini t ial i zati on i s complete, at which ti me

CON is then released. CON is an open collector signal.

After power-up initialization, forcing CON low begins the

configur at ion proce ss.

Configuration enable pin. All configuration pins are ig-

nored i f CS is high. CS must be held low througho ut the

configur at ion proce ss. CS is a TT L i nput pin.

M0, M1, M2

Configuration mode pins are used to determine the con-

f igurat ion mode. All three ar e TTL in put pins.

CCLK

C onfigur atio n clock pin. CCLK is a TTL input or a CMOS

out put dependin g on the mode of opera tion. In modes 1,

2, 3, and 6 it is an input. In modes 4 and 5 it is an output

w ith a typica l frequency of 1 M H z. In all modes, the rising

edge of the CCLK signal is used to sample inputs and

change outputs.

CLOCK

External logic source used to drive the internal global

cl ock line. Registers togg le on the r isi ng edge of C LOCK.

The CLO CK si gnal i s neither used nor affected by t he con-

f igurat ion modes. I t is always a TTL input.

RESET

Array register asynchronous reset. RESET drives the in-

ter nal globa l rese t. T he RES ET si gnal is neither used nor

affected by the configuration modes. It is always a TTL

input.

Dual-Function Pins

When CON is high, dual-function I/O pins act as device

I/Os; when CON is low, dual-function pins are used as

configuration cont rol or data signals as det ermined by the

configuration modes. Care must be taken when using

these pins to ensure that configuration activity does not

int erfere wi th other cir cuitry connected to these pi ns in th e

application.

D0 or I/O

Ser ial configuration modes use D0 as t he ser i al data input

pi n. Parallel configurat ion modes use D0 as the lea st-sig-

ni ficant bit . Input dat a m ust meet setup and hol d r equire-

ments with respect to the rising edge of CCLK. D0 is a TTL

i nput during confi gura tion.

D1 to D7 or I/O

Parallel configuration modes use these pins as inputs. Se-

rial conf iguration modes do not use t hem . Data must meet

setup and hold requirements with respect to the rising

edge of CCLK. D1-D7 are TTL inputs during configuration.

Chip Configurati on

The Integrated Development System generates the

SRAM bit pattern required to configure a AT600 0 Series

device. A PC parallel port, microprocessor, EPROM or se-

rial configurati on memory can be used to download con-

figuration patterns.

Users select fr om several conf i gur ation modes. M any f ac-

tors, including board area, configuration speed and the

numbe r of d esigns implemented in parallel can influence

the user’s final choice.

Configuration is contr olled by dedicated confi guration pins

and dual-function pins that double as I/O pins when the

device is in operation. The number of dual-function pins

requi red for each mode varies.

The devices can be partially reco nfigured while in o pera-

tion. Por t ions of t he device not being modified remain op-

erational during reconfiguration. Simultaneo us confi gura-

tion of more than one device is also possible. Ful l configu-

rat ion takes as little as a mil lisecon d, partial configurat ion

is even faster.

Refer to the Pi n Funct ion Description secti on following f or

a brief summary of the pins used in configuration. For

m ore information about confi gurati on, ref er to the AT6000

Series Conf iguration data sheet.

2-10 AT6000/LV Series

Pin Function Descripti on (Continued)

A0 to A16 or I/O

During configuration in modes 1, 2 and 5, these pins are

CMOS outputs and act as the address pins for a parallel

EPROM. A0-A16 e liminates the need f or an external ad-

dress counter w hen usi ng an ext ern al parall el nonvolati le

memory to configure the FPGA. Addresses change after

the ri sing edge of the CC LK signal.

CSOUT or I/O

When cascading devices, CSOUT is an out put used to en-

able other devices. CSOUT should be connected to the

CS inp ut of the downstream d evice. The CSOUT function

is opt i onal and can be di sabled during initial pr ogramming

when cascading is not used. When cascading devices,

CSOUT should be dedicated to configuration and not used

as a configurabl e I /O.

CHECK or I/O

During configuration, CHECK is a TTL input that can be

used to enable the data check funct ion at the beginning of

a configurati on cycl e. No data is wr itten to t he devi ce while

CHECK is low. Instead, the configuration file being applied

Device P i nout S election (Max. Number of User I/O)

AT6002 AT6003 AT6005 AT6010

84 PLC C 64 I/O 64 I/O 64 I/O —

100 VQ FP 80 I/O 80 I/O 80 I/O —

132 PQ FP 96 I/O 108 I/O 108 I/O 108 I/O

144 TQFP 96 I/O 120 I/O 108 I/O 120 I/O

208 PQ FP — — — 172 I/O

240 PQ FP — — — 204 I/O

Mode(s) Type (1, 2) Be ginn ing Sequ ence AT6002 AT6003 AT6005 AT6010

1 P Preamble 2677 4153 8077 16393

2 P Preamble 2677 4153 8077 16393

3 S Nu ll Byt e/Preamble 2678 4154 8078 16394

4 S Nu ll Byt e/Preamble 2678 4154 8078 16394

5 P Preamble 2677 4153 8077 16393

6 P Preamble/Preamble 2678 4154 8078 16394

Notes: 1. P = Parallel.

2. S = Serial.

Bit-Stream Size s

to D0 (or D0-D 7, in paral lel mode) is compared with the

current contents of the internal configuration RAM. If a

mismatch i s detect ed between the data being loa ded and

t he data already i n t he RAM, th e ERR pin goes low. T he

CHECK function is optional and can be disabled during

i nitial programming.

ERR or I/O

Dur ing configuration, E RR is an output. When the CHECK

function i s act ivat ed and a mismat ch is detected bet w een

the cur rent configuration data stream and t he data al r eady

loaded i n t he conf igurati on RA M, E RR goes lo w. The ERR

output is a registered signal. Once a mismatch is found,

the signal is set and is only reset after the configuration

cycle is restarted. ERR is also asserted for configuration

file errors. The ERR function is opti onal and can be dis-

abled dur ing initial pr ogr ammi ng.

AT6000/LV Series

2-11

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

— — — I/O51(A) ————B1 1 1

I/O24(A) or A7 I/O30(A) or A7 I/O27 (A) o r A 7 I/O50(A) or A7 12 1 18 1 C1 2 2

— I/O29(B) — I/O49(A) ———2 D1 3 3

— — — I/O48(B) ————— —4

———VCC————PWR

(1) 45

— — — I/O47(A) ————E1 5 6

———GND————GND

(2) 67

— I/O28(A) I/O26(A) I/O46(A) — — 19 3 G1 7 8

I/O23(A) or A6 I/O27(A) or A6 I/O25 (A) o r A 6 I/O4 5(A) or A6 13 2 20 4 H1 8 9

— — — I/O44(B) ————— —10

— — — I/O43(A) ————C2 9 11

I/O22(B) I/O26(A) I/O24(A) I/O42(A) — — 21 5 D2 10 12

I/O21(A) or A5 I/O25(A) or A5 I/O23 (A) o r A 5 I/O4 1(A) or A5 14 3 22 6 E2 11 13

— — — I/O40(B) ————— —14

— — — I/O39(A) ————F2 1215

I/O20(B) I/O24(B) I/O22(A) I/O38(A) — 4 23 7 G2 13 16

I/O19(A) or A4 I/O23(A) or A4 I/O21 (A) o r A 4 I/O3 7(A) or A4 15 5 24 8 H2 14 17

— — — I/O36(B) ————— —18

I/O18(B) I/O22(B) I/O20(A) I/O35(A) — — 25 9 D3 15 19

I/O17(A) or A3 I/O21(A) or A3 I/O19 (A) o r A 3 I/O3 4(A) or A3 16 6 26 10 E3 16 2 0

I/O16(B) I/O20(B) I/O18(A) I/O33(A) — 7 27 11 F3 17 21

— — — I/O32(B) ————— 1822

I/O15(A) or A2 I/O19(A) or A2 I/O17 (A) o r A 2 I/O3 1(A) or A2 17 8 28 12 G3 19 23

— I/O18(B) I/O16(A) I/O30(A) — — 29 13 H3 20 24

GND GND GND GND 18 9 30 14 GND (2) 21 25

VSS VSS VSS VSS 19 10 31 15 GND (2) 22 26

I/O14(A) or A1 I/O17(A) or A1 I/O15 (A) o r A 1 I/O2 9(A) or A1 20 11 32 16 F4 23 27

— — — I/O28(B) ————— 2428

— I/O16(B) — I/O27(A) ———17G4 2529

I/O13(A) or A0 I/O15(A) or A0 I/O14 (A) o r A 0 I/O2 6(A) or A0 21 12 33 18 H4 26 30

I/O12(B) or D7 I/O14 (A) or D7 I/O13(A) o r D7 I/O25(A) or D7 22 13 34 19 H5 27 3 1

— — — I/O24(B) ————— 2832

I/O11(A) or D6 I/O13 (A) or D6 I/O12(A) o r D6 I/O23(A) or D6 23 14 35 20 J4 29 33

I/O10(A) or D5 I/O12(A ) or D5 I/O11(A) or D5 I/O22(A) or D5 24 15 36 21 K4 30 34

VDD VDD VDD VDD 25 16 37 22 PWR (1 ) 31 35

VCC VCC VCC VCC 26 17 38 23 PWR (1) 32 36

I/O9(B) I/O11(B) I/O10(A) I/O21(A) — — 39 24 J3 33 37

— — — I/O20(B) ————— 3438

I/O8(A) or D4 I/O10 (A) or D4 I/O9( A) or D4 I/O19(A) or D4 27 18 40 25 K3 35 39

I/O7(B) I/O9(B) I/O8(A) I/O18(A) — 19 41 26 L3 36 40

— — — I/O17(A) ————M3 3741

— — — I/O16(B) ————— —42

I/O6(A) or D3 I/O8(A) o r D3 I/O7(A) or D3 I/O15(A) or D3 28 20 42 27 N3 38 43

— I/07(B) I/O6(A) I/014(A) — — 43 28 J2 39 44

— — — I/O13(A) ————K2 4045

GND GND GND GND — — 44 29 GND (2) 41 46

———VSS————GND

(2 ) 42 47

— — — I/O12(B) ————— —48

I/O5(A) or D2 I/O6(A) o r D2 I/O5(A) or D2 I/O11(A) or D2 29 21 45 30 M2 43 49

I/O4(B) I/O5(B) I/O4(A) I/O10(A) — 22 46 31 N2 44 50

Left Si de (T op t o Botto m)

(continued)

P inout Ass ignment

2-12 AT6000/LV Series

L e ft Side (Top to Bo ttom ) (Continued)

Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.

2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

(continued)

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

— — — I/O9(A) ————P2 4551

— — — I/O8(B) ————— —52

I/O3(A) or D1 I/O4(A) o r D1 I/O3(A) or D1 I/O7(A) or D1 30 23 47 32 J1 4 6 53

I/O2(B) I/O3(A) I/O2(A) I/O6(A) — — 48 33 K1 47 54

— — — I/O5(A) ————L1 4855

— — — I/O4(B) ————— —56

— I/O2(B) — I/O3(A) ———34M1 4957

I/O1(A) or D0 I/O1(A) o r D0 I/O1(A) or D0 I/O2(A) or D0 31 24 49 35 N1 50 58

— — — I/O1(A) ————P1 5159

CCLK CCLK CCLK CCLK 32 25 50 36 R1 52 60

Bottom S ide (L eft to Right)

P inout Ass ignment (Continued)

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

CON CON CON CON 33265137M5 5361

— — — I/O204(A) ————M6 5462

I/O96(A) I/O120(A) I/O108(A) I/O203(A) 34 27 52 38 M7 55 63

— I/O119(B) — I/O202(A) ———39R2 5664

— — — I/O201(B) ————— —65

———VCC————PWR

(1) 57 66

— — — I/O200(A) ————R3 5867

———GND————GND

(2) 59 68

— I/O118(A) I/O107(A) I/O199(A) — — 53 40 R5 60 69

I/O95(A) or CS OUT I/ O117(A) or C SO UT I/O1 06( A) or CSOUT I/O198(A) or CSOUT35285441R6 6170

— — — I/O197(B) ————— —71

— — — I/O196(A) ————R7 6272

I/O94(B) I/O116(A) I/O105(A) I/O195(A) — — 55 42 P3 63 73

I/O93(A) I/O115(A) I/O104(A) I/O194(A) 36 29 56 43 P4 64 74

— — — I/O193(B) ————— —75

— — — I/O192(A) ————P5 6576

I/O92(B) I/O114(B) I/O103(A) I/O191(A) — 30 57 44 P6 66 77

I/O91(A) or CHECK I/ O113 (A ) or CHECK I/O1 02( A) or CHECK I/O190( A) or CHECK 37 31 58 45 P7 67 78

— — — I/O189(B) ————— —79

I/O90(B) I/O112(B) I/O101(A) I/O188(A) — — 59 46 N4 68 80

I/O89(A) or ERR I/O111(A) or ERR I/O10 0 (A) or ERR I/O187(A) or ERR38326047N5 6981

I/O88(B) I/O110(B) I/O99(A) I/O186(A) — 33 61 48 N6 70 82

— — — I/O185(B) ————— 7183

I/O87(A) I/O109(A) I/O98(A) I/O184(A) 39 34 62 49 N7 72 84

I/O108(B) I/O97(A) I/O183(A) 63 50 M8 73 85

GND GND GND GND 40 35 64 51 GND

(2) 74 86

I/O86(A) I/O107(A) I/O96(A) I/O182(A) 41 36 65 52 M9 75 87

— — — I/O181(B) ————— 7688

— I/O106(B) — I/O180(A) ———53M107789

I/O85(A) I/O105(A) I/O95(A) I/O179(A) 42 37 66 54 M11 78 90

CS CS CS CS 43 38 67 55 L8 79 91

I/O84(B) I/O104(A) I/O94(A) I/O178(A) 44 39 68 56 M12 80 92

AT6000/LV Series

2-13

Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.

2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

Bottom Side (Left to Right) (Continued)

(continued)

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

— — — I/O177(B) ————— 8193

I/O83(A) I/O103(A) I/O93(A) I/O176(A) 45 40 69 57 N8 82 94

———VDD————PWR

(1) 83 95

VCC VCC VCC VCC 46 41 70 58 PWR

(1) 84 96

I/O82(A) I/O102(A) I/O92(A) I/O175(A) 47 42 71 59 N11 85 97

I/O81(B) I/O101(B) I/O91(A) I/O174(A) — — 72 60 N12 86 98

— — — I/O173(B) ————— 8799

I/O80(A) I/O100(A) I/O90(A) I/O172(A) 48 43 73 61 N13 88 100

I/O79(B) I/O99(B) I/O89(A) I/O171(A) — 44 74 62 P8 89 101

— — — I/O170(A) ————P9 90102

— — — I/O169(B) ————— —103

I/O78(A) I/O98(A) I/O88(A) I/O168(A) 49 45 75 63 P10 91 104

— I/O97(B) I/O87(A) I/O167(A) — — 76 64 P11 92 105

— — — I/O166(A) ————P1293106

GND GND GND GND — — 77 65 GND (2 ) 94 107

— — — I/O165(B) ————— —108

I/O77(A) I/O96(A) I/O86(A) I/O164(A) 50 46 78 66 P13 95 109

I/O76(B) I/O95(B) I/O85(A) I/O163(A) — 47 79 67 P14 96 110

— — — I/O162(A) ————R8 97111

— — — I/O161(B) ————— —112

I/O75(A) I/O94(A) I/O84(A) I/O160(A) 51 48 80 68 R9 98 113

I/O74(B) I/O93(A) I/O83(A) I/O159(A) — — 81 69 R10 99 114

— — — I/O158(A) ————R11100115

— — — I/O157(B) ————— —116

— I/O92(B) — I/O156(A) ———70R12101117

I/O73(A) I/O91(A) I/O82(A) I/O155(A) 52 49 82 71 R13 102 118

— — — I/O154(A) ————R14103119

RESET RESET RESET RESET 53 50 83 72 R15 104 120

P inout Ass ignment (Continued)

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

— — — I/O153(A) ————P15105121

I/O72(A) I/O90(A) I/O81(A) I/O152(A) 54 51 84 73 N15 106 122

— I/O89(B) I/O80(A) I/O151(A) — — 85 (3) 74 M15 107 123

— — — I/O150(B) ————— —124

———VCC————PWR

(1) 108 125

— — — I/O149(A) ————L15109126

———GND————GND

(2 ) 110 127

— I/O88(A) — I/O148(A) — — 85 (4) 75 J15 111 128

I/O71(A) I/O87(A) I/O79(A) I/O147(A) 55 52 86 76 H15 112 129

— — — I/O146(B) ————— —130

— — — I/O145(A) ————N14113131

I/O70(B) I/O86(A) I/O78(A) I/O144(A) — — 87 77 M14 114 132

I/O69(A) I/O85(A) I/O77(A) I/O143(A) 56 53 88 78 L14 115 133

— — — I/O142(B) ————— —134

Right Si de (Bott om to Top)

2-14 AT6000/LV Series

Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.

2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

Right Si de ( Bottom to Top) (Continued)

3. 85 = Pin 85 on AT6005.

4. 85 = pin 85 on AT6003 and

AT6010.

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

— — — I/O141(A) ————K14116135

I/O68(B) I/O84(B) I/O76(A) I/O140(A) — 54 89 79 J14 117 136

I/O67(A) I/O83(A) I/O75(A) I/O139(A) 57 55 90 80 H14 118 137

— — — I/O138(B) ————— —138

I/O66(B) I/O82(B) I/O74(A) I/O137(A) — — 91 81 M13 119 139

I/O65(A) I/O81(A) I/O73(A) I/O136(A) 58 56 92 82 L13 120 140

I/O64(B) I/O80(B) I/O72(A) I/O135(A) — 57 93 83 K13 121 141

— — — I/O134(B) ————— 122142

I/O63(A) I/O79(A) I/O71(A) I/O133(A) 59 58 94 84 J13 123 143

— I/O78(B) I/O70(A) I/O132(A) — — 95 85 H13 124 144

GND GND GND GND 60 59 96 86 GND(2) 125 145

VSS VSS VSS VSS 61 60 97 87 GND(2) 126 146

I/O62(A) I/O77(A) I/O69(A) I/O131(A) 62 61 98 88 K12 127 147

— — — I/O130(B) ————— 128148

— I/O76(B) — I/O129(A) ———89J12 129149

I/O61(A) I/O75(A) I/O68(A) I/O128(A) 63 62 99 90 H12 130 150

I/O60(B) I/O74(A) I/O67(A) I/O127(A) 64 63 100 91 H11 131 151

— — — I/O126(B) ————— 132152

I/O59(A) I/O73(A) I/O66(A) I/O125(A) 65 64 101 92 G12 133 153

I/O58(A) I/O72(A) I/O65(A) I/O124(A) 66 65 102 93 F12 134 154

VDD VDD VDD VDD 67 66 103 94 PWR(1) 135 155

VCC VCC VCC VCC 68 67 104 95 PWR(1) 136 156

I/O57(B) I/O71(B) I/O64(A) I/O123(A) — — 105 96 G13 137 157

— — — I/O122(B) ————— 138158

I/O56(A) I/O70(A) I/O63(A) I/O121(A) 69 68 106 97 F13 139 159

I/O55(B) I/O69(B) I/O62(A) I/O120(A) — 69 107 98 E13 140 160

— — — I/O119(A) ————D13141161

— — — I/O118(B) — — — — — 162

I/O54(A) I/O68(A) I/O61(A) I/O117(A) 70 70 108 99 C13 142 163

— I/O67(B) I/O60(A) I/O116(A) — — 109 100 G14 143 164

— — — I/O115(A) ————F14144165

GND GND GND GND — — 110 101 GND(2) 145 166

———VSS————GND

(2) 146 167

— — — I/O114(B) ————— —168

I/O53(A) I/O66(A) I/O59(A) I/O113(A) 71 71 111 102 D14 147 169

I/O52(B) I/O65(B) I/O58(A) I/O112(A) — 72 112 103 C14 148 170

— — — I/O111(A) ————B14149171

— — — I/O110(B) ————— —172

I/O51(A) I/O64(A) I/O57(A) I/O109(A) 72 73 113 104 G15 150 173

I/O50(B) I/O63(A) I/O56(A) I/O108(A) — — 114 105 F15 151 174

— — — I/O107(A) ————E15152175

— — — I/O106(B) ————— —176

— I/O62(B) — I/O105(A) ———106D15153177

I/O49(A) I/O61(A) I/O55(A) I/O104(A) 73 74 115 107 C15 154 178

— — — I/O103(A) ————B15155179

M2 M2 M2 M2 74 75 116 108 A15 156 180

P inout Ass ignment (Continued)

AT6000/LV Series

2-15

Top Side (Ri ght t o Left)

(continued)

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

M1 M1 M1 M1 75 76 117 109 D11 157 181

— — — I/O102(A) ————D10158182

I/O48(A) I/O60(A) I/O54(A) I/O101(A) 76 77 118 110 D9 159 183

— I/O59(B) — I/O100(A) ———111A14160184

— — — I/O99(B) ————— —185

———VCC————PWR

(1) 161 186

— — — I/O98(A) ————A13162187

———GND————GND

(2 ) 163 188

— I/O58(A) I/O53(A) I/O97(A) — — 119 112 A11 164 189

I/O47(A) I/O57(A) I/O52(A) I/O96(A) 77 78 120 113 A10 165 190

— — — I/O95(B) ————— —191

— — — I/O94(A) ————A9 166192

I/O46(B) I/O56(A) I/O51(A) I/O93(A) — — 121 114 B13 167 193

I/O45(A) I/O55(A) I/O50(A) I/O92(A) 78 79 122 115 B12 168 194

— — — I/O91(B) ————— —195

— — — I/O90(A) ————B11169196

I/O44(B) I/O54(B) I/O49(A) I/O89(A) — 80 123 116 B10 170 197

I/O43(A) I/O53(A) I/O48(A) I/O88(A) 79 81 124 117 B9 171 198

— — — I/O87(B) ————— —199

I/O42(B) I/O52(B) I/O47(A) I/O86(A) — — 125 118 C12 172 200

I/O41(A) I/O51(A) I/O46(A) I/O85(A) 80 82 126 119 C11 173 201

I/O40(B) I/O50(B) I/O45(A) I/O84(A) — 83 127 120 C10 174 202

— — — I/O83(B) ————— 175203

I/O39(A) I/O49(A) I/O44(A) I/O82(A) 81 84 128 121 C9 176 204

— I/O48(B) I/O43(A) I/O81(A) — — 129 122 D8 177 205

GND GND GND GND 82 85 130 123 GND (2) 178 206

I/O38(A) I/O47(A) I/O42(A) I/O80(A) 83 86 131 124 D7 179 207

— — — I/O79(B) ————— 180208

— I/O46(B) — I/O78(A) ———125D6 181209

I/O37(A) or A16 I/O45 (A) or A16 I/O41(A) or A 16 I/O77(A) or A16 84 87 132 12 6 D5 182 210

CLOCK CLOCK CLOCK CLOCK 1 88 1 127 E8 183 211

I/O36(B) or A15 I/O44 (A) or A15 I/O40(A) or A 15 I/O76(A) or A15 2 89 2 128 D4 184 21 2

— — — I/O75(B) ————— 185213

I/O35(A) or A14 I/O43 (A) or A14 I/O39(A) or A 14 I/O74(A) or A14 3 90 3 129 C8 186 21 4

———VDD————PWR

(1) 187 215

VCC VCC VCC VCC 4 91 4 130 PWR (1) 188 216

I/O34(A) or A13 I/O42 (A) or A13 I/O38(A) or A 13 I/O73(A) or A13 5 92 5 131 C5 189 21 7

I/O33(B) I/O41(B) I/O37(A) I/O72(A) — — 6 132 C4 190 218

— — — I/O71(B) ————— 191219

I/O32(A) or A12 I/O40 (A) or A12 I/O36(A) or A 12 I/O70(A) or A12 6 93 7 133 C3 192 22 0

I/O31(B) I/O39(B) I/O35(A) I/O69(A) — 94 8 134 B8 193 221

— — — I/O68(A) ————B7 194222

— — — I/O67(B) ————— —223

I/O30(A) or A11 I/O38 (A) or A11 I/O34(A) or A 11 I/O66(A) or A11 7 95 9 135 B6 195 22 4

— I/O37(B) I/O33(A) I/O65(A) — — 10 136 B5 196 225

— — — I/O64(A) ————B4 197226

GND GND GND GND — — 11 137 GND (2 ) 198 227

— — — I/O63(B) ————— —228

I/O29(A) or A10 I/O36 (A) or A10 I/O32(A) or A 10 I/O62(A) or A10 8 96 12 138 B3 199 22 9

P inout Ass ignment (Continued)

2-16 AT6000/LV Series

Top Side (Ri ght t o Left) (Continued)

Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12.

2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6.

84 100 132 144 180 208 240

AT6002 AT6003 AT6005 AT6010 PLCC VQFP PQFP TQFP CPGA PQFP PQFP

I/O28(B) I/O35(B) I/O31(A) I/O61(A) — 97 13 139 B2 200 230

— — — I/O60(A) ————A8 201231

— — — I/O59(B) ————— —232

I/O27(A) or A9 I/O34(A) or A9 I/O30 (A) o r A 9 I/O5 8(A) or A9 9 98 14 14 0 A7 20 2 233

I/O26(B) I/O33(A) I/O29(A) I/O57(A) — — 15 141 A6 203 234

— — — I/O56(A) ————A5 204235

— — — I/O55(B) ————— —236

— I/O32(B) — I/O54(A) ———142A4 205237

I/O25(A) or A8 I/O31(A) or A8 I/O28 (A) o r A 8 I/O5 3(A) or A8 10 99 16 14 3 A3 20 6 238

———I/O52(A) ————A2 207239

M0 M0 M0 M0 11 100 17 144 A1 208 240

P inout Ass ignment (Continued)

AT6000/LV Series

2-17

AC Timing Characteristics – 5V Operation

Dela ys are based on fi xed load. Loads for each t ype o f device are described in the not es. Delays ar e in nanoseconds.

Worst case: Vcc = 4.75V to 5.25V. T emperat ure = 0°C t o 70°C .

Cel l Funct ion Paramet er F rom To Load

D efi ni tion - 1 - 2 - 4 Units

Wire (4) tPD (ma x) (4) A, B, L A, B 1 0.8 1.2 1.8 n s

NAND tPD (max) A, B, L B 1 1.6 2.2 3.2 ns

XOR tPD (max) A, B , L A 1 1.8 2. 4 4.0 ns

AND tPD (max) A, B, L B 1 1.7 2. 2 3.2 ns

MUX tPD (max ) A, B A 1 1.7 2.3 4.0 ns

L A 1 2.1 3.0 4.9 ns

D-Flip-Flop (5) tsetup (min) A, B, L CLK 1.5 2.0 3 .0 ns

D-Flip-Flop (5) thold (min) CLK A, B, L 0.0 0.0 0.0 ns

D-Flip-Flop tPD (max) CLK A 1 1.5 2. 0 3.0 ns

Bus Dri ver tPD (max) A L 2 2.0 2.6 4.0 ns

Repeater tPD (m ax ) L, E E 3 1. 3 1.6 2.3 ns

L, E L 2 1. 7 2.1 3.0 ns

Co lum n Clo c k tPD (m a x ) GCL K, A, ES CLK 3 1 .8 2 .4 3.0 ns

Co lum n Re s et tPD (max) GRES, A, EN RES 3 1.8 2.4 3.0 ns

Cl ock Buffer (5) tPD (max) CLO CK PI N GCLK 1. 6 2.0 2.9 ns

R eset Buf fer (5) tPD (ma x) R ESET PIN GRES 1 .5 1 .9 2.8 ns

TTL Input (1) tPD (max) I /O A 3 1.0 1.2 1.5 ns

C MOS Input (2) tPD (max) I /O A 3 1.3 1.4 2.3 ns

F a s t Ou tp u t (3) tPD (m a x) A I/O PIN 4 3 .3 3.5 6.0 n s

S low Output (3) tPD (max) A I/O PIN 4 7.5 8. 0 12. 0 ns

Output Disable (5) tPXZ (max) L I/O PIN 4 3.1 3.3 5 .5 ns

Fast Enable (3, 5) tPZX (max) L I/O PIN 4 3.8 4.0 6.5 ns

S low Enabl e (3, 5 ) tPZX (max) L I/O PIN 4 8.2 8.5 12.5 ns

Notes:

1. TTL buffer delays are measured from a VIH

of 1.5V at the pad to the internal VIH at A.

The input buffer load is constant.

2. CMOS buffer delays are measured from a

VIH of 1/2 VCC at the pad to the internal

VIH at A. The input buffer load is constant.

3. Buffer delay is to a pad voltage of 1.5V

with one output switching.

4. Max specifications are the average of max

tPDLH and tPDHL.

5. Parameter based on characterization and

simulation; not tested in production.

6. Exact power calculation is available in an

Atmel application note.

Load Definition:

1. Load of one A or B input

2. Load of one L input

3. Constant Load

4. Tester Load of 50 pF

D evice Cell Types O utputs Icc (max)

Cell (6) Wire, XWire, Half- Adder, Flip-Flop A, B 4.5 µA/MHz

Bus (6) Wire, XWi re, Hal f-A dder , Flip-Flop, R epeater L 2.5 µA/MHz

Co lum n Clo c k (6) Column Clock Driver CL K 40 µA/MHz

= Preliminary Information

2-18 AT6000/LV Series

AC Timing Characteristics – 3.3V Operation

Dela ys are based on fi xed load. Loads for each t ype o f device are described in the not es. Delays ar e in nanoseconds.

Worst case: Vcc = 3.0V to 3.6V. Te mperat ure = 0°C t o 70°C.

Cel l Funct ion Parameter From To Load Defini tion - 4 Units

Wire (4) tPD (m a x ) (4 ) A, B, L A, B 1 1.8 ns

NAND tPD (max) A, B, L B 1 3.2 ns

XOR tPD (max) A, B, L A 1 4.0 ns

AND tPD (max) A, B, L B 1 3.2 ns

MUX tPD (m ax ) A, B A 1 4.0 ns

LA 14.9ns

D-Flip-Flop (5) tsetup (m in) A, B, L CLK 3.0 ns

D-Flip-Flop (5) thold (min) CLK A, B, L 0.0 ns

D-Flip-Flop tPD (max) CLK A 1 3.0 ns

Bus Dri ver t PD (max) A L 2 4. 0 ns

Repeater tPD (max ) L, E E 3 2.3 ns

L, E L 2 3. 0 ns

Co lum n Clo c k tPD (max) GCLK, A, ES CLK 3 3.0 ns

Co lum n Re s et tPD (max) GRES, A, EN RES 3 3.0 ns

Cl ock Buffer (5) tPD (m ax) CLO CK PI N G CLK 4 2. 9 ns

R eset Buf fer (5) tPD (m ax) RESET PIN GRES 5 2. 8 ns

TTL Input (1) tPD (max) I/ O A 3 1. 5 ns

C MOS Input (2) tPD (m ax) I/O A 3 2. 3 ns

F a s t Ou tp u t (3) tPD (max) A I/O PIN 6 6.0 ns

S low Output (3) tPD (max) A I/O PIN 6 12.0 ns

Output Disable (5) tPXZ (ma x ) L I/O PIN 6 5 .5 n s

Fast Enable (3, 5) tPZX (m a x ) L I/O PIN 6 6 .5 ns

S low Enabl e (3, 5 ) tPZX (m ax) L I/ O PIN 6 12.5 ns

D evice Cell Types O utputs Icc (max)

Cell (6) Wire, XWire, Half- Adder, Flip-Flop A, B 2.3 µA/MHz

Bus (6) Wire, XWi re, Hal f-A dder , Flip-Flop, R epeater L 1.3 µA/MHz

Co lum n Clo c k (6) Column Clock Driver CL K 20 µA/MHz

Notes:

1. TTL buffer delays are measured from a VIH of 1.5V at the

pad to the internal VIH at A. The input buffer load is constant.

2. CMOS buffer delays are measured from a VIH of 1/2 VCC at

the pad to the internal VIH at A. The input buffer load is con-

stant.

3. Buffer delay is to a pad voltage of 1.5V with one output

switching.

4. Max specifications are the average of max tPDLH and tPDHL.

5. Parameter based on characterization and simulation; not

tested in production.

6. Exact power calculation is available in an Atmel application

note.

Load Definition:

1. Load of one A or B input

2. Load of one L input

3. Constant Load

4. Load of 28 Clock Columns

5. Load of 28 Reset Columns

6. Tester Load of 50 pF

AT6000/LV Series

2-19

*NOTICE: Stresses beyond those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions beyond those

listed under Operating Conditions is not implied. Exposure

to Absolute Maximum Ratings conditions for extended peri-

ods of time may affect device reliability.

Absol u te Maximum Ratin gs*

S upply Voltage (VCC)... ...... ................-0.5V to +7 .0V

D C Input Voltage (V IN)...............-0.5V to VCC + 0.5V

DC O utput Voltage (VON)...........-0.5V to VCC + 0. 5 V

S torage Temp erature Range

(TSTG ).. .... ... ............... ............. .. .....-65°C to +150°C

Pow er Di ssipati on (PD)....... ..... ............... ...1500 mW

Lead Temperat ure (T L)

(Sol dering, 10 sec.).... ............. ............... ...... ....260°C

ESD (RZAP=1.5K, CZAP=100 pF).... ....... ...... ...2000V

DC and AC Op erating Range – 5V Operation

AT6002-2/4

AT6003-2/4

AT6005-2/4

AT6010-2/4

Commercial

AT6002-2/4

AT6003-2/4

AT6005-2/4

AT6010-2/4

Industrial

AT6002-4

AT6003-4

AT6005-4

AT6010-4

Military

Operat ing Temperatur e (Case) 0°C - 70°C -40°C - 85°C - 55°C - 125°C

VCC Power Suppl y 5V ± 5% 5V ± 10% 5V ± 10%

Input Vol tage Level

(TTL) High (VIHT)2.0V - V

CC 2.0V - V CC 2.0V - VCC

Low (VILT) 0V - 0. 8V 0V - 0.8V 0V - 0.8V

Input Vol tage Level

(CMOS) High (VIHC) 70% - 100% V CC 70% - 100% V CC 70% - 100% VCC

Low (VILC) 0 - 30% V CC 0 - 30% VCC 0 - 30% VCC

Input Signal Transi tion Time ( T IN) 50 ns (max) 5 0 ns (max) 50 ns (max)

DC and AC Operating Range – 3.3V Operation

AT 6002-4, AT6003-4

AT 6005-4, AT6010-4

Commercial

Operat ing Temperatur e (Case) 0°C - 70°C

VCC Power Suppl y 3.3V ± 10%

Input Vol tage Level

(TTL) High (VIHT)2.0V - V

Low (VILT)0V - 0.8V

Input Vol tage Level

(CMOS) High (VIHC) 70% - 100% V CC

Low (VILC)0 - 30% V

Input Signal Transi tion Time ( T IN) 5 0 ns (m ax)

2-20 AT6000/LV Series

DC Characterist ics – 5V Operation

Symbol Parameter Conditions Min Max Units

VIH High- Level Input Voltage Co mmerci al CMOS 70% VCC VCC V

TTL 2.0 VCC V

VIL Low- Level Input Volt age Com mercial CMOS 0 30% VCC V

TTL 0 0.8 V

VOH High- Level Out put

Voltage Commercial IOH = -4 mA, V CC mi n 3.9 V

IOH = -16 mA, V CC mi n 3.0 V

VOL Low- Level Out put V oltage Com mercial IOL = 4 mA, V CC mi n 0.4 V

IOL = 16 mA , V CC min 0.5 V

IOZH Hi gh- Level Tri state

Out put Leakage Cur rent VO = VCC (ma x) 1 0 µA

IOZL Low-Level Tri stat e Wi thout Pull-Up, VO = VSS -10 µA

Out put Leakage Cur rent With Pull -Up, VO = V SS -500 µA

IIH High- Level Input C urrent VIN = VCC (max ) 10 µA

IIL Low- Level Input Cur rent Without Pull-Up, VIN = VSS -10 µA

With Pull-Up, VIN = VSS -500 µA

ICC Power Consumption Without Internal O scillator (Standby) 500 µA

CIN Input Capacitance All Pins 10 pF

AT6000/LV Series

2-21

DC Characterist ics – 3.3V Operation

Symbol Parameter Conditions Min Max Units

VIH High- Level Input Voltage Co mmerci al CMOS 70% VCC VCC V

TTL 2.0 VCC V

VIL Low- Level Input Volt age Com mercial CMOS 0 30% VCC V

TTL 0 0.8 V

VOH High- Level Out put

Voltage Commercial IOH = -2 mA, V CC mi n 2.4 V

IOH = -6 mA, V CC mi n 2.0 V

VOL Low- Level Out put V oltage Com mercial IOL = +2 mA, V CC min 0.4 V

IOL = +6 m A, VCC mi n 0.5 V

IOZH Hi gh- Level Tri state

Out put Leakage Cur rent VO = VCC (ma x) 1 0 µA

IOZL Low-Level Tri stat e Wi thout Pull-Up, VO = VSS -10 µA

Out put Leakage Cur rent With Pull -Up, VO = V SS -250 µA

IIH High- Level Input C urrent VIN = VCC (max ) 10 µA

IIL Low- Level Input Cur rent Without Pull-Up, VIN = VSS -10 µA

With Pull-Up, VIN = VSS -250 µA

ICC Power Consumption Without Internal O scillator (Standby) 200 µA

CIN (1) I nput Capaci tance All Pins 10 pF

Note: 1. Parameter based on characterization and simulation; it is not tested in production.

2-22 AT6000/LV Series

Usable

Gates Speed

Grade (ns) Orde ring Code P ackage Operat io n R ange

6,000 2 AT6002-2AC 100A 5V Commercial

AT6002A-2AC 144A (0°C to 70°C)

AT6002-2JC 84J

AT6002-2QC 132Q

AT6002-2AI 100A 5V Industr ial

AT6002A-2AI 144A (-40°C to 85°C )

AT6002-2JI 84J

AT6002-2QI 132Q

6,000 4 AT6002-4AC 100A 5V Commercial

AT6002A-4AC 144A (0°C to 70°C)

AT6002-4JC 84J

AT6002-4QC 132Q

AT6002LV-4AC 100A 3.3V Com merci al

AT6002ALV-4AC 144A (0°C to 7 0°C)

AT6002LV-4JC 84J

AT6002LV-4QC 132Q

AT6002-4AI 100A 5V Industr ial

AT6002A-4AI 144A (-40°C to 85°C )

AT6002-4JI 84J

AT6002-4QI 132Q

Ordering I nform at ion

De vic e Timing: During Operation

AT6000/LV Series

2-23

Usable

Gates Speed

Grade (ns) Orde ring Code P ackage Operat io n R ange

9,000 2 AT6003-2AC 100A 5V Commercial

AT6003A-2AC 144A (0°C to 70°C)

AT6003-2JC 84J

AT6003-2QC 132Q

AT6003-2AI 100A Industrial

AT6003A-2AI 144A (-40°C to 85°C )

AT6003-2JI 84J

AT6003-2QI 132Q

9,000 4 AT6003-4AC 100A 5V Commercial

AT6003A-4AC 144A (0°C to 70°C)

AT6003-4JC 84J

AT6003-4QC 132Q

AT6003LV-4AC 100A 3.3V Com merci al

AT6003ALV-4AC 144A (0°C to 7 0°C)

AT6003LV-4JC 84J

AT6003LV-4QC 132Q

AT6003-4AI 100A 5V Industr ial

AT6003A-4AI 144A (-40°C to 85°C )

AT6003-4JI 84J

AT6003-4QI 132Q

Usable

Gates Speed

Grade (ns) Orde ring Code P ackage Operat io n R ange

15,000 2 AT6005-2AC 100A 5V Commercial

AT6005A-2AC 144A (0°C to 70°C)

AT6005-2JC 84J

AT6005-2QC 132Q

AT6005A-2QC 208Q

AT6005-2AI 100A Industrial

AT6005A-2AI 144A (-40°C to 85°C )

AT6005-2JI 84J

AT6005-2QI 132Q

AT6005A-2QI 208Q

15,000 4 AT6005-4AC 100A 5V Commercial

AT6005A-4AC 144A (0°C to 70°C)

AT6005-4JC 84J

AT6005-4QC 132Q

AT6005A-4QC 208Q

AT6005LV-4AC 100A 3.3V Com merci al

AT6005ALV-4AC 144A (0°C to 7 0°C)

AT6005LV-4JC 84J

AT6005LV-4QC 132Q

AT6005ALV-4QC 208Q

Orde r ing Information

2-24 AT6000/LV Series

P ackage Type

84J 84 Lead, Plastic J-Leaded Chip Carrier (PLCC)

100A 100 Lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP)

132Q 132 Lead, Bumpered Plastic Gull Wing Quad Flat Package (BQFP)

144A 144 Lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP)

208Q 208 Lead, Plastic Gull-Wing Quad Flat Package (PQFP)

240Q 240 Lead, Plastic Gull-Wing Quad Flat Package (PQFP)

Ordering Infor m ation

Usable

Gates Speed

Grade (ns) Orde ring Code P ackage Operat io n R ange

15,000 4 AT6005-4AI 100A 5V Indust r ial

AT6005A-4AI 144A (-40°C to 85°C )

AT6005-4JI 84J

AT6005-4QI 132Q

AT6005A-4QI 208Q

30,000 2 AT6010-2JC 84J 5V Commercial

AT6010A-2AC 144A (0°C to 70°C)

AT6010-2QC 132Q

AT6010A-2QC 208Q

AT6010H-2QC 240Q

AT6010-2JI 84J Industrial

AT6010A-2AI 144A (-40°C to 85°C )

AT6010-2QI 132Q

AT6010-2QI 208Q

AT6010-2QI 240Q

30,000 4 AT6010A-4AC 144A 5V Commercial

AT6010-4QC 132Q (0°C to 70° C)

AT6010-4JC 84J

AT6010A-4QC 208Q

AT6010H-4QC 240Q

AT6010ALV-4AC 144A 3.3V Com merci al

AT6010LV-4QC 132Q (0°C to 70 °C)

AT6010LV-4JC 84J

AT6010ALV-4QC 208Q

AT6010HLV-4QC 240Q

AT6010A-4AI 144A 5V Industr ial

AT6010-4QI 132Q (-40°C t o 85°C)

AT6010-4JI 84J

AT6010A-4QI 208Q

AT6010H-4QI 240Q

Ordering Informat io n

AT6000/LV Series

2-25