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© 1998

MOS INTEGRATED CIRCUIT

µ

µµ

µ

PD16750

384-OUTPUT TFT-LCD SOURCE DRIVER

(COMPATIBLE WITH 256-GRAY SCALES)

DATA SHEET

Document No. S13719EJ4V0DS00 (4th edition)

Date Published April 2000 NS CP (K)

Printed in Japan

The mar k •

••

• shows major revised points.

DESCRIPTION

The

µ

PD16750 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is

based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216

colors by output of 256 values

γ

-corrected by an internal D/A converter and 8-by-2 external power modules.

Because the output dynamic range is as large as VDD2 − 0.2 V to VSS2 + 0.2 V, level inversion operation of the LCD’s

common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and

column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter

circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.

Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to XGA-standard TFT-

LCD panels and SXGA TFT-LCD panels. This driver is applicable to SXGA TFT-LCD panels by input display signal 2

systems (Clock divide).

FEATURES

•CMOS level input

•384 outputs

•Input of 8 bits (gradation data) by 6 dots

•Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter

•Output dynamic range: VDD2 – 0.2 V to VSS2 + 0.2 V

•High-speed data transfer: fCLK = 40 MHz (internal data transfer speed when operating at 3.0 V)

•Apply for dot-line inversion, n-line inversion and column line inversion

•Output voltage polarity inversion function (POL)

•Display data inversion function (POL21/22)

•Logic power supply voltage (VDD1) : 3.3 V ± 0.3 V

•Driver power supply voltage (VDD2) : 9.0 V ± 0.5 V

•Low power control function (LPC)

ORDERING INFORMATION

Part Number Package

µ

PD16750N-xxx TCP (TAB package)

Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales

representatives.

Data Sheet S13719EJ4V0DS00

2

µ

µµ

µ

PD16750

1. BLOCK DIAGRAM

64-bit bidirectional shift register

C

1

C

2

C

63

C

64

Data register

Latch

Level shifter

D/A converter

Voltage follower output

S

1

S

2

S

3

S

384

V

0

- V

15

POL

D

00

- D

07

D

10

- D

17

D

20

- D

27

STHR

R,/L

CLK

STB

STHL

V

DD1

V

SS1

V

DD2

V

SS2

POL21

POL22

D

30

- D

37

D

40

- D

47

D

50

- D

57

LPC

Remark /xxx indicates active low signal.

2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER

V

0

V

7

V

8

V

15

··········

8

8

S

1

S

2

S

383

S

384

8-bit D/A converter

Multi-

plexer

POL

Data Sheet S13719EJ4V0DS00 3

µ

µµ

µ

PD16750

3. PIN CONFIGURATION (

µ

µµ

µ

PD16750N-xxx)

S384

S383

VSS2 S382

VDD2

V14

V12

V10

V8

V6

V4

V2

V0

R,/L

D50

D51

D52

D53

D54

D55

D56

D57

D40

D41

D42

D43

D44

D45

D46

D47

D30

D31

D32

D33

D34

D35

D36

D37

POL21

POL22

POL

STB

STHL

VDD1

CLK

VSS1

LPC

STHR

D20

D21

D22

D23

D24

D25

D26

D27

D10

D11

D12

D13

D14

D15

D16

D17

D00

D01

D02

D03

D04

D05

D06

D07

V1

V3

V5

V7

V9

V11 S3

V13 S2

V15 S1

VDD2

VSS2

Copper Foi l

Surface

Remark This figure does not specify the TCP package.

•

•

Data Sheet S13719EJ4V0DS00

4

µ

µµ

µ

PD16750

4. PIN FUNCTIONS

Pin Symbol Pin Nam e Descript i on

S1 to S384 Driver output The D/A convert ed 256-gray-scale analog vol tage is out put .

D00 to D07

D10 to D17

D20 to D27

D30 to D37

D40 to D47

D50 to D57

Display dat a i nput The display dat a i s input with a width of 48 bi ts, vi z. , the gray scale data (8 bit s) by 6 dots (2

pixels).

DX0: LSB, DX7: MSB

R,/L Shift di rection c ontrol

input

These refer to the start pulse input/output pi ns when driver ICs are connec t ed i n cascade.

The shift di rections of the shi f t regist ers are as fol l ows.

R,/L = H : STHR input, S1 → S384, STHL output

R,/L = L : STHL input, S384 → S1, STHR output

STHR Right shift start pul se

input/output

R,/L = H : Becomes the start pul se input pin.

R,/L = L : Becomes the start pul se output pi n.

STHL Left shift start pulse

input/output

R,/L = H : Becomes the start pul se output pi n.

R,/L = L : Becomes the start pul se input pin.

CLK Shift clock i nput Refers to the shif t regist er’ s shift clock i nput . The display data is incorporated int o t he data

register at the rising edge of the 64th clock af ter the st art pulse input, the start pulse output

reaches t he hi gh l evel , thus becoming t he start pulse of the next-level dri ver.

STB Latch input The contents of the data regist er are t ransferred to t he l atch ci rcuit at t he ri sing edge. A nd,

at the fal l i ng edge, the gray scale voltage i s supplied t o the driver. It is nec essary to ensure

input of one pul s e per hori zontal period.

POL Polarit y i nput POL = L : The S2n–1 output uses V0 to V7 as the referenc e supply. The S 2n out put uses V 8

to V15 as the reference supply.

POL = H : The S2n–1 output uses V8 to V15 as the reference suppl y. The S2n output uses V0

to V7 as the reference s uppl y.

S2n-1 indicates the odd out put: and S2n indi cates the even output. Input of t he P O L signal is

allowed the setup t i me(tPOL-STB) with respect t o S T B’s rising edge.

POL21

POL22

Data invers i on Data inversi on can invert when dis pl ay data is l oaded.

POL21/22 = H : Data inversion l oads display data after i nvert i ng i t.

POL21/22 = L : Data inversion does not invert i nput data.

POL21: D00 to D07, D10 to D17, D20 to D27

POL22: D30 to D37, D40 to D47, D50 to D57

LPC Low power control

input

The output buffer constant current source is bl ocked, reducing current c onsumption. I n l ower

power mode (LPC = L: DC-level i nput possi bl e), the ordinary st atic c urrent consumption c an

be reduced by approx. 33 %.

V0 to V15

γ

-correct ed power

supplies

Input the

γ

-correct ed power suppli es from outside by us i ng operat i onal amplifier. Make s ure

to m ai nt ai n the following relat i onships. Duri ng t he gray scale voltage output, be sure to keep

the gray sc al e l evel power suppl y at a const ant level.

VDD2 − 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 V DD2

0.5 VDD2 − 0.3 V > V 8 > V9 > V10 > V 11 > V 12 > V 13 > V 14 > V 15 > V SS2 + 0.2 V

VDD1 Logic power supply 3.3 V ± 0.3 V

VDD2 Driver power supply 9.0 V ± 0. 5 V

VSS1 Logic ground Grounding

VSS2 Driver ground Grounding

Data Sheet S13719EJ4V0DS00 5

µ

µµ

µ

PD16750

Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V15 in that order.

Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V15 is

possible.).

2. To stabilize the supply voltage, please be sure to insert a 0.1-

µ

µµ

µ

F bypass capacitor between

VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion

of a bypass capacitor of about 0.01

µ

µµ

µ

F is also advised between the

γ

γγ

γ

-corrected power supply

terminals (V0, V1, V2,....., V15) and VSS2.

Data Sheet S13719EJ4V0DS00

6

µ

µµ

µ

PD16750

5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE

This product incorporates a 8-bit D/A converter whose odd output pins and even output pins output respectively gray

scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A

converter consists of ladder resistors.

Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2,

common electrode potential VCOM, and

γ

-corrected voltages V0 to V15 and the input data. Be sure to maintain the

voltage relationships of VDD2 − 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2,

0.5 VDD2 − 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V

Figures 5−2 and 5−3 show the relationship between the input data and the output voltage. This driver IC is designed

for only single-sided mounting. Therefore, please do not use it for

γ

-corrected power supply level inversion in

double-sided mounting.

Figure 5–1. Relationship between Input Data and

γ

γγ

γ

-corrected Power Supplies

V

1

V

2

V

3

V

4

V

SS2

00 20 40 80 C0 E0 FF

V

0

V

10

V

7

V

11

V

DD2

64

32

32

V

5

V

6

32

32

E0

V

12

V

15

64

64

32

32

32

32

FE

V

13

V

14

Split interval

64

0.3 V V

8

0.5 V

DD2

0.2 V

V

9

0.2 V

Input data (HEX)

Data Sheet S13719EJ4V0DS00 7

µ

µµ

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (1/4)

VDD2 – 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

00H00000000 V

0'V0r0 400.0

01H00000001 V

1'V1+(V0-V1) X 3465.0 / 3865 r1 362.5

02H00000010 V2'V1+(V0-V1) X 3102.5 / 3865 r2 325.0

03H00000011 V3'V1+(V0-V1) X 2777.5 / 3865 r3 287.5

04H00000100 V4'V1+(V0-V1) X 2490.0 / 3865 r4 250.0

05H00000101 V5'V1+(V0-V1) X 2240.0 / 3865 r5 222.5

06H00000110 V6'V1+(V0-V1) X 2017.5 / 3865 r6 195.0

07H00000111 V7'V1+(V0-V1) X 1822.5 / 3865 r7 170.0

08H00001000 V8'V1+(V0-V1) X 1652.5 / 3865 r8 145.0

09H00001001 V9'V1+(V0-V1) X 1507.5 / 3865 r9 120.0

0AH00001010V10'V1+(V0-V1) X 1387.5 / 3865 r10 120.0

0BH00001011V11'V1+(V0-V1) X 1267.5 / 3865 r11 120.0

0CH00001100V12'V1+(V0-V1) X 1147.5 / 3865 r12 95.0

0DH00001101V13'V1+(V0-V1) X 1052.5 / 3865 r13 95.0

0EH00001110V14'V1+(V0-V1) X 957.5 / 3865 r14 95.0

0FH00001111V15'V1+(V0-V1) X 862.5 / 3865 r15 75.0

10H00010000V16'V1+(V0-V1) X 787.5 / 3865 r16 75.0

11H00010001V17'V1+(V0-V1) X 712.5 / 3865 r17 75.0

12H00010010V18'V1+(V0-V1) X 637.5 / 3865 r18 62.5

13H00010011V19'V1+(V0-V1) X 575.0 / 3865 r19 62.5

14H00010100V20'V1+(V0-V1) X 512.5 / 3865 r20 62.5

15H00010101V21'V1+(V0-V1) X 450.0 / 3865 r21 50.0

16H00010110V22'V1+(V0-V1) X 400.0 / 3865 r22 50.0

17H00010111V23'V1+(V0-V1) X 350.0 / 3865 r23 50.0

18H00011000V24'V1+(V0-V1) X 300.0 / 3865 r24 37.5

19H00011001V25'V1+(V0-V1) X 262.5 / 3865 r25 37.5

1AH00011010V26'V1+(V0-V1) X 225.0 / 3865 r26 37.5

1BH00011011V27'V1+(V0-V1) X 187.5 / 3865 r27 37.5

1CH00011100V28'V1+(V0-V1) X 150.0 / 3865 r28 37.5

1DH00011101V29'V1+(V0-V1) X 112.5 / 3865 r29 37.5

1EH00011110V30'V1+(V0-V1) X 75.0 / 3865 r30 37.5

1FH00011111V31'V1+(V0-V1) X 37.5 / 3865 r31 37.5

20H00100000V32'V1r32 35.0

21H00100001V33'V2+(V1-V2) X 965.0 / 1000 r33 35.0

22H00100010V34'V2+(V1-V2) X 930.0 / 1000 r34 35.0

23H00100011V35'V2+(V1-V2) X 895.0 / 1000 r35 35.0

24H00100100V36'V2+(V1-V2) X 860.0 / 1000 r36 35.0

25H00100101V37'V2+(V1-V2) X 825.0 / 1000 r37 35.0

26H00100110V38'V2+(V1-V2) X 790.0 / 1000 r38 35.0

27H00100111V39'V2+(V1-V2) X 755.0 / 1000 r39 35.0

28H00101000V40'V2+(V1-V2) X 720.0 / 1000 r40 32.5

29H00101001V41'V2+(V1-V2) X 687.5 / 1000 r41 32.5

2AH00101010V42'V2+(V1-V2) X 655.0 / 1000 r42 32.5

2BH00101011V43'V2+(V1-V2) X 622.5 / 1000 r43 32.5

2CH00101100V44'V2+(V1-V2) X 590.0 / 1000 r44 32.5

2DH00101101V45'V2+(V1-V2) X 557.5 / 1000 r45 32.5

2EH00101110V46'V2+(V1-V2) X 525.0 / 1000 r46 32.5

2FH00101111V47'V2+(V1-V2) X 492.5 / 1000 r47 32.5

30H00110000V48'V2+(V1-V2) X 460.0 / 1000 r48 30.0

31H00110001V49'V2+(V1-V2) X 430.0 / 1000 r49 30.0

32H00110010V50'V2+(V1-V2) X 400.0 / 1000 r50 30.0

33H00110011V51'V2+(V1-V2) X 370.0 / 1000 r51 30.0

34H00110100V52'V2+(V1-V2) X 340.0 / 1000 r52 30.0

35H00110101V53'V2+(V1-V2) X 310.0 / 1000 r53 30.0

36H00110110V54'V2+(V1-V2) X 280.0 / 1000 r54 30.0

37H00110111V55'V2+(V1-V2) X 250.0 / 1000 r55 30.0

38H00111000V56'V2+(V1-V2) X 220.0 / 1000 r56 27.5

39H00111001V57'V2+(V1-V2) X 192.5 / 1000 r57 27.5

3AH00111010V58'V2+(V1-V2) X 165.0 / 1000 r58 27.5

3BH00111011V59'V2+(V1-V2) X 137.5 / 1000 r59 27.5

3CH00111100V60'V2+(V1-V2) X 110.0 / 1000 r60 27.5

3DH00111101V61'V2+(V1-V2) X 82.5 / 1000 r61 27.5

3EH00111110V62'V2+(V1-V2) X 55.0 / 1000 r62 27.5

3FH00111111V63'V2+(V1-V2) X 27.5 / 1000 r63 27.5

Caution There is no connection between V7 and V8 in the chip.

V6

V7V255’

V1

V0’

V1’

V2’

V3’

V31’

V32’

V33’

V223’

V224’

V225’

V252’

V253’

V254’

V0r0

r1

r2

r3

r30

r31

r32

r33

r222

r223

V5r224

r225

r251

r252

r253

r254

Data Sheet S13719EJ4V0DS00

8

µ

µµ

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (2/4)

VDD2 – 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

40H01000000V64'V

2r64 25.0

41H01000001V65'V

3+(V2-V3) X 1575 / 1600 r65 25.0

42H01000010V66'V

3+(V2-V3) X 1550 / 1600 r66 25.0

43H01000011V67'V

3+(V2-V3) X 1525 / 1600 r67 25.0

44H01000100V68'V

3+(V2-V3) X 1500 / 1600 r68 25.0

45H01000101V69'V

3+(V2-V3) X 1475 / 1600 r69 25.0

46H01000110V70'V

3+(V2-V3) X 1450 / 1600 r70 25.0

47H01000111V71'V

3+(V2-V3) X 1425 / 1600 r71 25.0

48H01001000V72'V

3+(V2-V3) X 1400 / 1600 r72 25.0

49H01001001V73'V

3+(V2-V3) X 1375 / 1600 r73 25.0

4AH01001010V74'V

3+(V2-V3) X 1350 / 1600 r74 25.0

4BH01001011V75'V

3+(V2-V3) X 1325 / 1600 r75 25.0

4CH01001100V76'V

3+(V2-V3) X 1300 / 1600 r76 25.0

4DH01001101V77'V

3+(V2-V3) X 1275 / 1600 r77 25.0

4EH01001110V78'V

3+(V2-V3) X 1250 / 1600 r78 25.0

4FH01001111V79'V

3+(V2-V3) X 1225 / 1600 r79 25.0

50H01010000V80'V

3+(V2-V3) X 1200 / 1600 r80 25.0

51H01010001V81'V

3+(V2-V3) X 1175 / 1600 r81 25.0

52H01010010V82'V

3+(V2-V3) X 1150 / 1600 r82 25.0

53H01010011V83'V

3+(V2-V3) X 1125 / 1600 r83 25.0

54H01010100V84'V

3+(V2-V3) X 1100 / 1600 r84 25.0

55H01010101V85'V

3+(V2-V3) X 1075 / 1600 r85 25.0

56H01010110V86'V

3+(V2-V3) X 1050 / 1600 r86 25.0

57H01010111V87'V

3+(V2-V3) X 1025 / 1600 r87 25.0

58H01011000V88'V

3+(V2-V3) X 1000 / 1600 r88 25.0

59H01011001V89'V

3+(V2-V3) X 975 / 1600 r89 25.0

5AH01011010V90'V

3+(V2-V3) X 950 / 1600 r90 25.0

5BH01011011V91'V

3+(V2-V3) X 925 / 1600 r91 25.0

5CH01011100V92'V

3+(V2-V3) X 900 / 1600 r92 25.0

5DH01011101V93'V

3+(V2-V3) X 875 / 1600 r93 25.0

5EH01011110V94'V

3+(V2-V3) X 850 / 1600 r94 25.0

5FH01011111V95'V

3+(V2-V3) X 825 / 1600 r95 25.0

60H01100000V96'V

3+(V2-V3) X 800 / 1600 r96 25.0

61H01100001V97'V

3+(V2-V3) X 775 / 1600 r97 25.0

62H01100010V98'V

3+(V2-V3) X 750 / 1600 r98 25.0

63H01100011V99'V

3+(V2-V3) X 725 / 1600 r99 25.0

64H01100100V100'V

3+(V2-V3) X 700 / 1600 r100 25.0

65H01100101V101'V

3+(V2-V3) X 675 / 1600 r101 25.0

66H01100110V102'V

3+(V2-V3) X 650 / 1600 r102 25.0

67H01100111V103'V

3+(V2-V3) X 625 / 1600 r103 25.0

68H01101000V104'V

3+(V2-V3) X 600 / 1600 r104 25.0

69H01101001V105'V

3+(V2-V3) X 575 / 1600 r105 25.0

6AH01101010V106'V

3+(V2-V3) X 550 / 1600 r106 25.0

6BH01101011V107'V

3+(V2-V3) X 525 / 1600 r107 25.0

6CH01101100V108'V

3+(V2-V3) X 500 / 1600 r108 25.0

6DH01101101V109'V

3+(V2-V3) X 475 / 1600 r109 25.0

6EH01101110V110'V

3+(V2-V3) X 450 / 1600 r110 25.0

6FH01101111V111'V

3+(V2-V3) X 425 / 1600 r111 25.0

70H01110000V112'V

3+(V2-V3) X 400 / 1600 r112 25.0

71H01110001V113'V

3+(V2-V3) X 375 / 1600 r113 25.0

72H01110010V114'V

3+(V2-V3) X 350 / 1600 r114 25.0

73H01110011V115'V

3+(V2-V3) X 325 / 1600 r115 25.0

74H01110100V116'V

3+(V2-V3) X 300 / 1600 r116 25.0

75H01110101V117'V

3+(V2-V3) X 275 / 1600 r117 25.0

76H01110110V118'V

3+(V2-V3) X 250 / 1600 r118 25.0

77H01110111V119'V

3+(V2-V3) X 225 / 1600 r119 25.0

78H01111000V120'V

3+(V2-V3) X 200 / 1600 r120 25.0

79H01111001V121'V

3+(V2-V3) X 175 / 1600 r121 25.0

7AH01111010V122'V

3+(V2-V3) X 150 / 1600 r122 25.0

7BH01111011V123'V

3+(V2-V3) X 125 / 1600 r123 25.0

7CH01111100V124'V

3+(V2-V3) X 100 / 1600 r124 25.0

7DH01111101V125'V

3+(V2-V3) X 75 / 1600 r125 25.0

7EH01111110V126'V

3+(V2-V3) X 50 / 1600 r126 25.0

7FH01111111V127'V

3+(V2-V3) X 25 / 1600 r127 25.0

Caution There is no connection between V7 and V8 in the chip.

V6

V7V255’

V1

V0’

V1’

V2’

V3’

V31’

V32’

V33’

V223’

V224’

V225’

V252’

V253’

V254’

V0r0

r1

r2

r3

r30

r31

r32

r33

r222

r223

V5r224

r225

r251

r252

r253

r254

Data Sheet S13719EJ4V0DS00 9

µ

µµ

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (3/4)

VDD2 – 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

80H10000000V128'V

3r128 25.0

81H10000001V129'V

4+(V3-V4) X 1875.0 / 1900.0 r129 25.0

82H10000010V130'V

4+(V3-V4) X 1850.0 / 1900.0 r130 25.0

83H10000011V131'V

4+(V3-V4) X 1825.0 / 1900.0 r131 25.0

84H10000100V132'V

4+(V3-V4) X 1800.0 / 1900.0 r132 25.0

85H10000101V133'V

4+(V3-V4) X 1775.0 / 1900.0 r133 25.0

86H10000110V134'V

4+(V3-V4) X 1750.0 / 1900.0 r134 25.0

87H10000111V135'V

4+(V3-V4) X 1725.0 / 1900.0 r135 25.0

88H10001000V136'V

4+(V3-V4) X 1700.0 / 1900.0 r136 25.0

89H10001001V137'V

4+(V3-V4) X 1675.0 / 1900.0 r137 25.0

8AH10001010V138'V

4+(V3-V4) X 1650.0 / 1900.0 r138 25.0

8BH10001011V139'V

4+(V3-V4) X 1625.0 / 1900.0 r139 25.0

8CH10001100V140'V

4+(V3-V4) X 1600.0 / 1900.0 r140 25.0

8DH10001101V141'V

4+(V3-V4) X 1575.0 / 1900.0 r141 25.0

8EH10001110V142'V

4+(V3-V4) X 1550.0 / 1900.0 r142 25.0

8FH10001111V143'V

4+(V3-V4) X 1525.0 / 1900.0 r143 25.0

90H10010000V144'V

4+(V3-V4) X 1500.0 / 1900.0 r144 25.0

91H10010001V145'V

4+(V3-V4) X 1475.0 / 1900.0 r145 25.0

92H10010010V146'V

4+(V3-V4) X 1450.0 / 1900.0 r146 25.0

93H10010011V147'V

4+(V3-V4) X 1425.0 / 1900.0 r147 25.0

94H10010100V148'V

4+(V3-V4) X 1400.0 / 1900.0 r148 25.0

95H10010101V149'V

4+(V3-V4) X 1375.0 / 1900.0 r149 25.0

96H10010110V150'V

4+(V3-V4) X 1350.0 / 1900.0 r150 25.0

97H10010111V151'V

4+(V3-V4) X 1325.0 / 1900.0 r151 25.0

98H10011000V152'V

4+(V3-V4) X 1300.0 / 1900.0 r152 27.5

99H10011001V153'V

4+(V3-V4) X 1272.5 / 1900.0 r153 27.5

9AH10011010V154'V

4+(V3-V4) X 1245.0 / 1900.0 r154 27.5

9BH10011011V155'V

4+(V3-V4) X 1217.5 / 1900.0 r155 27.5

9CH10011100V156'V

4+(V3-V4) X 1190.0 / 1900.0 r156 27.5

9DH10011101V157'V

4+(V3-V4) X 1162.5 / 1900.0 r157 27.5

9EH10011110V158'V

4+(V3-V4) X 1135.0 / 1900.0 r158 27.5

9FH10011111V159'V

4+(V3-V4) X 1107.5 / 1900.0 r159 27.5

A0H10100000V160'V

4+(V3-V4) X 1080.0 1900.0 r160 30.0

A1H10100001V161'V

4+(V3-V4) X 1050.0 / 1900.0 r161 30.0

A2H10100010V162'V

4+(V3-V4) X 1020.0 / 1900.0 r162 30.0

A3H10100011V163'V

4+(V3-V4) X 990.0 / 1900.0 r163 30.0

A4H10100100V164'V

4+(V3-V4) X 960.0 / 1900.0 r164 30.0

A5H10100101V165'V

4+(V3-V4) X 930.0 / 1900.0 r165 30.0

A6H10100110V166'V

4+(V3-V4) X 900.0 / 1900.0 r166 30.0

A7H10100111V167'V

4+(V3-V4) X 870.0 / 1900.0 r167 30.0

A8H10101000V168'V

4+(V3-V4) X 840.0 / 1900.0 r168 32.5

A9H10101001V169'V

4+(V3-V4) X 807.5 / 1900.0 r169 32.5

AAH10101010V170'V

4+(V3-V4) X 775.0 / 1900.0 r170 32.5

ABH10101011V171'V

4+(V3-V4) X 742.5 / 1900.0 r171 32.5

ACH10101100V172'V

4+(V3-V4) X 710.0 / 1900.0 r172 32.5

ADH10101101V173'V

4+(V3-V4) X 677.5 / 1900.0 r173 32.5

AEH10101110V174'V

4+(V3-V4) X 645.0 / 1900.0 r174 32.5

AFH10101111V175'V

4+(V3-V4) X 612.5 / 1900.0 r175 32.5

B0H10110000V176'V

4+(V3-V4) X 580.0 / 1900.0 r176 35.0

B1H10110001V177'V

4+(V3-V4) X 545.0 / 1900.0 r177 35.0

B2H10110010V178'V

4+(V3-V4) X 510.0 / 1900.0 r178 35.0

B3H10110011V179'V

4+(V3-V4) X 475.0 / 1900.0 r179 35.0

B4H10110100V180'V

4+(V3-V4) X 440.0 / 1900.0 r180 35.0

B5H10110101V181'V

4+(V3-V4) X 405.0 / 1900.0 r181 35.0

B6H10110110V182'V

4+(V3-V4) X 370.0 / 1900.0 r182 35.0

B7H10110111V183'V

4+(V3-V4) X 335.0 / 1900.0 r183 35.0

B8H10111000V184'V

4+(V3-V4) X 300.0 / 1900.0 r184 37.5

B9H10111001V185'V

4+(V3-V4) X 262.5 / 1900.0 r185 37.5

BAH10111010V186'V

4+(V3-V4) X 225.0 / 1900.0 r186 37.5

BBH10111011V187'V

4+(V3-V4) X 187.5 / 1900.0 r187 37.5

BCH10111100V188'V

4+(V3-V4) X 150.0 / 1900.0 r188 37.5

BDH10111101V189'V

4+(V3-V4) X 112.5 / 1900.0 r189 37.5

BEH10111110V190'V

4+(V3-V4) X 75.0 / 1900.0 r190 37.5

BFH10111111V191'V

4+(V3-V4) X 37.5 / 1900.0 r191 37.5

Caution There is no connection between V7 and V8 in the chip.

V6

V7V255’

V1

V0’

V1’

V2’

V3’

V31’

V32’

V33’

V223’

V224’

V225’

V252’

V253’

V254’

V0r0

r1

r2

r3

r30

r31

r32

r33

r222

r223

V5r224

r225

r251

r252

r253

r254

Data Sheet S13719EJ4V0DS00

10

µ

µµ

µ

PD16750

Figure 5–2. Relationship between Input Data and Output Voltage (4/4)

VDD2 – 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

C0H11000000V192'V

4r192 42.5

C1H11000001V193'V

5+(V4-V5) X 1557.5 / 1600.0 r193 42.5

C2H11000010V194'V

5+(V4-V5) X 1515.0 / 1600.0 r194 42.5

C3H11000011V195'V

5+(V4-V5) X 1472.5 / 1600.0 r195 42.5

C4H11000100V196'V

5+(V4-V5) X 1430.0 / 1600.0 r196 42.5

C5H11000101V197'V

5+(V4-V5) X 1387.5 / 1600.0 r197 42.5

C6H11000110V198'V

5+(V4-V5) X 1345.0 / 1600.0 r198 42.5

C7H11000111V199'V

5+(V4-V5) X 1302.5 / 1600.0 r199 42.5

C8H11001000V200'V

5+(V4-V5) X 1260.0 / 1600.0 r200 47.5

C9H11001001V201'V

5+(V4-V5) X 1212.5 / 1600.0 r201 47.5

CAH11001010V202'V

5+(V4-V5) X 1165.0 / 1600.0 r202 47.5

CBH11001011V203'V

5+(V4-V5) X 1117.5 / 1600.0 r203 47.5

CCH11001100V204'V

5+(V4-V5) X 1070.0 / 1600.0 r204 47.5

CDH11001101V205'V

5+(V4-V5) X 1022.5 / 1600.0 r205 47.5

CEH11001110V206'V

5+(V4-V5) X 975.0 / 1600.0 r206 47.5

CFH11001111V207'V

5+(V4-V5) X 927.5 / 1600.0 r207 47.5

D0H11010000V208'V

5+(V4-V5) X 880.0 / 1600.0 r208 52.5

D1H11010001V209'V

5+(V4-V5) X 827.5 / 1600.0 r209 52.5

D2H11010010V210'V

5+(V4-V5) X 775.0 / 1600.0 r210 52.5

D3H11010011V211'V

5+(V4-V5) X 722.5 / 1600.0 r211 52.5

D4H11010100V212'V

5+(V4-V5) X 670.0 / 1600.0 r212 52.5

D5H11010101V213'V

5+(V4-V5) X 617.5 / 1600.0 r213 52.5

D6H11010110V214'V

5+(V4-V5) X 565.0 / 1600.0 r214 52.5

D7H11010111V215'V

5+(V4-V5) X 512.5 / 1600.0 r215 52.5

D8H11011000V216'V

5+(V4-V5) X 460.0 / 1600.0 r216 57.5

D9H11011001V217'V

5+(V4-V5) X 402.5 / 1600.0 r217 57.5

DAH11011010V218'V

5+(V4-V5) X 345.0 / 1600.0 r218 57.5

DBH11011011V219'V

5+(V4-V5) X 287.5 / 1600.0 r219 57.5

DCH11011100V220'V

5+(V4-V5) X 230.0 / 1600.0 r220 57.5

DDH11011101V221'V

5+(V4-V5) X 172.5 / 1600.0 r221 57.5

DEH11011110V222'V

5+(V4-V5) X 115.0 / 1600.0 r222 57.5

DFH11011111V223'V

5+(V4-V5) X 57.5 / 1600.0 r223 57.5

E0H11100000V224'V

5r224 57.5

E1H11100001V225'V

6+(V5-V6) X 4630.0 / 4687.5 r225 70.0

E2H11100010V226'V

6+(V5-V6) X 4560.0 / 4687.5 r226 70.0

E3H11100011V227'V

6+(V5-V6) X 4490.0 / 4687.5 r227 70.0

E4H11100100V228'V

6+(V5-V6) X 4420.0 / 4687.5 r228 82.5

E5H11100101V229'V

6+(V5-V6) X 4337.5 / 4687.5 r229 82.5

E6H11100110V230'V

6+(V5-V6) X 4255.0 / 4687.5 r230 82.5

E7H11100111V231'V

6+(V5-V6) X 4172.5 / 4687.5 r231 95.0

E8H11101000V232'V

6+(V5-V6) X 4077.5 / 4687.5 r232 95.0

E9H11101001V233'V

6+(V5-V6) X 3982.5 / 4687.5 r233 95.0

EAH11101010V234'V

6+(V5-V6) X 3887.5 / 4687.5 r234 112.5

EBH11101011V235'V

6+(V5-V6) X 3775.0 / 4687.5 r235 112.5

ECH11101100V236'V

6+(V5-V6) X 3662.5 / 4687.5 r236 112.5

EDH11101101V237'V

6+(V5-V6) X 3550.0 / 4687.5 r237 130.0

EEH11101110V238'V

6+(V5-V6) X 3420.0 / 4687.5 r238 130.0

EFH11101111V239'V

6+(V5-V6) X 3290.0 / 4687.5 r239 147.5

F0H11110000V240'V

6+(V5-V6) X 3142.5 / 4687.5 r240 147.5

F1H11110001V241'V

6+(V5-V6) X 2995.0 / 4687.5 r241 165.0

F2H11110010V242'V

6+(V5-V6) X 2830.0 / 4687.5 r242 165.0

F3H11110011V243'V

6+(V5-V6) X 2665.0 / 4687.5 r243 182.5

F4H11110100V244'V

6+(V5-V6) X 2482.5 / 4687.5 r244 182.5

F5H11110101V245'V

6+(V5-V6) X 2300.0 / 4687.5 r245 200.0

F6H11110110V246'V

6+(V5-V6) X 2100.0 / 4687.5 r246 200.0

F7H11110111V247'V

6+(V5-V6) X 1900.0 / 4687.5 r247 225.0

F8H11111000V248'V

6+(V5-V6) X 1675.0 / 4687.5 r248 225.0

F9H11111001V249'V

6+(V5-V6) X 1450.0 / 4687.5 r249 250.0

FAH11111010V250'V

6+(V5-V6) X 1200.0 / 4687.5 r250 250.0

FBH11111011V251'V

6+(V5-V6) X 950.0 / 4687.5 r251 300.0

FCH11111100V252'V

6+(V5-V6) X 650.0 / 4687.5 r252 300.0

FDH11111101V253'V

6+(V5-V6) X 350.0 / 4687.5 r253 350.0

FEH11111110V254'V

6r254 350.0

FFH11111111V255'V

7TOTAL 15002.5

Caution There is no connection between V7 and V8 in the chip.

V6

V7V255’

V1

V0’

V1’

V2’

V3’

V31’

V32’

V33’

V223’

V224’

V225’

V252’

V253’

V254’

V0r0

r1

r2

r3

r30

r31

r32

r33

r222

r223

V5r224

r225

r251

r252

r253

r254

Data Sheet S13719EJ4V0DS00 11

µ

µµ

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (1/4)

0.5 VDD2 – 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

00H00000000 V0"V

15 r0 400.0

01H00000001 V1"V

15+(V14-V15) X 400.0 / 3865 r1 362.5

02H00000010 V2"V

15+(V14-V15) X 762.5 / 3865 r2 325.0

03H00000011 V3"V

15+(V14-V15) X 1087.5 / 3865 r3 287.5

04H00000100 V4"V

15+(V14-V15) X 1375.0 / 3865 r4 250.0

05H00000101 V5"V

15+(V14-V15) X 1625.0 / 3865 r5 222.5

06H00000110 V6"V

15+(V14-V15) X 1847.5 / 3865 r6 195.0

07H00000111 V7"V

15+(V14-V15) X 2042.5 / 3865 r7 170.0

08H00001000 V8"V

15+(V14-V15) X 2212.5 / 3865 r8 145.0

09H00001001 V9"V

15+(V14-V15) X 2357.5 / 3865 r9 120.0

0AH00001010V10"V

15+(V14-V15) X 2477.5 / 3865 r10 120.0

0BH00001011V11"V

15+(V14-V15) X 2597.5 / 3865 r11 120.0

0CH00001100V12"V

15+(V14-V15) X 2717.5 / 3865 r12 95.0

0DH00001101V13"V

15+(V14-V15) X 2812.5 / 3865 r13 95.0

0EH00001110V14"V

15+(V14-V15) X 2907.5 / 3865 r14 95.0

0FH00001111V15"V

15+(V14-V15) X 3002.5 / 3865 r15 75.0

10H00010000V16"V

15+(V14-V15) X 3077.5 / 3865 r16 75.0

11H00010001V17"V

15+(V14-V15) X 3152.5 / 3865 r17 75.0

12H00010010V18"V

15+(V14-V15) X 3227.5 / 3865 r18 62.5

13H00010011V19"V

15+(V14-V15) X 3290.0 / 3865 r19 62.5

14H00010100V20"V

15+(V14-V15) X 3352.5 / 3865 r20 62.5

15H00010101V21"V

15+(V14-V15) X 3415.0 / 3865 r21 50.0

16H00010110V22"V

15+(V14-V15) X 3465.0 / 3865 r22 50.0

17H00010111V23"V

15+(V14-V15) X 3515.0 / 3865 r23 50.0

18H00011000V24"V

15+(V14-V15) X 3565.0 / 3865 r24 37.5

19H00011001V25"V

15+(V14-V15) X 3602.5 / 3865 r25 37.5

1AH00011010V26"V

15+(V14-V15) X 3640.0 / 3865 r26 37.5

1BH00011011V27"V

15+(V14-V15) X 3677.5 / 3865 r27 37.5

1CH00011100V28"V

15+(V14-V15) X 3715.0 / 3865 r28 37.5

1DH00011101V29"V

15+(V14-V15) X 3752.5 / 3865 r29 37.5

1EH00011110V30"V

15+(V14-V15) X 3790.0 / 3865 r30 37.5

1FH00011111V31"V

15+(V14-V15) X 3827.5 / 3865 r31 37.5

20H00100000V32"V

14 r32 35.0

21H00100001V33"V

14+(V13-V14) X 35.0 / 1000 r33 35.0

22H00100010V34"V

14+(V13-V14) X 70.0 / 1000 r34 35.0

23H00100011V35"V

14+(V13-V14) X 105.0 / 1000 r35 35.0

24H00100100V36"V

14+(V13-V14) X 140.0 / 1000 r36 35.0

25H00100101V37"V

14+(V13-V14) X 175.0 / 1000 r37 35.0

26H00100110V38"V

14+(V13-V14) X 210.0 / 1000 r38 35.0

27H00100111V39"V

14+(V13-V14) X 245.0 / 1000 r39 35.0

28H00101000V40"V

14+(V13-V14) X 280.0 / 1000 r40 32.5

29H00101001V41"V

14+(V13-V14) X 312.5 / 1000 r41 32.5

2AH00101010V42"V

14+(V13-V14) X 345.0 / 1000 r42 32.5

2BH00101011V43"V

14+(V13-V14) X 377.5 / 1000 r43 32.5

2CH00101100V44"V

14+(V13-V14) X 410.0 / 1000 r44 32.5

2DH00101101V45"V

14+(V13-V14) X 442.5 / 1000 r45 32.5

2EH00101110V46"V

14+(V13-V14) X 475.0 / 1000 r46 32.5

2FH00101111V47"V

14+(V13-V14) X 507.5 / 1000 r47 32.5

30H00110000V48"V

14+(V13-V14) X 540.0 / 1000 r48 30.0

31H00110001V49"V

14+(V13-V14) X 570.0 / 1000 r49 30.0

32H00110010V50"V

14+(V13-V14) X 600.0 / 1000 r50 30.0

33H00110011V51"V

14+(V13-V14) X 630.0 / 1000 r51 30.0

34H00110100V52"V

14+(V13-V14) X 660.0 / 1000 r52 30.0

35H00110101V53"V

14+(V13-V14) X 690.0 / 1000 r53 30.0

36H00110110V54"V

14+(V13-V14) X 720.0 / 1000 r54 30.0

37H00110111V55"V

14+(V13-V14) X 750.0 / 1000 r55 30.0

38H00111000V56"V

14+(V13-V14) X 780.0 / 1000 r56 27.5

39H00111001V57"V

14+(V13-V14) X 807.5 / 1000 r57 27.5

3AH00111010V58"V

14+(V13-V14) X 835.0 / 1000 r58 27.5

3BH00111011V59"V

14+(V13-V14) X 862.5 / 1000 r59 27.5

3CH00111100V60"V

14+(V13-V14) X 890.0 / 1000 r60 27.5

3DH00111101V61"V

14+(V13-V14) X 917.5 / 1000 r61 27.5

3EH00111110V62"V

14+(V13-V14) X 945.0 / 1000 r62 27.5

3FH00111111V63"V

14+(V13-V14) X 972.5 / 1000 r63 27.5

Caution There is no connection between V7 and V8 in the chip.

V

33

’’

V

0

’’

V

32

’’

V

31

’’

V

2

’’

V

1

’’

V

254

’’

V

253

’’

V

252

’’

V

225

’’

V

224

’’

V

223

’’

r

252

r

251

r

250

r

225

r

224

r

223

r

222

V

10

r

253

V

9

r

33

r

0

r

32

r

31

r

30

r

2

r

1

V

15

V

14

V

251

’’

V

255

’’

V

8

r

254

Data Sheet S13719EJ4V0DS00

12

µ

µµ

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (2/4)

0.5 VDD2 – 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

40H01000000V64"V

13 r64 25.0

41H01000001V65"V

13+(V12-V13) X 25 / 1600 r65 25.0

42H01000010V66"V

13+(V12-V13) X 50 / 1600 r66 25.0

43H01000011V67"V

13+(V12-V13) X 75 / 1600 r67 25.0

44H01000100V68"V

13+(V12-V13) X 100 / 1600 r68 25.0

45H01000101V69"V

13+(V12-V13) X 125 / 1600 r69 25.0

46H01000110V70"V

13+(V12-V13) X 150 / 1600 r70 25.0

47H01000111V71"V

13+(V12-V13) X 175 / 1600 r71 25.0

48H01001000V72"V

13+(V12-V13) X 200 / 1600 r72 25.0

49H01001001V73"V

13+(V12-V13) X 225 / 1600 r73 25.0

4AH01001010V74"V

13+(V12-V13) X 250 / 1600 r74 25.0

4BH01001011V75"V

13+(V12-V13) X 275 / 1600 r75 25.0

4CH01001100V76"V

13+(V12-V13) X 300 / 1600 r76 25.0

4DH01001101V77"V

13+(V12-V13) X 325 / 1600 r77 25.0

4EH01001110V78"V

13+(V12-V13) X 350 / 1600 r78 25.0

4FH01001111V79"V

13+(V12-V13) X 375 / 1600 r79 25.0

50H01010000V80"V

13+(V12-V13) X 400 / 1600 r80 25.0

51H01010001V81"V

13+(V12-V13) X 425 / 1600 r81 25.0

52H01010010V82"V

13+(V12-V13) X 450 / 1600 r82 25.0

53H01010011V83"V

13+(V12-V13) X 475 / 1600 r83 25.0

54H01010100V84"V

13+(V12-V13) X 500 / 1600 r84 25.0

55H01010101V85"V

13+(V12-V13) X 525 / 1600 r85 25.0

56H01010110V86"V

13+(V12-V13) X 550 / 1600 r86 25.0

57H01010111V87"V

13+(V12-V13) X 575 / 1600 r87 25.0

58H01011000V88"V

13+(V12-V13) X 600 / 1600 r88 25.0

59H01011001V89"V

13+(V12-V13) X 625 / 1600 r89 25.0

5AH01011010V90"V

13+(V12-V13) X 650 / 1600 r90 25.0

5BH01011011V91"V

13+(V12-V13) X 675 / 1600 r91 25.0

5CH01011100V92"V

13+(V12-V13) X 700 / 1600 r92 25.0

5DH01011101V93"V

13+(V12-V13) X 725 / 1600 r93 25.0

5EH01011110V94"V

13+(V12-V13) X 750 / 1600 r94 25.0

5FH01011111V95"V

13+(V12-V13) X 775 / 1600 r95 25.0

60H01100000V96"V

13+(V12-V13) X 800 1600 r96 25.0

61H01100001V97"V

13+(V12-V13) X 825 / 1600 r97 25.0

62H01100010V98"V

13+(V12-V13) X 850 / 1600 r98 25.0

63H01100011V99"V

13+(V12-V13) X 875 / 1600 r99 25.0

64H01100100V100"V

13+(V12-V13) X 900 / 1600 r100 25.0

65H01100101V101"V

13+(V12-V13) X 925 / 1600 r101 25.0

66H01100110V102"V

13+(V12-V13) X 950 / 1600 r102 25.0

67H01100111V103"V

13+(V12-V13) X 975 / 1600 r103 25.0

68H01101000V104"V

13+(V12-V13) X 1000 / 1600 r104 25.0

69H01101001V105"V

13+(V12-V13) X 1025 / 1600 r105 25.0

6AH01101010V106"V

13+(V12-V13) X 1050 / 1600 r106 25.0

6BH01101011V107"V

13+(V12-V13) X 1075 / 1600 r107 25.0

6CH01101100V108"V

13+(V12-V13) X 1100 / 1600 r108 25.0

6DH01101101V109"V

13+(V12-V13) X 1125 / 1600 r109 25.0

6EH01101110V110"V

13+(V12-V13) X 1150 / 1600 r110 25.0

6FH01101111V111"V

13+(V12-V13) X 1175 / 1600 r111 25.0

70H01110000V112"V

13+(V12-V13) X 1200 / 1600 r112 25.0

71H01110001V113"V

13+(V12-V13) X 1225 / 1600 r113 25.0

72H01110010V114"V

13+(V12-V13) X 1250 / 1600 r114 25.0

73H01110011V115"V

13+(V12-V13) X 1275 / 1600 r115 25.0

74H01110100V116"V

13+(V12-V13) X 1300 / 1600 r116 25.0

75H01110101V117"V

13+(V12-V13) X 1325 / 1600 r117 25.0

76H01110110V118"V

13+(V12-V13) X 1350 / 1600 r118 25.0

77H01110111V119"V

13+(V12-V13) X 1375 / 1600 r119 25.0

78H01111000V120"V

13+(V12-V13) X 1400 / 1600 r120 25.0

79H01111001V121"V

13+(V12-V13) X 1425 / 1600 r121 25.0

7AH01111010V122"V

13+(V12-V13) X 1450 / 1600 r122 25.0

7BH01111011V123"V

13+(V12-V13) X 1475 / 1600 r123 25.0

7CH01111100V124"V

13+(V12-V13) X 1500 / 1600 r124 25.0

7DH01111101V125"V

13+(V12-V13) X 1525 / 1600 r125 25.0

7EH01111110V126"V

13+(V12-V13) X 1550 / 1600 r126 25.0

7FH01111111V127"V

13+(V12-V13) X 1575 / 1600 r127 25.0

Caution There is no connection between V7 and V8 in the chip.

V

33

’’

V

0

’’

V

32

’’

V

31

’’

V

2

’’

V

1

’’

V

254

’’

V

253

’’

V

252

’’

V

225

’’

V

224

’’

V

223

’’

r

252

r

251

r

250

r

225

r

224

r

223

r

222

V

10

r

253

V

9

r

33

r

0

r

32

r

31

r

30

r

2

r

1

V

15

V

14

V

251

’’

V

255

’’

V

8

r

254

Data Sheet S13719EJ4V0DS00 13

µ

µµ

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (3/4)

0.5 VDD2 – 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

80H10000000V128"V

12 r128 25.0

81H10000001V129"V

12+(V11-V12) X 25.0 / 1900.0 r129 25.0

82H10000010V130"V

12+(V11-V12) X 50.0 / 1900.0 r130 25.0

83H10000011V131"V

12+(V11-V12) X 75.0 / 1900.0 r131 25.0

84H10000100V132"V

12+(V11-V12) X 100.0 / 1900.0 r132 25.0

85H10000101V133"V

12+(V11-V12) X 125.0 / 1900.0 r133 25.0

86H10000110V134"V

12+(V11-V12) X 150.0 / 1900.0 r134 25.0

87H10000111V135"V

12+(V11-V12) X 175.0 / 1900.0 r135 25.0

88H10001000V136"V

12+(V11-V12) X 200.0 / 1900.0 r136 25.0

89H10001001V137"V

12+(V11-V12) X 225.0 / 1900.0 r137 25.0

8AH10001010V138"V

12+(V11-V12) X 250.0 / 1900.0 r138 25.0

8BH10001011V139"V

12+(V11-V12) X 275.0 / 1900.0 r139 25.0

8CH10001100V140"V

12+(V11-V12) X 300.0 / 1900.0 r140 25.0

8DH10001101V141"V

12+(V11-V12) X 325.0 / 1900.0 r141 25.0

8EH10001110V142"V

12+(V11-V12) X 350.0 / 1900.0 r142 25.0

8FH10001111V143"V

12+(V11-V12) X 375.0 / 1900.0 r143 25.0

90H10010000V144"V

12+(V11-V12) X 400.0 / 1900.0 r144 25.0

91H10010001V145"V

12+(V11-V12) X 425.0 / 1900.0 r145 25.0

92H10010010V146"V

12+(V11-V12) X 450.0 / 1900.0 r146 25.0

93H10010011V147"V

12+(V11-V12) X 475.0 / 1900.0 r147 25.0

94H10010100V148"V

12+(V11-V12) X 500.0 / 1900.0 r148 25.0

95H10010101V149"V

12+(V11-V12) X 525.0 / 1900.0 r149 25.0

96H10010110V150"V

12+(V11-V12) X 550.0 / 1900.0 r150 25.0

97H10010111V151"V

12+(V11-V12) X 575.0 / 1900.0 r151 25.0

98H10011000V152"V

12+(V11-V12) X 600.0 / 1900.0 r152 27.5

99H10011001V153"V

12+(V11-V12) X 627.5 / 1900.0 r153 27.5

9AH10011010V154"V

12+(V11-V12) X 655.0 / 1900.0 r154 27.5

9BH10011011V155"V

12+(V11-V12) X 682.5 / 1900.0 r155 27.5

9CH10011100V156"V

12+(V11-V12) X 710.0 / 1900.0 r156 27.5

9DH10011101V157"V

12+(V11-V12) X 737.5 / 1900.0 r157 27.5

9EH10011110V158"V

12+(V11-V12) X 765.0 / 1900.0 r158 27.5

9FH10011111V159"V

12+(V11-V12) X 792.5 / 1900.0 r159 27.5

A0H10100000V160"V

12+(V11-V12) X 820.0 1900.0 r160 30.0

A1H10100001V161"V

12+(V11-V12) X 850.0 / 1900.0 r161 30.0

A2H10100010V162"V

12+(V11-V12) X 880.0 / 1900.0 r162 30.0

A3H10100011V163"V

12+(V11-V12) X 910.0 / 1900.0 r163 30.0

A4H10100100V164"V

12+(V11-V12) X 940.0 / 1900.0 r164 30.0

A5H10100101V165"V

12+(V11-V12) X 970.0 / 1900.0 r165 30.0

A6H10100110V166"V

12+(V11-V12) X 1000.0 / 1900.0 r166 30.0

A7H10100111V167"V

12+(V11-V12) X 1030.0 / 1900.0 r167 30.0

A8H10101000V168"V

12+(V11-V12) X 1060.0 / 1900.0 r168 32.5

A9H10101001V169"V

12+(V11-V12) X 1092.5 / 1900.0 r169 32.5

AAH10101010V170"V

12+(V11-V12) X 1125.0 / 1900.0 r170 32.5

ABH10101011V171"V

12+(V11-V12) X 1157.5 / 1900.0 r171 32.5

ACH10101100V172"V

12+(V11-V12) X 1190.0 / 1900.0 r172 32.5

ADH10101101V173"V

12+(V11-V12) X 1222.5 / 1900.0 r173 32.5

AEH10101110V174"V

12+(V11-V12) X 1255.0 / 1900.0 r174 32.5

AFH10101111V175"V

12+(V11-V12) X 1287.5 / 1900.0 r175 32.5

B0H10110000V176"V

12+(V11-V12) X 1320.0 / 1900.0 r176 35.0

B1H10110001V177"V

12+(V11-V12) X 1355.0 / 1900.0 r177 35.0

B2H10110010V178"V

12+(V11-V12) X 1390.0 / 1900.0 r178 35.0

B3H10110011V179"V

12+(V11-V12) X 1425.0 / 1900.0 r179 35.0

B4H10110100V180"V

12+(V11-V12) X 1460.0 / 1900.0 r180 35.0

B5H10110101V181"V

12+(V11-V12) X 1495.0 / 1900.0 r181 35.0

B6H10110110V182"V

12+(V11-V12) X 1530.0 / 1900.0 r182 35.0

B7H10110111V183"V

12+(V11-V12) X 1565.0 / 1900.0 r183 35.0

B8H10111000V184"V

12+(V11-V12) X 1600.0 / 1900.0 r184 37.5

B9H10111001V185"V

12+(V11-V12) X 1637.5 / 1900.0 r185 37.5

BAH10111010V186"V

12+(V11-V12) X 1675.0 / 1900.0 r186 37.5

BBH10111011V187"V

12+(V11-V12) X 1712.5 / 1900.0 r187 37.5

BCH10111100V188"V

12+(V11-V12) X 1750.0 / 1900.0 r188 37.5

BDH10111101V189"V

12+(V11-V12) X 1787.5 / 1900.0 r189 37.5

BEH10111110V190"V

12+(V11-V12) X 1825.0 / 1900.0 r190 37.5

BFH10111111V191"V

12+(V11-V12) X 1862.5 / 1900.0 r191 37.5

Caution There is no connection between V7 and V8 in the chip.

V

33

’’

V

0

’’

V

32

’’

V

31

’’

V

2

’’

V

1

’’

V

254

’’

V

253

’’

V

252

’’

V

225

’’

V

224

’’

V

223

’’

r

252

r

251

r

250

r

225

r

224

r

223

r

222

V

10

r

253

V

9

r

33

r

0

r

32

r

31

r

30

r

2

r

1

V

15

V

14

V

251

’’

V

255

’’

V

8

r

254

Data Sheet S13719EJ4V0DS00

14

µ

µµ

µ

PD16750

Figure 5–3. Relationship between Input Data and Output Voltage (4/4)

0.5 VDD2 – 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V, POL21/22 = L

Data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 Output voltage rn (Ω)

C0H11000000V192"V

11 r192 42.5

C1H11000001V193"V

11+(V10-V11) X 42.5 / 1600.0 r193 42.5

C2H11000010V194"V

11+(V10-V11) X 85.0 / 1600.0 r194 42.5

C3H11000011V195"V

11+(V10-V11) X 127.5 / 1600.0 r195 42.5

C4H11000100V196"V

11+(V10-V11) X 170.0 / 1600.0 r196 42.5

C5H11000101V197"V

11+(V10-V11) X 212.5 / 1600.0 r197 42.5

C6H11000110V198"V

11+(V10-V11) X 255.0 / 1600.0 r198 42.5

C7H11000111V199"V

11+(V10-V11) X 297.5 / 1600.0 r199 42.5

C8H11001000V200"V

11+(V10-V11) X 340.0 / 1600.0 r200 47.5

C9H11001001V201"V

11+(V10-V11) X 387.5 / 1600.0 r201 47.5

CAH11001010V202"V

11+(V10-V11) X 435.0 / 1600.0 r202 47.5

CBH11001011V203"V

11+(V10-V11) X 482.5 / 1600.0 r203 47.5

CCH11001100V204"V

11+(V10-V11) X 530.0 / 1600.0 r204 47.5

CDH11001101V205"V

11+(V10-V11) X 577.5 / 1600.0 r205 47.5

CEH11001110V206"V

11+(V10-V11) X 625.0 / 1600.0 r206 47.5

CFH11001111V207"V

11+(V10-V11) X 672.5 / 1600.0 r207 47.5

D0H11010000V208"V

11+(V10-V11) X 720.0 / 1600.0 r208 52.5

D1H11010001V209"V

11+(V10-V11) X 772.5 / 1600.0 r209 52.5

D2H11010010V210"V

11+(V10-V11) X 825.0 / 1600.0 r210 52.5

D3H11010011V211"V

11+(V10-V11) X 877.5 / 1600.0 r211 52.5

D4H11010100V212"V

11+(V10-V11) X 930.0 / 1600.0 r212 52.5

D5H11010101V213"V

11+(V10-V11) X 982.5 / 1600.0 r213 52.5

D6H11010110V214"V

11+(V10-V11) X 1035.0 / 1600.0 r214 52.5

D7H11010111V215"V

11+(V10-V11) X 1087.5 / 1600.0 r215 52.5

D8H11011000V216"V

11+(V10-V11) X 1140.0 / 1600.0 r216 57.5

D9H11011001V217"V

11+(V10-V11) X 1197.5 / 1600.0 r217 57.5

DAH11011010V218"V

11+(V10-V11) X 1255.0 / 1600.0 r218 57.5

DBH11011011V219"V

11+(V10-V11) X 1312.5 / 1600.0 r219 57.5

DCH11011100V220"V

11+(V10-V11) X 1370.0 / 1600.0 r220 57.5

DDH11011101V221"V

11+(V10-V11) X 1427.5 / 1600.0 r221 57.5

DEH11011110V222"V

11+(V10-V11) X 1485.0 / 1600.0 r222 57.5

DFH11011111V223"V

11+(V10-V11) X 1542.5 / 1600.0 r223 57.5

E0H11100000V224"V

10 r224 57.5

E1H11100001V225"V

10+(V9-V10) X 57.5 / 4687.5 r225 70.0

E2H11100010V226"V

10+(V9-V10) X 127.5 / 4687.5 r226 70.0

E3H11100011V227"V

10+(V9-V10) X 197.5 / 4687.5 r227 70.0

E4H11100100V228"V

10+(V9-V10) X 267.5 / 4687.5 r228 82.5

E5H11100101V229"V

10+(V9-V10) X 350.0 / 4687.5 r229 82.5

E6H11100110V230"V

10+(V9-V10) X 432.5 / 4687.5 r230 82.5

E7H11100111V231"V

10+(V9-V10) X 515.0 / 4687.5 r231 95.0

E8H11101000V232"V

10+(V9-V10) X 610.0 / 4687.5 r232 95.0

E9H11101001V233"V

10+(V9-V10) X 705.0 / 4687.5 r233 95.0

EAH11101010V234"V

10+(V9-V10) X 800.0 / 4687.5 r234 112.5

EBH11101011V235"V

10+(V9-V10) X 912.5 / 4687.5 r235 112.5

ECH11101100V236"V

10+(V9-V10) X 1025.0 / 4687.5 r236 112.5

EDH11101101V237"V

10+(V9-V10) X 1137.5 / 4687.5 r237 130.0

EEH11101110V238"V

10+(V9-V10) X 1267.5 / 4687.5 r238 130.0

EFH11101111V239"V

10+(V9-V10) X 1397.5 / 4687.5 r239 147.5

F0H11110000V240"V

10+(V9-V10) X 1545.0 / 4687.5 r240 147.5

F1H11110001V241"V

10+(V9-V10) X 1692.5 / 4687.5 r241 165.0

F2H11110010V242"V

10+(V9-V10) X 1857.5 / 4687.5 r242 165.0

F3H11110011V243"V

10+(V9-V10) X 2022.5 / 4687.5 r243 182.5

F4H11110100V244"V

10+(V9-V10) X 2205.0 / 4687.5 r244 182.5

F5H11110101V245"V

10+(V9-V10) X 2387.5 / 4687.5 r245 200.0

F6H11110110V246"V

10+(V9-V10) X 2587.5 / 4687.5 r246 200.0

F7H11110111V247"V

10+(V9-V10) X 2787.5 / 4687.5 r247 225.0

F8H11111000V248"V

10+(V9-V10) X 3012.5 / 4687.5 r248 225.0

F9H11111001V249"V

10+(V9-V10) X 3237.5 / 4687.5 r249 250.0

FAH11111010V250"V

10+(V9-V10) X 3487.5 / 4687.5 r250 250.0

FBH11111011V251"V

10+(V9-V10) X 3737.5 / 4687.5 r251 300.0

FCH11111100V252"V

10+(V9-V10) X 4037.5 / 4687.5 r252 300.0

FDH11111101V253"V

10+(V9-V10) X 4337.5 / 4687.5 r253 350.0

FEH11111110V254"V

9r254 350.0

FFH11111111V255"V

8TOTAL 15002.5

Caution There is no connection between V7 and V8 in the chip.

V

33

’’

V

0

’’

V

32

’’

V

31

’’

V

2

’’

V

1

’’

V

254

’’

V

253

’’

V

252

’’

V

225

’’

V

224

’’

V

223

’’

r

252

r

251

r

250

r

225

r

224

r

223

r

222

V

10

r

253

V

9

r

33

r

0

r

32

r

31

r

30

r

2

r

1

V

15

V

14

V

251

’’

V

255

’’

V

8

r

254

Data Sheet S13719EJ4V0DS00 15

µ

µµ

µ

PD16750

6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN

Data format : 8 bits x 2 RGBs (6 dots)

Input width : 48 bits (2-pixel data)

(1) R,/L = H (Right shift)

Output S1S2S3S4xxx S383 S384

Data D00 to D07 D10 to D17 D20 to D27 D30 to D37 xxx D40 to D47 D50 to D57

(2) R,/L = L (Left shift)

Output S1S2S3 S4 xxx S383 S384

Data D00 to D07 D10 to D17 D20 to D27 D30 to D37 xxx D40 to D47 D50 to D57

POL S2n–1Note S2nNote

LV

0 to V7V8 to V15

HV

8 to V15 V0 to V7

Note S2n–1 (Odd output), S2n (Even output)

7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM

The output voltage is written to the LCD panel synchronized with the STB falling edge.

Selected voltage V

0

to

V

7

Hi-Z

STB

POL

S

2n

S

2n-1

Hi-Z Hi-Z

Selected voltage V

8

to

V

15

Selected voltage V

0

to

V

7

Selected voltage V

0

to

V

7

Selected voltage V

8

to

V

15

Selected voltage V

8

to

V

15

Data Sheet S13719EJ4V0DS00

16

µ

µµ

µ

PD16750

8. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°

°°

°C, VSS1 = VSS2 = 0 V)

Parameter Symbol Rating Unit

Logic Part Supply V ol tage VDD1 –0.5 t o +4.0 V

Driver Part S upply Volt age VDD2 –0.5 to +10.0 V

Logic Part Input Vol t age VI1 –0.5 to V DD1 + 0.5 V

Driver Part I nput Voltage VI2 –0.5 to VDD2 + 0.5 V

Logic Part Output Vol t age VO1 –0.5 to V DD1 + 0.5 V

Driver Part Out put Voltage VO2 –0.5 to VDD2 + 0.5 V

Operating Ambient Temperature TA–10 to +75 °C

Storage Temperature Tstg –55 to +125 °C

Caution If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)

Parameter Symbol MIN. TYP. MAX. Unit

Logic Part Supply V ol tage VDD1 3.0 3.3 3.6 V

Driver Part S upply Volt age VDD2 8.5 9.0 9.5 V

High-Level Input V ol tage VIH 0.7 VDD1 VDD1 V

Low-Level Input Volt age VIL 0 0.3 VDD1 V

γ

-Corrected Vol tage V0 to V70.5 VDD2 VDD2 – 0.2 V

V8 to V15 VSS2 + 0.2 0.5 VDD2 – 0.3 V

Driver Part Output Voltage VOVSS2 + 0.2 VDD2 – 0.2 V

Clock Frequency fCLK 40 MHz

Data Sheet S13719EJ4V0DS00 17

µ

µµ

µ

PD16750

Electrical Characteristics (TA = –10 to +75°C, VDD1 = 3.3 V ±

±±

± 0.3 V, VDD2 = 9.0 V ±

±±

± 0.5 V, VSS1 = VSS2 = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit

Input Leak Current IIL ±0.1 ±1.0

µ

A

High-Level Output V ol tage VOH ST HR (STHL), IOH = 0 mA VDD1 – 0.1 VDD1 V

Low-Level Output Volt age VOL STHR (S T HL), IOL = 0 mA 0 0.1 V

γ

-Corrected S uppl y Current I

γ

V0 to V7 = V8 to V15 V0 pin, V8 pin 225 450 900

µ

A

= 4.0 V V7 pin, V15 pin –900 –450 –225

µ

A

IVOH VX = 7.0 V, VOUT = 6.5 VNote –185 –90

µ

ADriver Output Current

IVOL VX = 1.0 V, VOUT = 1.5 VNote 120 238

µ

A

Output Vol tage Deviation ∆VOVO = 0.2 V to 1.2 V

VO = VDD2 – 1.2 V t o V DD2 – 0.2 V

±30 ±50 mV

VO = 1.2 V to 0.5 VDD2 – 0.3 V

VO = 0.5 VDD2 to VDD2 – 1.2 V

±10 ±20 mV

Output Swing Dif ference

Deviation

∆VP–P VO = 0.2 V to 0. 8 V

VO = VDD2 – 0.8 V t o V DD2 – 0.2 V

±20 ±40 mV

VO = 0.8 V to 1.2 V

VO = VDD2 – 1.2 V t o V DD2 – 0.8 V

±10 ±20 mV

VO = 1.2 V to 0.5 VDD2 – 0.3 V

VO = 0.5 VDD2 to VDD2 – 1.2 V

±3±10 mV

Output Swing Average

Difference Deviati on

AVOVDD2 = 8.5 V, V0 = 7. 9 V , V3 = 6.22 V,

V7 = 4.0 V, V8 = 4.0 V , V12 = 1.78 V,

V12 = 0.1 V, V1, V2, V4, V5, V6, V9, V10,

V11, V13, V14 : Open, TA = 25°C,

Input data: 80 H

4.433 4.440 4.447 V

Output Vol tage Range VO0.2 VDD2 – 0.2 V

Logic Part Dynamic Current

Consumption

IDD1 VDD1, with no load 0.8 6.0 m A

Driver Part Dynamic Current

Consumption

IDD2 VDD2, with no load 4.5 11.0 m A

Note VX refers to the output voltage of analog output pins S1 to S384.

VOUT refers to the voltage applied to analog output pins S1 to S384.

Cautions 1. The STB cycle is defined to be 20

µ

µµ

µ

s at fCLK. = 40 MHz.

2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the

measured values in the dot checkerboard input pattern.

3. Refers to the current consumption per driver when cascades are connected under the

assumption of XGA single-sided mounting (8 units).

Data Sheet S13719EJ4V0DS00

18

µ

µµ

µ

PD16750

Switching Characteristics (TA = –10 to +75 °

°°

°C, VDD1 = 3.3 V ±

±±

± 0.3 V, VDD2 = 9.0 V ±

±±

± 0.5 V, VSS1 = VSS2 = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit

Start Pulse Delay Time tPLH1 CL = 15 pF 8 20 ns

tPLH2 36

µ

s

tPLH3 48

µ

s

tPHL2 36

µ

s

Driver Output Delay Ti me

tPHL3

CL = 75 pF, RL = 5 kΩ

48

µ

s

CI1 STHR (STHL) excluded, TA = 25° C 4.8 10 pFInput Capaci tance

CI2 STHR (STHL), T A = 25° C 8.6 15 pF

<Measurement Condition>

OUTPUT

R

L

R

L

R

L

R

L

R

L

= 1 kΩ

C

L

C

L

C

L

C

L

C

L

C

L

= 15 pF

R

L

Data Sheet S13719EJ4V0DS00 19

µ

µµ

µ

PD16750

Timing Requirements (TA = –10 to +75°

°°

°C, VDD1 = 3.3 V ±

±±

± 0.3 V, VSS1 = 0 V, tr = tf = 8.0 ns)

Parameter Symbol Condition MIN. TYP. MAX. Unit

Clock Pulse Width PWCLK 25 ns

Clock Pulse Hi gh Period PWCLK(H) 4ns

Clock Pulse Low Period PWCLK(L) 4ns

Data Setup Time tSETUP1 2ns

Data Hold Ti me tHOLD1 2ns

Start P ul s e Setup Time tSETUP2 2ns

Start Pulse Hold Time tHOLD2 2ns

POL21/22 Set up Ti me tSETUP3 2ns

POL21/22 Hold Time tHOLD3 2ns

Start Pulse Low Period tSPL 1CLK

STB Pulse Width PWSTB 2

µ

s

Data Invalid Period tINV 1CLK

Last Data Timing tLDT 2CLK

CLK-STB Time tCLK-STB CLK ↑ → STB ↑6ns

STB-CLK Time tSTB-CLK STB ↑ → CLK ↑6ns

Time B et ween STB and Start P ulse tSTB-STH STB ↑ → STHR(STHL) ↑2CLK

POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑–5 ns

STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑6ns

Remark Unless otherwi se specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.

•

•

Data Sheet S13719EJ4V0DS00

20

µ

µµ

µ

PD16750

9. SWITCHING CHARACTERISTIC WAVEFORM (R,/L= H)

Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.

PWCLK(L)

CLK

POL

VOUT

STB

Dn0 - Dn7

STHR

(1st Dr.)

STHL

(1st Dr.)

PWCLK(H) tr

tSETUP2

INVALID

D

1

-

D

6

tHOLD2

12

12

3646566

513 514

tf

VDD1

VSS1

VDD1

VSS1

VDD1

VSS1

VDD1

VSS1

VDD1

VSS1

VDD1

VSS1

PWCLK

tCLK-STB tSTB-CLK

tSTB-STH

tSETUP1/3

90

%

10

%

tHOLD1/3

tPLH1

tINV

tPOL-STB tSTB-POL

tPLH3

tPLH2

tPHL2

tPHL3

Hi-Z

Target Voltage ± 0.1 VDD2

8-bit accuracy

tLDT PWSTB

D

7

-

D

12

D

1

-

D

6

D

7

-

D

12

D

373

-

D

378

D

379

-

D

384

D

385

-

D

390

INVALID

INVALID VDD1

VSS1

INVALID

tSETUP3 tHOLD3

POL21/22

D

3067

-

D

3072

Data Sheet S13719EJ4V0DS00 21

µ

µµ

µ

PD16750

10. RECOMMENDED MOUNTING CONDITIONS

The following conditions must be met for mounting conditions of the

µ

PD16750.

For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).

Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under

different conditions.

µ

PD16750N-xxx : TCP (TAB Package)

Mounting Condition Mounting Method Condition

Thermoc ompression Soldering Heating tool 300 to 350°C, heat i ng f or 2 to 3 seconds : pressure 100g

(per solder)

ACF

(Adhesive

Conductive Fi l m)

Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm2: time 3 to 5

sec. Real bondi ng 165 t o 180°C: pressure 25 to 45 kg/c m2: time 30 to

40 sec. (When using t he ani s otropy conductive fil m SUMIZA C1003 of

Sumi tomo Bakelite,Ltd).

Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF

manufacturing company. Be sure to avoid using two or more mounting methods at a time.

Data Sheet S13719EJ4V0DS00

22

µ

µµ

µ

PD16750

[MEMO]

Data Sheet S13719EJ4V0DS00 23

µ

µµ

µ

PD16750

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µ

µµ

µ

PD16750

Reference Documents

NEC Semiconductor Device Reliability/Quality Control System(C10983E)

Quality Grades to NEC’s Semiconductor Devices(C11531E)

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8