S-25C010A/020A/040A
www.sii-ic.com SPI SERIAL E2PROM
© SII Semiconductor Corporation, 2007-2015 Rev.4.3_01_C
1
The S-25C010A/020A/040A is a SPI serial E2PROM which operate at high speed, with low current consumption and the wide
range operation. The S-25C010A/020A/040A has the capacity of 1 K-bit, 2 K-bit, 4 K-bit and the organization of 128 words × 8-
bit, 256 words × 8-bit, 512 words × 8-bit. Page write and sequential read are available.
Features
• Operating voltage range: Read 1.6 V to 5.5 V
Write 1.7 V to 5.5 V
• Operation frequency: 5.0 MHz (VCC = 2.5 V to 5.5 V)
• Write time: 4.0 ms max.
• SPI mode (0, 0) and (1, 1)
• Page write: 16 bytes / page
• Sequential read
• Write protect: Software, Hardware
Protect area: 25%, 50%, 100%
• Monitors write to the memory by a status register
• Function to prevent malfunction by monitoring clock pulse
• Write protect function during the low power supply
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance: 106cycles / word*1 (Ta = +25°C)
• Data retention: 100 years (Ta = +25°C)
• Memory capacity: S-25C010A 1 K-bit
S-25C020A 2 K-bit
S-25C040A 4 K-bit
• Initial delivery state: FFh, BP1 = 0, BP0 = 0
• Operation temperature range: Ta = −40°C to +85°C
• Lead-free, Sn 100%, halogen-free*2
*1. For each address (Word: 8-bit)
*2. Refer to “ Product Name Structure” for details.
Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
• TMSOP-8
• SNT-8A
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to SII
Semiconductor Corporation is indispensable.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
2
Pin Configurations
1. 8-Pin SOP (JEDEC)
2. 8-Pin TSSOP
Remark 1. Refer to the “Package drawings” for the details
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
8-Pin SOP (JEDEC)
Top view
Table 1
7
6
5
8
2
3
4
1
Figure 1
S-25C010A0I-J8T1x
S-25C020A0I-J8T1x
S-25C040A0I-J8T1x
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
*1. Do not use it in high impedance.
8-Pin TSSOP
Top view
Table 2
7
6
5
8
2
3
4
1
Figure 2
S-25C010A0I-T8T1x
S-25C020A0I-T8T1x
S-25C040A0I-T8T1x
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
*1. Do not use it in high impedance.
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
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3. TMSOP-8
4. SNT-8A
Remark Refer to the “Package drawings” for the details
TMSOP-8
Top view
Table 3
7
6
5
8
2
3
4
1
Figure 3
S-25C010A0I-K8T3U
S-25C020A0I-K8T3U
S-25C040A0I-K8T3U
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
*1. Do not use it in high impedance.
SNT-8A
Top view
Table 4
7
6
5
8
2
3
4
1
Figure 4
S-25C010A0I-I8T1U
S-25C020A0I-I8T1U
S-25C040A0I-I8T1U
Pin No. Symbol Description
1 CS *1 Chip select input
2 SO Serial data output
3 WP *1 Write protect input
4 GND Ground
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply
*1. Do not use it in high impedance.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
4
Block Diagram
Mode
Decoder
Status RegisterAddress Register
Data Register
WP
CS
HOLD
SI
SCK
SO
VCC
GND
Memory
Cell
Array
Status
Memory Cell Array
Voltage Detector
Read Circuit
Clock Counter
Y Decoder
X Decoder
Input Control Circuit
Output
Control
Circuit
Step-up Circuit
Page Latch
Figure 5
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
5
Absolute Maximum Ratings
Table 5
Item Symbol Absolute Maximum Rating Unit
Power supply voltage VCC −0.3 to +7.0 V
Input voltage VIN −0.3 to +7.0 V
Output voltage VOUT −0.3 to VCC + 0.3 V
Operation ambient temperature Topr −40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 6
Item Symbol Condition
Ta = −40°C to +85°C Unit
Min. Max.
Power supply voltage VCC Read operation 1.6 5.5 V
Write operation 1.7 5.5 V
High level input voltage VIH VCC = 1.6 V to 5.5 V 0.7 × VCC V
CC + 1.0 V
Low level input voltage VIL VCC = 1.6 V to 5.5 V −0.3 0.3 × VCC V
Pin Capacitance
Table 7
(Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)
Item Symbol Condition Min. Max. Unit
Input capacitance CIN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) − 8 pF
Output capacitance COUT VOUT = 0 V (SO) − 10 pF
Endurance
Table 8
Item Symbol Operation Ambient Temperature Min. Max. Unit
Endurance NW Ta = +25°C 106 − cycles / word*1
*1. For each address (Word: 8-bit)
Data Retention
Table 9
Item Symbol Operation Ambient Temperature Min. Max. Unit
Data retention − Ta = +25°C 100 − year
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
6
DC Electrical Characteristics
Table 10
Item Symbol Condition
Ta = −40°C to +85°C
Unit
VCC = 1.6 V to 2.5 V
fSCK = 2.0 MHz
VCC = 2.5 V to 4.5 V
fSCK = 5.0 MHz
VCC = 4.5 V to 5.5 V
fSCK = 5.0 MHz
Min. Max. Min. Max. Min. Max.
Current consumption (READ) ICC1 No load at
SO pin − 1.5 − 2.0 − 2.5 mA
Table 11
Item Symbol Condition
Ta = −40°C to +85°C
Unit
VCC = 1.7 V to 2.5 V
fSCK = 2.0 MHz
VCC = 2.5 V to 4.5 V
fSCK = 5.0 MHz
VCC = 4.5 V to 5.5 V
fSCK = 5.0 MHz
Min. Max. Min. Max. Min. Max.
Current consumption (WRITE) ICC2 No load at
SO pin − 2.0 − 2.5 − 3.0 mA
Table 12
Item
Symbol
Condition
Ta = −40°C to +85°C
Unit
VCC=1.6 V to 2.5 V VCC=2.5 V to 4.5 V VCC=4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
Standby current
consumption ISB
CS = VCC,
SO = Open
Other inputs are
VCC or GND
− 1.5 − 1.5 − 1.5 μA
Input leakage current ILI V
IN = GND to VCC − 1.0 − 1.0 − 1.0 μA
Output leakage current ILO V
OUT = GND to VCC − 1.0 − 1.0 − 1.0 μA
Low level
output voltage
VOL1 I
OL = 2.0 mA − − − 0.4 − 0.4 V
VOL2 I
OL = 1.5 mA − 0.4 − 0.4 − 0.4 V
High level
output voltage
VOH1 I
OH = −2.0 mA − − 0.8 × VCC − 0.8 × VCC − V
VOH2 I
OH = −0.4 mA 0.8 × VCC − 0.8 × VCC − 0.8 × VCC − V
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
7
AC Electrical Characteristics
Table 13 Measurement Conditions
Input pulse voltage 0.2 × VCC to 0.8 × VCC
Output reference voltage 0.5 × VCC
Output load 100 pF
Table 14
Item Symbol
Ta = −40°C to +85°C
Unit
VCC = 1.6 V to 2.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V
Min. Max. Min. Max. Min. Max.
SCK clock frequency fSCK − 2.0 − 5.0 − 5.0 MHz
CS setup time during CS falling tCSS.CL 150 − 90 − 90 − ns
CS setup time during CS rising tCSS.CH 150 − 90 − 90 − ns
CS deselect time tCDS 200 − 90 − 90 − ns
CS hold time during CS falling tCSH.CL 200 − 90 − 90 − ns
CS hold time during CS rising tCSH.CH 150 − 90 − 90 − ns
SCK clock time “H” *1 t
HIGH 200 − 90 − 90 − ns
SCK clock time “L” *1 t
LOW 200 − 90 − 90 − ns
Rising time of SCK clock *2 t
RSK − 1 − 1 − 1 μs
Falling time of SCK clock *2 t
FSK − 1 − 1 − 1 μs
SI data input setup time tDS 50 − 20 − 20 − ns
SI data input hold time tDH 60 − 30 − 30 − ns
SCK “L” hold time
during HOLD rising tSKH.HH 150 − 70 − 70 − ns
SCK “L” hold time
during HOLD falling tSKH.HL 100 − 40 − 40 − ns
SCK “L” setup time
during HOLD falling tSKS.HL 150 − 60 − 60 − ns
SCK “L” setup time
during HOLD rising tSKS.HH 150 − 60 − 60 − ns
Disable time of SO output *2 t
OZ − 200 − 100 − 100 ns
Delay time of SO output tOD − 150 − 70 − 70 ns
Hold time of SO output tOH 0 − 0 − 0 − ns
Rising time of SO output *2 t
RO − 100 − 40 − 40 ns
Falling time of SO output *2 t
FO − 100 − 40 − 40 ns
Disable time of SO output
during HOLD falling *2 tOZ.HL − 200 − 100 − 100 ns
Delay time of SO output
during HOLD rising *2 tOD.HH − 150 − 50 − 50 ns
WP setup time tWS1 0 − 0 − 0 − ns
WP hold time tWH1 0 − 0 − 0 − ns
WP release / setup time tWS2 0 − 0 − 0 − ns
WP release / hold time tWH2 60 − 30 − 30 − ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK μs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) + tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
8
Table 15
Item Symbol
Ta = −40°C to +85°C
Unit VCC = 1.7 V to 5.5 V
Min. Max.
Write time tPR − 4.0 ms
SO
tCSH.CL
SCK
CS
SI
tCSS.CL
tDS tDH
MSB IN LSB IN
tCSH.CH
tCSS.CH
tCDS
tFSKtRSK
High-Z
Figure 6 Serial Input Timing
SO
SCK
HOLD
CS
SI
tSKH.HL
tOZ.HL tOD.HH
tSKH.HH
tSKS.HL
tSKS.HH
Figure 7 Hold Timing
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
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SO
SCK
CS
SI
t
HIGH
t
OH
t
RO
t
OZ
t
LOW
t
SCK
t
OD
t
FO
t
OD
t
OH
ADDR
LSB IN
LSB OUT
Figure 8 Serial Output Timing
WP
CS
t
WH1
t
WS1
Figure 9 Valid Timing in Write Protect
WP
CS
t
WH2
t
WS2
Figure 10 Invalid Timing in Write Protect
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
10
Pin Functions
1. CS (Chip select input ) pin
This is an input pin to set a chip in the select status. In the “H” input level, the device is in the non-select status and its
output is high impedance. The device is in standby as long as it is not in Write inside. The device goes in active by
setting the chip select to “L”. Input any instruction code after power-on and a falling of chip select.
2. SI (Serial data input ) pin
This pin is to input serial data. This pin receives an instruction code, an address and Write data. This pin latches data at
rising edge of serial clock.
3. SO (Serial data output ) pin
This pin is to output serial data. The data output changes at falling edge of serial clock.
4. SCK (Serial clock input ) pin
This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at a
rising edge of clock. Data is output at falling edge of clock.
5. WP (Write protect input ) pin
This is an input pin to protect memory data when Write instruction (WRITE, WRSR) is being input. By setting this pin to
“L”, the WEL bit in the status register is set to “L”. Therefore S-25C010A/020A/040A does not Write to the E2PROM,
however, it accepts other instructions. Fix this pin “H” or “L” not to set it in the floating state.
Refer to “ Protect Operation” for details.
6. HOLD (HOLD input ) pin
This pin is used to pause serial communications without setting the device in the non-select status.
In the hold status, the serial output goes in high impedance, the serial input and the serial clock go in “Don’t care”.
During the hold operation, be sure to set the device in active by setting the chip select ( CS pin) to “L”.
Refer to “ Hold Operation” for details.
Initial Delivery State
Initial delivery state of all addresses is “FFh”.
Moreover, initial delivery state of the status register nonvolatile memory is as follows.
• BP1 = 0
• BP0 = 0
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
11
Instruction Sets
Table 16 and 17 are the lists of instruction for the S-25C010A/020A/040A. The instruction is able to be input by changing
the CS pin “H” to “L”. Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown
below.
If the S-25C010A/020A/040A receives any invalid instruction code, the device goes in the non-select status.
1. S-25C010A/020A
Table 16 Instruction Set
Instruction Operation
Instruction Code Address Data
SCK Input Clock
1 to 8
SCK Input Clock
9 to 16
SCK Input Clock
17 to 24
WREN Write enable 0000 X110 − −
WRDI Write disable 0000 X100 − −
RDSR Read the status register 0000 X101 b7 to b0 output *1 −
WRSR Write in the status register 0000 X001 b7 to b0 input −
READ Read memory data 0000 X011 A7*2 to A0 D7 to D0 output *3
WRITE Write memory data 0000 X010 A7*2 to A0 D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25C010A, A7 = Don’t care because the address range is A6 to A0.
*3. After outputting data in the specified address, data in the following address is output.
Remark X = Don’t care.
2. S-25C040A
Table 17 Instruction Set
Instruction Operation
Instruction Code Address Data
SCK Input Clock
1 to 8
SCK Input Clock
9 to 16
SCK Input Clock
17 to 24
WREN Write enable 0000 X110 − −
WRDI Write disable 0000 X100 − −
RDSR Read the status register 0000 X101 b7 to b0 output *1 −
WRSR Write in the status register 0000 X001 b7 to b0 input −
READ Read memory data 0000 [A8*2] 011 A7 to A0 D7 to D0 output *3
WRITE Write memory data 0000 [A8*2] 010 A7 to A0 D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code.
*3. After outputting data in the specified address, data in the following address is output.
Remark X = Don’t care.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
12
Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
1
b7 b6
1
b5
1
b4
BP1
b3
BP0
b2
WEL
b1
WIP
b0
Block Protect
Write Enable Latch
Write In Progress
1
Figure 11 Organization of Status Register
The status/control bits of the status register are as follows.
1. 1 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area
against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible
unless they are in Hardware Protect mode ( WP pin is “L”). Refer to “ Protect Operation” for details of “Block
Protect”.
1. 2 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the S-
25C010A/020A/040A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the Write operation by the WRSR instruction has completed
• After the Write operation by the WRITE instruction has completed
• After setting the WP pin to “L”
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
13
1. 3 WIP (b0) : Write In Progress
Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or WRSR
instruction. Bit WIP is “1” during the Write operation but “0” during any other status. Figure 12 shows the usage
example.
1111 1111 1111 00
B
P
1
B
P
0
B
P
1
B
P
0
B
t
PR
P
1
B
P
0
WEL, WIP WEL, WIP WEL, WIP
CS
SI
SO
RDSR instruction RDSR instruction RDSR instruction
RDSR RDSR RDSR
11 11
WRITE or WRSR instruction
D2 D1 D0
Figure 12 Usage Example of WEL, WIP Bits during Write
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
14
2. Write enable (WREN)
Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit WEL.
Its operation is below.
After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL,
set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction,
input the clock different from a specified value (n = 8 clock) while CS is in “L”.
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
X
–
Remark X = Don’t care.
Figure 13 WREN Operation
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
15
3. Write disable (WRDI)
The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select
(CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI
instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”.
Bit WEL is reset after the operations shown below.
• The power supply voltage is dropping
• Power on
• After performing WRDI
• After the completion of Write operation by the WRSR instruction
• After the completion of Write operation by the WRITE instruction
• After setting the WP pin to “L”
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
X
Remark X = Don’t care.
Figure 14 WRDI Operation
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
16
4. Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the Write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) “L” first. After that, input the instruction code from serial data input (SI). The status of bit in the
status register is output from serial data output (SO). Sequential Read is available for the status register. To stop the
Read cycle, set CS to “H”.
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits BP1 and BP0 can be acquired
by performing a new RDSR instruction after verifying the completion of the write cycle.
b7, b6, b5, b4 are “1” when they are read by the RDSR instruction.
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 10111213141516
Outputs Data in the Status Register
b7 b6 b5 b7b0b1b2b3b4
X
Remark X = Don’t care.
Figure 15 RDSR Operation
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
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5. Write in the status register (WRSR)
The values of status register (BP1, BP0) can be rewritten by inputting the WRSR instruction. But b7, b6, b5, b4, b1, b0 of
status register cannot be rewritten. b7 to b4 are always “1” when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below.
Set the chip select ( CS ) “L” first. After that, input the instruction code and data from serial data input (SI). To start
WRSR Write (tPR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial clock.
It is possible to confirm the operation status by reading the value of bit WIP during WRSR Write. Bit WIP is “1” during
Write, “0” during any other status. Bit WEL is reset when Write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the Read
Only memory; can be changed. But if the signal WP is in “L”, S-25C010A/020A/040A does not send the WRSR
instruction (Refer to “ Protect Operation”).
Bit BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly
updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16clock) while CS is in “L”.
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
9 10111213141516
Inputs Data in the Status Register
b7 b6 b5 b0b1b2b3b4
X
Remark X = Don’t care.
Figure 16 WRSR Operation
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
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6. Read memory data (READ)
The Read operation is shown below. Input the instruction code and the address from serial data input (SI) after inputting
“L” to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the address is output
from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in “L”, the address is automatically incremented so
that data in the following address is sequentially output. The address counter rolls over to the first address by increment
in the last address.
To finish the Read cycle, set CS to “H”. It is possible to raise the chip select always during the cycle. During Write, the
read instruction code is not be accepted or operated.
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 1011 1314151617
8-bit Address
A7
*1
A6 A5 A0A1A2A3
Outputs the First Byte
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D7
Outputs
the Second
A4
12
X
*1 In the S-25C010A, A7 = Don’t care because the address range is A6 to A0.
Remark X = Don’t care.
Figure 17 READ Operation (S-25C010A/020A)
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
19
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High / Low
9 1011 1314151617
8-bit Address
A7 A6 A5 A0A1A2A3
Outputs the First Byte
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D7
Outputs
the Second
A4
12
A8
*1
*1 In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure 18 READ Operation (S-25C040A)
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
20
7. Write memory data (WRITE)
Figure 19 and 20 show the timing chart when inputting 1-byte data. Input the instruction code, the address and data
from serial data input (SI) after inputting “L” to the chip select ( CS ). To start Write (tPR), set the chip select ( CS ) to “H”
after inputting data or before inputting a rising of the next serial clock. Bit WIP is reset to “0” when Write has completed.
The S-25C010A/020A/040A can Page Write of 16 bytes. Its function to transmit data is as same as Byte Write basically,
but it operates Page Write by receiving sequential 8-bit Write data as much data as page size has. Input the instruction
code, the address and data from serial data input (SI) after inputting “L” in CS , as the WRITE operation (page) shown in
Figure 21 and 22. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit sequentially. At
the end, by setting CS to “H”, the WRITE operation starts (tPR).
4 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus,
even if Write data exceeds 16 bytes, the higher bits in the address do not change. And 4 of lower bits in the address roll
over so that Write data which is previously input is overwritten.
These are cases when the WRITE instruction is not accepted or operated.
• Bit WEL is not set to “1” (not set to “1” beforehand immediately before the WRITE instruction)
• During Write
• The address to be written is in the protect area by BP1 and BP0.
• The signal WP is in “L”.
To cancel the WRITE instruction, input the clock different from a specified value (n = 16+m × 8clock) while CS is in “L”.
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
21
SO
WP
CS
High-Z
High
SCK
123456789 1011 131415161718 19 20 21 22 23 2412
SI
Instruction 8-bit Address
A7
*1
A6 A5 A0A1A2A3
A4 A7 A6 A5 A0A1A2A3
A4
Data Byte 1
X
*1 In the S-25C010A, A7 = Don’t care because the address range is A6 to A0.
Remark X = Don’t care.
Figure 19 WRITE Operation (1-byte) (S-25C010A/020A)
SO
WP
CS
High-Z
High
SCK
123456789 1011 131415161718 19 20 21 22 23 2412
SI
Instruction 8-bit Address
A7 A6 A5 A0A1A2A3
A4 A7 A6 A5 A0A1A2A3
A4
Data Byte 1
A8
*1
*1 In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure 20 WRITE Operation (1-byte ) (S-25C040A)
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
22
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
91011 14151617
8-bit Address
A7
*1
A6 A5
A0A1A2
Data Byte (n) Data Byte (n + x)
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D0D1D2D3
D4A3A4
12 13
X
*1 In the S-25C010A, A7 = Don’t care because the address range is A6 to A0.
Remark X = Don’t care.
Figure21 WRITE Operation (page) (S-25C010A/020A)
SO
SCK
WP
CS
SI
Instruction
High-Z
12345678
High
91011 14151617
8-bit Address
A7 A6 A5
A0A1A2
Data Byte (n) Data Byte (n + x)
D4D5D6D7
18 19 20 21 22 23 24
D0D1D2D3 D0D1D2D3
D4A3A4
12 13
A8
*1
*1 In the S-25C040A, assign bit A8 in the address into the fifth bit in an instruction code.
Figure22 WRITE Operation (page) (S-25C040A)
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
23
Protect Operation
Table 18 shows the block settings of Write protect. Setting value in Protect Bit (BP1, BP0) in the status register protects
data in the area of all/50%/25% of the memory address.
Setting signal WP to “L” provides the following settings.
• Write protect for the WRITE, WRSR instructions
• Reset bit WEL
Figure 9 and 10 show the Valid timing in Write protect and Invalid timing in Write protect.
Table 18 Block Settings of Write Protect
Status Register Area of Write Protect Address of Write Protect Block
BP1 BP0 S-25C040A S-25C020A S-25C010A
0 0 0 % None None None
0 1 25 % 180h to 1FFh C0h to FFh 60h to 7Fh
1 0 50 % 100h to 1FFh 80h to FFh 40h to 7Fh
1 1 100 % 000h to 1FFh 00h to FFh 00h to 7Fh
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
24
Hold Operation
The hold operation is used to pause serial communications without setting the device in the non-select status. In the hold
status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in “Don’t
care”. Be sure to set the chip select ( CS ) to “L” to set the device in the select status during the hold status.
Generally, during the hold status, the device holds the select status. But if setting the device in the non-select status, the
users can finish the operation even in progress.
Figure 23 shows the hold operation. Set Hold ( HOLD ) to “L” when the serial clock (SCK) is in “L”, Hold ( HOLD ) is
switched at the same time the hold status starts. If setting Hold ( HOLD ) to “H”, Hold ( HOLD ) is switched at the same
time the hold status ends.
Set Hold ( HOLD ) to “L” when the serial clock (SCK) is in “H”; the hold status starts when the serial clock goes in “L” after
Hold ( HOLD ) is switched. If setting Hold ( HOLD ) to “H”, the hold status ends when the serial clock goes in “L” after
Hold ( HOLD ) is switched.
SCK
HOLD
Hold status Hold status
Figure 23 Hold Operation
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
25
Write Protect Function during the Low Power Supply Voltage
The S-25C010A/020A/040A has a built-in detection circuit which operates with the low power supply voltage. The S-
25C010A/020A/040A cancels the Write operation (WRITE, WRSR) when the power supply voltage drops and power-on,
at the same time, goes in the Write protect status (WRDI) automatically to reset bit WEL. Its detection and release
voltages are 1.20 V typ. (Refer to Figure 24).
To operate Write, after the power supply voltage dropped once but rose to the voltage level which allows Write again, be
sure to set the Write Enable Latch bit (WEL) before operating Write (WRITE, WRSR).
In the Write operation, data in the address written during the low power supply voltage is not assured.
Cancel the Write instruction
Set in Write protect (WRDI) automatically
Release voltage (+V
DET
)
1.20 V typ.
Detection voltage (−V
DET
)
1.20 V typ.
Power supply voltage
Figure 24 Operation during Low Power Supply Voltage
Input Pin and Output Pin
1. Connection of input pin
All input pins in the S-25C010A/020A/040A have the CMOS structure. Do not set these pins in high impedance during
operation when you design. Especially, set the CS input in the non-select status “H” during power-on/off and standby.
The error Write does not occur as long as the CS pin is in the non-select status “H”. Set the CS pin to VCC via a resistor
(the pull-up resistor of 10 kΩ to 100 kΩ).
If the CS pin and the SCK pin change from “L” to “H” simultaneously, data may be input from the SI pin.
To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to pull
up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting the
WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.
2. Equivalent circuit of input pin and output
Figure 25 and 26 show the equivalent circuits of input pins in the S-25C010A/020A/040A. A pull-up and pull-down
elements are not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 27 shows the equivalent circuit of the output pin. This pin has the tri-state output of “H” level / “L” level / High-Z.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
26
2. 1 Input pin
CS, SCK
Figure 25 CS , SCK Pin
SI, WP, HOLD
Figure 26 SI, WP , HOLD Pin
2. 2 Output pin
SO
V
CC
Figure 27 SO Pin
3. Precautions for use
• Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the detailed
operation condition in the data sheet.
• Operations with moisture on the S-25C010A/020A/040A pins may occur malfunction by short-circuit between pins.
Especially, in occasions like picking the S-25C010A/020A/040A up from low temperature tank during the evaluation.
Be sure that not remain frost on the S-25C010A/020A/040A pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
SPI SERIAL E2PROM
Rev.4.3_01_C S-25C010A/020A/040A
27
Precautions
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
● SII Semiconductor Corporation claims no responsibility for any and all disputes arising out of or in connection with any
infringement of the products including this IC upon patents owned by a third party.
SPI SERIAL E2PROM
S-25C010A/020A/040A Rev.4.3_01_C
28
Product Name Structure
1. Product name
1. 1 8-Pin SOP (JEDEC), 8-Pin TSSOP
S-25Cxxxx 0I - xxxx x
Fixed
Product name
S-25C010A: 1 K-bit
S-25C020A: 2 K-bit
S-25C040A: 4 K-bit
Package name (abbreviation) and IC packing specification
J8T1: 8-Pin SOP (JEDEC) , Tape
T8T1: 8-Pin TSSOP, Tape
Environmental code
U: Lead-free (Sn 100%), halogen-free
G: Lead-free (for details, please contact our sales office)
1. 2 TMSOP-8, SNT-8A
S-25Cxxxx 0I - xxxx U
Fixed
Product name
S-25C010A: 1 K-bit
S-25C020A: 2 K-bit
S-25C040A: 4 K-bit
Package name (abbreviation) and IC packing specification
K8T3: TMSOP-8, Tape
I8T1: SNT-8A, Tape
Environmental code
U: Lead-free (Sn 100%), halogen-free
2. Packages
Package Name Drawing Code
Package Tape Reel Land
8-Pin SOP (JEDEC) Environmental code = G FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD −
Environmental code = U FJ008-Z-P-SD FJ008-Z-C-SD FJ008-Z-R-SD −
8-Pin TSSOP Environmental code = G FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD −
Environmental code = U FT008-Z-P-SD FT008-Z-C-SD FT008-Z-R-SD −
TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD −
SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
No. FJ008-A-P-SD-2.1
No.
TITLE
SCALE
UNIT mm
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.1
0.4±0.05
1.27
0.20±0.05
5.02±0.2
14
85
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT mm
5
8
1
4
ø2.0±0.05
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
5°max.
6.7±0.1
2.0±0.05
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT mm
QTY. 2,000
2±0.5
13.5±0.5
60°
2±0.5
ø13±0.2
ø21±0.8
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
SII Semiconductor Corporation
No. FJ008-Z-P-SD-2.0
No.
TITLE
SCALE
UNIT mm
SOP8J-Z-PKG Dimensions
FJ008-Z-P-SD-2.0
0.4
1.27
0.20±0.05
5.02
14
85
+0.20
-0.35
+0.11
-0.07
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT mm
5
8
1
4
ø1.5 min.
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
6.5
2.0±0.05
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-Z-Carrier Tape
No. FJ008-Z-C-SD-1.0
FJ008-Z-C-SD-1.0
+0.30
-0.25
SII Semiconductor Corporation
No.
TITLE
UNIT mm
SCALE QTY. 4,000
13.4±1.0
2±0.5
ø13±0.2
ø21±0.8
Enlarged drawing in the central part
SOP8J-Z-Reel
No. FJ008-Z-R-SD-1.0
FJ008-Z-R-SD-1.0
17.5±1.5
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
TSSOP8-Z-PKG Dimensions
No. FT008-Z-P-SD-1.0
FT008-Z-P-SD-1.0
0.15±0.07
3.00
0.65
0.2±0.1
14
5
8
+0.3
-0.2
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.2
-0.05
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-Z-Carrier Tape
No. FT008-Z-C-SD-1.0
FT008-Z-C-SD-1.0
+0.4
-0.2
6.6
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
Enlarged drawing in the central part
No. FT008-Z-R-SD-1.0
2±0.5
ø13±0.2
ø21±0.8
13.4±1.0
17.5±1.0
4,000
QTY.
TSSOP8-Z-Reel
FT008-Z-R-SD-1.0
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
2.90±0.2
85
0.2±0.1
0.65±0.1
0.13±0.1
14
TMSOP8-A-PKG Dimensions
No. FM008-A-P-SD-1.1
FM008-A-P-SD-1.1
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
0.30±0.05
1.00±0.1
1.05±0.05
1.5
2.00±0.05
4.00±0.1
3.25±0.05
4.00±0.1
1
4
58
TMSOP8-A-Carrier Tape
Feed direction
No. FM008-A-C-SD-2.0
FM008-A-C-SD-2.0
+0.1
-0
mm
No.
TITLE
SCALE
UNIT
SII Semiconductor Corporation
16.5max.
13.0±0.3
QTY. 4,000
(60°)
(60°)
13±0.2
Enlarged drawing in the central part
TMSOP8-A-Reel
No. FM008-A-R-SD-1.0
FM008-A-R-SD-1.0
mm
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT
1.97±0.03
0.2±0.05
0.48±0.02
0.08
mm
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.0
No. PH008-A-P-SD-2.0
0.5
+0.05
-0.02
123 4
56
78
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT mm
PH008-A-C-SD-1.0
SNT-8A-A-Carrier Tape
No. PH008-A-C-SD-1.0
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.1
2.25±0.05
0.65±0.05
0.25±0.05
2134
7865
5°
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0
mm
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
SII Semiconductor Corporation
No.
TITLE
SCALE
UNIT mm
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
0.3
0.2
0.52
2.01
0.52
No. PH008-A-L-SD-4.1
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.96 mm ~ 2.06 mm)
1.
2. 0.03 mm
3.
4. SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
1
2
1.
2. (1.96 mm ~ 2.06 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or
infringement of third-party intellectual property rights and any other rights due to the use of the information described
herein.
3. SII Semiconductor Corporation is not responsible for damages caused by the incorrect information described herein.
4. Take care to use the products described herein within their specified ranges. Pay special attention to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
SII Semiconductor Corporation is not responsible for damages caused by failures and/or accidents, etc. that occur
due to the use of products outside their specified ranges.
5. When using the products described herein, confirm their applications, and the laws and regulations of the region or
country where they are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products described herein, comply with the Foreign Exchange and Foreign Trade Act and all
other export-related laws, and follow the required procedures.
7. The products described herein must not be used or provided (exported) for the purposes of the development of
weapons of mass destruction or military use. SII Semiconductor Corporation is not responsible for any provision
(export) to those whose purpose is to develop, manufacture, use or store nuclear, biological or chemical weapons,
missiles, or other military use.
8. The products described herein are not designed to be used as part of any device or equipment that may affect the
human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems,
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aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle
use or other uses. Do not use those products without the prior written permission of SII Semiconductor Corporation.
Especially, the products described herein cannot be used for life support devices, devices implanted in the human
body and devices that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
SII Semiconductor Corporation is not responsible for damages caused by unauthorized or unspecified use of our
products.
9. Semiconductor products may fail or malfunction with some probability.
The user of these products should therefore take responsibility to give thorough consideration to safety design
including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing
injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products described herein are not designed to be radiation-proof. The necessary radiation measures should be
taken in the product design by the customer depending on the intended use.
11. The products described herein do not affect human health under normal use. However, they contain chemical
substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips
may be sharp. Take care when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products described herein, comply with the laws and ordinances of the country or region where
they are used.
13. The information described herein contains copyright information and know-how of SII Semiconductor Corporation.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to SII Semiconductor Corporation or a third party. Reproduction or copying of the information
described herein for the purpose of disclosing it to a third-party without the express permission of SII Semiconductor
Corporation is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
1.0-2016.01
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