QPro Family of XC1700D QML Serial Configuration PROMs - Xilinx, Inc.

DS070 (v2.1) June 1, 2000 www.xilinx.com 1

Product Specification 1-800-255-7778

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Features

• Certified to MIL-PRF-38535 Appendix A QML

(Qualified Manufacturer List ing.)

• Also av ailable under the following Standard Microcircuit

Drawings (SMD ): 5962-94717 and 5962-95617.

• Configuration one-time prog rammabl e (O TP) read-only

memory designed to store configuration bitstreams of

Xilinx FP GA d evice s

• On-chip address count er, increment ed by ea ch rising

edge on the clock inpu t

• Simple interf ace to the FPGA requires only one user

I/O p i n

• Cascadable for storing longer or multiple bitstreams

• Programmable reset pola rity (active High or active

Low) for compatibility with different FPG A solutions

• Lo w-power CMOS EPROM process

• Available in 5V version only

• Programming support by leading programmer

manufacturers.

• Design support using the Xilinx Alliance and

Found ation ser ies software packages.

Description

The XC1700D QPRO™ f amily of configuration PROMs pro-

vide an easy-to-use, cost-effect iv e method for storing Xilinx

FPGA configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA DIN pin. The

FP GA generate s the ap propri ate number of clock pulses to

complete the configuration. Once configured, it disabl es the

PROM. When the FPGA is in Slav e Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded wit h other members of the family.

For device program ming, either the Xilinx Al liance™ or the

Foundation™ series development systems compiles the

FP GA design f ile into a st andard HE X format wh ich is then

transferred to most commercial PROM programm ers.

0QPRO Family of XC1 700D QML

Configuration PROMs

DS070 (v2.1) June 1, 2000 02P rod uc t Sp ec if i c ation

Figure 1: S implif ie d B lo ck Diag ram (d oes not s how prog ra m m i ng ci rcuit)

EPROM

Cell

Matrix

Address Counter

DATA

Output

CLK

VCC VPP GND

DS027_01_021500

RESET/

OE/

RESET

or CEO

QPRO Family of XC1700D QML Configuration PROMs

2www.xilinx.com DS070 (v2. 1) June 1, 2000

1-800-255-7778 Product Specification

Pin Description

DATA

Data output, 3-stated when either CE or OE are inactive.

During programming, the DATA pin is I/O. Note that OE can

be programmed to be either a ctive High or active Low.

CLK

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

When High, t his input hol ds the ad dress counter res et and

3-states the DATA output. The polarity of this input pin is

progr ammab le as eithe r RESET/OE or OE/RESET. To a v oi d

confusion, this document descr ibes the p in as RESET/OE,

although the opposite polarity is possible on all devices.

When RESET is active, the address counter is held at zero,

and the DATA output is p ut in a high-impedance s tate. The

polarity of this input is programmable. The default is active

High RESET, but the preferred option is active Low RESET,

because it can be driven by the FPGA s INIT pin.

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 programmer software. Third-party programmers

have different methods to inve rt this pin.

When High, this pin disables the internal address counter,

3-states the D ATA output, and fo rces the device into low-ICC

standby mode.

CEO

Chip Enable o utput, to be connected to the CE input of the

next PROM in the daisy c hain. Thi s output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other w ords: when the PROM has been read,

CEO will follow C E as long as OE is ac tive. W hen OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

VPP

Programming voltage. No overshoot above the specified

max voltage is per mi tted o n t his pin . For norm al re ad oper-

ation, this pin must be connected to VCC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debug ging. Do not le ave

VPP floating!

VCC and GND

VCC is positiv e supply pin and GND is ground pin.

PROM Pinouts

Capacity

Number of Configuration Bits, Including

Header for Xilinx FPGAs and Compatible

PROMs

Pin Na m e 8-pi n

DATA 1

CLK 2

RESET/OE (OE/RESET)3

CE 4

GND 5

CEO 6

VPP 7

VCC 8

Device Configuration Bits

XC1736D 36,288

XC1765D 65,536

XC17128D 131,072

XC17256D 262,144

Device Co nf ig ur a tio n B its PROM

XC3000 /A series 14,81 9 to 94,984 XC1765D to

XC17128D

XC4000 ser ies 95,008 to 247,968 XC1712 8D to

XC17256D

XQ4005E 95,008 XC17128D

XQ40 10E 178,1 44 XC17256 D

XQ40 13E 247,9 68 XC17256 D

QP RO Fa mily of XC1700D QML Co nfiguration PROMs

DS070 (v2.1) June 1, 2000 www.xilinx.com 3

Product Specification 1-800-255-7778

Controlling PROMs

Connecting the FPGA device with the PROM.

•The DATA output(s) of the PROM(s) drives the DIN

input of the l ead FPGA device.

•The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s).

•The CEO output of a PROM dri ves the CE input of the

next PROM in a daisy chain (if any).

•The RESET/OE input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

when a reconfiguration is initiated by a VCC glitch.

Other m ethods —such as driving RESET/OE from LDC

or system reset—assume the PROM internal

power-on-reset is always in step with the FPGA’s

internal power-on-reset. This may not be a safe

assumption.

•The PROM CE input can be driven from ei ther the LDC

or DONE pins. Using LDC avoids potential contention

on the DIN pin .

•The CE input of the lead (or only) PROM is driven by

the DONE output of the lead FPGA device, provided

that DONE is not permanently grounded. Otherwise,

LDC can be used to drive CE, but must then be

unconditionally High during user operation. CE can

also be per m anently tied Low, but this ke eps the DATA

output active and causes an unnecessary supply

current of 10 mA maximum.

FPGA Mast er Serial Mod e Summa ry

The I/O and l ogic f unc tions of the Configurable Logic B lock

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the state of th e three FP GA m ode pin s. In Master Ser ial

mode, the FPGA automat ically loads the configuration pro-

gram from an external memory. The Xilinx PROMs have

been designed for compatibility with the Master Serial

mode.

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the PROM sequentially on a single data line. S yn-

chronization is provided by t he rising edge of the temporary

signal CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line and two control lines are

required to configure an FPGA. Data from the PROM is

read sequenti ally, accessed via the internal address and bit

coun ters which a re incremented on ever y va lid risin g edge

of CCLK.

If the user-programmable, dual-function DIN pin on the

FPGA is used only for configuration, it m ust still be held at a

defined level during normal operation. Xilinx FPGAs take

care of this automatically with an on-chip default pull-up

resistor.

Programming the FPGA With Counters

Unchanged Upon Co mpletion

When multiple FPGA-configurations for a single FPGA are

stored in a PROM, the OE pin should be tied Low. Upon

power-up, t he i nternal ad dress count ers are reset and con-

figuration begins with the first program stored in memory.

Since the OE pi n is h eld Low, the address count ers are l eft

unchanged after configuration is complete. Therefore, to

reprogram the FPGA with another program, the DO NE line

is pulled Low and configuration begins at the last value of

the address counters.

This method f a ils if a user applies RESET duri ng the FPGA

configuration process. The FPGA aborts the configuration

and th en restar ts a new configuration, as i ntended, but the

PROM does not reset its address counter, since it never

saw a High level on its OE input. The new configuration,

therefore, reads the remaining dat a in the P ROM and inter-

prets it as preamble, length count etc. Since the FPGA is

the master, it issues the necessary number of CCLK pulses,

up to 16 million (224) and DONE goes High. However, the

FPGA configuration will be completely wrong, with potential

contentions inside the FPGA and on its output pins. This

method must, therefore, never be used when there is any

chance of external reset during configuration.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for

future FPGAs requiring larger configuration memories, cas-

cade d PROM s provide additiona l memory. After the last bit

from the first PROM is read, the next clock signal to the

PROM asserts its CEO output Low and disables its DATA

line. The second PROM recognizes the Low level on its CE

input and enables its DATA output. See Figure 2.

After configuration is complete, the address counters of all

cascaded PROMs are reset if the FPGA RESET pin goes

Low, assuming the PROM reset polarity option has been

inverted.

To reprogram the FPGA with another program, the DONE

line g oes Low and c onfiguration begins where the address

counters had stopped. In this case, avoid contention

between DATA and the configured I/O use of DIN.

QPRO Family of XC1700D QML Configuration PROMs

4www.xilinx.com DS070 (v2. 1) June 1, 2000

1-800-255-7778 Product Specification

Figure 2: Master Serial Mode. The one-time-programmable PR OM supports automatic loading of configuration program s.

Multiple devices can be cas caded to support additional FPGAs. An ea rly DONE inhibits the PROM d ata output one CCLK

cycle bef ore the FPGA I/Os become activ e.

DIN

DOUT

CCLK

INIT

DONE

PROM

DATA

CLK

CE CE

FPGA

(Low Resets the Address Pointer)

* For mode pin connections,

refer to the appropriate FPGA data sheet.

Vcc

VCC

OPTIONAL

Daisy-chained

FPGAs with

Different

configurations

OPTIONAL

Slave FPGAs

with Identical

Configurations

RESET RESET

DS027_02_052200

CCLK

(Output)

DIN

DOUT

(Output)

OE/RESET

MODES*

VPP

Cascaded

Serial

Memory

DATA

CLK

CEO

OE/RESET

3.3V

4.7K

QP RO Fa mily of XC1700D QML Co nfiguration PROMs

DS070 (v2.1) June 1, 2000 www.xilinx.com 5

Product Specification 1-800-255-7778

Standby M ode

The PROM enters a low-pow er standby mode whenev er CE

is asser ted High. The output remains in a high impedance

state regardless of the state of the OE input.

Programming

The devices ca n be programmed on programm ers supplied

by Xilinx or qualified third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently dam age the device.

Important: Always tie the VPP pin to VCC in you r application. Never leave VPP floating.

Table 1: Truth Table for XC1 700 Con trol Inp uts

Contro l Inputs

Internal Address

Outputs

RESET CE DATA CEO ICC

Inactive Low If address < TC: increment

If addres s > TC: don’t change Active

High-Z High

Low Active

reduced

Active Low Held reset High-Z High Active

Inactive High Not changing High-Z High Standby

Active High Held reset High-Z High Standby

Notes:

1. The XC1700 RESET input has programm able pola rit y

2. TC = Terminal Count = highest address value. TC + 1 = address 0.

QPRO Family of XC1700D QML Configuration PROMs

6www.xilinx.com DS070 (v2. 1) June 1, 2000

1-800-255-7778 Product Specification

XC1736D, XC1765D , XC17128D and XC17256D

Absolute Maximum Ratings

Operating Conditions

Note: During normal read operation VPP must be con nec ted to VCC

DC Characteristics Over Operating Condition

Symbol Description Units

VCC Suppl y voltage relative to GND –0.5 to +7.0 V

VPP Supply volt age relative to GND –0 .5 to +12.5 V

VIN Input voltage relativ e to GND –0 .5 to VCC + 0.5 V

VTS Voltage applied to High-Z output –0 .5 to VCC + 0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Max imum solder ing tempe rature (10s @ 1/16 in.) +260 °C

Notes:

1. Stresses beyond those l isted under Abs olute Maximum Ratings may cause permanent damage to the device. These are s tr ess

ratings onl y, and functional operation of t he de vice at these or any other condi tions beyond those list ed under O perati ng Conditions

is not imp lied. Exposure to Absolute Maxim um Ratings condition s for extended periods of time may affec t device reliability.

Symbol Description Min Max Units

VCC Supply voltage relative to GND (TC = –55°C to +125°C) Military 4.50 5.50 V

Symbol Description Min Max Units

VIH High -level input volt ag e 2.0 V CC V

VIL Low-l evel input voltage 0 0.8 V

VOH High-le vel output voltage (IOH = –4 m A) Military 3.7 - V

VOL Low-level output voltage (IOL = +4 mA) - 0.4 V

ICCA Supply current, active mode (at maximum frequency) - 10 mA

ICCS Su pply current, standby mode XC17 128D, XC17256D - 50 µA

XC1736D, XC1765D - 1.5 mA

ILInp ut or output leakage current –10 10 µA

CIN Input capacitance (VIN = GND, f = 1.0 MHz) sample tested - 10 pF

COUT Output capacitance (VIN = GND, f = 1.0 MHz) sample tested - 10 pF

QP RO Fa mily of XC1700D QML Co nfiguration PROMs

DS070 (v2.1) June 1, 2000 www.xilinx.com 7

Product Specification 1-800-255-7778

AC Characteristics Over Operating Condition(1,2)

Symbol Description

XC1736D

XC1765D XC17128D

XC17256D

UnitsMin Max Min Max

TOE OE to data delay - 45 - 25 ns

TCE CE to data delay - 60 - 45 ns

TCAC CLK to data delay - 15 0 - 50 ns

TOH Data hold from CE, O E, or CLK(3) 0-0-ns

TDF CE or OE to data float delay(3,4) -50-50ns

TCYC Clock periods 200 - 80 - ns

TLC CLK Low time(3) 100 - 20 - ns

THC CLK High time(3) 100 - 20 - ns

TSCE CE setup t ime to CLK (to gu arantee proper count ing) 25 - 20 - n s

THCE CE hold time to CL K (to guarantee proper counting) 0 - 0 - ns

THOE OE hold time (guarantees counters are reset) 100 - 20 - ns

Notes:

1. A C test load = 50 pF

2. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

3. Guaranteed by design, not tested.

4. Float delays are measure d with 5 pF AC loads. Transiti on is mea sured at ±200mV from steady stat e acti ve lev els.

RESET/OE

CLK

DATA TCE

TOE

TLC

TSCE TSCE THCE

THOE

TCAC TOH TDF

TOH

THC

DS027_03_021500

TCYC

QPRO Family of XC1700D QML Configuration PROMs

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1-800-255-7778 Product Specification

AC Characteristics Over Operating Condition When Cascading(1,2)

Symbol Description

XC1736D

XC1765D

XC17128D

XC17256D

UnitsMin Max Min Max

TCDF CLK to data float delay(3,4) - 50 - 50 ns

TOCK CLK to CEO del ay(3) - 65 - 30 ns

TOCE CE to CEO delay(3) - 45 - 35 ns

TOOE RESET/OE to CEO delay(3) - 40 - 30 ns

Notes:

1. A C test load = 50 pF

2. All AC parameters are measur ed wit h VIL = 0.0V and VIH = 3.0V.

3. Guaranteed by design, not tested.

4. Float delays are measure d with 5 pF AC loads. Transiti on is mea sured at ±200mV from steady stat e acti ve lev els.

RESET/OE

CLK

DATA

TOOE

CEO

First Bit Last Bit

TOCE

TOCK

TCDF

DS027_04_021500

TOCE

QP RO Fa mily of XC1700D QML Co nfiguration PROMs

DS070 (v2.1) June 1, 2000 www.xilinx.com 9

Product Specification 1-800-255-7778

Ordering Information

Valid Ordering Combinations

Mark in g Inform at ion

Due to the sm all size of the PR OM package, t he com ple te

ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified.

Device mar k ing is as follows.

Revision History

The following table shows the revision histor y for this docum ent

XC17128DDD8M XC17256DDD8M XC1736DDD8M XC1765DDD8M

5962-9561701MPA 5962-9471701MPA

XC17256D DD8 M

Operating Range/ P rocessing

M = Military (TC = –55° to +125°C)

B = Military (TC = –55° to +1 2 5°C)

QML cert ified to MIL-PRF-38 535

Package Type

DD8 = 8-pin Cera mic DIP

Device Number

XC1736D

XC1765D

XC17128D

XC17256D

Date Version Revision

02/08 /99 2.0 Removed the now obsole te Comm ercial and Industr ial Grade part numbers and design

support.

06/01/00 2. 1 Updated format and assigned data sheet number (DS070).

17256D DD8 M

Opera t ing Range/ P rocessing

M = Milit a ry ( TC = –55° to +12 5°C)

B = Military ( TC = –55° to +125°C)

QML certified to MIL-PRF-38535

Package Type

DD8 = 8-pin Ceramic DIP

Device Number

XC1736D

XC1765D

XC17128D

XC17256D

QPRO Family of XC1700D QML Configuration PROMs

10 www.xilinx.com DS070 (v2. 1) June 1, 2000

1-800-255-7778 Product Specification