HM678127UH Series 131072-word x 8-bit High Speed Static Access Memory Features Pin Arrangement * 131072-word x 8-bit organization * Directly TTL compatible input and output * Choice of 5.0 V or 3.3 V power supplies for output buffers * Completely static memory * No clock or timing strobe required * Super fast access time: 10/12 ns (max) * Revolutional pin arrangement A10 1 32 A11 A5 2 31 A12 A4 3 30 A6 A3 4 29 A7 CS 5 28 OE I/O0 6 27 I/O7 I/O1 7 26 I/O6 VCC 8 25 VSSO VSS 9 24 VCCO I/O2 10 23 I/O5 I/O3 11 22 I/O4 WE 12 21 A13 A0 13 20 A14 A1 14 19 A15 A2 15 18 A16 A9 16 17 A8 Ordering Information Access Type No. time Package --------------------------------------------- HM678127UHJ-10 10 ns 400 mil 32 pin --------------------------- Plastic SOJ HM678127UHJ-12 12 ns (CP-32DB) --------------------------------------------- (Top View) Pin Description Pin name Function ----------------------------------------- A0 - A16 Address input ----------------------------------------- I/O0 - I/O7 Data input/output ----------------------------------------- WE Write enable ----------------------------------------- CS Chip select ----------------------------------------- OE Output enable ----------------------------------------- VCC +5 V power supply VCCO Output buffer power supply VSSO Output buffer ground VSS Ground ----------------------------------------- ----------------------------------------- ----------------------------------------- ----------------------------------------- 1 HM678127UH Series HM678127UH Series Block Diagram A0 VCC VCCO VSSO VSS Memory Matrix 512 x 2048 Row Decoder A7 A16 I/O0 Column I/O Input Data Control I/O7 Column Decoder A8 CS WE OE A15 Read / Write Control Function Table Input --------------- CS WE OE Output Mode VCC current Reference cycle -------------------------------------------------------------------------------------- H X X High-Z Not selected ISB, ISB1 -- -------------------------------------------------------------------------------------- L H H High-Z Output disable ICC, ICC1 -- -------------------------------------------------------------------------------------- L H L Data out Read ICC, ICC1 Read cycle 1, 2, 3 -------------------------------------------------------------------------------------- L L H Data in Write ICC, ICC1 Write cycle 1, 2, 3, 4 -------------------------------------------------------------------------------------- L L L Data in Write ICC, ICC1 Write cycle 5, 6 -------------------------------------------------------------------------------------- Note: 2 X: H or L HM678127UH Series HM678127UH Series Absolute Maximum Ratings Parameter Symbol Value Unit -------------------------------------------------------------------------------------- Supply voltage*1 VCC -0.5 to +7.0 V -------------------------------------------------------------------------------------- Voltage on any pin relative to VSS*1 VT -0.5 to VCC + 0.5 V -------------------------------------------------------------------------------------- Power dissipation 1.0*2, 1.3*3 PT W -------------------------------------------------------------------------------------- Operating temperature range Topr 0 to +70 C -------------------------------------------------------------------------------------- Storage temperature range (with bias) Tstg(bias) -10 to +85 C -------------------------------------------------------------------------------------- Storage temperature range Tstg -55 to +125 C -------------------------------------------------------------------------------------- Notes: 1. With respect to VSS = VSSO 2. Under the transverse air flow < 500 linear feet/minute 3. Under the transverse air flow 500 linear feet/minute For the DC and AC specifications shown in these tables, this device was tested under a minimum transverse air flow exceeding 500 linear feet per minute. Recommended DC Operating Conditions (0C Ta +70C) Parameter Symbol Min Typ Max Unit -------------------------------------------------------------------------------------- Supply voltage VCC 4.5 5.0 5.5 V ------------------------------------------------------------------------------ 5 V TTL compatible VCCO 4.5 5.0 5.5 V ------------------- -------------------------------------------- 3.3 V TTL compatible 3.0 3.3 3.6 V ------------------------------------------------------------------------------ VSS, VSSO 0.0 0.0 0.0 V -------------------------------------------------------------------------------------- Input high voltage VIH 2.2 -- VCC + 0.5 V -------------------------------------------------------------------------------------- Input low voltage VIL -0.5 -- 0.8 V -------------------------------------------------------------------------------------- 3 HM678127UH Series HM678127UH Series DC Characteristics (VCC = 5.0 V 10%, VCCO = 5.0 V 10 % or 3.3 V 0.3 V, VSS = VSSO = 0 V, Ta = 0 to +70C) HM678127UH --------------------- -10 -12 ---------- ---------- Parameter Symbol Min Max Min Max Unit Test conditions -------------------------------------------------------------------------------------- Input leakage current |ILI| -- 2 -- 2 A VCC = 5.5 V, VIN = 0 V to VCC -------------------------------------------------------------------------------------- Output leakage current |ILO| -- 10 -- 10 A CS = VIH or OE = VIH, WE = VIL, VI/O = 0 V to VCCO -------------------------------------------------------------------------------------- Operating power supply current ICC -- 120 -- 120 mA CS = VIL, II/O = 0 mA -------------------------------------------------------------------------------------- Average operating current ICC1 -- 200 -- 190 mA Min. cycle, II/O = 0 mA -------------------------------------------------------------------------------------- Standby power supply current ISB -- 45 -- 45 mA CS = VIH --------------------------------------------------------------- ISB1 -- 35 -- 35 mA CS VCC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V -------------------------------------------------------------------------------------- Output low voltage VOL -- 0.4 -- 0.4 V IOL = 8 mA -------------------------------------------------------------------------------------- Output high voltage VOH 2.4 -- 2.4 -- V IOH = -4 mA -------------------------------------------------------------------------------------- Capacitance (Ta =25C, f=1 MHz) Parameter Symbol Max Unit Test condition -------------------------------------------------------------------------------------- Input capacitance CIN*1 6 pF VIN = 0 V -------------------------------------------------------------------------------------- Input/output capacitance CI/O*1 10 pF VI/O = 0 V -------------------------------------------------------------------------------------- Note: 4 1. This parameter is sampled and has not been 100% tested. HM678127UH Series HM678127UH Series AC Characteristics (VCC = 5 V 10%, VCCO = 5.0 V 10 % or 3.3 V 0.3 V, VSS = VSSO = 0 V, Ta = 0 to +70C, unless otherwise noted) Test conditions * Input pulse levels: VSS to 3.0 V * Input timing reference levels: 1.5 V * Output load: See figure * Input rise and fall time: 4 ns * Output reference level: 1.5 V +5V +5V 480 Output 255 480 Output 30 pF *1 255 5 pF *1 Output load A Output load B (for t HZ , t LZ , t OHZ , tOLZ , tWZ & OW t ) Note: 1. including scope and jig capacitance Read Cycle HM678127UH ------------------------- -10 -12 ------------ ------------ Parameter Symbol Min Max Min Max Unit -------------------------------------------------------------------------------------- Read cycle time tRC 10 -- 12 -- ns -------------------------------------------------------------------------------------- Address access time tAA -- 10 -- 12 ns -------------------------------------------------------------------------------------- Chip select access time tACS -- 10 -- 12 ns -------------------------------------------------------------------------------------- Chip selection to output in low-Z tLZ*1, *2 3 -- 4 -- ns -------------------------------------------------------------------------------------- Output enable to output valid tOE -- 5 -- 6 ns -------------------------------------------------------------------------------------- Output enable to output in low-Z tOLZ*1, *2 0 -- 0 -- ns -------------------------------------------------------------------------------------- Chip deselection to output in high-Z tHZ*1, *2 0 5 0 6 ns -------------------------------------------------------------------------------------- Output hold from address change tOH 3 -- 4 -- ns -------------------------------------------------------------------------------------- Notes: 1. This parameter is sampled and has not been 100% tested. 2. Transition is measured 200 mV from steady state voltage with specified loading in Load (B). 5 HM678127UH Series HM678127UH Series Write Cycle HM678127UH ------------------------------ Parameter Symbol -10 -12 -------------- -------------- Min Min Max Max Unit -------------------------------------------------------------------------------------- Write cycle time tWC*1 10 - 12 - ns -------------------------------------------------------------------------------------- Chip selection to end of write tCW 8 - 10 - ns -------------------------------------------------------------------------------------- Address valid to end of write tAW 8 - 10 - ns -------------------------------------------------------------------------------------- Address setup time tAS 0 - 0 - ns -------------------------------------------------------------------------------------- Write pulse width tWP 8 - 10 - ns -------------------------------------------------------------------------------------- Write recovery time tWR 0 - 0 - ns -------------------------------------------------------------------------------------- Data valid to end of write tDW 5 - 6 - ns -------------------------------------------------------------------------------------- Data hold time tDH 0 - 0 - ns -------------------------------------------------------------------------------------- Write enable to output in high-Z tWZ*2, *3 0 5 0 6 ns -------------------------------------------------------------------------------------- Output disable to output in high-Z tOHZ*2, *3 0 5 0 6 ns -------------------------------------------------------------------------------------- Output active from end of write tOW*2, *3 0 - 0 - ns -------------------------------------------------------------------------------------- Notes: 6 1. All write cycle timings are referred from the last valid address to the first transitioning address. 2. This parameter is sampled and has not been 100% tested. 3. Transition is measured 200 mV from steady state voltage with specified loading in Load (B). HM678127UH Series HM678127UH Series Timing Waveforms Read Cycle 1 t RC Address t AA OE t OH t OE t OLZ CS t OHZ t HZ t ACS t LZ Data Out Valid Data High Impedance Note: 1. WE = VIH Read Cycle 2 t RC Address t OH Data Out Notes: Previous Valid Data t AA t OH Valid Data 1. WE = VIH 2. CS = VIL 3. OE = VIL 7 HM678127UH Series HM678127UH Series Read Cycle 3 t RC CS t HZ t ACS t LZ Valid Data Data Out High Impedance Notes: 1. WE = VIH 2. OE = VIL 3. Address valid prior to or coincident with CS transition low. Write Cycle 1 (OE = H, WE Controlled) t WC Address t CW CS t AS t AW t WR t WP WE *1 t DW Data In Data Out Note: 8 t DH Valid Data High Impedance 1. A write occurs during the overlap of a low CS and a low WE (tWP). HM678127UH Series HM678127UH Series Write Cycle 2 (OE = H, CS Controlled) t WC Address t AS t CW CS t WR t AW WE *1 t WP t DH t DW Data In Valid Data High Impedance Data Out Note: 1. A write occurs during the overlap of a low CS and a low WE (tWP). Write Cycle 3 (OE = clocked, WE controlled) t WC Address OE t CW CS t AW t AS t WR t WP *1 WE t OHZ t OLZ *2 High Impedance Data Out t DW Data In Notes: *2 High Impedance Valid Data t DH High Impedance 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 9 HM678127UH Series HM678127UH Series Write Cycle 4 (OE = clocked, CS controlled) t WC Address *2 OE t AS t CW CS t WR t AW *1 t WP WE t DW Data In Data Out Notes: t DH Valid Data High Impedance 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in a high impedance state. Write Cycle 5 (OE = L, WE controlled) t WC Address t CW CS t WR t AW t AS t WP WE *1 t OH t WZ *2 t OW High Impedance Data Out t DW Data In Notes: 10 High Impedance Valid Data *3 t DH *4 High Impedance 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. During this period, I/O pins are output state so that the input signals of opposite phase to the outputs must not be applied. 3. Output data is the same phase of write data of this write cycle. 4. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. HM678127UH Series HM678127UH Series Write Cycle 6 (OE = L, CS controlled) t WC Address t AS t CW CS t WR t AW t WP WE t LZ t WZ *2 Data Out *1 High Impedance t DW Data In Notes: High Impedance t DH Valid Data 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. If the CS low transition occurs after the WE low transition, output remain in a high impedance state. 11