2 Ps/DIV
10 pF
VS = 10V, AV = +1, RL = 1 M:
2000 pF
10,000 pF
20,000 pF
5V/DIV
0.1 1 10 100 1000
ISOURCE (mA)
0.01
0.1
1
10
100
VOUT FROM RAIL (V)
125°C
85°C
-40°C
25°C
VS = 30V
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LM7332
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LM7332 Dual Rail-to-Rail Input and Output 30-V, Wide Voltage Range, High Output,
Operational Amplifier
1 Features 3 Description
The LM7332 device is a dual rail-to-rail input and
1• VS= ±15 V, TA= 25°C, Typical Values Unless output amplifier with a wide operating temperature
Specified range (−40°C to +125°C) that meets the needs of
• Wide Supply Voltage Range 2.5 V to 32 V automotive, industrial, and power supply applications.
• Wide Input Common Mode Voltage 0.3 V Beyond The LM7332 has an output current of 100 mA, which
is higher than that of most monolithic operational
Rails amplifiers. Circuit designs with high output current
• Output Short Circuit Current > 100 mA requirements often require discrete transistors
• High Output Current (1 V from Rails) ±70 mA because many operational amplifiers have low
• GBWP 21 MHz current output. The LM7332 has enough current
output to drive many loads directly, saving the cost
• Slew Rate 15.2 V/µs and space of the discrete transistors.
• Capacitive Load Tolerance Unlimited The exceptionally wide operating supply voltage
• Total Supply Current 2 mA range of 2.5 V to 32 V alleviates any concerns over
• Temperature Range −40°C to +125°C functionality under extreme conditions and offers
• Tested at −40°C, +125°C, flexibility of use in a multitude of applications. Most
and +25°C at 5 V, ±5 V, ±15 V parameters of this device are insensitive to power
supply variations; this design enhancement is another
step in simplifying usage. Greater than rail-to-rail
2 Applications input common mode voltage range allows operation
• MOSFET and Power Transistor Driver in many applications, including high-side and low-side
• Replaces Discrete Transistors in High Current sensing, without exceeding the input range.
Output Circuits The LM7332 can drive unlimited capacitive loads
• Instrumentation 4–20 mA Current Loops without oscillations.
• Analog Data Transmission The LM7332 is offered in the 8-pin VSSOP and SOIC
• Multiple Voltage Power Supplies and Battery packages.
Chargers Device Information(1)
• High-Side and Low-Side Current Sensing PART NUMBER PACKAGE BODY SIZE (NOM)
• Bridge and Sensor Driving VSSOP (8) 3.00 mm × 3.00 mm
• Digital-to-Analog Converter Output LM7332 SOIC (8) 3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Swing vs Sourcing Current Large Signal Step Response for Various
Capacitive Loads
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.3 Feature Description................................................. 17
1 Features.................................................................. 17.4 Device Functional Modes........................................ 18
2 Applications ........................................................... 18 Application and Implementation ........................ 20
3 Description............................................................. 18.1 Application Information............................................ 20
4 Revision History..................................................... 28.2 Typical Application ................................................. 20
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 22
6 Specifications......................................................... 410 Layout................................................................... 23
6.1 Absolute Maximum Ratings ..................................... 410.1 Layout Guidelines ................................................. 23
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 23
6.3 Recommended Operating Conditions....................... 410.3 Output Short Circuit Current and Dissipation
6.4 Thermal Information.................................................. 4Issues....................................................................... 23
6.5 5-V Electrical Characteristics................................... 511 Device and Documentation Support................. 26
6.6 ±5-V Electrical Characteristics ................................ 611.1 Community Resources.......................................... 26
6.7 ±15-V Electrical Characteristics .............................. 711.2 Trademarks........................................................... 26
6.8 Typical Characteristics.............................................. 911.3 Electrostatic Discharge Caution............................ 26
7 Detailed Description............................................ 17 11.4 Glossary................................................................ 26
7.1 Overview................................................................. 17 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 17 Information........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B Page
• Added Device Information, ESD Ratings and Thermal Information table, Feature Description section, Device
Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...... 1
Changes from Original (March 2013) to Revision A Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 20
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OUT B
1
2
3
45
6
7
8
OUT A
IN- A
IN+ A
V-
V+
IN- B
IN+ B
-
+
-
+
A
B
OUT B
1
2
3
4 5
6
7
8
OUT A
IN- A
IN+ A
V-
V+
IN- B
IN+ B
-
+
-
+
A
B
LM7332
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
D Package
8-Pin SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN+ A 3 I Noninverting Input for Amplifier A
IN– A 2 I Inverting Input for Amplifier A
IN+ B 5 I Noninverting Input for Amplifier B
IN– B 6 I Inverting Input for Amplifier AB
OUT A 1 O Output for Amplifier A
OUT B 7 O Output for Amplifier B
V+8 P Positive Supply
V–4 P Negative Supply
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)(2)
MIN MAX UNIT
VIN differential ±10 V
Output short-circuit duration See (3)(4)
Supply voltage (VS= V+– V−) 35 V
Voltage at input/output pins V++ 0.3 V−−0.3 V
Junction temperature(5) 150 °C
Infrared or convection (20 sec.) 235 °C
Soldering information Wave soldering (10 sec.) 260 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(4) Short-circuit test is a momentary test. Output short circuit duration is infinite for VS≤6 V at room temperature and below. For VS> 6 V,
allowable short circuit duration is 1.5 ms.
(5) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000
V(ESD) Electrostatic discharge V
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions MIN MAX UNIT
Supply voltage (VS= V+– V−) 2.5 32 V
Temperature range(1) −40 125 °C
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information LM7332
THERMAL METRIC(1) DGK (VSSOP) D (SOIC) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance (2) 161.1 109.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55 55.8 °C/W
RθJB Junction-to-board thermal resistance 80.5 49.2 °C/W
ψJT Junction-to-top characterization parameter 5.5 10.7 °C/W
ψJB Junction-to-board characterization parameter 79.2 48.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
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6.5 5-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = 0.5 V, VO= 2.5 V, and RL> 1 MΩ
to 2.5 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
VCM = 0.5 V and VCM = 4.5 V −4 ±1.6 4
VOS Input offset voltage mV
At the temperature extremes –5 5
Input offset voltage temperature
TC VOS VCM = 0.5 V and VCM = 4.5 V (4) ±2 µV/°C
drift See (5) −2 ±1 2
IBInput bias current µA
At the temperature extremes −2.5 2.5
20 250
IOS Input offset current nA
At the temperature extremes 300
0 V ≤VCM ≤3 V 67 80
At the temperature extremes 65
CMRR Common-mode Rejection Ratio dB
0 V ≤VCM ≤5 V 62 70
At the temperature extremes 60
5 V ≤V+≤30 V 78 100
PSRR Power supply Rejection Ratio dB
At the temperature extremes 74
−0.3 −0.1
CMRR > 50 dB 5.1
Input common-mode Voltage
CMVR V
Range 5.3 0
At the temperature extremes 5
0.5 V ≤VO≤4.5 V 70 77
RL= 10 kΩto 2.5 V
AVOL Large signal Voltage Gain dB
At the temperature extremes 65
RL= 10 kΩto 2.5 V 60 150
VID = 100 mV
At the temperature extremes 200
Output swing
high RL= 2 kΩto 2.5 V 100 300
VID = 100 mV
At the temperature extremes 350 mV from
VOeither rail
RL= 10 kΩto 2.5 V 5 150
VID =−100 mV
At the temperature extremes 200
Output swing
low RL= 2 kΩto 2.5 V 20 300
VID =−100 mV
At the temperature extremes 350
Sourcing from V+, VID = 200 mV(6) 60 90
ISC Output short circuit current mA
Sinking to V−, VID = –200 mV(6) 60 90
IOUT Output current VID = ±200 mV, VO= 1 V from rails ±55 mA
No Load, VCM = 0.5 V 1.5 2.3
ISTotal supply current mA
At the temperature extremes 2.6
AV= +1, VI= 5-V Step, RL= 1 MΩ,
SR Slew rate(7) 12 V/µs
CL= 10 pF
fuUnity-gain frequency RL= 10 MΩ, CL= 20 pF 7.5 MHz
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing in the device.
(6) Short-circuit test is a momentary test. Output short circuit duration is infinite for VS≤6 V at room temperature and below. For VS> 6 V,
allowable short circuit duration is 1.5 ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
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5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5 V, V−= 0 V, VCM = 0.5 V, VO= 2.5 V, and RL> 1 MΩ
to 2.5 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
GBWP Gain bandwidth product f = 50 kHz 19.3 MHz
enInput-referred voltage noise f = 2 kHz 14.8 nV/√HZ
inInput-referred current noise f = 2 kHz 1.35 pA/√HZ
AV= +2, RL= 100 kΩ, f = 1 kHz,
THD+N Total harmonic distortion + noise −84 dB
VO= 4 VPP
CT Rej. Crosstalk rejection f = 3 MHz, Driver RL= 10 kΩ68 dB
6.6 ±5-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +5 V, V−=−5 V, VCM = 0 V, VO= 0 V, and RL> 1 MΩto
0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
VCM =−4.5 V and VCM = 4.5 V −4 ±1.6 4
VOS Input offset voltage mV
At the temperature extremes −5 5
Input offset voltage temperature
TC VOS VCM =−4.5 V and VCM = 4.5 V (4) ±2 µV/°C
drift See (5) −2 ±1 2
IBInput bias current µA
At the temperature extremes −2.5 2.5
20 250
IOS Input offset current nA
At the temperature extremes 300
−5 V ≤VCM ≤3 V 74 88
At the temperature extremes 75
CMRR Common-mode rejection ratio dB
−5 V ≤VCM ≤5 V 70 74
At the temperature extremes 65
5 V ≤V+≤30 V, VCM =−4.5 V 78 100
PSRR Power supply rejection ration dB
At the temperature extremes 74
CMRR > 50 dB 5.1 –5.3 –5.1
Input common-mode voltage
CMVR V
range At the temperature extremes 5 5.3 –5.1
−4 V ≤VO≤4 V 72 80
RL= 10 kΩto 0 V
AVOL Large signal voltage gain dB
At the temperature extremes 70
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing in the device.
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±5-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +5 V, V−=−5 V, VCM = 0 V, VO= 0 V, and RL> 1 MΩto
0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
RL= 10 kΩto 0 V 75 250
VID = 100 mV
At the temperature extremes 300
Output swing
high RL= 2 kΩto 0 V 125 350
VID = 100 mV
At the temperature extremes 400 mV from
VOeither rail
RL= 10 kΩto 0 V 10 250
VID =−100 mV
At the temperature extremes 300
Output swing
low RL= 2 kΩto 0V 30 350
VID =−100 mV
At the temperature extremes 400
Sourcing from V+, VID = 200 mV (6) 90 120
ISC Output short circuit current mA
Sinking to V−, VID =−200 mV (6) 90 100
IOUT Output current VID = ±200 mV, VO= 1 V from rails ±65 mA
No Load, VCM =−4.5 V 1.5 2.4
ISTotal supply current mA
At the temperature extremes 2.6
AV= +1, VI= 8-V step, RL= 1 MΩ,
SR Slew rate(7) 13.2 V/µs
CL= 10 pF
ROUT Close-loop output resistance AV= +1, f = 100 kHz 3 Ω
fuUnity-gain frequency RL= 10 MΩ, CL= 20 pF 7.9 MHz
GBWP Gain bandwidth product f = 50 kHz 19.9 MHz
enInput-referred voltage noise f = 2 kHz 14.7 nV/√HZ
inInput-referred current noise f = 2 kHz 1.3 pA/√HZ
AV= +2, RL= 100 kΩ, f = 1 kHz
THD+N Total harmonic distortion + noise −87 dB
VO= 8 VPP
CT Rej. Crosstalk rejection f = 3 MHz, driver RL= 10 kΩ68 dB
(6) Short-circuit test is a momentary test. Output short circuit duration is infinite for VS≤6 V at room temperature and below. For VS> 6 V,
allowable short circuit duration is 1.5 ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
6.7 ±15-V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +15 V, V−=−15 V, VCM = 0 V, VO= 0 V, and RL> 1 MΩ
to 0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
VCM =−14.5 V and VCM = 14.5 V −5 ±2 5
VOS Input offset voltage mV
At the temperature extremes −6 6
Input offset voltage temperature VCM =−14.5 V and VCM = 14.5 V
TC VOS ±2 µV/°C
drift (4)
See (5) −2 ±1 2
IBInput bias current µA
At the temperature extremes −2.5 2.5
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ> TA.
(2) All limits are ensured by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage temperature drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
(5) Positive current corresponds to current flowing in the device.
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±15-V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +15 V, V−=−15 V, VCM = 0 V, VO= 0 V, and RL> 1 MΩ
to 0 V.(1)
PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT
20 250
IOS Input offset current nA
At the temperature extremes 300
−15 V ≤VCM ≤12 V 74 88
At the temperature extremes 74
CMRR Common-mode rejection ratio dB
−15 V ≤VCM ≤15 V 72 80
At the temperature extremes 72
−10 V ≤V+≤15 V, VCM =−14.5 V 78 100
PSRR Power supply rejection ratio dB
At the temperature extremes 74
−15.3 −15.1
CMRR > 50 dB 15.1
Input common-mode voltage
CMVR V
range 15.3 −15
At the temperature extremes 15
−14 V ≤VO≤14 V 72 80
RL= 10 kΩto 0 V
AVOL Large signal voltage gain dB
At the temperature extremes 70
RL= 10 kΩto 0 V 100 350
VID = 100 mV
At the temperature extremes 400
Output swing
high RL= 2 kΩto 0 V 200 550
VID = 100 mV
At the temperature extremes 600 mV from
VOeither rail
RL= 10 kΩto 0 V 20 450
VID =−100 mV
At the temperature extremes 500
Output swing
low RL= 2 kΩto 0 V 25 550
VID =−100 mV
At the temperature extremes 600
Sourcing from V+, VID = 200 mV(6) 140
ISC Output short circuit current mA
Sinking to V−, VID =−200 mV (6) 140
IOUT Output current VID = ±200 mV, VO= 1 V from rails ±70 mA
No Load, VCM =−14.5 V 2 2.5
ISTotal supply current mA
At the temperature extremes 3
AV= +1, VI= 20-V Step, RL= 1 MΩ,
SR Slew rate(7) 15.2 V/µs
CL= 10 pF
fuUnity-gain frequency RL= 10 MΩ, CL= 20 pF 9 MHz
GBWP Gain bandwidth product f = 50 kHz 21 MHz
enInput-referred voltage noise f = 2 kHz 15.5 nV/√HZ
inInput-referred current noise f = 2 kHz 1 pA/√HZ
Total harmonic distortion plus AV= +2, RL= 100 kΩ, f = 1 kHz
THD+N −93 dB
noise VO= 25 VPP
CT Rej. Crosstalk rejection f = 3 MHz, Driver RL= 10 kΩ68 dB
(6) Short-circuit test is a momentary test. Output short circuit duration is infinite for VS≤6 V at room temperature and below. For VS> 6V,
allowable short circuit duration is 1.5 ms.
(7) Slew rate is the slower of the rising and falling slew rates. Connected as a voltage follower.
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05 10 15 20 25 30
VCM (V)
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
VOS (mV)
-5 35
25°C
-40°C
VS = 30V
85°C
125°C
-1 0 1 2 3 4 5
VCM (V)
-4
-3.5
-3
-2.5
-2
-1.5
-1
VOS (mV)
6
125°C
-40°C
25°C
125°C
VS = 5V
85°C
-1 0 1 2 3 4 5
VCM (V)
0
0.5
1
1.5
2
2.5
VOS (mV)
6
-40°C 25°C
125°C 85°C
VS = 5V
-1 0 1 2 3 4 5 6
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
VOS (mV)
VCM (V)
85°C
25°C
125°C
-40°C
VS = 5V
-3 -2 -1 0 1 2 3
VOS (mV)
0
2
4
6
8
10
12
PERCENTAGE (%)
VS = 10V
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6.8 Typical Characteristics
Unless otherwise specified, TA= 25°C.
Figure 1. VOS Distribution Figure 2. VOS vs VCM (Unit 1)
Figure 3. VOS vs VCM (Unit 2) Figure 4. VOS vs VCM (Unit 3)
Figure 5. VOS vs VCM (Unit 1) Figure 6. VOS vs VCM (Unit 2)
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0 1 2 3 4 5
-600
-400
-200
0
200
400
600
800
1000
1200
1400
IBIAS (nA)
VCM (V)
-40°C 25°C
125°C 85°C
VS = 5V
05 10 15 20 25 30 35 40
VS (V)
800
900
1000
1100
1200
1300
IBIAS (nA)
-40°C
25°C
85°C
125°C
VCM = V- + 0.5V
0 10 20 30 40
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOS (mV)
VS (V)
-40°C
25°C
85°C
125°C
0 10 20 30 40
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOS (mV)
VS (V)
-40°C
25°C
85°C
125°C
-5 0 5 10 15 20 35
VCM (V)
-0.5
0
0.5
1
1.5
2
VOS (mV)
25 30
VS = 30V
25°C -40°C
85°C 125°C
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 7. VOS vs VCM (Unit 3) Figure 8. VOS vs VS(Unit 1)
Figure 9. VOS vs VS(Unit 2) Figure 10. VOS vs VS(Unit 3)
Figure 12. IBIAS vs Supply Voltage
Figure 11. IBIAS vs VCM
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0 10 20 30 40
1
1.2
1.4
1.6
1.8
2
2.2
2.4
IS (mA)
VS (V)
125°C
85°C
25°C
-40°C
VCM = V- + 0.5V
0.1 1 10 100 1000
ISINK (mA)
0.001
0.01
0.1
1
10
VOUT FROM RAIL (V)
-40°C
125°C
85°C
25°C
VS = 5V
-5 0 5 10 15 20 25 30 35
VCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
IS (mA)
125°C
85°C 25°C
-40°C
VS = 30V
-1 0 1 2 3 4 5 6
VCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
IS (mA)
125°C
85°C
25°C
-40°C
VS = 5V
-1 13 5 7 9 11 13
VCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
IS (mA)
125°C
85°C
25°C
-40°C
VS = 12V
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 13. ISvs VCM Figure 14. ISvs VCM
Figure 15. ISvs VCM Figure 16. ISvs Supply Voltage
Figure 18. Output Swing vs Sinking Current
Figure 17. ISvs Supply Voltage
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Product Folder Links: LM7332
0 5 10 15 20 25 30 35
0
20
40
60
80
100
120
140
160
VOUT from RAIL (mV)
VS (V)
125°C
85°C
-40°C
25°C
RL = 10 k:
0 5 10 15 20 25 30 35
0
10
20
30
40
50
60
70
80
90
100
VOUT from RAIL (mV)
VS (V)
125°C
85°C
25°C
-40°C
RL = 2 k:
05 10 15 20 25 30
VS (V)
0
50
100
150
200
250
300
VOUT from RAIL (mV)
35
125°C
85°C
25°C
-40°C
RL = 2 k:
0.1 1 10 100 1000
ISOURCE (mA)
0.01
0.1
1
10
100
VOUT FROM RAIL (V)
125°C
85°C
-40°C
25°C
VS = 30V
0.1 1 10 100 1000
ISINK (mA)
0.001
0.01
0.1
10
100
VOUT FROM RAIL (V)
1
125°C
85°C
25°C
-40°C
VS = 30V
0.01 11000
ISOURCE (mA)
0.01
0.1
10
VOUT FROM RAIL (V)
100
10
0.1
1
VS = 5V
125°C
85°C 25°C
-40°C
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 19. Output Swing vs Sinking Current Figure 20. Output Swing vs Sourcing Current
Figure 21. Output Swing vs Sourcing Current Figure 22. Positive Output Swing vs Supply Voltage
Figure 23. Positive Output Swing vs Supply Voltage Figure 24. Negative Output Swing vs Supply Voltage
12 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: LM7332
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = 30V
CL = 20 pF
PHASE
GAIN
10 k:
0
23
45
68
90
113
135
PHASE (q)
-23
158
10 M:
1 M:
100 k:
10 k:
100 k:1 M:10 M:
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
RL = 1 M:
CL = 20 pF
PHASE
GAIN
0
23
45
68
90
113
135
PHASE (q)
-23
158
VS = 30V
VS = 10V
VS = 5V
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = 10V
RL = 10 M:
PHASE
GAIN
20 pF
200 pF
100 pF
50 pF
0
23
45
68
90
113
135
PHASE (q)
-23
158
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = 30V
RL = 10 M:
PHASE
GAIN
20 pF
200 pF
100 pF
50 pF
0
23
45
68
90
113
135
PHASE (q)
-23
158
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = 5V
RL = 10 M:
PHASE
GAIN
20 pF
200 pF
100 pF
50 pF
-23
0
23
45
68
158
90
113
135
PHASE (q)
03 10 15 20 25 30
VS (V)
0
5
10
15
20
25
VOUT from RAIL (mV)
35
125°C
-40°C
25°C
85°C
RL = 10 k:
LM7332
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 25. Negative Output Swing vs Supply Voltage Figure 26. Open-Loop Frequency Response With
Various Capacitive Loads
Figure 27. Open-Loop Frequency Response With Figure 28. Open-Loop Frequency Response With
Various Capacitive Loads Various Capacitive Loads
Figure 30. Open-Loop Frequency Response vs
Figure 29. Open-Loop Frequency Response vs With Various Supply Voltages
With Various Resistive Loads
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Product Folder Links: LM7332
20 100 1000
0
10
20
30
40
50
60
70
PHASE MARGIN (°)
CAPACITIVE LOAD (pF)
RL = 600:
RL = 2 k:
RL = 10 k:
RL = 100 k:10 M:
VS = 30V
90
10 1k 100k
FREQUENCY (Hz)
0
30
60
CMRR (dB)
1M10k
100
80
70
50
40
20
10
VS = 10V
-20
0
20
40
60
140
GAIN (dB)
1k 10k 100k 1M 10M
FREQUENCY (Hz)
80
100
120
100M
VS = 30V
RL = 1 M:
CL = 20 pF
PHASE
GAIN
0
23
45
68
90
113
135
PHASE (q)
-23
158
-40qC
125qC
-40qC
125qC
125qC
20 100 1000
0
10
20
30
40
50
60
70
PHASE MARGIN (°)
CAPACITIVE LOAD (pF)
RL = 600:
RL = 2 k:
RL = 10 k:
RL = 100 k:10 M:
VS = 5V
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 32. Phase Margin vs Capacitive Load
Figure 31. Open-Loop Frequency Response at Various
Temperatures
Figure 34. CMRR vs Frequency
Figure 33. Phase Margin vs Capacitive Load
Figure 35. +PSRR vs Frequency Figure 36. −PSRR vs Frequency
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Product Folder Links: LM7332
110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
VOLTAGE NOISE (nV/
Hz)
0.1
1
10
100
CURRENT NOISE (pA/
Hz)
CURRENT
VOLTAGE
VS = 10V
110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
VOLTAGE NOISE (nV/
Hz)
0.1
1
10
100
CURRENT NOISE (pA/
Hz)
CURRENT
VOLTAGE
VS = 30V
2 Ps/DIV
10 pF
VS = 10V, AV = +1, RL = 1 M:
2000 pF
10,000 pF
20,000 pF
5V/DIV
110 100 1k 100k
FREQUENCY (Hz)
1
10
100
1000
10k
VOLTAGE NOISE (nV/
Hz)
0.1
1
10
100
CURRENT NOISE (pA/
Hz)
CURRENT
VOLTAGE
VS = 5V
200 ns/DIV
100 mVPP
VS = 10V, AV = +1, CL = 10 pF, RL = 1 M:
1 VPP
2 VPP
5 VPP
500 ns/DIV
100 mVPP
VS = 10V, AV = +1, CL = 500 pF, RL = 1 M:
1 VPP
2 VPP
5 VPP
LM7332
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 37. Step Response for Various Amplitudes Figure 38. Step Response for Various Amplitudes
Figure 40. Input-Referred Noise Density vs Frequency
Figure 39. Large Signal Step Response for Various
Capacitive Loads
Figure 41. Input-Referred Noise Density vs Frequency Figure 42. Input-Referred Noise Density vs Frequency
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0.02 0.1 1 10 40
OUTPUT AMPLITUDE (VPP)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
THD+N (dB)
VS = 30V
f = 1 kHz
AV = +2
RL = 100 k:
1k 100k 100M
FREQUENCY (Hz)
20
60
90
130
CROSSTALK REJECTION (dB)
10M
1M
10k
120
80
40
30
50
70
100
110
VS = 5V
RL = 10 k:
0.02 0.1 1 10 20
OUTPUT AMPLITUDE (VPP)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
THD+N (dB)
VS = 10V
f = 1 kHz
AV = +2
RL = 100 k:
0.02 0.1 1 6
OUTPUT AMPLITUDE (VPP)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
THD+N (dB)
VS = 5V
f = 1 kHz
AV = +2
RL = 100 k:
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C.
Figure 43. THD+N vs Output Amplitude (VPP)Figure 44. THD+N vs Output Amplitude (VPP)
Figure 46. Crosstalk vs Frequency
Figure 45. THD+N vs Output Amplitude (VPP)
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Product Folder Links: LM7332
OUT B
1
2
3
4 5
6
7
8
OUT A
IN- A
IN+ A
V-
V+
IN- B
IN+ B
-
+
-
+
A
B
LM7332
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
7 Detailed Description
7.1 Overview
The LM7332 device is a rail-to-rail input and output amplifier with wide operating voltages and high-output
currents. The LM7322 is efficient, achieving 15.2-V/µs slew rate and 21-MHz unity gain bandwidth while requiring
only 2 mA of total supply current. The LM7332 device performance is fully specified for operation at 5 V, ±5 V
and ±15 V.
The LM7332 device is designed to drive unlimited capacitive loads without oscillations. The LM7332 is fully
tested at −40°C, 125°C, and 25°C, with modern automatic test equipment. High performance from −40°C to
+125°C, detailed specifications, and extensive testing makes them suitable for industrial, automotive, and
communications applications.
Most device parameters are insensitive to power supply voltage, and this makes the parts easier to use where
supply voltage may vary, such as automotive electrical systems and battery-powered equipment. The LM7332
has a true rail-to-rail output and can supply a respectable amount of current (±70 mA) with minimal head room
from either rail (1 V).
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Estimating the Output Voltage Swing
It is important to keep in mind that the steady-state output current will be less than the current available when
there is an input overdrive present. For steady-state conditions, Figure 47 and Figure 48 plots can be used to
predict the output swing. These plots also show several load lines corresponding to loads tied between the
output and ground. In each case, the intersection of the device plot at the appropriate temperature with the load
line would be the typical output swing possible for that load. For example, a 600-Ωload can accommodate an
output swing to within 100 mV of V−and to 250 mV of V+(VS= ±5 V) corresponding to a typical 9.65-VPP
unclipped swing.
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Product Folder Links: LM7332
10p 1n 100n 10µ
CL (pF)
100n
1µ
10µ
100µ
±1% SETTLING TIME (S)
1µ10n
100p
SLEW RATE (V/µS)
0.1
1
10
100
SETTLING TIME
100 mVPP STEP
SLEW RATE
VS = 10V
AV = +1
VOUT FROM V+ (V)
10µ 100µ 1m 10m
IOUT (A)
10m
100m
1
10
100m
VS = 10V
VID = 20 mV 20:
100:
50:
200:
2 k:
600:
1 k:
VOUT FROM V- (V)
10µ 100µ 1m 10m
IOUT (A)
1m
10m
100m
10
VS = 10V
VID = -20 mV
200:
2 k:
600:
1 k:
100:
20:
50:
100m
1
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Feature Description (continued)
Figure 48. Steady-State Output Sinking Characteristics
Figure 47. Steady-State Output Sourcing Characteristics With Load Lines
With Load Lines
7.4 Device Functional Modes
7.4.1 Driving Capacitive Loads
The LM7332 is specifically designed to drive unlimited capacitive loads without oscillations as shown in
Figure 49.
Figure 49. Settling Time and Slew Rate vs Capacitive Load
In addition, the output current handling capability of the device allows for good slewing characteristics even with
large capacitive loads as shown in Figure 49. The combination of these features is ideal for applications such as
TFT flat panel buffers, A/D converter input amplifiers and power transistor driver.
However, as in most operational amplifiers, addition of a series isolation resistor between the operational
amplifier and the capacitive load improves the settling and overshoot performance.
Output current drive is an important parameter when driving capacitive loads. This parameter will determine how
fast the output voltage can change. Referring to Figure 49, two distinct regions can be identified. Below about
10,000 pF, the output slew rate is solely determined by the compensation capacitor value of the operational
amplifier and available current into that capacitor. Beyond 10 nF, the slew rate is determined by the available
output current of the operational amplifier. An estimate of positive and negative slew rates for loads larger than
100 nF can be made by dividing the short circuit current value by the capacitor.
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Device Functional Modes (continued)
7.4.2 Output Voltage Swing Close to V−
The output stage design of the LM7332 allows voltage swings to within millivolts of either supply rail for
maximum flexibility and improved useful range. Because of this design architecture, with output approaching
either supply rail, the output transistor collector-base junction reverse bias decreases. With output less than a Vbe
from either rail, the corresponding output transistor operates near saturation. In this mode of operation, the
transistor exhibits higher junction capacitance and lower ftwhich reduces phase margin. With the Noise Gain
(NG=1+RF/RG, RFand RGare external gain setting resistors) of 2 or higher, there is sufficient phase margin
that this reduction in phase margin is of no consequence. However, with lower Noise Gain (<2) and with less
than 150 mV to the supply rail, if the output loading is light, the phase margin reduction could result in unwanted
oscillations.
In the case of the LM7332, due to inherent architectural specifics, the oscillation occurs only with respect to the
output transistor at V−when output swings to within 150 mV of V−. However, if this output transistor's collector
current is larger than its idle value of a few microamps, the phase margin loss becomes insignificant. In this case,
300 μA is the required collector current of the output transistor to remedy this situation. Therefore, when all the
aforementioned critical conditions are present at the same time (NG < 2, VOUT < 150 mV from supply rails and
output load is light) it is possible to ensure stability by adding a load resistor to the output to provide the output
transistor the necessary minimum collector current (300 μA).
For 12-V (or ±6-V) operation, for example, add a 39-kΩresistor from the output to V+to cause 300-µA output
sinking current and ensure stability. This is equivalent to about 15% increase in total quiescent power dissipation.
Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM7332
-Ro
Input Signal
SAR ADC
Rflt
Cflt
+CSH
RON
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM7332 is a rail-to-rail input and output part with a slightly higher GBW of 20 MHz. It has current capability
of 40-mA sourcing and 65-mA sinking, and can drive unlimited capacitive loads. The LM7332 is available in both
VSSOP and SOIC packages.
8.1.1 Similar High Current Output Devices
The LM6172 has a higher GBW of 100 MHz and over 80 mA of current output. There is also a single version, the
LM6171. The LM7372 has 120 MHz of GBW and 150 mA of current output. The LM7372 is available in an 8-pin
SO PowerPAD™, and 16-pin SOIC packages with higher power dissipation.
The LME49600 buffer has 250 mA of current out and a 110-MHz bandwidth. The LME49600 is available in a
DDPAK/TO-263 package for higher power dissipation.
Detailed information on these parts can be found at www.ti.com.
8.2 Typical Application
Figure 50. Drive Amplifier for SAR ADC Schematic
8.2.1 Design Requirements
Assume a portable application requires the use of a 12-bit SAR ADC with acquisition time (tAQ) of 1 µs and
sample and hold capacitance (CSH) of 80 pF.
The ADC runs on a single supply voltage of 5 V and has a full scale input of 2.5 VPP. A total harmonic distortion
plus noise (THD+N) of less than –80 dB is required to maintain signal fidelity. Determine if the LM7332 is a
suitable drive amplifier and find the values of Rflt and Cflt.
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Typical Application (continued)
8.2.2 Detailed Design Procedure
The LM7332 can be used as a drive amplifier for SAR ADCs as shown in Figure 50.
The values of Rflt and Cflt depend on the ADC specifications as well as amplifier gain bandwidth product (GBWP)
and output resistance (RO). It is also common to have a single ground-referenced supply voltage and sample
signals up to half of the supply voltage with low distortion.
To determine whether or not the LM7332 is a suitable driver for this application, one must compare the settling
time of the amplifier to the acquisition time of the ADC with Equation 1:
GBWPmin ≥4 × (N+1) × ln(2) / (2π× tAQ)
where
• GBWPmin: The minimum required gain bandwidth product of the drive amplifier
• N: Number of bits in ADC
• tAQ: The acquisition time of the ADC (1)
Using a value of 12 bits for N and 1µs for tAQ, the GBWPmin must be greater than 5.7 MHz. The LM7332 has a
GBWP of 21 MHz so it is indeed a suitable driver for this application.
Next, determine the value of Cflt with Equation 2:
20 × CSH ≤Cflt ≤60 × CSH
where
• CSH: The ADC sample and hold capacitance
• Cflt: The external filter capacitance (2)
Using a value of 80 pF for CSH, the value of Cflt must be between 1600 pF and 4800 pF. According to Figure 39,
the LM7332 can drive a capacitive load of 2000 pF with 5 VPP and settle within 1 µs, therefore select 1800 pF as
the nearest common capacitor value within the range.
Next determine the value of Rflt with Equation 3:
Rflt = 40 / (2π× Cflt ×GBWPmin) – RO
where
• Rflt: The external filter resistance
• Cflt: The external filter capacitance determined above
• GBWPmin: The minimum required gain bandwidth product of the drive amplifier determined above
• RO: The closed loop output impedance of the drive amplifier typically specified in the electrical characteristics
table (3)
Using a value of 1800 pF for Cflt, 5.7 MHz for GBWPmin, and a value of 3 Ωfor ROthe value of Rflt is determined
to be 617.5 Ω. Use closest value of 620 Ωfor a filter frequency (fflt) of 142 kHz given Equation 4:
fflt=1 / (2π× (RO+ Rflt) × Cflt) (4)
The last requirement is to drive input signals of 2.5 VPP on a single 5-V supply with THD+N less than –80 dB.
Figure 51 shows the THD+N response of the LM7332 with a single supply voltage of 5 V. The LM7332 can
maintain THD+N levels as low as –83 dB for output levels up to 4 VPP. Therefore the final requirement has been
met, and the LM7332 is a suitable drive amplifier for the 12-bit SAR ADC in this design example.
Driving two independent channels of the SAR ADC within minimal crosstalk between the channels may also be
required. Figure 52 shows the crosstalk rejection over frequency. The LM7332 achieves 105 dB of crosstalk
rejection up to 20 kHz and greater than 75 dB up to 1MHz which demonstrates the suitability of measuring very
large input signals without interfering with adjacent channels.
Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM7332
0.02 0.1 1 6
OUTPUT AMPLITUDE (VPP)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
THD+N (dB)
VS = 5V
f = 1 kHz
AV = +2
RL = 100 k:
1k 100k 100M
FREQUENCY (Hz)
20
60
90
130
CROSSTALK REJECTION (dB)
10M
1M
10k
120
80
40
30
50
70
100
110
VS = 5V
RL = 10 k:
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Typical Application (continued)
8.2.3 Application Curves
Figure 52. Crosstalk Rejection vs. Frequency
Figure 51. THD+N vs Output Amplitude
9 Power Supply Recommendations
The use of supply decoupling is mandatory in most applications. As with most relatively high-speed or high
output current operational amplifiers, best results are achieved when each supply line is decoupled with two
capacitors: a small value ceramic capacitor (approximately 0.01 µF) placed very close to the supply lead in
addition to a large value tantalum or aluminum capacitor (> 4.7 µF). The large capacitor can be shared by more
than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies
while the large capacitor acts as the charge bucket for fast load current spikes at the operational amplifier output.
The combination of these capacitors provides supply decoupling and helps keep the operational amplifier
oscillation free under any load.
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Product Folder Links: LM7332
IN+B
IN+A
OUT+A
OUT+B
VA
VOUT
4. GND
3. IN+A
2. IN–A
1. OUTA
5. IN+B
6. IN–B
7. OUTB
+3.3V
GND
8. +3.3V
1
GND
2
IN–B
1
IN–B
1
IN–B
2
OUTB
2
OUTB
1
+3.3V
2
GND
1
GND
2
IN–A
1
IN–A
1
IN–A
2
OUTA
2
OUTA
LM7332
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SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
10 Layout
10.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground must have a
nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply
pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins lowers the power supply
inductance and provide a more stable power supply.
The feedback components must be placed as close to the device as possible to minimize stray parasitics.
10.2 Layout Example
Figure 53. LM7332 Layout Example
10.3 Output Short Circuit Current and Dissipation Issues
The LM7332 output stage is designed for maximum output current capability. Even though momentary output
shorts to ground and either supply can be tolerated at all operating voltages, longer-lasting short conditions can
cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher
supply voltage conditions. Below a supply voltage of 6 V, the output short circuit condition can be tolerated
indefinitely.
With the operational amplifier tied to a load, the device power dissipation consists of the quiescent power due to
the supply current flow into the device, in addition to power dissipation due to the load current. The load portion
of the power itself could include an average value (due to a DC load current) and an AC component. DC load
current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the
operational amplifier operates in a single-supply application where the output is maintained somewhere in the
range of linear operation.
Therefore,
PTOTAL = PQ+ PDC + PAC (5)
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Product Folder Links: LM7332
PD(MAX) =
150°C ± 125°C
109.1°C/W = 0.23W
PD(MAX) =
150°C ± 125°C
161.1°C/W = 0.16W
PD(MAX) = 150°C ± 25°C
109.1°C/W = 1.15W
PD(MAX) = 150°C ± 25°C
161.1°C/W = 0.78W
PD(MAX) = TJ(MAX) - TA
RTJA
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
Output Short Circuit Current and Dissipation Issues (continued)
The operational amplifier quiescent power dissipation is calculated by Equation 6:
PQ= IS× VS
where
• IS: Supply Current
• VS: Total Supply Voltage (V+−V−) (6)
The DC load power is calculated by Equation 7:
PDC = IO× (Vr– Vo)
where
• VO: Average Output Voltage
• Vr: V+for sourcing and V−for sinking current (7)
The AC load power is calculated as PAC = the value shown in Table 1.
Table 1 shows the maximum AC component of the load power dissipated by the operational amplifier for
standard sinusoidal, triangular, and square waveforms:
Table 1. Normalized AC Power Dissipated in the Output Stage for Standard
Waveforms
PAC (W.Ω/V2)
SINUSOIDAL TRIANGULAR SQUARE
50.7 x 10−346.9 x 10−362.5 x 10−3
The table entries are normalized to VS2/RL. To figure out the AC load current component of power dissipation,
simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with ±12-
V supplies, a 600-Ωload, and triangular waveform power dissipation in the output stage is calculated as:
PAC = (46.9 × 10−3) × [242/600] = 45.0 mW (8)
The maximum power dissipation allowed at a certain temperature is a function of maximum die junction
temperature (TJ(MAX)) allowed, ambient temperature TA, and package thermal resistance from junction to ambient,
RθJA.
(9)
For the LM7332, the maximum junction temperature allowed is 150°C at which no power dissipation is allowed.
The power capability at 25°C is given by Equation 10 and Equation 11.
For VSSOP package:
(10)
For SOIC package:
(11)
Similarly, the power capability at 125°C is given by Equation 12 and Equation 13.
For VSSOP package:
(12)
For SOIC package:
(13)
24 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: LM7332
-40 -20 0 20 40 60 80 100 120 140 160
0
0.2
0.4
0.6
0.8
1
1.2
1.4
POWER CAPABILITY (W)
TEMPERATURE (°C)
Operating area
Maximum thermal capability line (SOIC)
Maximum thermal capability line (MSOP)
LM7332
www.ti.com
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
Figure 54 shows the power capability vs temperature for VSSOP and SOIC packages. The area under the
maximum thermal capability line is the operating area for the device. When the device works in the operating
area where PTOTAL is less than PD(MAX), the device junction temperature will remain below 150°C. If the
intersection of ambient temperature and package power is above the maximum thermal capability line, the
junction temperature will exceed 150°C, and this must be strictly prohibited.
Figure 54. Power Capability vs Temperature
When high power is required and ambient temperature cannot be reduced, providing air flow is an effective
approach to reduce thermal resistance therefore to improve power capability.
Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM7332
LM7332
SNOSAV4B –APRIL 2008–REVISED JANUARY 2016
www.ti.com
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: LM7332
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM7332MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM733
2MA
LM7332MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LM733
2MA
LM7332MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AA5A
LM7332MME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AA5A
LM7332MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 AA5A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM7332MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM7332MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM7332MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM7332MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM7332MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM7332MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM7332MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LM7332MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Sep-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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