DAC7615E/1K - Texas Instruments

DAC7615

Quad, Serial Input, 12-Bit, Voltage Output

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● LOW POWER: 20mW

● UNIPOLAR OR BIPOLAR OPERATION

●SETTLING TIME: 10µs to 0.012%

● 12-BIT LINEARITY AND MONOTONICITY:

–40°C to +85°C

● DOUBLE-BUFFERED DATA INPUTS

● SMALL 20-LEAD SSOP PACKAGE

APPLICATIONS

● PROCESS CONTROL

● ATE PIN ELECTRONICS

● CLOSED-LOOP SERVO-CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

● DAC-PER-PIN PROGRAMMERS

DESCRIPTION

The DAC7615 is a quad, serial input, 12-bit, voltage

output digital-to-analog converter (DAC) with guar-

anteed 12-bit monotonic performance over the –40°C

to +85°C temperature range. An asynchronous reset

clears all registers to either mid-scale (800H) or zero-

scale (000H), selectable via the RESETSEL pin. The

individual DAC inputs are double buffered to allow

for simultaneous update of all DAC outputs. The

device can be powered from a single +5V supply or

from dual +5V and –5V supplies.

Low power and small size makes the DAC7615 ideal

for automatic test equipment, DAC-per-pin program-

mers, data acquisition systems, and closed-loop servo-

control. The device is available in 16-pin plastic DIP,

16-lead SOIC, and 20-lead SSOP packages and is

guaranteed over the –40°C to +85°C temperature range.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

DAC A

DAC

Input

DAC B

DAC

Input

DAC C

DAC

Input

DAC D

DAC

Input

VREFH

VDD

VSS

VOUTD

VOUTC

VOUTB

VOUTA

VREFLLOADDACS

GND

CLK

SDI

RESETRESETSELLOADREG

Serial-to-

Parallel

Shift

DAC

Select

DAC7615

SBAS091

DAC7615

SPECIFICATIONS

At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted.

DAC7615E, P, U DAC7615EB, PB, UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ACCURACY

Linearity Error(1) VSS = 0V or –5V ±2±1 LSB(2)

Linearity Matching(3) VSS = 0V or –5V ±2±1 LSB

Differential Linearity Error VSS = 0V or –5V ±1±1 LSB

Monotonicity 12 ✻Bits

Zero-Scale Error Code = 000H±4✻LSB

Zero-Scale Drift 25 ✻✻ppm/°C

Zero-Scale Matching(3) ±2±1 LSB

Full-Scale Error Code = FFFH±4✻LSB

Full-Scale Matching(3) ±2±1 LSB

Zero-Scale Error Code = 00AH, VSS = 0V ±8✻LSB

Zero-Scale Drift VSS = 0V 5 10 ✻✻ppm/°C

Zero-Scale Matching(3) VSS = 0V ±4±2 LSB

Full-Scale Error Code = FFFH, VSS = 0V ±8✻LSB

Full-Scale Matching(3) VSS = 0V ±4±2 LSB

Power Supply Rejection 30 ✻ppm/V

ANALOG OUTPUT

Voltage Output(4) VSS = 0V or –5V VREFL VREFH ✻✻V

Output Current –1.25 +1.25 ✻✻mA

Load Capacitance No Oscillation 100 ✻pF

Short-Circuit Current +5, –15 ✻mA

Short-Circuit Duration

Indefinite

✻

REFERENCE INPUT

VREFH Input Range VSS = 0V or –5V

VREFL+1.25

+2.5 ✻✻V

VREFL Input Range VSS = 0V 0

VREFH–1.25

✻✻V

VREFL Input Range VSS = –5V –2.5

VREFH–1.25

✻✻V

DYNAMIC PERFORMANCE

Settling Time(5) To ±0.012% 5 10 ✻✻ µs

Channel-to-Channel Crosstalk Full-Scale Step 0.1 ✻LSB

On Any Other DAC, RL = 2kΩ

Output Noise Voltage Bandwidth: 0Hz to 1MHz 40 ✻nV/√Hz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible CMOS ✻

Logic Levels

VIH | IIH | ≤ 10µA 2.4 VDD+0.3 ✻✻V

VIL | IIL | ≤ 10µA –0.3 0.8 ✻✻V

Data Format Straight Binary ✻

POWER SUPPLY REQUIREMENTS

VDD 4.75 5.25 ✻✻V

VSS If VSS ≠ 0V –5.25 –4.75 ✻✻V

IDD 1.5 1.9 ✻✻ mA

ISS –2.1 –1.6 ✻✻ mA

Power Dissipation VSS = –5V 15 20 ✻✻ mW

VSS = 0V 7.5 10 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

✻ Specification same as grade to the left.

NOTES: (1) If VSS = 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with VREFH equal to +2.5V and VREFL equal to –2.5V,

one LSB is 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.

(5) If VSS = –5V, full-scale step from code 000H to FFFH or vice-versa. If VSS = 0V, full-scale positive step from code 000H to FFFH and negative step from code

FFFH to 00AH.

DAC7615

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

ABSOLUTE MAXIMUM RATINGS(1)

VDD to VSS ........................................................................... –0.3V to +11V

VDD to GND ........................................................................ –0.3V to +5.5V

VREFL to VSS ...............................................................–0.3V to (VDD – VSS)

VDD to VREFH ..............................................................–0.3V to (VDD – VSS)

VREFH to VREFL ............................................................–0.3V to (VDD – VSS)

Digital Input Voltage to GND...................................... –0.3V to VDD + 0.3V

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ......................................... –40°C to +85°C

Storage Temperature Range .......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION

ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT

PRODUCT (LSB) (LSB) PACKAGE NUMBER(1) RANGE NUMBER(2) MEDIA

DAC7615P ±2±1 16-Pin DIP 180 –40°C to +85°C DAC7615P Rails

DAC7615PB """""DAC7615PB Rails

DAC7615U ±2±1 16-Lead SOIC 211 –40°C to +85°C DAC7615U Rails

"" """ "DAC7615U/1K Tape and Reel

DAC7615UB ±1±1 16-Lead SOIC 211 –40 °C to +85°C DAC7615UB Rails

"" """ "DAC7615UB/1K Tape and Reel

DAC7615E ±2±1 20-Lead SSOP 334 –40°C to +85°C DAC7615E Rails

"" """ "DAC7615E/1K Tape and Reel

DAC7615EB ±1±1 20-Lead SSOP 334 –40°C to +85°C DAC7615EB Rails

"" """ "DAC7615EB/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7615EB/1K” will get a single

1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

DAC7615

PIN CONFIGURATION—P, U Packages

Top View PDIP, SOIC

PIN CONFIGURATION—E Package

Top View SSOP

PIN DESCRIPTIONS—E Package

PIN LABEL DESCRIPTION

DD Positive Analog Supply Voltage, +5V nominal.

OUTD DAC D Voltage Output

OUTC DAC C Voltage Output

REFL Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.

5 NIC Not Internally Connected.

6 NIC Not Internally Connected.

REFH Reference Input Voltage High. Sets maximum out-

put voltage for all DACs.

OUTB DAC B Voltage Output

OUTA DAC A Voltage Output

10 VSS Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

11 GND Ground

12 SDI Serial Data Input

13 CLK Serial Data Clock

14 CS Chip Select Input

15 NIC Not Internally Connected.

16 NIC Not Internally Connected.

17 LOADDACS All DAC registers becomes transparent when

LOADDACS is LOW. They are in the latched state

when LOADDACS is HIGH.

18 LOADREG The selected input register becomes transparent

when LOADREG is LOW. It is in the latched state

when LOADREG is HIGH.

19 RESET Asynchronous Reset Input. Sets all DAC registers

to either zero-scale (000H) or mid-scale (800H)

when LOW. RESETSEL determines which code is

active.

20 RESETSEL When LOW, a LOW on RESET will cause all DAC

registers to be set to code 000H. When RESETSEL

is HIGH, a LOW on RESET will set the registers to

code 800H.

PIN DESCRIPTIONS—P, U Packages

PIN LABEL DESCRIPTION

DD Positive Analog Supply Voltage, +5V nominal.

OUTD DAC D Voltage Output

OUTC DAC C Voltage Output

REFL Reference Input Voltage Low. Sets minimum out-

put voltage for all DACs.

REFH Reference Input Voltage High. Sets maximum out-

put voltage for all DACs.

OUTB DAC B Voltage Output

OUTA DAC A Voltage Output

SS Negative Analog Supply Voltage, 0V or –5V nomi-

nal.

9 GND Ground

10 SDI Serial Data Input

11 CLK Serial Data Clock

12 CS Chip Select Input

13 LOADDACS All DAC registers become transparent when

LOADDACS is LOW. They are in the latched state

when LOADDACS is HIGH.

14 LOADREG The selected input register becomes transparent

when LOADREG is LOW. It is in the latched state

when LOADREG is HIGH.

15 RESET Asynchronous Reset Input. Sets DAC and input

registers to either zero-scale (000H) or mid-scale

(800H) when LOW. RESETSEL determines which

code is active.

16 RESETSEL When LOW, a LOW on RESET will cause the DAC

and input registers to be set to code 000H. When

RESETSEL is HIGH, a LOW on RESET will set the

registers to code 800H.

OUTD

OUTC

REFL

REFH

OUTB

OUTA

RESETSEL

RESET

LOADREG

LOADDACS

CLK

SDI

GND

DAC7615P, U

OUTD

OUTC

REFL

NIC

REFH

OUTB

OUTA

RESETSEL

RESET

LOADREG

LOADDACS

NIC

CLK

SDI

GND

DAC7615E

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = 0V

At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

200

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and DIFFERENTIAL

LINEARITY ERROR vs CODE

(DAC D)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25 +85°C

–40°C

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25 +85°C

–40°C

200

400

600

800

A00

C00

E00

FFF

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT)

At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25 +85°C

–40°C

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR vs CODE

(DAC D, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25 +85°C

–40°C

200

400

600

800

A00

C00

E00

FFF

POSITIVE SLEW RATE and SETTLING TIME

–2 8–1 Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from +2.5V (LSB)

–0.25

2.25

1.75

2.75

1.25

0.75

0.25

–9

–3

–6

01234567

LOADDACS

NEGATIVE SLEW RATE and SETTLING TIME

–2 8–1 Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from Code 00A

(LSB)

–0.25

2.25

1.75

2.75

1.25

0.75

0.25

–9

–3

–6

01234567

LOADDACS

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = –5V

At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC A)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC C)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC B)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR and

DIFFERENTIAL LINEARITY ERROR vs CODE

(DAC D)

000

Digital Input Code

DLE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR vs CODE

(DAC A, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50 +85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

LINEARITY ERROR vs CODE

(DAC B, –40°C and +85°C)

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50 +85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

200

400

600

800

A00

C00

E00

FFF

DAC7615

TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT)

At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, representative unit, unless otherwise specified.

LINEARITY ERROR vs CODE

(DAC C, –40°C and +85°C)

200

000

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50 +85°C

–40°C

0.25

0.00

–0.50

–0.25

0.25

400

600

800

A00

C00

E00

FFF

600

REFH

CURRENT vs CODE

(All DACs Set to Indicated Code)

000

FFF

400

C00

800

Digital Input Code

REH

Current (µA)

100

200

300

400

500

REFL

CURRENT vs CODE

(All DACs Set to Indicated Code)

000

FFF

400

C00

800

Digital Input Code

REL

Current (µA)

–600

–500

–400

–300

–200

–100

POSITIVE SLEW RATE and SETTLING TIME

–2 8–1 Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from +2.5V (LSB)

–3

–1

–2

–6

–2

–4

01234567

LOADDACS

NEGATIVE SLEW RATE and SETTLING TIME

–2 8–1 Time (µs)

A: Output Voltage (V)

B: Output Voltage, Deviation from –2.5V (LSB)

–3

–1

–2

–6

–2

–4

01234567

LOADDACS

LINEARITY ERROR vs CODE

(DAC D, –40˚C and +85˚C)

000

200

Digital Input Code

LE (LSB) LE (LSB)

0.50

0.00

–0.25

–0.50

0.50 +85˚C

–40˚C

0.25

0.00

–0.50

–0.25

0.25

400

600

800

A00

C00

E00

FFF

DAC7615

THEORY OF OPERATION

The DAC7615 is a quad, serial input, 12-bit, voltage output

DAC. The architecture is a classic R-2R ladder configuration

followed by an operational amplifier that serves as a buffer.

Each DAC has its own R-2R ladder network and output op

amp, but all share the reference voltage inputs. The minimum

voltage output (“zero-scale”) and maximum voltage output

(“full-scale”) are set by external voltage references (VREFL

and VREFH, respectively). The digital input is a 16-bit serial

word that contains the 12-bit DAC code and a 2-bit address

code that selects one of the four DACs (the two remaining

bits are unused). The converter can be powered from a single

+5V supply or a dual ±5V supply. Each device offers a reset

function which immediately sets all DAC output voltages and

internal registers to either zero-scale (code 000H) or mid-scale

(code 800H). The reset code is selected by the state of the

RESETSEL pin (LOW = 000H, HIGH = 800H). See Figures

1 and 2 for the basic operation of the DAC7615.

ANALOG OUTPUTS

When VSS = –5V (dual supply operation), the output

amplifier can swing to within 2.25V of the supply rails,

over the –40°C to +85°C temperature range. With VSS = 0V

(single-supply operation), the output can swing to ground.

Note that the settling time of the output op amp will be

longer with voltages very near ground. Also, care must be

taken when measuring the zero-scale error when VSS = 0V.

If the output amplifier has a negative offset, the output

voltage may not change for the first few digital input codes

(000H, 001H, 002H, etc.) since the output voltage cannot

swing below ground.

The behavior of the output amplifier can be critical in some

applications. Under short-circuit conditions (DAC output

shorted to ground), the output amplifier can sink a great deal

more current than it can source. See the Specifications table

for more details concerning short circuit current.

FIGURE 1. Basic Single-Supply Operation of the DAC7615.

FIGURE 2. Basic Dual-Supply Operation of the DAC7615.

NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers

to code 000

(0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800

(1.25V).

OUTD

OUTC

REFL

REFH

OUTB

OUTA

RESETSEL

RESET

LOADREG

LOADDACS

CLK

SDI

GND

Reset DACs

(2)

Update Selected Register

Update All DAC Registers

Chip Select

Clock

Serial Data In

DAC7615

(1)

0.1µF

0V to +2.5V

1µF to 10µF

+5V

0V to +2.5V

+2.500V

NOTE: (1) P and U package pin configurations shown. (2) As configured, RESET LOW sets all internal registers

to code 800

(0V). If RESETSEL is LOW, RESET LOW sets all internal registers to code 000

(–2.5V).

OUTD

OUTC

REFL

REFH

OUTB

OUTA

RESETSEL

RESET

LOADREG

LOADDACS

CLK

SDI

GND

Reset DACs

(2)

Update Selected Register

Update All DAC Registers

Chip Select

Clock

Serial Data In

DAC7615

(1)

0.1µF

–2.5V to +2.5V

1µF to 10µF

+5V

–5V

0.1µF

1µF to 10µF

–2.5V to +2.5V

–2.500V

0.1µF

+2.500V

–2.5V to +2.5V

+5V

DAC7615

REFERENCE INPUTS

The reference inputs, VREFL and VREFH, can be any voltage

between VSS + 2.25V and VDD – 2.25V provided that VREFH

is at least 1.25V greater than VREFL. The minimum output

of each DAC is equal to VREFL – 1LSB plus a small offset

voltage (essentially, the offset of the output op amp). The

maximum output is equal to VREFH plus a similar offset

voltage. Note that VSS (the negative power supply) must

either be connected to ground or must be in the range of –

4.75V to –5.25V. The voltage on VSS sets several bias

points within the converter. If VSS is not in one of these two

configurations, the bias values may be in error and proper

operation of the device is not guaranteed.

The current into the reference inputs depends on the DAC

output voltages and can vary from a few microamps to

approximately 0.6 milliamp. Bypassing the reference volt-

age or voltages with a 0.1µF capacitor placed as close as

possible to the DAC7615 package is strongly recommended.

DIGITAL INTERFACE

Figure 3 and Table I provide the basic timing for the

DAC7615. The interface consists of a serial clock (CLK),

serial data (SDI), a load register signal (LOADREG), and a

“load all DAC registers” signal (LOADDACS). In addition,

a chip select (CS) input is available to enable serial commu-

nication when there are multiple serial devices. An asyn-

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tDS

Data Valid to CLK Rising

25 ns

tDH

Data Held Valid after CLK Rises

20 ns

tCH

CLK HIGH

30 ns

tCL

CLK LOW

50 ns

tCSS

CS LOW to CLK Rising

55 ns

tCSH

CLK HIGH to CS Rising

15 ns

tLD1

LOADREG HIGH to CLK Rising

40 ns

tLD2

CLK Rising to LOADREG LOW

15 ns

tLDRW

LOADREG LOW Time

45 ns

tLDDW

LOADDACS LOW Time

45 ns

tRSSH

RESETSEL Valid to RESET LOW

25 ns

tRSTW

RESET LOW Time

70 ns

Settling Time

10 µs

FIGURE 3. DAC7615 Timing.

chronous reset input (RESET) is provided to simplify start-

up conditions, periodic resets, or emergency resets to a

known state.

The DAC code and address are provided via a 16-bit serial

interface as shown in Figure 3. The first two bits select the

input register that will be updated when LOADREG goes

LOW (see Table II). The next two bits are not used. The last

12 bits are the DAC code which is provided, most significant

bit first.

TABLE I. Timing Specifications (TA = –40°C to +85°C).

(MSB) (LSB)

SDI

CLK

LOADREG

A0 X X D11 D10 D9 D3 D2 D1 D0

SDI

CLK

LOADDACS

RESET

VOUT

tcss

tLD1

tCL tCH

tDS tDH

tLD2

tLDRW

LDDW

tRSTW

tRSSH

tCSH

1 LSB

ERROR BAND 1 LSB

ERROR BAND

RESETSEL

DAC7615

STATE OF

SELECTED SELECTED STATE OF

INPUT INPUT ALL DAC

A1 A0 LOADREG LOADDACS RESET REGISTER REGISTER REGISTERS

L(1) LLH

(2) H A Transparent Latched

L H L H H B Transparent Latched

H L L H H C Transparent Latched

H H L H H D Transparent Latched

X(3) X H L H NONE (All Latched) Transparent

X X H H H NONE (All Latched) Latched

X X X X L ALL Reset(4) Reset(4)

NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H).

When RESET rises, all registers that are in their latched state retain the reset value.

TABLE II. Control Logic Truth Table.

CS(1) CLK(1) LOADREG RESET SERIAL SHIFT REGISTER

H(2) X(3) H H No Change

L(4) L H H No Change

L↑(5) H H Advanced One Bit

↑L H H Advanced One Bit

H(6) XL

(7) H No Change

H(6) XHL

(8) No Change

NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =

Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH

value is suggested in order to avoid a “false clock” from advancing the shift

shift register bits “flow” through A1 and A0. This will corrupt the data in each

input register that has been erroneously selected. (8) RESET LOW causes no

change in the contents of the serial shift register.

TABLE III. Serial Shift Register Truth Table.

If both CS and CLK are used, then CS should rise only when

CLK is HIGH. If not, then either CS or CLK can be used to

operate the shift register. See Table III for more information.

The digital data into the DAC7615 is double-buffered. This

allows new data to be entered for each DAC without disturb-

ing the analog outputs. When the new settings have been

entered into the device, all of the DAC outputs can be

updated simultaneously. The transfer from the input regis-

ters to the DAC registers is accomplished with a HIGH to

LOW transition on the LOADDACS input.

Because the DAC registers become transparent when

LOADDACS is LOW, it is possible to keep this pin LOW

and update each DAC via LOADREG. However, as each

new data word is entered into the device, the corresponding

output will update immediately when LOADREG is taken

LOW.

Digital Input Coding

The DAC7615 input data is in Straight Binary format. The

output voltage is given by the following equation:

Note that CS and CLK are combined with an OR gate and

the output controls the serial-to-parallel shift register inter-

nal to the DAC7615 (see the block diagram on the front of

this data sheet). These two inputs are completely inter-

changeable. In addition, care must be taken with the state of

CLK when CS rises at the end of a serial transfer. If CLK is

LOW when CS rises, the OR gate will provide a rising edge

to the shift register, shifting the internal data one additional

bit. The result will be incorrect data and possible selection of

the wrong input register. where N is the digital input code (in decimal). This equation

does not include the effects of offset (zero-scale) or gain

(full-scale) errors.

(VREFH – VREFL) • N

4096

VOUT = VREFL +

DAC7615

LAYOUT

A precision analog component requires careful layout, ad-

equate bypassing, and clean, well-regulated power supplies.

As the DAC7615 offers single-supply operation, it will often

be used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more

digital logic present in the design and the higher the switch-

ing speed, the more difficult it will be to achieve good

performance from the converter.

Because the DAC7615 has a single ground pin, all return

currents, including digital and analog return currents, must

flow through the GND pin. Ideally, GND would be con-

nected directly to an analog ground plane. This plane would

be separate from the ground connection for the digital

components until they were connected at the power entry

point of the system (see Figure 4).

The power applied to VDD (as well as VSS, if not grounded)

should be well regulated and low noise. Switching power

supplies and DC/DC converters will often have high-fre-

quency glitches or spikes riding on the output voltage. In

addition, digital components can create similar high-fre-

quency spikes as their internal logic switches states. This

noise can easily couple into the DAC output voltage through

various paths between the power connections and analog

output.

As with the GND connection, VDD should be connected to

a +5V power supply plane or trace that is separate from the

connection for digital logic until they are connected at the

power entry point. In addition, the 1µF to 10µF and 0.1µF

capacitors shown in Figure 4 are strongly recommended. In

some situations, additional bypassing may be required, such

as a 100µF electrolytic capacitor or even a “Pi” filter made

up of inductors and capacitors—all designed to essentially

lowpass filter the +5V supply, removing the high frequency

noise (see Figure 4).

FIGURE 4. Suggested Power and Ground Connections for a DAC7615 Sharing a +5V Supply with a Digital System.

+5V

Power Supply

Optional

Digital Circuits

DAC7615

Other

Analog

Components

+5V

100µF 1µF to

10µF

Ground

+5V

Ground

GND

0.1µF

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

DAC7615E ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615E/1K ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615E/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615EB ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615EB/1K ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615EB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615EBG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615EG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615P NRND PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

DAC7615PB NRND PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

DAC7615PBG4 NRND PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

DAC7615PG4 NRND PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

DAC7615U ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615U/1K ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615UB ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615UB/1K ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615UB/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615UBG4 ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

DAC7615UG4 ACTIVE SOIC DW 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

PACKAGE OPTION ADDENDUM

www.ti.com 3-Jul-2009

Addendum-Page 1

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 3-Jul-2009

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

DAC7615E/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

DAC7615EB/1K SSOP DB 20 1000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

DAC7615U/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1

DAC7615UB/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jan-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC7615E/1K SSOP DB 20 1000 346.0 346.0 33.0

DAC7615EB/1K SSOP DB 20 1000 346.0 346.0 33.0

DAC7615U/1K SOIC DW 16 1000 346.0 346.0 33.0

DAC7615UB/1K SOIC DW 16 1000 346.0 346.0 33.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Jan-2009

Pack Materials-Page 2

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