MCP14700T-E/MF - Microchip Technology, Inc.

 2009-2013 Microchip Technology Inc. DS22201B-page 1

MCP14700

Features:

• Ideally suited to drive low Figure-of-Merit (FOM)

MOSFETs such as Microchip’s MCP87000

MOSFET family

• Independent PWM Input Control for High-Side

and Low-Side Gate Drive

• Input Logic Level Threshold 3.0V TTL Compatible

• Dual Output MOSFET Drive for Synchronous

Applications

• High Peak Output Current: 2A (typical)

• Internal Bootstrap Blocking Device

• +36V BOOT Pin Maximum Rating

• Low Supply Current: 45 µA (typical)

• High Capacitive Load Drive Capability:

- 3300 pF in 10.0 ns (typical)

• Input Voltage Undervoltage Lockout Protection

• Overtemperature Protection

• Space Saving Packages:

- 8-Lead SOIC

- 8-Lead 3x3 DFN

Applications:

• 3-Phase BLDC Motor Control

• High Efficient Synchronous DC/DC Buck

Converters

• High-Current Low Output Voltage Synchronous

DC/DC Buck Converters

• High Input Voltage Synchronous DC/DC Buck

Converters

• Core Voltage Supplies for Microprocessors

General Description:

The MCP14700 is a high-speed synchronous

MOSFET driver designed to optimally drive a high-side

and low-side N-Channel MOSFET. It is particularly well

suited for driving low-FOM MOSFETs, including

Microchip’s MCP87000 family of high-speed

MOSFETs. The MCP14700 has two PWM inputs to

allow independent control of the external N-Channel

MOSFETs. Since there is no internal cross conduction

protection circuitry the external MOSFET dead time

can be tightly controlled allowing for more efficient

systems or unique motor control algorithms.

The transition thresholds for the PWM inputs are

typically 1.6V on a rising PWM input signal and typically

1.2V on a falling PWM input signal. This makes the

MCP14700 ideally suited for controllers that utilize 3.0V

TTL/CMOS logic. The PWM inputs are internally pulled

low ensuring the output drive signals are low if the

inputs are floating.

The HIGHDR and LOWDR peak source current

capability of the MCP14700 device is typically 2A.

While the HIGHDR can sink 2A peak typically, the

LOWDR can sink 3.5A peak typically. The low

resistance pull-up and pull-down drive allow the

MCP14700 to quickly transition a 3300 pF load in

typically 10 ns. Bootstrapping for the high-side drive is

internally implemented which allows for a reduced

system cost and design complexity.

The MCP14700 features undervoltage lockout (UVLO)

with a typical hysteresis of 500 mV. Overtemperature

protection with hysteresis is also featured on the

device.

Package Types

MCP14700

3x3 DFN*

PWMLO

PWMHI

GND

BOOT

VCC

5LOWDR

HIGHDRPHASE

* Includes Exposed Thermal Pad (EP); see Tabl e 3 - 1 .

MCP14700

SOIC

PWMLO

PWMHI

GND

BOOT

VCC

5LOWDR

HIGHDRPHASE

Dual Input Synchronous MOSFET Driver

MCP14700

DS22201B-page 2  2009-2013 Microchip Technology Inc.

Typical Application Schematic

HIGHDR

LOWDR

PHASE

VCC

PWMLO

BOOT

GND

PWMHI

VBUCK =12V

VCC =5.0V

CBOOT

dsPIC33FJ06GS101

CURRENT

SENSE

CURRENT

SENSE

PWM1L

PWM1H

AN0

AN1

MCP14700

Synchronous Buck Application

MCP87050

MCP87022

HIGHDR

LOWDR

PHASE

VCC

PWMLO

BOOT

GND

PWMHI

HIGHDR

LOWDR

PHASE

VCC

PWMLO

BOOT

GND

PWMHI

HIGHDR

LOWDR

PHASE

VCC

PWMLO

BOOT

GND

PWMH

PWM2

PWM1

VCC

PWM4

PWM3

VCC

PWM6

PWM5

VCC

24V 24V

24V

SENSE

NODE

VREF

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

dsPIC®

MCP14700 MCP14700

SENSE

NODE

MCP14700

3-Phase BLDC Motor Control Application

SENSE

NODE

 2009-2013 Microchip Technology Inc. DS22201B-page 3

MCP14700

Functional Block Diagram

BOOT

HIGHDR

PHASE

LOWDR

VCC

PWMHI

PWMLO

GND

Level

Shift

Input

Protection

Logic VCC

Circuitry

GND

VCC

MCP14700

DS22201B-page 4  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS22201B-page 5

MCP14700

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VCC........................................................ -0.3V to +7.0V

VBOOT.................................................. -0.3V to +36.0V

VPHASE ............................ VBOOT -7VtoV

BOOT +0.3V

VPWM.............................................-0.3V to VCC +0.3V

VHIGHDR ......................VPHASE -0.3VtoV

BOOT +0.3V

VLOWDR .........................................-0.3V to VCC +0.3V

ESD Protection on all Pins.........................2 kV (HBM)

....................................................................400V (MM)

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational sections of this specifica-

tion is not intended. Exposure to maximum rating con-

ditions for extended periods may affect device

reliability.

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, VCC =5.0V, T

J= -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

VCC Supply Requirements

VCC Operating Range VCC 4.5 5.0 5.5 V

Bias Supply Voltage IVCC —45—µAPWM

HI and PWMLO pin

floating

UVLO (Rising VCC)V

UVLO — 3.50 4.00 V

UVLO Hysteresis VHYS —500—mV

PWM Input Requirements

PWM Input Current IPWM —7.010µAV

PWM =3.0V

PWM Input Current IPWM —1.0—nAV

PWM =0V

PWMLO and PWMHI Rising

Threshold

PWMHI_TH 1.40 1.60 1.80 V VCC =5.0V

PWMLO and PWMHI Falling

Threshold

PWMLO_TH 1.10 1.20 1.30 V VCC =5.0V

PWM Input Hysteresis PWMHYS —400—mVV

CC =5.0V

Output Requirements

High Output Voltage (HIGHDR

and LOWDR)

VOH VCC -0.025 — — V V

CC =5.0V

Low Output Voltage (HIGHDR

and LOWDR)

VOL ——0.025VV

CC =5.0V

High Drive Source Resistance RHI_SRC —1.02.5500 mA source current,

Note 1

High Drive Sink Resistance RHI_SINK —1.02.5500 mA sink current, Note 1

High Drive Source Current IHI_SRC —2.0—ANote 1

High Drive Sink Current IHI_SINK —2.0—ANote 1

Low Drive Source Resistance RLO_SRC —1.02.5500 mA source current,

Note 1

Low Drive Sink Resistance RLO_SINK —0.51.0500 mA sink current, Note 1

Low Drive Source Current ILO_SRC —2.0—ANote 1

Low Drive Sink Current ILO_SINK —3.5—ANote 1

Note 1: Parameter ensured by characterization, not production tested.

2: See Figure 4-1 and Figure 4-2 for parameter definition.

MCP14700

DS22201B-page 6  2009-2013 Microchip Technology Inc.

Switching Times

HIGHDR Rise Time tRH —10—nsC

L=3.3nF, Note 1, Note 2

LOWDR Rise Time tRL —10—nsC

L=3.3nF, Note 1, Note 2

HIGHDR Fall Time tFH —10—nsC

L=3.3nF, Note 1, Note 2

LOWDR Fall Time tFL —6.0—nsC

L=3.3nF, Note 1, Note 2

HIGHDR Turn-off Propagation

Delay

tPDLH 20 27 36 ns No Load, Note 1, Note 2

LOWDR Turn-off Propagation

Delay

tPDLL 10 17 25 ns No Load, Note 1, Note 2

HIGHDR Turn-on Propagation

Delay

tPDHH 20 27 36 ns No Load, Note 1, Note 2

LOWDR Turn-on Propagation

Delay

tPDHL 10 17 25 ns No Load, Note 1, Note 2

Protection Requirements

Thermal Shutdown TSHDN —147—°CNote 1

Thermal Shutdown Hysteresis TSHDN_HYS —20—°CNote 1

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted, VCC = 5.0V, TJ= -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: Parameter ensured by characterization, not production tested.

2: See Figure 4-1 and Figure 4-2 for parameter definition.

TEMPERATURE CHARACTERISTICS

Unless otherwise noted, all parameters apply with VCC =5.0V

Parameter Sym. Min. Typ. Max. Units Comments

Temperature Ranges

Maximum Junction Temperature TJ— — +150 °C

Storage Temperature TA-65 — +150 °C

Specified Temperature Range TA-40 — +125 °C

Package Thermal Resistances

Thermal Resistance, 8L-3x3 DFN JA — 64 — °C/W Typical four-layer board with

vias to ground plane

JC —12—°C/W

Thermal Resistance, 8L-SOIC JA —163—°C/W

JC —42—°C/W

 2009-2013 Microchip Technology Inc. DS22201B-page 7

MCP14700

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA=+25°C with V

CC =5.0V.

FIGURE 2-1: Rise Time vs. Capacitive

Load.

FIGURE 2-2: HIGHDR Rise and Fall Time

vs. Temperature.

FIGURE 2-3: HIGHDR Propagation Delay

vs. Temperature.

FIGURE 2-4: Fall Time vs. Capacitive

Load.

FIGURE 2-5: LOWDR Rise and Fall Time

vs. Temperature.

FIGURE 2-6: LOWDR Propagation Delay

vs. Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0 1500 3000 4500 6000 7500

Capacitive Load (pF)

Rise Time (ns)

tRL

tRH

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (oC)

Time (ns)

tRH

tFH

CLOAD = 3,300 pF

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (oC)

Propagation Delay (ns)

tPDLH

tPDHH

CLOAD = 3,300 pF

0 1500 3000 4500 6000 7500

Capacitive Load (pF)

Fall Time (ns)

tFL

tFH

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (oC)

Time (ns)

tRL

tFL

LOAD = 3,300 pF

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (oC)

Propagation Delay (ns)

tPDHL

tPDLL

CLOAD = 3,300 pF

MCP14700

DS22201B-page 8  2009-2013 Microchip Technology Inc.

Note: Unless otherwise indicated, TA=+25°C with V

CC =5.0V.

FIGURE 2-7: Supply Current vs.

Frequency.

FIGURE 2-8: Supply Current vs.

Temperature.

100 1000 10000

Frequency (kHz)

Supply Current (mA)

CLOAD = 3,300 pF

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C)

Supply Current (µA)

PWM = 1

PWM = 0

CLOAD = 3,300 pF

 2009-2013 Microchip Technology Inc. DS22201B-page 9

MCP14700

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 Switch Node (PHASE)

The PHASE pin provides a return path for the high-side

gate driver. The source of the high-side and the drain of

the low-side power MOSFETs are connected to this

pin.

3.2 High-Side PWM Control Input

Signal (PWMHI)

The PWM input signal to control the high-side power

MOSFET is applied to the PWMHI pin. A logic high on

the PWMHI pin causes the HIGHDR pin to also

transition high.

3.3 Low-Side PWM Control Input

Signal (PWMLO)

The PWM input signal to control the low-side power

MOSFET is applied to the PWMLO pin. A logic high on

the PWMLO pin causes the LOWDR pin to also

transition high.

3.4 Ground (GND)

The GND pin provides ground for the MCP14700

circuitry. It should have a low-impedance connection to

the bias supply source return. High peak currents will

flow out the GND pin when the low-side power

MOSFET is being turned off.

3.5 Low-side Gate Drive (LOWDR)

The LOWDR pin provides the gate drive signal to

control the low-side power MOSFET. The gate of the

low-side power MOSFET is connected to this pin.

3.6 Supply Input Voltage (VCC)

The VCC pin provides bias to the MCP14700 device. A

bypass capacitor is to be placed between this pin and

the GND pin. This capacitor should be placed as close

to the MCP14700 as possible.

3.7 Floating Bootstrap Supply (BOOT)

The BOOT pin is the floating bootstrap supply pin for

the high-side gate drive. A capacitor is connected

between this pin and the PHASE pin to provide the

necessary charge to turn on the high-side power

MOSFET.

3.8 High-Side Gate Drive (HIGHDR)

The HIGHDR pin provides the gate drive signal to

control the high-side power MOSFET. The gate of the

high-side power MOSFET is connected to this pin.

3.9 Exposed Metal Pad (EP)

The exposed metal pad of the DFN package is not

internally connected to any potential. Therefore, this

pad can be connected to a ground plane or other

copper plane on a printed circuit board to aid in heat

removal from the package.

TABLE 3-1: PIN FUNCTION TABLE

MCP14700

Symbol Description

3x3 DFN SOIC

1 1 PHASE Switch Node

22PWM

HI High-Side PWM Control Input Signal

33PWM

LO Low-Side PWM Control Input Signal

44GNDGround

5 5 LOWDR Low-side Gate Drive

66V

CC Supply Input Voltage

7 7 BOOT Floating Bootstrap Supply

8 8 HIGHDR High-Side Gate Drive

9 — EP Exposed Metal Pad

MCP14700

DS22201B-page 10  2009-2013 Microchip Technology Inc.

NOTES:

 2009-2013 Microchip Technology Inc. DS22201B-page 11

MCP14700

4.0 DETAILED DESCRIPTION

4.1 Device Overview

The MCP14700 is a synchronous MOSFET driver with

dual independent PWM inputs capable of controlling

both a ground referenced and floating N-Channel

MOSFET. The PWM input threshold levels are truly

3.0V logic tolerant and have 400 mV of typical

hystereses making the MCP14700 ideal for use with

low-voltage controllers.

The MCP14700 is capable of suppling 2A (typical)

peak current to the floating high-side MOSFET that is

connected to the HIGHDR. With the exception of a

capacitor, all of the circuitry needed to drive this

high-side N-channel MOSFET is internal to the

MCP14700. A blocking device is placed between the

VCC and BOOT pins that allows the bootstrap capacitor

to be charged to VCC when the low-side power

MOSFET is conducting. Refer to the application

section, Section 5.1 “Bootstrap Capacitor Select”,

for information on determining the proper size of the

bootstrap capacitor. The HIGHDR is also capable of

sinking 2A (typical) peak current.

The LOWDR is capable of sourcing 2A (typical) peak

current and sinking 3.5A (typical) peak current. This

helps ensure that the low-side MOSFET stays turned

off during the high dv/dt of the PHASE node.

4.2 PWM Inputs

A logic high on either PWM pin causes the

corresponding output drive signal to be high. See

Figure 4-1 and Figure 4-2 for a graphical

representation of the MCP14700 operation. Internally

the PWM pins are pulled to ground to ensure there is

no drive signal to the external MOSFETs if the pins are

left floating. For reliable operation, it is recommended

that the rising and falling slew rate of the PWM signal

be faster than 1V/50 ns.

When designing with the MCP14700 in applications

where cross conduction of the external MOSFETs is

not desired, care must be taken to ensure the PWM

inputs have the proper timing. There is no internal

cross conduction protection in the MCP14700.

4.3 Under Voltage Lockout (UVLO)

The UVLO feature of the MCP14700 does not allow the

HIGHDR or LOWDR output to function when the input

voltage, VCC, is below the UVLO threshold regardless

of the state of the PWMHI and PWMLO pins.

Once VCC reaches the UVLO threshold, the HIGHDR

and LOWDR outputs will respond to the state of the

PWMHI or PWMLO pins. There is a 500 mV hystereses

on the UVLO threshold.

4.4 Overtemperature Protection

The MCP14700 is protected from an overtemperature

condition by an internal thermal shutdown feature.

When the internal temperature of the MCP14700

reaches 147°C typically, the HIGHDR and LOWDR

outputs will transition to a low state regardless of the

state of the PWMHI or PWMLO pins. Once the internal

temperature is reduced by 20°C typically, the

MCP14700 will automatically respond to the states of

the PWMHI and PWMLO pins.

4.5 Timing Diagram

The PWM signal applied to the MCP14700 is supplied

by a controller IC. The timing diagram in Figure 4-1

graphically depicts the PWM signal and the output

signals of the MCP14700.

FIGURE 4-1: MCP14700 LOWDR Timing Diagram.

PWMLO

LOWDR

tPDHL

tRL

tPDLL

tFL

MCP14700

DS22201B-page 12  2009-2013 Microchip Technology Inc.

FIGURE 4-2: MCP14700 HIGHDR Timing Diagram.

PWMHI

HIGHDR

tPDHH

tRH

tPDLH

tFH

 2009-2013 Microchip Technology Inc. DS22201B-page 13

MCP14700

5.0 APPLICATION INFORMATION

5.1 Bootstrap Capacitor Select

The selection of the bootstrap capacitor is based upon

the total gate charge of the high-side power MOSFET

and the allowable droop in gate drive voltage while the

high-side power MOSFET is conducting.

EQUATION 5-1:

For example:

QGATE = 30 nC

VDROOP = 200 mV

CBOOT 0.15 uF

A low ESR ceramic capacitor is recommend with a

maximum voltage rating that exceeds the maximum

input voltage, VCC, plus the maximum supply voltage,

VSUPPLY

. It is also recommended that the capacitance

of CBOOT does not exceed 1.2 uF.

5.2 Decoupling Capacitor

Proper decoupling of the MCP14700 is highly

recommended to help ensure reliable operation. This

decoupling capacitor should be placed as close to the

MCP14700 as possible. The large currents required to

quickly charge the capacitive loads are provided by this

capacitor. A low ESR ceramic capacitor is

recommended.

5.3 Power Dissipation

The power dissipated in the MCP14700 consists of the

power loss associated with the quiescent power and

the gate charge power.

The quiescent power loss can be calculated by the

following equation and is typically negligible compared

to the gate drive power loss.

EQUATION 5-2:

The main power loss occurs from the gate charge

power loss. This power loss can be defined in terms of

both the high-side and low-side power MOSFETs.

EQUATION 5-3:

CBOOT

QGATE



DROOP

-----------------------------



Where:

CBOOT = Bootstrap capacitor value

QGATE = Total gate charge of the high-side

MOSFET

VDROO = Allowable gate drive voltage droop

PQIVCC VCC



Where:

PQ= Quiescent power loss

IVCC = No Load Bias Current

VCC = Bias Voltage

PGATE PHIGHDR PLOWDR

PHIGHDR VCC QHIGH



FSW



PLOWDR VCC QLOW



FSW



Where:

PGATE = Total Gate Charge Power Loss

PHIGHDR = High-Side Gate Charge Power Loss

PLOWDR = Low-Side Gate Charge Power Loss

VCC = Bias Supply Voltage

QHIGH = High-Side MOSFET Total Gate

Charge

QLOW = Low-Side MOSFET Total GAte

Charge

FSW = Switching Frequency

MCP14700

DS22201B-page 14  2009-2013 Microchip Technology Inc.

5.4 PCB Layout

Proper PCB layout is important in a high current, fast

switching circuit to provide proper device operation.

Improper component placement may cause errant

switching, excessive voltage ringing, or circuit latch-up.

There are two important states of the MCP14700

outputs, high and low. Figure 5-1 depicts the current

flow paths when the outputs of the MCP14700 are high

and the power MOSFETs are turned on. The charge

needed to turn on the low-side power MOSFET comes

from the decoupling capacitor CVCC. The current flows

from this capacitor through the internal LOWDR

circuitry, into the gate of the low-side power MOSFET,

out the source, into the ground plane, and back to

CVCC. To reduce any excess voltage ringing or spiking,

the inductance and area of this current loop must be

minimized.

FIGURE 5-1: Turn On Current Paths.

The charge needed to turn on the high-side power

MOSFET comes from the bootstrap capacitor CBOOT

Current flows from CBOOT through the internal

HIGHDR circuitry, into the gate of the high-side power

MOSFET, out the source and back to CBOOT

. The

printed circuit board traces that construct this current

loop need to have a small area and low inductance. To

control the inductance, short and wide traces must be

used.

Figure 5-2 depicts the current flow paths when the

outputs of the MCP14700 are low and the power

MOSFETs are turned off. These current paths should

also have low inductance and a small loop area to

minimize the voltage ringing and spiking.

FIGURE 5-2: Turn Off Current Paths.

The following recommendations should be followed for

optimal circuit performance:

- The components that construct the high

current paths previously mentioned should be

placed close the MCP14700 device. The

traces used to construct these current loops

should be wide and short to keep the

inductance and impedance low.

- A ground plane should be used to keep both

the parasitic inductance and impedance

minimized. The MCP14700 device is capable

of sourcing and sinking high peaks current

and any extra parasitic inductance or

impedance will result in non-optimal

performance.

VCC

PWMHI

CVCC

CBOOT VSUPPLY

MCP14700

PWMLO

VCC

PWMHI

CVCC

CBOOT VSUPPLY

MCP14700

PWMLO

 2009-2013 Microchip Technology Inc. DS22201B-page 15

MCP14700

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

14700E

SN 0933

256

8-Lead DFN (3x3) Example:

XXXX

YYWW

NNN

DABR

0933

256

Device Code

MCP14700 DABR

Note: Applies to 8-Lead

3x3 DFN

MCP14700

DS22201B-page 16  2009-2013 Microchip Technology Inc.