HEF4017BT,653 - NXP Semiconductors

1. General description

The HEF4017B is a 5-stage Johnson decade counter with te n spike-free decoded active

HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop

(Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding

asynchronous master reset input (MR).

The counter is advanced by either a LOW -t o-HIGH t ransi tion at CP 0 while CP1 is LOW or

a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3).

When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,

6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR

resets the counter to zero (Q0 = Q 5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock

inputs (CP0, CP1).

Automatic counter code correction is provided by an internal circuit: following any illegal

code the counter returns to a proper counting mode within 11 clock pulses.

Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to V SS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Automatic counter correct ion

Tolerant of slow clock rise and fall times

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +125 C

Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4017B

5-stage Johnson decade counter

Rev. 8 — 18 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4017BP DIP16 plastic dual in-l ine package; 16 lead s (300 mil) SOT38-4

HEF4017BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 18 November 2011 2 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

4. Functional diagram

Fig 1. Functional di agram

Fig 2. Logic diag ram

001aah242

DECODING AND OUTPUT CIRCUITRY

5-STAGE JOHNSON COUNTER

CP0

13 CP1

Q5-9

001aah243

CP1

CP0

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q5-9

Product data sheet Rev. 8 — 18 November 2011 3 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 3. Logic symbol Fig 4. IEE logic symbol

Q5-9

Q8 9

MR15

13 CP0

CP1

Q7 6

Q5 1

Q3 7

Q2 4

Q1 2

Q0 3

001aah239

CT≥5

CT = 0

CTRDIV10/DEC

001aah240

Fig 5. Pin configuratio n

HEF4017B

Q5 V

Q1 MR

Q0 CP0

Q2 CP1

Q6 Q5-9

Q7 Q9

Q3 Q4

001aae574

Table 2. Pin description

Symbol Pin Description

Q0 to Q9 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output

VSS 8 ground supply voltage

Q5-9 12 carry output (active LOW)

CP1 13 clock input (HIGH-to-LOW edge-triggered)

Product data sheet Rev. 8 — 18 November 2011 4 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

6. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = positive-going transition;  = negative-going transition.

CP0 14 clock input (LOW-to-HIGH edge-triggered)

MR 15 master reset input

VDD 16 supply voltage

Table 2. Pin description …continued

Symbol Pin Description

Table 3. Function table [1]

MR CP0 CP1Operation

HXXQ0 = Q

5-9 = H; Q1 to Q9 = L

LHcounter advances

LL counter advances

L L X no change

L X H no change

LHno change

LL no change

Product data sheet Rev. 8 — 18 November 2011 5 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

7. Limiting values

Fig 6. Timing diagram

001aah244

CP0 INPUT

CP1 INPUT

MR INPUT

Q0 OUTPUT

Q1 OUTPUT

Q2 OUTPUT

Q3 OUTPUT

Q4 OUTPUT

Q5 OUTPUT

Q6 OUTPUT

Q7 OUTPUT

Q8 OUTPUT

Q9 OUTPUT

Q5-9 OUTPUT

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping curre nt VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

Product data sheet Rev. 8 — 18 November 2011 6 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

8. Recommended operating conditions

9. Static characteristics

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +125 C

Ptot total power dissipation Tamb = 40 C to +125 C

DIP16 package [1] -750mW

SO16 package [2] -500mW

P power dissipation per output - 100 mW

Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +125 C

t/V input transition rise and fall rate VDD = 5 V --3.75s/V

VDD = 10 V --0.5s/V

VDD = 15 V --0.08s/V

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - 11.0 - V

VIL LOW-level

input voltage IO < 1 A 5V -1.5-1.5-1.5-1.5V

10V -3.0-3.0-3.0-3.0V

15V -4.0-4.0-4.0-4.0V

VOH HIGH-level

output voltage IO < 1 A;

VI=V

SS or VDD

5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage IO < 1 A;

VI=V

SS or VDD

5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

Product data sheet Rev. 8 — 18 November 2011 7 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

10. Dynamic characteristics

IOH HIGH-level

output cur rent VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

IOL LOW-level

output cur rent VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

IIinput leakage

current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

IDD supply current IO = 0 A;

VI = VSS or VDD

5 V - 5 - 5 - 150 - 150 A

10 V - 10 - 10 - 300 - 300 A

15 V - 20 - 20 - 600 - 600 A

CIinput

capacitance ----7.5----pF

Table 6. Static characteristics …continued

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit

Min Max Min Max Min Max Min Max

Table 7. Dynamic characteristics

Tamb = 25



C; VSS = 0 V; for test circuit see Figure 10

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP0, CP1  Q0 to Q9;

see Figure 7 5 V 113 ns + (0.55 ns/pF)CL- 140 280 ns

10 V 44 ns + (0.23 ns/pF)CL-55110ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

CP0, CP1  Q5-9;

see Figure 7 5 V 118 ns + (0.55 ns/pF)CL- 145 290 ns

10 V 44 ns + (0.23 ns/pF)CL-55110ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

MR  Q1 to Q9;

see Figure 8 5 V 88 ns + (0.55 ns/pF)CL- 115 230 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

Product data sheet Rev. 8 — 18 November 2011 8 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

[2] tt is the same as tTHL and tTLH.

tPLH LOW to HIGH

propagation delay CP0, CP1  Q0 to Q9;

see Figure 7 5 V 98 ns + (0.55 ns/pF)CL- 125 250 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

CP0, CP1  Q5-9;

see Figure 7 5 V 98 ns + (0.55 ns/pF)CL- 125 250 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

MR Q5-9;

see Figure 8 5 V 83 ns + (0.55 ns/pF)CL- 110 220 ns

10 V 34 ns + (0.23 ns/pF)CL-4590ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

MR Q0;

see Figure 8 5 V 103 ns + (0.55 ns/pF)CL- 130 260 ns

10 V 44 ns + (0.23 ns/pF)CL- 55 105 ns

15 V 32 ns + (0.16 ns/pF)CL-4075ns

tttransition time see Figure 7 5V [2] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

thhold time CP0  CP1;

see Figure 9 5 V 90 45 - ns

10 V 40 20 - ns

15 V 20 10 - ns

CP1  CP0;

see Figure 9 5 V 80 40 - ns

10 V 40 20 - ns

15 V 30 10 - ns

tWpulse width CP0 input LOW;

minimum width;

see Figure 8

5 V 80 40 - ns

10 V 40 20 - ns

15 V 30 15 - ns

CP1 input HIGH;

minimum width;

see Figure 8

5 V 80 40 - ns

10 V 40 20 - ns

15 V 30 15 - ns

MR input HIGH;

minimum width;

see Figure 8

5 V 50 25 - ns

10 V 30 15 - ns

15 V 20 10 - ns

trec recovery time MR input;

see Figure 8 5 V 60 30 - ns

10 V 30 15 - ns

15 V 20 10 - ns

fmax maximum

frequency see Figure 8 5V 6 12 - MHz

10 V 12 30 - MHz

15 V 15 30 - MHz

Table 7. Dynamic characteristics …continued

Tamb = 25



C; VSS = 0 V; for test circuit see Figure 10

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

Product data sheet Rev. 8 — 18 November 2011 9 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

11. Waveforms

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula for PD (W) where:

PDdynamic power

dissipation 5V P

D = 500  fi + (fo  CL)  VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

(CL  fo) = sum of the outputs.

10 V PD = 2200  fi + (fo  CL)  VDD2

15 V PD = 6000  fi + (fo  CL)  VDD2

Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition. CP1 triggers on a HIGH-to-LOW transition;

The shaded areas indicate where the output state is set by the input count.

Measurement points given in Table 9.

Fig 7. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition

times

CP0 input

Q1 - Q9

output

CP1 input

PLH

PHL

PLH

PHL

TLH

THL

001aaj305

Q0, Q5 - Q9

output

Product data sheet Rev. 8 — 18 November 2011 10 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, tW and trec are measured when CP0 = HIGH and

CP1 triggers on a HIGH-to-LOW transition.

The shaded areas indicate where the output state is set by the input count.

Measurement points given in Table 9.

Fig 8. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for

CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays

CP0 input

Q1 - Q9

output

MR input

CP1 input

1/f

max

rec

1/f

max

PLH

PHL

001aaj306

Q0, Q5 - Q9

output

Hold times are shown as positive values, but may be specified as negative values;

Measurement points given in Table 9.

Fig 9. Waveforms showing hold times for CP0 to CP1 and CP 1 to CP0

001aae578

CP0 input

VSS

CP1 input

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 8 — 18 November 2011 11 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

12. Application information

Some examples of applications for the HEF4017B are:

•Decade counter with decimal decoding

•1 out of n decoding counter (when cascaded)

•Sequential controller

•Timer

Figure 11 shows a technique for extending the number of decoded output states for the

HEF4017B. Decoded outputs are sequential within each stage and from stage to stage,

with no dead time (except propagation delay).

a. Input waveforms

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test;

CL= load capacitance including jig and probe capacitance;

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 10. Test circuit for measuring switching times

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

90 %

10 %

001aaj781

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD 20 ns 50 pF

Product data sheet Rev. 8 — 18 November 2011 12 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

Enabling the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, causes an extra count.

Fig 11. Cou nte r expansion

001aae577

8 decoded

outputs

8 decoded

outputs

CP0

CP1

Q0 Q1 Q8 Q9

HEF4017B

- - - -

CP0

CP1

Q0 Q1 Q8 Q9

HEF4017B

- - - -

CP0

CP1

Q1 Q8 Q9

HEF4017B

- - - - - -

clock first stage last stageintermediate stages

MR MR

9 decoded

outputs

Product data sheet Rev. 8 — 18 November 2011 13 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

13. Package outline

Fig 12. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 8 — 18 November 2011 14 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

Fig 13. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 18 November 2011 15 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4017B v.8 201 11118 Product data sheet - HEF4017B v.7

Modifications: •Legal pages updated.

•Changes in “General description” and “Features and benefits”.

•Section “Applications” removed.

HEF4017B v.7 20110914 Product data sheet - HEF4017B v.6

HEF4017B v.6 20091105 Product data sheet - HEF4017B v.5

HEF4017B v.5 20090709 Product data sheet - HEF4017B v.4

HEF4017B v.4 20081209 Product data sheet - HEF4017B_CNV v.3

HEF4017B_CNV v.3 19950101 Product specification - HEF4017B_CNV v.2

HEF4017B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 8 — 18 November 2011 16 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

15. Legal information

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[1] Please consult the most recently issued document before initiating or completing a design.

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[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

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other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 8 — 18 November 2011 17 of 18

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product cl aims resulting f rom customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4017B

5-stage Johnson decade counter

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 18 November 2011

Document iden tifier: HEF4017B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Application information. . . . . . . . . . . . . . . . . . 11

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 Contact information. . . . . . . . . . . . . . . . . . . . . 17

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18